xref: /linux/drivers/net/pcs/pcs-rzn1-miic.c (revision d6fd48ef) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2022 Schneider Electric
4  *
5  * Clément Léger <clement.leger@bootlin.com>
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/device.h>
10 #include <linux/mdio.h>
11 #include <linux/of.h>
12 #include <linux/of_platform.h>
13 #include <linux/pcs-rzn1-miic.h>
14 #include <linux/phylink.h>
15 #include <linux/pm_runtime.h>
16 #include <dt-bindings/net/pcs-rzn1-miic.h>
17 
18 #define MIIC_PRCMD			0x0
19 #define MIIC_ESID_CODE			0x4
20 
21 #define MIIC_MODCTRL			0x20
22 #define MIIC_MODCTRL_SW_MODE		GENMASK(4, 0)
23 
24 #define MIIC_CONVCTRL(port)		(0x100 + (port) * 4)
25 
26 #define MIIC_CONVCTRL_CONV_SPEED	GENMASK(1, 0)
27 #define CONV_MODE_10MBPS		0
28 #define CONV_MODE_100MBPS		1
29 #define CONV_MODE_1000MBPS		2
30 
31 #define MIIC_CONVCTRL_CONV_MODE		GENMASK(3, 2)
32 #define CONV_MODE_MII			0
33 #define CONV_MODE_RMII			1
34 #define CONV_MODE_RGMII			2
35 
36 #define MIIC_CONVCTRL_FULLD		BIT(8)
37 #define MIIC_CONVCTRL_RGMII_LINK	BIT(12)
38 #define MIIC_CONVCTRL_RGMII_DUPLEX	BIT(13)
39 #define MIIC_CONVCTRL_RGMII_SPEED	GENMASK(15, 14)
40 
41 #define MIIC_CONVRST			0x114
42 #define MIIC_CONVRST_PHYIF_RST(port)	BIT(port)
43 #define MIIC_CONVRST_PHYIF_RST_MASK	GENMASK(4, 0)
44 
45 #define MIIC_SWCTRL			0x304
46 #define MIIC_SWDUPC			0x308
47 
48 #define MIIC_MAX_NR_PORTS		5
49 
50 #define MIIC_MODCTRL_CONF_CONV_NUM	6
51 #define MIIC_MODCTRL_CONF_NONE		-1
52 
53 /**
54  * struct modctrl_match - Matching table entry for  convctrl configuration
55  *			  See section 8.2.1 of manual.
56  * @mode_cfg: Configuration value for convctrl
57  * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN,
58  *	  then index 1 - 5 are CONV1 - CONV5.
59  */
60 struct modctrl_match {
61 	u32 mode_cfg;
62 	u8 conv[MIIC_MODCTRL_CONF_CONV_NUM];
63 };
64 
65 static struct modctrl_match modctrl_match_table[] = {
66 	{0x0, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
67 	       MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
68 	{0x1, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
69 	       MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
70 	{0x2, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
71 	       MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
72 	{0x3, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
73 	       MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}},
74 
75 	{0x8, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
76 	       MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
77 	{0x9, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
78 	       MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
79 	{0xA, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
80 	       MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
81 	{0xB, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
82 	       MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}},
83 
84 	{0x10, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
85 		MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
86 	{0x11, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
87 		MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
88 	{0x12, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
89 		MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
90 	{0x13, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
91 		MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}
92 };
93 
94 static const char * const conf_to_string[] = {
95 	[MIIC_GMAC1_PORT]	= "GMAC1_PORT",
96 	[MIIC_GMAC2_PORT]	= "GMAC2_PORT",
97 	[MIIC_RTOS_PORT]	= "RTOS_PORT",
98 	[MIIC_SERCOS_PORTA]	= "SERCOS_PORTA",
99 	[MIIC_SERCOS_PORTB]	= "SERCOS_PORTB",
100 	[MIIC_ETHERCAT_PORTA]	= "ETHERCAT_PORTA",
101 	[MIIC_ETHERCAT_PORTB]	= "ETHERCAT_PORTB",
102 	[MIIC_ETHERCAT_PORTC]	= "ETHERCAT_PORTC",
103 	[MIIC_SWITCH_PORTA]	= "SWITCH_PORTA",
104 	[MIIC_SWITCH_PORTB]	= "SWITCH_PORTB",
105 	[MIIC_SWITCH_PORTC]	= "SWITCH_PORTC",
106 	[MIIC_SWITCH_PORTD]	= "SWITCH_PORTD",
107 	[MIIC_HSR_PORTA]	= "HSR_PORTA",
108 	[MIIC_HSR_PORTB]	= "HSR_PORTB",
109 };
110 
111 static const char *index_to_string[MIIC_MODCTRL_CONF_CONV_NUM] = {
112 	"SWITCH_PORTIN",
113 	"CONV1",
114 	"CONV2",
115 	"CONV3",
116 	"CONV4",
117 	"CONV5",
118 };
119 
120 /**
121  * struct miic - MII converter structure
122  * @base: base address of the MII converter
123  * @dev: Device associated to the MII converter
124  * @lock: Lock used for read-modify-write access
125  */
126 struct miic {
127 	void __iomem *base;
128 	struct device *dev;
129 	spinlock_t lock;
130 };
131 
132 /**
133  * struct miic_port - Per port MII converter struct
134  * @miic: backiling to MII converter structure
135  * @pcs: PCS structure associated to the port
136  * @port: port number
137  * @interface: interface mode of the port
138  */
139 struct miic_port {
140 	struct miic *miic;
141 	struct phylink_pcs pcs;
142 	int port;
143 	phy_interface_t interface;
144 };
145 
146 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs)
147 {
148 	return container_of(pcs, struct miic_port, pcs);
149 }
150 
151 static void miic_reg_writel(struct miic *miic, int offset, u32 value)
152 {
153 	writel(value, miic->base + offset);
154 }
155 
156 static u32 miic_reg_readl(struct miic *miic, int offset)
157 {
158 	return readl(miic->base + offset);
159 }
160 
161 static void miic_reg_rmw(struct miic *miic, int offset, u32 mask, u32 val)
162 {
163 	u32 reg;
164 
165 	spin_lock(&miic->lock);
166 
167 	reg = miic_reg_readl(miic, offset);
168 	reg &= ~mask;
169 	reg |= val;
170 	miic_reg_writel(miic, offset, reg);
171 
172 	spin_unlock(&miic->lock);
173 }
174 
175 static void miic_converter_enable(struct miic *miic, int port, int enable)
176 {
177 	u32 val = 0;
178 
179 	if (enable)
180 		val = MIIC_CONVRST_PHYIF_RST(port);
181 
182 	miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val);
183 }
184 
185 static int miic_config(struct phylink_pcs *pcs, unsigned int mode,
186 		       phy_interface_t interface,
187 		       const unsigned long *advertising, bool permit)
188 {
189 	struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
190 	struct miic *miic = miic_port->miic;
191 	u32 speed, conv_mode, val, mask;
192 	int port = miic_port->port;
193 
194 	switch (interface) {
195 	case PHY_INTERFACE_MODE_RMII:
196 		conv_mode = CONV_MODE_RMII;
197 		speed = CONV_MODE_100MBPS;
198 		break;
199 	case PHY_INTERFACE_MODE_RGMII:
200 	case PHY_INTERFACE_MODE_RGMII_ID:
201 	case PHY_INTERFACE_MODE_RGMII_TXID:
202 	case PHY_INTERFACE_MODE_RGMII_RXID:
203 		conv_mode = CONV_MODE_RGMII;
204 		speed = CONV_MODE_1000MBPS;
205 		break;
206 	case PHY_INTERFACE_MODE_MII:
207 		conv_mode = CONV_MODE_MII;
208 		/* When in MII mode, speed should be set to 0 (which is actually
209 		 * CONV_MODE_10MBPS)
210 		 */
211 		speed = CONV_MODE_10MBPS;
212 		break;
213 	default:
214 		return -EOPNOTSUPP;
215 	}
216 
217 	val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, conv_mode);
218 	mask = MIIC_CONVCTRL_CONV_MODE;
219 
220 	/* Update speed only if we are going to change the interface because
221 	 * the link might already be up and it would break it if the speed is
222 	 * changed.
223 	 */
224 	if (interface != miic_port->interface) {
225 		val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed);
226 		mask |= MIIC_CONVCTRL_CONV_SPEED;
227 		miic_port->interface = interface;
228 	}
229 
230 	miic_reg_rmw(miic, MIIC_CONVCTRL(port), mask, val);
231 	miic_converter_enable(miic, miic_port->port, 1);
232 
233 	return 0;
234 }
235 
236 static void miic_link_up(struct phylink_pcs *pcs, unsigned int mode,
237 			 phy_interface_t interface, int speed, int duplex)
238 {
239 	struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
240 	struct miic *miic = miic_port->miic;
241 	u32 conv_speed = 0, val = 0;
242 	int port = miic_port->port;
243 
244 	if (duplex == DUPLEX_FULL)
245 		val |= MIIC_CONVCTRL_FULLD;
246 
247 	/* No speed in MII through-mode */
248 	if (interface != PHY_INTERFACE_MODE_MII) {
249 		switch (speed) {
250 		case SPEED_1000:
251 			conv_speed = CONV_MODE_1000MBPS;
252 			break;
253 		case SPEED_100:
254 			conv_speed = CONV_MODE_100MBPS;
255 			break;
256 		case SPEED_10:
257 			conv_speed = CONV_MODE_10MBPS;
258 			break;
259 		default:
260 			return;
261 		}
262 	}
263 
264 	val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, conv_speed);
265 
266 	miic_reg_rmw(miic, MIIC_CONVCTRL(port),
267 		     (MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val);
268 }
269 
270 static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported,
271 			 const struct phylink_link_state *state)
272 {
273 	if (phy_interface_mode_is_rgmii(state->interface) ||
274 	    state->interface == PHY_INTERFACE_MODE_RMII ||
275 	    state->interface == PHY_INTERFACE_MODE_MII)
276 		return 1;
277 
278 	return -EINVAL;
279 }
280 
281 static const struct phylink_pcs_ops miic_phylink_ops = {
282 	.pcs_validate = miic_validate,
283 	.pcs_config = miic_config,
284 	.pcs_link_up = miic_link_up,
285 };
286 
287 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np)
288 {
289 	struct platform_device *pdev;
290 	struct miic_port *miic_port;
291 	struct device_node *pcs_np;
292 	struct miic *miic;
293 	u32 port;
294 
295 	if (!of_device_is_available(np))
296 		return ERR_PTR(-ENODEV);
297 
298 	if (of_property_read_u32(np, "reg", &port))
299 		return ERR_PTR(-EINVAL);
300 
301 	if (port > MIIC_MAX_NR_PORTS || port < 1)
302 		return ERR_PTR(-EINVAL);
303 
304 	/* The PCS pdev is attached to the parent node */
305 	pcs_np = of_get_parent(np);
306 	if (!pcs_np)
307 		return ERR_PTR(-ENODEV);
308 
309 	if (!of_device_is_available(pcs_np)) {
310 		of_node_put(pcs_np);
311 		return ERR_PTR(-ENODEV);
312 	}
313 
314 	pdev = of_find_device_by_node(pcs_np);
315 	of_node_put(pcs_np);
316 	if (!pdev || !platform_get_drvdata(pdev))
317 		return ERR_PTR(-EPROBE_DEFER);
318 
319 	miic_port = kzalloc(sizeof(*miic_port), GFP_KERNEL);
320 	if (!miic_port)
321 		return ERR_PTR(-ENOMEM);
322 
323 	miic = platform_get_drvdata(pdev);
324 	device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
325 
326 	miic_port->miic = miic;
327 	miic_port->port = port - 1;
328 	miic_port->pcs.ops = &miic_phylink_ops;
329 
330 	return &miic_port->pcs;
331 }
332 EXPORT_SYMBOL(miic_create);
333 
334 void miic_destroy(struct phylink_pcs *pcs)
335 {
336 	struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
337 
338 	miic_converter_enable(miic_port->miic, miic_port->port, 0);
339 	kfree(miic_port);
340 }
341 EXPORT_SYMBOL(miic_destroy);
342 
343 static int miic_init_hw(struct miic *miic, u32 cfg_mode)
344 {
345 	int port;
346 
347 	/* Unlock write access to accessory registers (cf datasheet). If this
348 	 * is going to be used in conjunction with the Cortex-M3, this sequence
349 	 * will have to be moved in register write
350 	 */
351 	miic_reg_writel(miic, MIIC_PRCMD, 0x00A5);
352 	miic_reg_writel(miic, MIIC_PRCMD, 0x0001);
353 	miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE);
354 	miic_reg_writel(miic, MIIC_PRCMD, 0x0001);
355 
356 	miic_reg_writel(miic, MIIC_MODCTRL,
357 			FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
358 
359 	for (port = 0; port < MIIC_MAX_NR_PORTS; port++) {
360 		miic_converter_enable(miic, port, 0);
361 		/* Disable speed/duplex control from these registers, datasheet
362 		 * says switch registers should be used to setup switch port
363 		 * speed and duplex.
364 		 */
365 		miic_reg_writel(miic, MIIC_SWCTRL, 0x0);
366 		miic_reg_writel(miic, MIIC_SWDUPC, 0x0);
367 	}
368 
369 	return 0;
370 }
371 
372 static bool miic_modctrl_match(s8 table_val[MIIC_MODCTRL_CONF_CONV_NUM],
373 			       s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM])
374 {
375 	int i;
376 
377 	for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) {
378 		if (dt_val[i] == MIIC_MODCTRL_CONF_NONE)
379 			continue;
380 
381 		if (dt_val[i] != table_val[i])
382 			return false;
383 	}
384 
385 	return true;
386 }
387 
388 static void miic_dump_conf(struct device *dev,
389 			   s8 conf[MIIC_MODCTRL_CONF_CONV_NUM])
390 {
391 	const char *conf_name;
392 	int i;
393 
394 	for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) {
395 		if (conf[i] != MIIC_MODCTRL_CONF_NONE)
396 			conf_name = conf_to_string[conf[i]];
397 		else
398 			conf_name = "NONE";
399 
400 		dev_err(dev, "%s: %s\n", index_to_string[i], conf_name);
401 	}
402 }
403 
404 static int miic_match_dt_conf(struct device *dev,
405 			      s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM],
406 			      u32 *mode_cfg)
407 {
408 	struct modctrl_match *table_entry;
409 	int i;
410 
411 	for (i = 0; i < ARRAY_SIZE(modctrl_match_table); i++) {
412 		table_entry = &modctrl_match_table[i];
413 
414 		if (miic_modctrl_match(table_entry->conv, dt_val)) {
415 			*mode_cfg = table_entry->mode_cfg;
416 			return 0;
417 		}
418 	}
419 
420 	dev_err(dev, "Failed to apply requested configuration\n");
421 	miic_dump_conf(dev, dt_val);
422 
423 	return -EINVAL;
424 }
425 
426 static int miic_parse_dt(struct device *dev, u32 *mode_cfg)
427 {
428 	s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM];
429 	struct device_node *np = dev->of_node;
430 	struct device_node *conv;
431 	u32 conf;
432 	int port;
433 
434 	memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(dt_val));
435 
436 	if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0)
437 		dt_val[0] = conf;
438 
439 	for_each_child_of_node(np, conv) {
440 		if (of_property_read_u32(conv, "reg", &port))
441 			continue;
442 
443 		if (!of_device_is_available(conv))
444 			continue;
445 
446 		if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0)
447 			dt_val[port] = conf;
448 	}
449 
450 	return miic_match_dt_conf(dev, dt_val, mode_cfg);
451 }
452 
453 static int miic_probe(struct platform_device *pdev)
454 {
455 	struct device *dev = &pdev->dev;
456 	struct miic *miic;
457 	u32 mode_cfg;
458 	int ret;
459 
460 	ret = miic_parse_dt(dev, &mode_cfg);
461 	if (ret < 0)
462 		return ret;
463 
464 	miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL);
465 	if (!miic)
466 		return -ENOMEM;
467 
468 	spin_lock_init(&miic->lock);
469 	miic->dev = dev;
470 	miic->base = devm_platform_ioremap_resource(pdev, 0);
471 	if (IS_ERR(miic->base))
472 		return PTR_ERR(miic->base);
473 
474 	ret = devm_pm_runtime_enable(dev);
475 	if (ret < 0)
476 		return ret;
477 
478 	ret = pm_runtime_resume_and_get(dev);
479 	if (ret < 0)
480 		return ret;
481 
482 	ret = miic_init_hw(miic, mode_cfg);
483 	if (ret)
484 		goto disable_runtime_pm;
485 
486 	/* miic_create() relies on that fact that data are attached to the
487 	 * platform device to determine if the driver is ready so this needs to
488 	 * be the last thing to be done after everything is initialized
489 	 * properly.
490 	 */
491 	platform_set_drvdata(pdev, miic);
492 
493 	return 0;
494 
495 disable_runtime_pm:
496 	pm_runtime_put(dev);
497 
498 	return ret;
499 }
500 
501 static int miic_remove(struct platform_device *pdev)
502 {
503 	pm_runtime_put(&pdev->dev);
504 
505 	return 0;
506 }
507 
508 static const struct of_device_id miic_of_mtable[] = {
509 	{ .compatible = "renesas,rzn1-miic" },
510 	{ /* sentinel */ },
511 };
512 MODULE_DEVICE_TABLE(of, miic_of_mtable);
513 
514 static struct platform_driver miic_driver = {
515 	.driver = {
516 		.name	 = "rzn1_miic",
517 		.suppress_bind_attrs = true,
518 		.of_match_table = miic_of_mtable,
519 	},
520 	.probe = miic_probe,
521 	.remove = miic_remove,
522 };
523 module_platform_driver(miic_driver);
524 
525 MODULE_LICENSE("GPL");
526 MODULE_DESCRIPTION("Renesas MII converter PCS driver");
527 MODULE_AUTHOR("Clément Léger <clement.leger@bootlin.com>");
528