1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/firmware.h> 10 #include <linux/of.h> 11 #include <linux/property.h> 12 #include <linux/dmi.h> 13 #include <linux/ctype.h> 14 #include <linux/pm_qos.h> 15 #include <linux/nvmem-consumer.h> 16 #include <asm/byteorder.h> 17 18 #include "core.h" 19 #include "mac.h" 20 #include "htc.h" 21 #include "hif.h" 22 #include "wmi.h" 23 #include "bmi.h" 24 #include "debug.h" 25 #include "htt.h" 26 #include "testmode.h" 27 #include "wmi-ops.h" 28 #include "coredump.h" 29 30 unsigned int ath10k_debug_mask; 31 EXPORT_SYMBOL(ath10k_debug_mask); 32 33 static unsigned int ath10k_cryptmode_param; 34 static bool uart_print; 35 static bool skip_otp; 36 static bool rawmode; 37 static bool fw_diag_log; 38 39 unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) | 40 BIT(ATH10K_FW_CRASH_DUMP_CE_DATA); 41 42 /* FIXME: most of these should be readonly */ 43 module_param_named(debug_mask, ath10k_debug_mask, uint, 0644); 44 module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644); 45 module_param(uart_print, bool, 0644); 46 module_param(skip_otp, bool, 0644); 47 module_param(rawmode, bool, 0644); 48 module_param(fw_diag_log, bool, 0644); 49 module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444); 50 51 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 52 MODULE_PARM_DESC(uart_print, "Uart target debugging"); 53 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode"); 54 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software"); 55 MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath"); 56 MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file"); 57 MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging"); 58 59 static const struct ath10k_hw_params ath10k_hw_params_list[] = { 60 { 61 .id = QCA988X_HW_2_0_VERSION, 62 .dev_id = QCA988X_2_0_DEVICE_ID, 63 .bus = ATH10K_BUS_PCI, 64 .name = "qca988x hw2.0", 65 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 66 .uart_pin = 7, 67 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 68 .otp_exe_param = 0, 69 .channel_counters_freq_hz = 88000, 70 .max_probe_resp_desc_thres = 0, 71 .cal_data_len = 2116, 72 .fw = { 73 .dir = QCA988X_HW_2_0_FW_DIR, 74 .board = QCA988X_HW_2_0_BOARD_DATA_FILE, 75 .board_size = QCA988X_BOARD_DATA_SZ, 76 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 77 }, 78 .rx_desc_ops = &qca988x_rx_desc_ops, 79 .hw_ops = &qca988x_ops, 80 .decap_align_bytes = 4, 81 .spectral_bin_discard = 0, 82 .spectral_bin_offset = 0, 83 .vht160_mcs_rx_highest = 0, 84 .vht160_mcs_tx_highest = 0, 85 .n_cipher_suites = 8, 86 .ast_skid_limit = 0x10, 87 .num_wds_entries = 0x20, 88 .target_64bit = false, 89 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 90 .shadow_reg_support = false, 91 .rri_on_ddr = false, 92 .hw_filter_reset_required = true, 93 .fw_diag_ce_download = false, 94 .credit_size_workaround = false, 95 .tx_stats_over_pktlog = true, 96 .dynamic_sar_support = false, 97 }, 98 { 99 .id = QCA988X_HW_2_0_VERSION, 100 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT, 101 .name = "qca988x hw2.0 ubiquiti", 102 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 103 .uart_pin = 7, 104 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 105 .otp_exe_param = 0, 106 .channel_counters_freq_hz = 88000, 107 .max_probe_resp_desc_thres = 0, 108 .cal_data_len = 2116, 109 .fw = { 110 .dir = QCA988X_HW_2_0_FW_DIR, 111 .board = QCA988X_HW_2_0_BOARD_DATA_FILE, 112 .board_size = QCA988X_BOARD_DATA_SZ, 113 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 114 }, 115 .rx_desc_ops = &qca988x_rx_desc_ops, 116 .hw_ops = &qca988x_ops, 117 .decap_align_bytes = 4, 118 .spectral_bin_discard = 0, 119 .spectral_bin_offset = 0, 120 .vht160_mcs_rx_highest = 0, 121 .vht160_mcs_tx_highest = 0, 122 .n_cipher_suites = 8, 123 .ast_skid_limit = 0x10, 124 .num_wds_entries = 0x20, 125 .target_64bit = false, 126 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 127 .shadow_reg_support = false, 128 .rri_on_ddr = false, 129 .hw_filter_reset_required = true, 130 .fw_diag_ce_download = false, 131 .credit_size_workaround = false, 132 .tx_stats_over_pktlog = true, 133 .dynamic_sar_support = false, 134 }, 135 { 136 .id = QCA9887_HW_1_0_VERSION, 137 .dev_id = QCA9887_1_0_DEVICE_ID, 138 .bus = ATH10K_BUS_PCI, 139 .name = "qca9887 hw1.0", 140 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR, 141 .uart_pin = 7, 142 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 143 .otp_exe_param = 0, 144 .channel_counters_freq_hz = 88000, 145 .max_probe_resp_desc_thres = 0, 146 .cal_data_len = 2116, 147 .fw = { 148 .dir = QCA9887_HW_1_0_FW_DIR, 149 .board = QCA9887_HW_1_0_BOARD_DATA_FILE, 150 .board_size = QCA9887_BOARD_DATA_SZ, 151 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ, 152 }, 153 .rx_desc_ops = &qca988x_rx_desc_ops, 154 .hw_ops = &qca988x_ops, 155 .decap_align_bytes = 4, 156 .spectral_bin_discard = 0, 157 .spectral_bin_offset = 0, 158 .vht160_mcs_rx_highest = 0, 159 .vht160_mcs_tx_highest = 0, 160 .n_cipher_suites = 8, 161 .ast_skid_limit = 0x10, 162 .num_wds_entries = 0x20, 163 .target_64bit = false, 164 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 165 .shadow_reg_support = false, 166 .rri_on_ddr = false, 167 .hw_filter_reset_required = true, 168 .fw_diag_ce_download = false, 169 .credit_size_workaround = false, 170 .tx_stats_over_pktlog = false, 171 .dynamic_sar_support = false, 172 }, 173 { 174 .id = QCA6174_HW_3_2_VERSION, 175 .dev_id = QCA6174_3_2_DEVICE_ID, 176 .bus = ATH10K_BUS_SDIO, 177 .name = "qca6174 hw3.2 sdio", 178 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 179 .uart_pin = 19, 180 .otp_exe_param = 0, 181 .channel_counters_freq_hz = 88000, 182 .max_probe_resp_desc_thres = 0, 183 .cal_data_len = 0, 184 .fw = { 185 .dir = QCA6174_HW_3_0_FW_DIR, 186 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 187 .board_size = QCA6174_BOARD_DATA_SZ, 188 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 189 }, 190 .rx_desc_ops = &qca988x_rx_desc_ops, 191 .hw_ops = &qca6174_sdio_ops, 192 .hw_clk = qca6174_clk, 193 .target_cpu_freq = 176000000, 194 .decap_align_bytes = 4, 195 .n_cipher_suites = 8, 196 .num_peers = 10, 197 .ast_skid_limit = 0x10, 198 .num_wds_entries = 0x20, 199 .uart_pin_workaround = true, 200 .tx_stats_over_pktlog = false, 201 .credit_size_workaround = false, 202 .bmi_large_size_download = true, 203 .supports_peer_stats_info = true, 204 .dynamic_sar_support = true, 205 }, 206 { 207 .id = QCA6174_HW_2_1_VERSION, 208 .dev_id = QCA6164_2_1_DEVICE_ID, 209 .bus = ATH10K_BUS_PCI, 210 .name = "qca6164 hw2.1", 211 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 212 .uart_pin = 6, 213 .otp_exe_param = 0, 214 .channel_counters_freq_hz = 88000, 215 .max_probe_resp_desc_thres = 0, 216 .cal_data_len = 8124, 217 .fw = { 218 .dir = QCA6174_HW_2_1_FW_DIR, 219 .board = QCA6174_HW_2_1_BOARD_DATA_FILE, 220 .board_size = QCA6174_BOARD_DATA_SZ, 221 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 222 }, 223 .rx_desc_ops = &qca988x_rx_desc_ops, 224 .hw_ops = &qca988x_ops, 225 .decap_align_bytes = 4, 226 .spectral_bin_discard = 0, 227 .spectral_bin_offset = 0, 228 .vht160_mcs_rx_highest = 0, 229 .vht160_mcs_tx_highest = 0, 230 .n_cipher_suites = 8, 231 .ast_skid_limit = 0x10, 232 .num_wds_entries = 0x20, 233 .target_64bit = false, 234 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 235 .shadow_reg_support = false, 236 .rri_on_ddr = false, 237 .hw_filter_reset_required = true, 238 .fw_diag_ce_download = false, 239 .credit_size_workaround = false, 240 .tx_stats_over_pktlog = false, 241 .dynamic_sar_support = false, 242 }, 243 { 244 .id = QCA6174_HW_2_1_VERSION, 245 .dev_id = QCA6174_2_1_DEVICE_ID, 246 .bus = ATH10K_BUS_PCI, 247 .name = "qca6174 hw2.1", 248 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 249 .uart_pin = 6, 250 .otp_exe_param = 0, 251 .channel_counters_freq_hz = 88000, 252 .max_probe_resp_desc_thres = 0, 253 .cal_data_len = 8124, 254 .fw = { 255 .dir = QCA6174_HW_2_1_FW_DIR, 256 .board = QCA6174_HW_2_1_BOARD_DATA_FILE, 257 .board_size = QCA6174_BOARD_DATA_SZ, 258 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 259 }, 260 .rx_desc_ops = &qca988x_rx_desc_ops, 261 .hw_ops = &qca988x_ops, 262 .decap_align_bytes = 4, 263 .spectral_bin_discard = 0, 264 .spectral_bin_offset = 0, 265 .vht160_mcs_rx_highest = 0, 266 .vht160_mcs_tx_highest = 0, 267 .n_cipher_suites = 8, 268 .ast_skid_limit = 0x10, 269 .num_wds_entries = 0x20, 270 .target_64bit = false, 271 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 272 .shadow_reg_support = false, 273 .rri_on_ddr = false, 274 .hw_filter_reset_required = true, 275 .fw_diag_ce_download = false, 276 .credit_size_workaround = false, 277 .tx_stats_over_pktlog = false, 278 .dynamic_sar_support = false, 279 }, 280 { 281 .id = QCA6174_HW_3_0_VERSION, 282 .dev_id = QCA6174_2_1_DEVICE_ID, 283 .bus = ATH10K_BUS_PCI, 284 .name = "qca6174 hw3.0", 285 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 286 .uart_pin = 6, 287 .otp_exe_param = 0, 288 .channel_counters_freq_hz = 88000, 289 .max_probe_resp_desc_thres = 0, 290 .cal_data_len = 8124, 291 .fw = { 292 .dir = QCA6174_HW_3_0_FW_DIR, 293 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 294 .board_size = QCA6174_BOARD_DATA_SZ, 295 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 296 }, 297 .rx_desc_ops = &qca988x_rx_desc_ops, 298 .hw_ops = &qca988x_ops, 299 .decap_align_bytes = 4, 300 .spectral_bin_discard = 0, 301 .spectral_bin_offset = 0, 302 .vht160_mcs_rx_highest = 0, 303 .vht160_mcs_tx_highest = 0, 304 .n_cipher_suites = 8, 305 .ast_skid_limit = 0x10, 306 .num_wds_entries = 0x20, 307 .target_64bit = false, 308 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 309 .shadow_reg_support = false, 310 .rri_on_ddr = false, 311 .hw_filter_reset_required = true, 312 .fw_diag_ce_download = false, 313 .credit_size_workaround = false, 314 .tx_stats_over_pktlog = false, 315 .dynamic_sar_support = false, 316 }, 317 { 318 .id = QCA6174_HW_3_2_VERSION, 319 .dev_id = QCA6174_2_1_DEVICE_ID, 320 .bus = ATH10K_BUS_PCI, 321 .name = "qca6174 hw3.2", 322 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 323 .uart_pin = 6, 324 .otp_exe_param = 0, 325 .channel_counters_freq_hz = 88000, 326 .max_probe_resp_desc_thres = 0, 327 .cal_data_len = 8124, 328 .fw = { 329 /* uses same binaries as hw3.0 */ 330 .dir = QCA6174_HW_3_0_FW_DIR, 331 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 332 .board_size = QCA6174_BOARD_DATA_SZ, 333 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 334 }, 335 .rx_desc_ops = &qca988x_rx_desc_ops, 336 .hw_ops = &qca6174_ops, 337 .hw_clk = qca6174_clk, 338 .target_cpu_freq = 176000000, 339 .decap_align_bytes = 4, 340 .spectral_bin_discard = 0, 341 .spectral_bin_offset = 0, 342 .vht160_mcs_rx_highest = 0, 343 .vht160_mcs_tx_highest = 0, 344 .n_cipher_suites = 8, 345 .ast_skid_limit = 0x10, 346 .num_wds_entries = 0x20, 347 .target_64bit = false, 348 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 349 .shadow_reg_support = false, 350 .rri_on_ddr = false, 351 .hw_filter_reset_required = true, 352 .fw_diag_ce_download = true, 353 .credit_size_workaround = false, 354 .tx_stats_over_pktlog = false, 355 .supports_peer_stats_info = true, 356 .dynamic_sar_support = true, 357 }, 358 { 359 .id = QCA99X0_HW_2_0_DEV_VERSION, 360 .dev_id = QCA99X0_2_0_DEVICE_ID, 361 .bus = ATH10K_BUS_PCI, 362 .name = "qca99x0 hw2.0", 363 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, 364 .uart_pin = 7, 365 .otp_exe_param = 0x00000700, 366 .continuous_frag_desc = true, 367 .cck_rate_map_rev2 = true, 368 .channel_counters_freq_hz = 150000, 369 .max_probe_resp_desc_thres = 24, 370 .tx_chain_mask = 0xf, 371 .rx_chain_mask = 0xf, 372 .max_spatial_stream = 4, 373 .cal_data_len = 12064, 374 .fw = { 375 .dir = QCA99X0_HW_2_0_FW_DIR, 376 .board = QCA99X0_HW_2_0_BOARD_DATA_FILE, 377 .board_size = QCA99X0_BOARD_DATA_SZ, 378 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 379 }, 380 .sw_decrypt_mcast_mgmt = true, 381 .rx_desc_ops = &qca99x0_rx_desc_ops, 382 .hw_ops = &qca99x0_ops, 383 .decap_align_bytes = 1, 384 .spectral_bin_discard = 4, 385 .spectral_bin_offset = 0, 386 .vht160_mcs_rx_highest = 0, 387 .vht160_mcs_tx_highest = 0, 388 .n_cipher_suites = 11, 389 .ast_skid_limit = 0x10, 390 .num_wds_entries = 0x20, 391 .target_64bit = false, 392 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 393 .shadow_reg_support = false, 394 .rri_on_ddr = false, 395 .hw_filter_reset_required = true, 396 .fw_diag_ce_download = false, 397 .credit_size_workaround = false, 398 .tx_stats_over_pktlog = false, 399 .dynamic_sar_support = false, 400 }, 401 { 402 .id = QCA9984_HW_1_0_DEV_VERSION, 403 .dev_id = QCA9984_1_0_DEVICE_ID, 404 .bus = ATH10K_BUS_PCI, 405 .name = "qca9984/qca9994 hw1.0", 406 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR, 407 .uart_pin = 7, 408 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 409 .otp_exe_param = 0x00000700, 410 .continuous_frag_desc = true, 411 .cck_rate_map_rev2 = true, 412 .channel_counters_freq_hz = 150000, 413 .max_probe_resp_desc_thres = 24, 414 .tx_chain_mask = 0xf, 415 .rx_chain_mask = 0xf, 416 .max_spatial_stream = 4, 417 .cal_data_len = 12064, 418 .fw = { 419 .dir = QCA9984_HW_1_0_FW_DIR, 420 .board = QCA9984_HW_1_0_BOARD_DATA_FILE, 421 .eboard = QCA9984_HW_1_0_EBOARD_DATA_FILE, 422 .board_size = QCA99X0_BOARD_DATA_SZ, 423 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 424 .ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ, 425 }, 426 .sw_decrypt_mcast_mgmt = true, 427 .rx_desc_ops = &qca99x0_rx_desc_ops, 428 .hw_ops = &qca99x0_ops, 429 .decap_align_bytes = 1, 430 .spectral_bin_discard = 12, 431 .spectral_bin_offset = 8, 432 433 /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz 434 * or 2x2 160Mhz, long-guard-interval. 435 */ 436 .vht160_mcs_rx_highest = 1560, 437 .vht160_mcs_tx_highest = 1560, 438 .n_cipher_suites = 11, 439 .ast_skid_limit = 0x10, 440 .num_wds_entries = 0x20, 441 .target_64bit = false, 442 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 443 .shadow_reg_support = false, 444 .rri_on_ddr = false, 445 .hw_filter_reset_required = true, 446 .fw_diag_ce_download = false, 447 .credit_size_workaround = false, 448 .tx_stats_over_pktlog = false, 449 .dynamic_sar_support = false, 450 }, 451 { 452 .id = QCA9888_HW_2_0_DEV_VERSION, 453 .dev_id = QCA9888_2_0_DEVICE_ID, 454 .bus = ATH10K_BUS_PCI, 455 .name = "qca9888 hw2.0", 456 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR, 457 .uart_pin = 7, 458 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 459 .otp_exe_param = 0x00000700, 460 .continuous_frag_desc = true, 461 .channel_counters_freq_hz = 150000, 462 .max_probe_resp_desc_thres = 24, 463 .tx_chain_mask = 3, 464 .rx_chain_mask = 3, 465 .max_spatial_stream = 2, 466 .cal_data_len = 12064, 467 .fw = { 468 .dir = QCA9888_HW_2_0_FW_DIR, 469 .board = QCA9888_HW_2_0_BOARD_DATA_FILE, 470 .board_size = QCA99X0_BOARD_DATA_SZ, 471 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 472 }, 473 .sw_decrypt_mcast_mgmt = true, 474 .rx_desc_ops = &qca99x0_rx_desc_ops, 475 .hw_ops = &qca99x0_ops, 476 .decap_align_bytes = 1, 477 .spectral_bin_discard = 12, 478 .spectral_bin_offset = 8, 479 480 /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or 481 * 1x1 160Mhz, long-guard-interval. 482 */ 483 .vht160_mcs_rx_highest = 780, 484 .vht160_mcs_tx_highest = 780, 485 .n_cipher_suites = 11, 486 .ast_skid_limit = 0x10, 487 .num_wds_entries = 0x20, 488 .target_64bit = false, 489 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 490 .shadow_reg_support = false, 491 .rri_on_ddr = false, 492 .hw_filter_reset_required = true, 493 .fw_diag_ce_download = false, 494 .credit_size_workaround = false, 495 .tx_stats_over_pktlog = false, 496 .dynamic_sar_support = false, 497 }, 498 { 499 .id = QCA9377_HW_1_0_DEV_VERSION, 500 .dev_id = QCA9377_1_0_DEVICE_ID, 501 .bus = ATH10K_BUS_PCI, 502 .name = "qca9377 hw1.0", 503 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 504 .uart_pin = 6, 505 .otp_exe_param = 0, 506 .channel_counters_freq_hz = 88000, 507 .max_probe_resp_desc_thres = 0, 508 .cal_data_len = 8124, 509 .fw = { 510 .dir = QCA9377_HW_1_0_FW_DIR, 511 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 512 .board_size = QCA9377_BOARD_DATA_SZ, 513 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 514 }, 515 .rx_desc_ops = &qca988x_rx_desc_ops, 516 .hw_ops = &qca988x_ops, 517 .decap_align_bytes = 4, 518 .spectral_bin_discard = 0, 519 .spectral_bin_offset = 0, 520 .vht160_mcs_rx_highest = 0, 521 .vht160_mcs_tx_highest = 0, 522 .n_cipher_suites = 8, 523 .ast_skid_limit = 0x10, 524 .num_wds_entries = 0x20, 525 .target_64bit = false, 526 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 527 .shadow_reg_support = false, 528 .rri_on_ddr = false, 529 .hw_filter_reset_required = true, 530 .fw_diag_ce_download = false, 531 .credit_size_workaround = false, 532 .tx_stats_over_pktlog = false, 533 .dynamic_sar_support = false, 534 }, 535 { 536 .id = QCA9377_HW_1_1_DEV_VERSION, 537 .dev_id = QCA9377_1_0_DEVICE_ID, 538 .bus = ATH10K_BUS_PCI, 539 .name = "qca9377 hw1.1", 540 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 541 .uart_pin = 6, 542 .otp_exe_param = 0, 543 .channel_counters_freq_hz = 88000, 544 .max_probe_resp_desc_thres = 0, 545 .cal_data_len = 8124, 546 .fw = { 547 .dir = QCA9377_HW_1_0_FW_DIR, 548 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 549 .board_size = QCA9377_BOARD_DATA_SZ, 550 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 551 }, 552 .rx_desc_ops = &qca988x_rx_desc_ops, 553 .hw_ops = &qca6174_ops, 554 .hw_clk = qca6174_clk, 555 .target_cpu_freq = 176000000, 556 .decap_align_bytes = 4, 557 .spectral_bin_discard = 0, 558 .spectral_bin_offset = 0, 559 .vht160_mcs_rx_highest = 0, 560 .vht160_mcs_tx_highest = 0, 561 .n_cipher_suites = 8, 562 .ast_skid_limit = 0x10, 563 .num_wds_entries = 0x20, 564 .target_64bit = false, 565 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 566 .shadow_reg_support = false, 567 .rri_on_ddr = false, 568 .hw_filter_reset_required = true, 569 .fw_diag_ce_download = true, 570 .credit_size_workaround = false, 571 .tx_stats_over_pktlog = false, 572 .dynamic_sar_support = false, 573 }, 574 { 575 .id = QCA9377_HW_1_1_DEV_VERSION, 576 .dev_id = QCA9377_1_0_DEVICE_ID, 577 .bus = ATH10K_BUS_SDIO, 578 .name = "qca9377 hw1.1 sdio", 579 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 580 .uart_pin = 19, 581 .otp_exe_param = 0, 582 .channel_counters_freq_hz = 88000, 583 .max_probe_resp_desc_thres = 0, 584 .cal_data_len = 8124, 585 .fw = { 586 .dir = QCA9377_HW_1_0_FW_DIR, 587 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 588 .board_size = QCA9377_BOARD_DATA_SZ, 589 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 590 }, 591 .rx_desc_ops = &qca988x_rx_desc_ops, 592 .hw_ops = &qca6174_ops, 593 .hw_clk = qca6174_clk, 594 .target_cpu_freq = 176000000, 595 .decap_align_bytes = 4, 596 .n_cipher_suites = 8, 597 .num_peers = TARGET_QCA9377_HL_NUM_PEERS, 598 .ast_skid_limit = 0x10, 599 .num_wds_entries = 0x20, 600 .uart_pin_workaround = true, 601 .credit_size_workaround = true, 602 .dynamic_sar_support = false, 603 }, 604 { 605 .id = QCA4019_HW_1_0_DEV_VERSION, 606 .dev_id = 0, 607 .bus = ATH10K_BUS_AHB, 608 .name = "qca4019 hw1.0", 609 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR, 610 .uart_pin = 7, 611 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 612 .otp_exe_param = 0x0010000, 613 .continuous_frag_desc = true, 614 .cck_rate_map_rev2 = true, 615 .channel_counters_freq_hz = 125000, 616 .max_probe_resp_desc_thres = 24, 617 .tx_chain_mask = 0x3, 618 .rx_chain_mask = 0x3, 619 .max_spatial_stream = 2, 620 .cal_data_len = 12064, 621 .fw = { 622 .dir = QCA4019_HW_1_0_FW_DIR, 623 .board = QCA4019_HW_1_0_BOARD_DATA_FILE, 624 .board_size = QCA4019_BOARD_DATA_SZ, 625 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ, 626 }, 627 .sw_decrypt_mcast_mgmt = true, 628 .rx_desc_ops = &qca99x0_rx_desc_ops, 629 .hw_ops = &qca99x0_ops, 630 .decap_align_bytes = 1, 631 .spectral_bin_discard = 4, 632 .spectral_bin_offset = 0, 633 .vht160_mcs_rx_highest = 0, 634 .vht160_mcs_tx_highest = 0, 635 .n_cipher_suites = 11, 636 .ast_skid_limit = 0x10, 637 .num_wds_entries = 0x20, 638 .target_64bit = false, 639 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 640 .shadow_reg_support = false, 641 .rri_on_ddr = false, 642 .hw_filter_reset_required = true, 643 .fw_diag_ce_download = false, 644 .credit_size_workaround = false, 645 .tx_stats_over_pktlog = false, 646 .dynamic_sar_support = false, 647 }, 648 { 649 .id = WCN3990_HW_1_0_DEV_VERSION, 650 .dev_id = 0, 651 .bus = ATH10K_BUS_SNOC, 652 .name = "wcn3990 hw1.0", 653 .continuous_frag_desc = true, 654 .tx_chain_mask = 0x7, 655 .rx_chain_mask = 0x7, 656 .max_spatial_stream = 4, 657 .fw = { 658 .dir = WCN3990_HW_1_0_FW_DIR, 659 }, 660 .sw_decrypt_mcast_mgmt = true, 661 .rx_desc_ops = &wcn3990_rx_desc_ops, 662 .hw_ops = &wcn3990_ops, 663 .decap_align_bytes = 1, 664 .num_peers = TARGET_HL_TLV_NUM_PEERS, 665 .n_cipher_suites = 11, 666 .ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT, 667 .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES, 668 .target_64bit = true, 669 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC, 670 .shadow_reg_support = true, 671 .rri_on_ddr = true, 672 .hw_filter_reset_required = false, 673 .fw_diag_ce_download = false, 674 .credit_size_workaround = false, 675 .tx_stats_over_pktlog = false, 676 .dynamic_sar_support = true, 677 }, 678 }; 679 680 static const char *const ath10k_core_fw_feature_str[] = { 681 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx", 682 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x", 683 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx", 684 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p", 685 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2", 686 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps", 687 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan", 688 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp", 689 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad", 690 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init", 691 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode", 692 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca", 693 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp", 694 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl", 695 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param", 696 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war", 697 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast", 698 [ATH10K_FW_FEATURE_NO_PS] = "no-ps", 699 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference", 700 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi", 701 [ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel", 702 [ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate", 703 [ATH10K_FW_FEATURE_IRAM_RECOVERY] = "iram-recovery", 704 }; 705 706 static unsigned int ath10k_core_get_fw_feature_str(char *buf, 707 size_t buf_len, 708 enum ath10k_fw_features feat) 709 { 710 /* make sure that ath10k_core_fw_feature_str[] gets updated */ 711 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) != 712 ATH10K_FW_FEATURE_COUNT); 713 714 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) || 715 WARN_ON(!ath10k_core_fw_feature_str[feat])) { 716 return scnprintf(buf, buf_len, "bit%d", feat); 717 } 718 719 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]); 720 } 721 722 void ath10k_core_get_fw_features_str(struct ath10k *ar, 723 char *buf, 724 size_t buf_len) 725 { 726 size_t len = 0; 727 int i; 728 729 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 730 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) { 731 if (len > 0) 732 len += scnprintf(buf + len, buf_len - len, ","); 733 734 len += ath10k_core_get_fw_feature_str(buf + len, 735 buf_len - len, 736 i); 737 } 738 } 739 } 740 741 static void ath10k_send_suspend_complete(struct ath10k *ar) 742 { 743 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n"); 744 745 complete(&ar->target_suspend); 746 } 747 748 static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode) 749 { 750 bool mtu_workaround = ar->hw_params.credit_size_workaround; 751 int ret; 752 u32 param = 0; 753 754 ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256); 755 if (ret) 756 return ret; 757 758 ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99); 759 if (ret) 760 return ret; 761 762 ret = ath10k_bmi_read32(ar, hi_acs_flags, ¶m); 763 if (ret) 764 return ret; 765 766 param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET; 767 768 if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround) 769 param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 770 else 771 param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 772 773 if (mode == ATH10K_FIRMWARE_MODE_UTF) 774 param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 775 else 776 param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 777 778 ret = ath10k_bmi_write32(ar, hi_acs_flags, param); 779 if (ret) 780 return ret; 781 782 ret = ath10k_bmi_read32(ar, hi_option_flag2, ¶m); 783 if (ret) 784 return ret; 785 786 param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST; 787 788 ret = ath10k_bmi_write32(ar, hi_option_flag2, param); 789 if (ret) 790 return ret; 791 792 return 0; 793 } 794 795 static int ath10k_init_configure_target(struct ath10k *ar) 796 { 797 u32 param_host; 798 int ret; 799 800 /* tell target which HTC version it is used*/ 801 ret = ath10k_bmi_write32(ar, hi_app_host_interest, 802 HTC_PROTOCOL_VERSION); 803 if (ret) { 804 ath10k_err(ar, "settings HTC version failed\n"); 805 return ret; 806 } 807 808 /* set the firmware mode to STA/IBSS/AP */ 809 ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host); 810 if (ret) { 811 ath10k_err(ar, "setting firmware mode (1/2) failed\n"); 812 return ret; 813 } 814 815 /* TODO following parameters need to be re-visited. */ 816 /* num_device */ 817 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT); 818 /* Firmware mode */ 819 /* FIXME: Why FW_MODE_AP ??.*/ 820 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT); 821 /* mac_addr_method */ 822 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 823 /* firmware_bridge */ 824 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 825 /* fwsubmode */ 826 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT); 827 828 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host); 829 if (ret) { 830 ath10k_err(ar, "setting firmware mode (2/2) failed\n"); 831 return ret; 832 } 833 834 /* We do all byte-swapping on the host */ 835 ret = ath10k_bmi_write32(ar, hi_be, 0); 836 if (ret) { 837 ath10k_err(ar, "setting host CPU BE mode failed\n"); 838 return ret; 839 } 840 841 /* FW descriptor/Data swap flags */ 842 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0); 843 844 if (ret) { 845 ath10k_err(ar, "setting FW data/desc swap flags failed\n"); 846 return ret; 847 } 848 849 /* Some devices have a special sanity check that verifies the PCI 850 * Device ID is written to this host interest var. It is known to be 851 * required to boot QCA6164. 852 */ 853 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext, 854 ar->dev_id); 855 if (ret) { 856 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret); 857 return ret; 858 } 859 860 return 0; 861 } 862 863 static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, 864 const char *dir, 865 const char *file) 866 { 867 char filename[100]; 868 const struct firmware *fw; 869 int ret; 870 871 if (file == NULL) 872 return ERR_PTR(-ENOENT); 873 874 if (dir == NULL) 875 dir = "."; 876 877 snprintf(filename, sizeof(filename), "%s/%s", dir, file); 878 ret = firmware_request_nowarn(&fw, filename, ar->dev); 879 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", 880 filename, ret); 881 882 if (ret) 883 return ERR_PTR(ret); 884 885 return fw; 886 } 887 888 static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data, 889 size_t data_len) 890 { 891 u32 board_data_size = ar->hw_params.fw.board_size; 892 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size; 893 u32 board_ext_data_addr; 894 int ret; 895 896 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr); 897 if (ret) { 898 ath10k_err(ar, "could not read board ext data addr (%d)\n", 899 ret); 900 return ret; 901 } 902 903 ath10k_dbg(ar, ATH10K_DBG_BOOT, 904 "boot push board extended data addr 0x%x\n", 905 board_ext_data_addr); 906 907 if (board_ext_data_addr == 0) 908 return 0; 909 910 if (data_len != (board_data_size + board_ext_data_size)) { 911 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n", 912 data_len, board_data_size, board_ext_data_size); 913 return -EINVAL; 914 } 915 916 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr, 917 data + board_data_size, 918 board_ext_data_size); 919 if (ret) { 920 ath10k_err(ar, "could not write board ext data (%d)\n", ret); 921 return ret; 922 } 923 924 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config, 925 (board_ext_data_size << 16) | 1); 926 if (ret) { 927 ath10k_err(ar, "could not write board ext data bit (%d)\n", 928 ret); 929 return ret; 930 } 931 932 return 0; 933 } 934 935 static int ath10k_core_get_board_id_from_otp(struct ath10k *ar) 936 { 937 u32 result, address; 938 u8 board_id, chip_id; 939 bool ext_bid_support; 940 int ret, bmi_board_id_param; 941 942 address = ar->hw_params.patch_load_addr; 943 944 if (!ar->normal_mode_fw.fw_file.otp_data || 945 !ar->normal_mode_fw.fw_file.otp_len) { 946 ath10k_warn(ar, 947 "failed to retrieve board id because of invalid otp\n"); 948 return -ENODATA; 949 } 950 951 if (ar->id.bmi_ids_valid) { 952 ath10k_dbg(ar, ATH10K_DBG_BOOT, 953 "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n", 954 ar->id.bmi_board_id, ar->id.bmi_chip_id); 955 goto skip_otp_download; 956 } 957 958 ath10k_dbg(ar, ATH10K_DBG_BOOT, 959 "boot upload otp to 0x%x len %zd for board id\n", 960 address, ar->normal_mode_fw.fw_file.otp_len); 961 962 ret = ath10k_bmi_fast_download(ar, address, 963 ar->normal_mode_fw.fw_file.otp_data, 964 ar->normal_mode_fw.fw_file.otp_len); 965 if (ret) { 966 ath10k_err(ar, "could not write otp for board id check: %d\n", 967 ret); 968 return ret; 969 } 970 971 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 972 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 973 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 974 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID; 975 else 976 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID; 977 978 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result); 979 if (ret) { 980 ath10k_err(ar, "could not execute otp for board id check: %d\n", 981 ret); 982 return ret; 983 } 984 985 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP); 986 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP); 987 ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT); 988 989 ath10k_dbg(ar, ATH10K_DBG_BOOT, 990 "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n", 991 result, board_id, chip_id, ext_bid_support); 992 993 ar->id.ext_bid_supported = ext_bid_support; 994 995 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 || 996 (board_id == 0)) { 997 ath10k_dbg(ar, ATH10K_DBG_BOOT, 998 "board id does not exist in otp, ignore it\n"); 999 return -EOPNOTSUPP; 1000 } 1001 1002 ar->id.bmi_ids_valid = true; 1003 ar->id.bmi_board_id = board_id; 1004 ar->id.bmi_chip_id = chip_id; 1005 1006 skip_otp_download: 1007 1008 return 0; 1009 } 1010 1011 static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data) 1012 { 1013 struct ath10k *ar = data; 1014 const char *bdf_ext; 1015 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC; 1016 u8 bdf_enabled; 1017 int i; 1018 1019 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE) 1020 return; 1021 1022 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) { 1023 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1024 "wrong smbios bdf ext type length (%d).\n", 1025 hdr->length); 1026 return; 1027 } 1028 1029 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET); 1030 if (!bdf_enabled) { 1031 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n"); 1032 return; 1033 } 1034 1035 /* Only one string exists (per spec) */ 1036 bdf_ext = (char *)hdr + hdr->length; 1037 1038 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) { 1039 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1040 "bdf variant magic does not match.\n"); 1041 return; 1042 } 1043 1044 for (i = 0; i < strlen(bdf_ext); i++) { 1045 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) { 1046 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1047 "bdf variant name contains non ascii chars.\n"); 1048 return; 1049 } 1050 } 1051 1052 /* Copy extension name without magic suffix */ 1053 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic), 1054 sizeof(ar->id.bdf_ext)) < 0) { 1055 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1056 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1057 bdf_ext); 1058 return; 1059 } 1060 1061 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1062 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 1063 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext); 1064 } 1065 1066 static int ath10k_core_check_smbios(struct ath10k *ar) 1067 { 1068 ar->id.bdf_ext[0] = '\0'; 1069 dmi_walk(ath10k_core_check_bdfext, ar); 1070 1071 if (ar->id.bdf_ext[0] == '\0') 1072 return -ENODATA; 1073 1074 return 0; 1075 } 1076 1077 int ath10k_core_check_dt(struct ath10k *ar) 1078 { 1079 struct device_node *node; 1080 const char *variant = NULL; 1081 1082 node = ar->dev->of_node; 1083 if (!node) 1084 return -ENOENT; 1085 1086 of_property_read_string(node, "qcom,ath10k-calibration-variant", 1087 &variant); 1088 if (!variant) 1089 return -ENODATA; 1090 1091 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0) 1092 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1093 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1094 variant); 1095 1096 return 0; 1097 } 1098 EXPORT_SYMBOL(ath10k_core_check_dt); 1099 1100 static int ath10k_download_fw(struct ath10k *ar) 1101 { 1102 u32 address, data_len; 1103 const void *data; 1104 int ret; 1105 struct pm_qos_request latency_qos; 1106 1107 address = ar->hw_params.patch_load_addr; 1108 1109 data = ar->running_fw->fw_file.firmware_data; 1110 data_len = ar->running_fw->fw_file.firmware_len; 1111 1112 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file); 1113 if (ret) { 1114 ath10k_err(ar, "failed to configure fw code swap: %d\n", 1115 ret); 1116 return ret; 1117 } 1118 1119 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1120 "boot uploading firmware image %pK len %d\n", 1121 data, data_len); 1122 1123 /* Check if device supports to download firmware via 1124 * diag copy engine. Downloading firmware via diag CE 1125 * greatly reduces the time to download firmware. 1126 */ 1127 if (ar->hw_params.fw_diag_ce_download) { 1128 ret = ath10k_hw_diag_fast_download(ar, address, 1129 data, data_len); 1130 if (ret == 0) 1131 /* firmware upload via diag ce was successful */ 1132 return 0; 1133 1134 ath10k_warn(ar, 1135 "failed to upload firmware via diag ce, trying BMI: %d", 1136 ret); 1137 } 1138 1139 memset(&latency_qos, 0, sizeof(latency_qos)); 1140 cpu_latency_qos_add_request(&latency_qos, 0); 1141 1142 ret = ath10k_bmi_fast_download(ar, address, data, data_len); 1143 1144 cpu_latency_qos_remove_request(&latency_qos); 1145 1146 return ret; 1147 } 1148 1149 void ath10k_core_free_board_files(struct ath10k *ar) 1150 { 1151 if (!IS_ERR(ar->normal_mode_fw.board)) 1152 release_firmware(ar->normal_mode_fw.board); 1153 1154 if (!IS_ERR(ar->normal_mode_fw.ext_board)) 1155 release_firmware(ar->normal_mode_fw.ext_board); 1156 1157 ar->normal_mode_fw.board = NULL; 1158 ar->normal_mode_fw.board_data = NULL; 1159 ar->normal_mode_fw.board_len = 0; 1160 ar->normal_mode_fw.ext_board = NULL; 1161 ar->normal_mode_fw.ext_board_data = NULL; 1162 ar->normal_mode_fw.ext_board_len = 0; 1163 } 1164 EXPORT_SYMBOL(ath10k_core_free_board_files); 1165 1166 static void ath10k_core_free_firmware_files(struct ath10k *ar) 1167 { 1168 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware)) 1169 release_firmware(ar->normal_mode_fw.fw_file.firmware); 1170 1171 if (!IS_ERR(ar->cal_file)) 1172 release_firmware(ar->cal_file); 1173 1174 if (!IS_ERR(ar->pre_cal_file)) 1175 release_firmware(ar->pre_cal_file); 1176 1177 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file); 1178 1179 ar->normal_mode_fw.fw_file.otp_data = NULL; 1180 ar->normal_mode_fw.fw_file.otp_len = 0; 1181 1182 ar->normal_mode_fw.fw_file.firmware = NULL; 1183 ar->normal_mode_fw.fw_file.firmware_data = NULL; 1184 ar->normal_mode_fw.fw_file.firmware_len = 0; 1185 1186 ar->cal_file = NULL; 1187 ar->pre_cal_file = NULL; 1188 } 1189 1190 static int ath10k_fetch_cal_file(struct ath10k *ar) 1191 { 1192 char filename[100]; 1193 1194 /* pre-cal-<bus>-<id>.bin */ 1195 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", 1196 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1197 1198 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1199 if (!IS_ERR(ar->pre_cal_file)) 1200 goto success; 1201 1202 /* cal-<bus>-<id>.bin */ 1203 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", 1204 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1205 1206 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1207 if (IS_ERR(ar->cal_file)) 1208 /* calibration file is optional, don't print any warnings */ 1209 return PTR_ERR(ar->cal_file); 1210 success: 1211 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n", 1212 ATH10K_FW_DIR, filename); 1213 1214 return 0; 1215 } 1216 1217 static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type) 1218 { 1219 const struct firmware *fw; 1220 1221 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1222 if (!ar->hw_params.fw.board) { 1223 ath10k_err(ar, "failed to find board file fw entry\n"); 1224 return -EINVAL; 1225 } 1226 1227 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1228 ar->hw_params.fw.dir, 1229 ar->hw_params.fw.board); 1230 if (IS_ERR(ar->normal_mode_fw.board)) 1231 return PTR_ERR(ar->normal_mode_fw.board); 1232 1233 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data; 1234 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size; 1235 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1236 if (!ar->hw_params.fw.eboard) { 1237 ath10k_err(ar, "failed to find eboard file fw entry\n"); 1238 return -EINVAL; 1239 } 1240 1241 fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 1242 ar->hw_params.fw.eboard); 1243 ar->normal_mode_fw.ext_board = fw; 1244 if (IS_ERR(ar->normal_mode_fw.ext_board)) 1245 return PTR_ERR(ar->normal_mode_fw.ext_board); 1246 1247 ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data; 1248 ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size; 1249 } 1250 1251 return 0; 1252 } 1253 1254 static int ath10k_core_parse_bd_ie_board(struct ath10k *ar, 1255 const void *buf, size_t buf_len, 1256 const char *boardname, 1257 int bd_ie_type) 1258 { 1259 const struct ath10k_fw_ie *hdr; 1260 bool name_match_found; 1261 int ret, board_ie_id; 1262 size_t board_ie_len; 1263 const void *board_ie_data; 1264 1265 name_match_found = false; 1266 1267 /* go through ATH10K_BD_IE_BOARD_ elements */ 1268 while (buf_len > sizeof(struct ath10k_fw_ie)) { 1269 hdr = buf; 1270 board_ie_id = le32_to_cpu(hdr->id); 1271 board_ie_len = le32_to_cpu(hdr->len); 1272 board_ie_data = hdr->data; 1273 1274 buf_len -= sizeof(*hdr); 1275 buf += sizeof(*hdr); 1276 1277 if (buf_len < ALIGN(board_ie_len, 4)) { 1278 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n", 1279 buf_len, ALIGN(board_ie_len, 4)); 1280 ret = -EINVAL; 1281 goto out; 1282 } 1283 1284 switch (board_ie_id) { 1285 case ATH10K_BD_IE_BOARD_NAME: 1286 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "", 1287 board_ie_data, board_ie_len); 1288 1289 if (board_ie_len != strlen(boardname)) 1290 break; 1291 1292 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1293 if (ret) 1294 break; 1295 1296 name_match_found = true; 1297 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1298 "boot found match for name '%s'", 1299 boardname); 1300 break; 1301 case ATH10K_BD_IE_BOARD_DATA: 1302 if (!name_match_found) 1303 /* no match found */ 1304 break; 1305 1306 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1307 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1308 "boot found board data for '%s'", 1309 boardname); 1310 1311 ar->normal_mode_fw.board_data = board_ie_data; 1312 ar->normal_mode_fw.board_len = board_ie_len; 1313 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1314 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1315 "boot found eboard data for '%s'", 1316 boardname); 1317 1318 ar->normal_mode_fw.ext_board_data = board_ie_data; 1319 ar->normal_mode_fw.ext_board_len = board_ie_len; 1320 } 1321 1322 ret = 0; 1323 goto out; 1324 default: 1325 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n", 1326 board_ie_id); 1327 break; 1328 } 1329 1330 /* jump over the padding */ 1331 board_ie_len = ALIGN(board_ie_len, 4); 1332 1333 buf_len -= board_ie_len; 1334 buf += board_ie_len; 1335 } 1336 1337 /* no match found */ 1338 ret = -ENOENT; 1339 1340 out: 1341 return ret; 1342 } 1343 1344 static int ath10k_core_search_bd(struct ath10k *ar, 1345 const char *boardname, 1346 const u8 *data, 1347 size_t len) 1348 { 1349 size_t ie_len; 1350 struct ath10k_fw_ie *hdr; 1351 int ret = -ENOENT, ie_id; 1352 1353 while (len > sizeof(struct ath10k_fw_ie)) { 1354 hdr = (struct ath10k_fw_ie *)data; 1355 ie_id = le32_to_cpu(hdr->id); 1356 ie_len = le32_to_cpu(hdr->len); 1357 1358 len -= sizeof(*hdr); 1359 data = hdr->data; 1360 1361 if (len < ALIGN(ie_len, 4)) { 1362 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1363 ie_id, ie_len, len); 1364 return -EINVAL; 1365 } 1366 1367 switch (ie_id) { 1368 case ATH10K_BD_IE_BOARD: 1369 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1370 boardname, 1371 ATH10K_BD_IE_BOARD); 1372 if (ret == -ENOENT) 1373 /* no match found, continue */ 1374 break; 1375 1376 /* either found or error, so stop searching */ 1377 goto out; 1378 case ATH10K_BD_IE_BOARD_EXT: 1379 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1380 boardname, 1381 ATH10K_BD_IE_BOARD_EXT); 1382 if (ret == -ENOENT) 1383 /* no match found, continue */ 1384 break; 1385 1386 /* either found or error, so stop searching */ 1387 goto out; 1388 } 1389 1390 /* jump over the padding */ 1391 ie_len = ALIGN(ie_len, 4); 1392 1393 len -= ie_len; 1394 data += ie_len; 1395 } 1396 1397 out: 1398 /* return result of parse_bd_ie_board() or -ENOENT */ 1399 return ret; 1400 } 1401 1402 static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar, 1403 const char *boardname, 1404 const char *fallback_boardname1, 1405 const char *fallback_boardname2, 1406 const char *filename) 1407 { 1408 size_t len, magic_len; 1409 const u8 *data; 1410 int ret; 1411 1412 /* Skip if already fetched during board data download */ 1413 if (!ar->normal_mode_fw.board) 1414 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1415 ar->hw_params.fw.dir, 1416 filename); 1417 if (IS_ERR(ar->normal_mode_fw.board)) 1418 return PTR_ERR(ar->normal_mode_fw.board); 1419 1420 data = ar->normal_mode_fw.board->data; 1421 len = ar->normal_mode_fw.board->size; 1422 1423 /* magic has extra null byte padded */ 1424 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1; 1425 if (len < magic_len) { 1426 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n", 1427 ar->hw_params.fw.dir, filename, len); 1428 ret = -EINVAL; 1429 goto err; 1430 } 1431 1432 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) { 1433 ath10k_err(ar, "found invalid board magic\n"); 1434 ret = -EINVAL; 1435 goto err; 1436 } 1437 1438 /* magic is padded to 4 bytes */ 1439 magic_len = ALIGN(magic_len, 4); 1440 if (len < magic_len) { 1441 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n", 1442 ar->hw_params.fw.dir, filename, len); 1443 ret = -EINVAL; 1444 goto err; 1445 } 1446 1447 data += magic_len; 1448 len -= magic_len; 1449 1450 /* attempt to find boardname in the IE list */ 1451 ret = ath10k_core_search_bd(ar, boardname, data, len); 1452 1453 /* if we didn't find it and have a fallback name, try that */ 1454 if (ret == -ENOENT && fallback_boardname1) 1455 ret = ath10k_core_search_bd(ar, fallback_boardname1, data, len); 1456 1457 if (ret == -ENOENT && fallback_boardname2) 1458 ret = ath10k_core_search_bd(ar, fallback_boardname2, data, len); 1459 1460 if (ret == -ENOENT) { 1461 ath10k_err(ar, 1462 "failed to fetch board data for %s from %s/%s\n", 1463 boardname, ar->hw_params.fw.dir, filename); 1464 ret = -ENODATA; 1465 } 1466 1467 if (ret) 1468 goto err; 1469 1470 return 0; 1471 1472 err: 1473 ath10k_core_free_board_files(ar); 1474 return ret; 1475 } 1476 1477 static int ath10k_core_create_board_name(struct ath10k *ar, char *name, 1478 size_t name_len, bool with_variant, 1479 bool with_chip_id) 1480 { 1481 /* strlen(',variant=') + strlen(ar->id.bdf_ext) */ 1482 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 }; 1483 1484 if (with_variant && ar->id.bdf_ext[0] != '\0') 1485 scnprintf(variant, sizeof(variant), ",variant=%s", 1486 ar->id.bdf_ext); 1487 1488 if (ar->id.bmi_ids_valid) { 1489 scnprintf(name, name_len, 1490 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s", 1491 ath10k_bus_str(ar->hif.bus), 1492 ar->id.bmi_chip_id, 1493 ar->id.bmi_board_id, variant); 1494 goto out; 1495 } 1496 1497 if (ar->id.qmi_ids_valid) { 1498 if (with_chip_id) 1499 scnprintf(name, name_len, 1500 "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s", 1501 ath10k_bus_str(ar->hif.bus), 1502 ar->id.qmi_board_id, ar->id.qmi_chip_id, 1503 variant); 1504 else 1505 scnprintf(name, name_len, 1506 "bus=%s,qmi-board-id=%x", 1507 ath10k_bus_str(ar->hif.bus), 1508 ar->id.qmi_board_id); 1509 goto out; 1510 } 1511 1512 scnprintf(name, name_len, 1513 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s", 1514 ath10k_bus_str(ar->hif.bus), 1515 ar->id.vendor, ar->id.device, 1516 ar->id.subsystem_vendor, ar->id.subsystem_device, variant); 1517 out: 1518 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name); 1519 1520 return 0; 1521 } 1522 1523 static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name, 1524 size_t name_len) 1525 { 1526 if (ar->id.bmi_ids_valid) { 1527 scnprintf(name, name_len, 1528 "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d", 1529 ath10k_bus_str(ar->hif.bus), 1530 ar->id.bmi_chip_id, 1531 ar->id.bmi_eboard_id); 1532 1533 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name); 1534 return 0; 1535 } 1536 /* Fallback if returned board id is zero */ 1537 return -1; 1538 } 1539 1540 int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type) 1541 { 1542 char boardname[100], fallback_boardname1[100], fallback_boardname2[100]; 1543 int ret; 1544 1545 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1546 /* With variant and chip id */ 1547 ret = ath10k_core_create_board_name(ar, boardname, 1548 sizeof(boardname), true, 1549 true); 1550 if (ret) { 1551 ath10k_err(ar, "failed to create board name: %d", ret); 1552 return ret; 1553 } 1554 1555 /* Without variant and only chip-id */ 1556 ret = ath10k_core_create_board_name(ar, fallback_boardname1, 1557 sizeof(boardname), false, 1558 true); 1559 if (ret) { 1560 ath10k_err(ar, "failed to create 1st fallback board name: %d", 1561 ret); 1562 return ret; 1563 } 1564 1565 /* Without variant and without chip-id */ 1566 ret = ath10k_core_create_board_name(ar, fallback_boardname2, 1567 sizeof(boardname), false, 1568 false); 1569 if (ret) { 1570 ath10k_err(ar, "failed to create 2nd fallback board name: %d", 1571 ret); 1572 return ret; 1573 } 1574 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1575 ret = ath10k_core_create_eboard_name(ar, boardname, 1576 sizeof(boardname)); 1577 if (ret) { 1578 ath10k_err(ar, "fallback to eboard.bin since board id 0"); 1579 goto fallback; 1580 } 1581 } 1582 1583 ar->bd_api = 2; 1584 ret = ath10k_core_fetch_board_data_api_n(ar, boardname, 1585 fallback_boardname1, 1586 fallback_boardname2, 1587 ATH10K_BOARD_API2_FILE); 1588 if (!ret) 1589 goto success; 1590 1591 fallback: 1592 ar->bd_api = 1; 1593 ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type); 1594 if (ret) { 1595 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n", 1596 ar->hw_params.fw.dir); 1597 return ret; 1598 } 1599 1600 success: 1601 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api); 1602 return 0; 1603 } 1604 EXPORT_SYMBOL(ath10k_core_fetch_board_file); 1605 1606 static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar) 1607 { 1608 u32 result, address; 1609 u8 ext_board_id; 1610 int ret; 1611 1612 address = ar->hw_params.patch_load_addr; 1613 1614 if (!ar->normal_mode_fw.fw_file.otp_data || 1615 !ar->normal_mode_fw.fw_file.otp_len) { 1616 ath10k_warn(ar, 1617 "failed to retrieve extended board id due to otp binary missing\n"); 1618 return -ENODATA; 1619 } 1620 1621 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1622 "boot upload otp to 0x%x len %zd for ext board id\n", 1623 address, ar->normal_mode_fw.fw_file.otp_len); 1624 1625 ret = ath10k_bmi_fast_download(ar, address, 1626 ar->normal_mode_fw.fw_file.otp_data, 1627 ar->normal_mode_fw.fw_file.otp_len); 1628 if (ret) { 1629 ath10k_err(ar, "could not write otp for ext board id check: %d\n", 1630 ret); 1631 return ret; 1632 } 1633 1634 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result); 1635 if (ret) { 1636 ath10k_err(ar, "could not execute otp for ext board id check: %d\n", 1637 ret); 1638 return ret; 1639 } 1640 1641 if (!result) { 1642 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1643 "ext board id does not exist in otp, ignore it\n"); 1644 return -EOPNOTSUPP; 1645 } 1646 1647 ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK; 1648 1649 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1650 "boot get otp ext board id result 0x%08x ext_board_id %d\n", 1651 result, ext_board_id); 1652 1653 ar->id.bmi_eboard_id = ext_board_id; 1654 1655 return 0; 1656 } 1657 1658 static int ath10k_download_board_data(struct ath10k *ar, const void *data, 1659 size_t data_len) 1660 { 1661 u32 board_data_size = ar->hw_params.fw.board_size; 1662 u32 eboard_data_size = ar->hw_params.fw.ext_board_size; 1663 u32 board_address; 1664 u32 ext_board_address; 1665 int ret; 1666 1667 ret = ath10k_push_board_ext_data(ar, data, data_len); 1668 if (ret) { 1669 ath10k_err(ar, "could not push board ext data (%d)\n", ret); 1670 goto exit; 1671 } 1672 1673 ret = ath10k_bmi_read32(ar, hi_board_data, &board_address); 1674 if (ret) { 1675 ath10k_err(ar, "could not read board data addr (%d)\n", ret); 1676 goto exit; 1677 } 1678 1679 ret = ath10k_bmi_write_memory(ar, board_address, data, 1680 min_t(u32, board_data_size, 1681 data_len)); 1682 if (ret) { 1683 ath10k_err(ar, "could not write board data (%d)\n", ret); 1684 goto exit; 1685 } 1686 1687 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1); 1688 if (ret) { 1689 ath10k_err(ar, "could not write board data bit (%d)\n", ret); 1690 goto exit; 1691 } 1692 1693 if (!ar->id.ext_bid_supported) 1694 goto exit; 1695 1696 /* Extended board data download */ 1697 ret = ath10k_core_get_ext_board_id_from_otp(ar); 1698 if (ret == -EOPNOTSUPP) { 1699 /* Not fetching ext_board_data if ext board id is 0 */ 1700 ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n"); 1701 return 0; 1702 } else if (ret) { 1703 ath10k_err(ar, "failed to get extended board id: %d\n", ret); 1704 goto exit; 1705 } 1706 1707 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT); 1708 if (ret) 1709 goto exit; 1710 1711 if (ar->normal_mode_fw.ext_board_data) { 1712 ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET; 1713 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1714 "boot writing ext board data to addr 0x%x", 1715 ext_board_address); 1716 ret = ath10k_bmi_write_memory(ar, ext_board_address, 1717 ar->normal_mode_fw.ext_board_data, 1718 min_t(u32, eboard_data_size, data_len)); 1719 if (ret) 1720 ath10k_err(ar, "failed to write ext board data: %d\n", ret); 1721 } 1722 1723 exit: 1724 return ret; 1725 } 1726 1727 static int ath10k_download_and_run_otp(struct ath10k *ar) 1728 { 1729 u32 result, address = ar->hw_params.patch_load_addr; 1730 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param; 1731 int ret; 1732 1733 ret = ath10k_download_board_data(ar, 1734 ar->running_fw->board_data, 1735 ar->running_fw->board_len); 1736 if (ret) { 1737 ath10k_err(ar, "failed to download board data: %d\n", ret); 1738 return ret; 1739 } 1740 1741 /* OTP is optional */ 1742 1743 if (!ar->running_fw->fw_file.otp_data || 1744 !ar->running_fw->fw_file.otp_len) { 1745 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n", 1746 ar->running_fw->fw_file.otp_data, 1747 ar->running_fw->fw_file.otp_len); 1748 return 0; 1749 } 1750 1751 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n", 1752 address, ar->running_fw->fw_file.otp_len); 1753 1754 ret = ath10k_bmi_fast_download(ar, address, 1755 ar->running_fw->fw_file.otp_data, 1756 ar->running_fw->fw_file.otp_len); 1757 if (ret) { 1758 ath10k_err(ar, "could not write otp (%d)\n", ret); 1759 return ret; 1760 } 1761 1762 /* As of now pre-cal is valid for 10_4 variants */ 1763 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1764 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 1765 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 1766 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL; 1767 1768 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result); 1769 if (ret) { 1770 ath10k_err(ar, "could not execute otp (%d)\n", ret); 1771 return ret; 1772 } 1773 1774 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result); 1775 1776 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT, 1777 ar->running_fw->fw_file.fw_features)) && 1778 result != 0) { 1779 ath10k_err(ar, "otp calibration failed: %d", result); 1780 return -EINVAL; 1781 } 1782 1783 return 0; 1784 } 1785 1786 static int ath10k_download_cal_file(struct ath10k *ar, 1787 const struct firmware *file) 1788 { 1789 int ret; 1790 1791 if (!file) 1792 return -ENOENT; 1793 1794 if (IS_ERR(file)) 1795 return PTR_ERR(file); 1796 1797 ret = ath10k_download_board_data(ar, file->data, file->size); 1798 if (ret) { 1799 ath10k_err(ar, "failed to download cal_file data: %d\n", ret); 1800 return ret; 1801 } 1802 1803 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n"); 1804 1805 return 0; 1806 } 1807 1808 static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name) 1809 { 1810 struct device_node *node; 1811 int data_len; 1812 void *data; 1813 int ret; 1814 1815 node = ar->dev->of_node; 1816 if (!node) 1817 /* Device Tree is optional, don't print any warnings if 1818 * there's no node for ath10k. 1819 */ 1820 return -ENOENT; 1821 1822 if (!of_get_property(node, dt_name, &data_len)) { 1823 /* The calibration data node is optional */ 1824 return -ENOENT; 1825 } 1826 1827 if (data_len != ar->hw_params.cal_data_len) { 1828 ath10k_warn(ar, "invalid calibration data length in DT: %d\n", 1829 data_len); 1830 ret = -EMSGSIZE; 1831 goto out; 1832 } 1833 1834 data = kmalloc(data_len, GFP_KERNEL); 1835 if (!data) { 1836 ret = -ENOMEM; 1837 goto out; 1838 } 1839 1840 ret = of_property_read_u8_array(node, dt_name, data, data_len); 1841 if (ret) { 1842 ath10k_warn(ar, "failed to read calibration data from DT: %d\n", 1843 ret); 1844 goto out_free; 1845 } 1846 1847 ret = ath10k_download_board_data(ar, data, data_len); 1848 if (ret) { 1849 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n", 1850 ret); 1851 goto out_free; 1852 } 1853 1854 ret = 0; 1855 1856 out_free: 1857 kfree(data); 1858 1859 out: 1860 return ret; 1861 } 1862 1863 static int ath10k_download_cal_eeprom(struct ath10k *ar) 1864 { 1865 size_t data_len; 1866 void *data = NULL; 1867 int ret; 1868 1869 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len); 1870 if (ret) { 1871 if (ret != -EOPNOTSUPP) 1872 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n", 1873 ret); 1874 goto out_free; 1875 } 1876 1877 ret = ath10k_download_board_data(ar, data, data_len); 1878 if (ret) { 1879 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n", 1880 ret); 1881 goto out_free; 1882 } 1883 1884 ret = 0; 1885 1886 out_free: 1887 kfree(data); 1888 1889 return ret; 1890 } 1891 1892 static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name) 1893 { 1894 struct nvmem_cell *cell; 1895 void *buf; 1896 size_t len; 1897 int ret; 1898 1899 cell = devm_nvmem_cell_get(ar->dev, cell_name); 1900 if (IS_ERR(cell)) { 1901 ret = PTR_ERR(cell); 1902 return ret; 1903 } 1904 1905 buf = nvmem_cell_read(cell, &len); 1906 if (IS_ERR(buf)) 1907 return PTR_ERR(buf); 1908 1909 if (ar->hw_params.cal_data_len != len) { 1910 kfree(buf); 1911 ath10k_warn(ar, "invalid calibration data length in nvmem-cell '%s': %zu != %u\n", 1912 cell_name, len, ar->hw_params.cal_data_len); 1913 return -EMSGSIZE; 1914 } 1915 1916 ret = ath10k_download_board_data(ar, buf, len); 1917 kfree(buf); 1918 if (ret) 1919 ath10k_warn(ar, "failed to download calibration data from nvmem-cell '%s': %d\n", 1920 cell_name, ret); 1921 1922 return ret; 1923 } 1924 1925 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name, 1926 struct ath10k_fw_file *fw_file) 1927 { 1928 size_t magic_len, len, ie_len; 1929 int ie_id, i, index, bit, ret; 1930 struct ath10k_fw_ie *hdr; 1931 const u8 *data; 1932 __le32 *timestamp, *version; 1933 1934 /* first fetch the firmware file (firmware-*.bin) */ 1935 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 1936 name); 1937 if (IS_ERR(fw_file->firmware)) 1938 return PTR_ERR(fw_file->firmware); 1939 1940 data = fw_file->firmware->data; 1941 len = fw_file->firmware->size; 1942 1943 /* magic also includes the null byte, check that as well */ 1944 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; 1945 1946 if (len < magic_len) { 1947 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n", 1948 ar->hw_params.fw.dir, name, len); 1949 ret = -EINVAL; 1950 goto err; 1951 } 1952 1953 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) { 1954 ath10k_err(ar, "invalid firmware magic\n"); 1955 ret = -EINVAL; 1956 goto err; 1957 } 1958 1959 /* jump over the padding */ 1960 magic_len = ALIGN(magic_len, 4); 1961 1962 len -= magic_len; 1963 data += magic_len; 1964 1965 /* loop elements */ 1966 while (len > sizeof(struct ath10k_fw_ie)) { 1967 hdr = (struct ath10k_fw_ie *)data; 1968 1969 ie_id = le32_to_cpu(hdr->id); 1970 ie_len = le32_to_cpu(hdr->len); 1971 1972 len -= sizeof(*hdr); 1973 data += sizeof(*hdr); 1974 1975 if (len < ie_len) { 1976 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n", 1977 ie_id, len, ie_len); 1978 ret = -EINVAL; 1979 goto err; 1980 } 1981 1982 switch (ie_id) { 1983 case ATH10K_FW_IE_FW_VERSION: 1984 if (ie_len > sizeof(fw_file->fw_version) - 1) 1985 break; 1986 1987 memcpy(fw_file->fw_version, data, ie_len); 1988 fw_file->fw_version[ie_len] = '\0'; 1989 1990 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1991 "found fw version %s\n", 1992 fw_file->fw_version); 1993 break; 1994 case ATH10K_FW_IE_TIMESTAMP: 1995 if (ie_len != sizeof(u32)) 1996 break; 1997 1998 timestamp = (__le32 *)data; 1999 2000 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n", 2001 le32_to_cpup(timestamp)); 2002 break; 2003 case ATH10K_FW_IE_FEATURES: 2004 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2005 "found firmware features ie (%zd B)\n", 2006 ie_len); 2007 2008 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 2009 index = i / 8; 2010 bit = i % 8; 2011 2012 if (index == ie_len) 2013 break; 2014 2015 if (data[index] & (1 << bit)) { 2016 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2017 "Enabling feature bit: %i\n", 2018 i); 2019 __set_bit(i, fw_file->fw_features); 2020 } 2021 } 2022 2023 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "", 2024 fw_file->fw_features, 2025 sizeof(fw_file->fw_features)); 2026 break; 2027 case ATH10K_FW_IE_FW_IMAGE: 2028 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2029 "found fw image ie (%zd B)\n", 2030 ie_len); 2031 2032 fw_file->firmware_data = data; 2033 fw_file->firmware_len = ie_len; 2034 2035 break; 2036 case ATH10K_FW_IE_OTP_IMAGE: 2037 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2038 "found otp image ie (%zd B)\n", 2039 ie_len); 2040 2041 fw_file->otp_data = data; 2042 fw_file->otp_len = ie_len; 2043 2044 break; 2045 case ATH10K_FW_IE_WMI_OP_VERSION: 2046 if (ie_len != sizeof(u32)) 2047 break; 2048 2049 version = (__le32 *)data; 2050 2051 fw_file->wmi_op_version = le32_to_cpup(version); 2052 2053 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n", 2054 fw_file->wmi_op_version); 2055 break; 2056 case ATH10K_FW_IE_HTT_OP_VERSION: 2057 if (ie_len != sizeof(u32)) 2058 break; 2059 2060 version = (__le32 *)data; 2061 2062 fw_file->htt_op_version = le32_to_cpup(version); 2063 2064 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n", 2065 fw_file->htt_op_version); 2066 break; 2067 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE: 2068 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2069 "found fw code swap image ie (%zd B)\n", 2070 ie_len); 2071 fw_file->codeswap_data = data; 2072 fw_file->codeswap_len = ie_len; 2073 break; 2074 default: 2075 ath10k_warn(ar, "Unknown FW IE: %u\n", 2076 le32_to_cpu(hdr->id)); 2077 break; 2078 } 2079 2080 /* jump over the padding */ 2081 ie_len = ALIGN(ie_len, 4); 2082 2083 len -= ie_len; 2084 data += ie_len; 2085 } 2086 2087 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) && 2088 (!fw_file->firmware_data || !fw_file->firmware_len)) { 2089 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n", 2090 ar->hw_params.fw.dir, name); 2091 ret = -ENOMEDIUM; 2092 goto err; 2093 } 2094 2095 return 0; 2096 2097 err: 2098 ath10k_core_free_firmware_files(ar); 2099 return ret; 2100 } 2101 2102 static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name, 2103 size_t fw_name_len, int fw_api) 2104 { 2105 switch (ar->hif.bus) { 2106 case ATH10K_BUS_SDIO: 2107 case ATH10K_BUS_USB: 2108 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin", 2109 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus), 2110 fw_api); 2111 break; 2112 case ATH10K_BUS_PCI: 2113 case ATH10K_BUS_AHB: 2114 case ATH10K_BUS_SNOC: 2115 scnprintf(fw_name, fw_name_len, "%s-%d.bin", 2116 ATH10K_FW_FILE_BASE, fw_api); 2117 break; 2118 } 2119 } 2120 2121 static int ath10k_core_fetch_firmware_files(struct ath10k *ar) 2122 { 2123 int ret, i; 2124 char fw_name[100]; 2125 2126 /* calibration file is optional, don't check for any errors */ 2127 ath10k_fetch_cal_file(ar); 2128 2129 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) { 2130 ar->fw_api = i; 2131 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", 2132 ar->fw_api); 2133 2134 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api); 2135 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name, 2136 &ar->normal_mode_fw.fw_file); 2137 if (!ret) 2138 goto success; 2139 } 2140 2141 /* we end up here if we couldn't fetch any firmware */ 2142 2143 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d", 2144 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir, 2145 ret); 2146 2147 return ret; 2148 2149 success: 2150 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); 2151 2152 return 0; 2153 } 2154 2155 static int ath10k_core_pre_cal_download(struct ath10k *ar) 2156 { 2157 int ret; 2158 2159 ret = ath10k_download_cal_nvmem(ar, "pre-calibration"); 2160 if (ret == 0) { 2161 ar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM; 2162 goto success; 2163 } else if (ret == -EPROBE_DEFER) { 2164 return ret; 2165 } 2166 2167 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2168 "boot did not find a pre-calibration nvmem-cell, try file next: %d\n", 2169 ret); 2170 2171 ret = ath10k_download_cal_file(ar, ar->pre_cal_file); 2172 if (ret == 0) { 2173 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE; 2174 goto success; 2175 } 2176 2177 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2178 "boot did not find a pre calibration file, try DT next: %d\n", 2179 ret); 2180 2181 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data"); 2182 if (ret) { 2183 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2184 "unable to load pre cal data from DT: %d\n", ret); 2185 return ret; 2186 } 2187 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT; 2188 2189 success: 2190 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2191 ath10k_cal_mode_str(ar->cal_mode)); 2192 2193 return 0; 2194 } 2195 2196 static int ath10k_core_pre_cal_config(struct ath10k *ar) 2197 { 2198 int ret; 2199 2200 ret = ath10k_core_pre_cal_download(ar); 2201 if (ret) { 2202 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2203 "failed to load pre cal data: %d\n", ret); 2204 return ret; 2205 } 2206 2207 ret = ath10k_core_get_board_id_from_otp(ar); 2208 if (ret) { 2209 ath10k_err(ar, "failed to get board id: %d\n", ret); 2210 return ret; 2211 } 2212 2213 ret = ath10k_download_and_run_otp(ar); 2214 if (ret) { 2215 ath10k_err(ar, "failed to run otp: %d\n", ret); 2216 return ret; 2217 } 2218 2219 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2220 "pre cal configuration done successfully\n"); 2221 2222 return 0; 2223 } 2224 2225 static int ath10k_download_cal_data(struct ath10k *ar) 2226 { 2227 int ret; 2228 2229 ret = ath10k_core_pre_cal_config(ar); 2230 if (ret == 0) 2231 return 0; 2232 2233 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2234 "pre cal download procedure failed, try cal file: %d\n", 2235 ret); 2236 2237 ret = ath10k_download_cal_nvmem(ar, "calibration"); 2238 if (ret == 0) { 2239 ar->cal_mode = ATH10K_CAL_MODE_NVMEM; 2240 goto done; 2241 } else if (ret == -EPROBE_DEFER) { 2242 return ret; 2243 } 2244 2245 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2246 "boot did not find a calibration nvmem-cell, try file next: %d\n", 2247 ret); 2248 2249 ret = ath10k_download_cal_file(ar, ar->cal_file); 2250 if (ret == 0) { 2251 ar->cal_mode = ATH10K_CAL_MODE_FILE; 2252 goto done; 2253 } 2254 2255 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2256 "boot did not find a calibration file, try DT next: %d\n", 2257 ret); 2258 2259 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data"); 2260 if (ret == 0) { 2261 ar->cal_mode = ATH10K_CAL_MODE_DT; 2262 goto done; 2263 } 2264 2265 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2266 "boot did not find DT entry, try target EEPROM next: %d\n", 2267 ret); 2268 2269 ret = ath10k_download_cal_eeprom(ar); 2270 if (ret == 0) { 2271 ar->cal_mode = ATH10K_CAL_MODE_EEPROM; 2272 goto done; 2273 } 2274 2275 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2276 "boot did not find target EEPROM entry, try OTP next: %d\n", 2277 ret); 2278 2279 ret = ath10k_download_and_run_otp(ar); 2280 if (ret) { 2281 ath10k_err(ar, "failed to run otp: %d\n", ret); 2282 return ret; 2283 } 2284 2285 ar->cal_mode = ATH10K_CAL_MODE_OTP; 2286 2287 done: 2288 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2289 ath10k_cal_mode_str(ar->cal_mode)); 2290 return 0; 2291 } 2292 2293 static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar) 2294 { 2295 struct device_node *node; 2296 u8 coex_support = 0; 2297 int ret; 2298 2299 node = ar->dev->of_node; 2300 if (!node) 2301 goto out; 2302 2303 ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support); 2304 if (ret) { 2305 ar->coex_support = true; 2306 goto out; 2307 } 2308 2309 if (coex_support) { 2310 ar->coex_support = true; 2311 } else { 2312 ar->coex_support = false; 2313 ar->coex_gpio_pin = -1; 2314 goto out; 2315 } 2316 2317 ret = of_property_read_u32(node, "qcom,coexist-gpio-pin", 2318 &ar->coex_gpio_pin); 2319 if (ret) 2320 ar->coex_gpio_pin = -1; 2321 2322 out: 2323 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n", 2324 ar->coex_support, ar->coex_gpio_pin); 2325 } 2326 2327 static int ath10k_init_uart(struct ath10k *ar) 2328 { 2329 int ret; 2330 2331 /* 2332 * Explicitly setting UART prints to zero as target turns it on 2333 * based on scratch registers. 2334 */ 2335 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0); 2336 if (ret) { 2337 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret); 2338 return ret; 2339 } 2340 2341 if (!uart_print) { 2342 if (ar->hw_params.uart_pin_workaround) { 2343 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, 2344 ar->hw_params.uart_pin); 2345 if (ret) { 2346 ath10k_warn(ar, "failed to set UART TX pin: %d", 2347 ret); 2348 return ret; 2349 } 2350 } 2351 2352 return 0; 2353 } 2354 2355 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin); 2356 if (ret) { 2357 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2358 return ret; 2359 } 2360 2361 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1); 2362 if (ret) { 2363 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2364 return ret; 2365 } 2366 2367 /* Set the UART baud rate to 19200. */ 2368 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200); 2369 if (ret) { 2370 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret); 2371 return ret; 2372 } 2373 2374 ath10k_info(ar, "UART prints enabled\n"); 2375 return 0; 2376 } 2377 2378 static int ath10k_init_hw_params(struct ath10k *ar) 2379 { 2380 const struct ath10k_hw_params *hw_params; 2381 int i; 2382 2383 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { 2384 hw_params = &ath10k_hw_params_list[i]; 2385 2386 if (hw_params->bus == ar->hif.bus && 2387 hw_params->id == ar->target_version && 2388 hw_params->dev_id == ar->dev_id) 2389 break; 2390 } 2391 2392 if (i == ARRAY_SIZE(ath10k_hw_params_list)) { 2393 ath10k_err(ar, "Unsupported hardware version: 0x%x\n", 2394 ar->target_version); 2395 return -EINVAL; 2396 } 2397 2398 ar->hw_params = *hw_params; 2399 2400 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n", 2401 ar->hw_params.name, ar->target_version); 2402 2403 return 0; 2404 } 2405 2406 void ath10k_core_start_recovery(struct ath10k *ar) 2407 { 2408 if (test_and_set_bit(ATH10K_FLAG_RESTARTING, &ar->dev_flags)) { 2409 ath10k_warn(ar, "already restarting\n"); 2410 return; 2411 } 2412 2413 queue_work(ar->workqueue, &ar->restart_work); 2414 } 2415 EXPORT_SYMBOL(ath10k_core_start_recovery); 2416 2417 void ath10k_core_napi_enable(struct ath10k *ar) 2418 { 2419 lockdep_assert_held(&ar->conf_mutex); 2420 2421 if (test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2422 return; 2423 2424 napi_enable(&ar->napi); 2425 set_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2426 } 2427 EXPORT_SYMBOL(ath10k_core_napi_enable); 2428 2429 void ath10k_core_napi_sync_disable(struct ath10k *ar) 2430 { 2431 lockdep_assert_held(&ar->conf_mutex); 2432 2433 if (!test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2434 return; 2435 2436 napi_synchronize(&ar->napi); 2437 napi_disable(&ar->napi); 2438 clear_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2439 } 2440 EXPORT_SYMBOL(ath10k_core_napi_sync_disable); 2441 2442 static void ath10k_core_restart(struct work_struct *work) 2443 { 2444 struct ath10k *ar = container_of(work, struct ath10k, restart_work); 2445 int ret; 2446 2447 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2448 2449 /* Place a barrier to make sure the compiler doesn't reorder 2450 * CRASH_FLUSH and calling other functions. 2451 */ 2452 barrier(); 2453 2454 ieee80211_stop_queues(ar->hw); 2455 ath10k_drain_tx(ar); 2456 complete(&ar->scan.started); 2457 complete(&ar->scan.completed); 2458 complete(&ar->scan.on_channel); 2459 complete(&ar->offchan_tx_completed); 2460 complete(&ar->install_key_done); 2461 complete(&ar->vdev_setup_done); 2462 complete(&ar->vdev_delete_done); 2463 complete(&ar->thermal.wmi_sync); 2464 complete(&ar->bss_survey_done); 2465 wake_up(&ar->htt.empty_tx_wq); 2466 wake_up(&ar->wmi.tx_credits_wq); 2467 wake_up(&ar->peer_mapping_wq); 2468 2469 /* TODO: We can have one instance of cancelling coverage_class_work by 2470 * moving it to ath10k_halt(), so that both stop() and restart() would 2471 * call that but it takes conf_mutex() and if we call cancel_work_sync() 2472 * with conf_mutex it will deadlock. 2473 */ 2474 cancel_work_sync(&ar->set_coverage_class_work); 2475 2476 mutex_lock(&ar->conf_mutex); 2477 2478 switch (ar->state) { 2479 case ATH10K_STATE_ON: 2480 ar->state = ATH10K_STATE_RESTARTING; 2481 ath10k_halt(ar); 2482 ath10k_scan_finish(ar); 2483 ieee80211_restart_hw(ar->hw); 2484 break; 2485 case ATH10K_STATE_OFF: 2486 /* this can happen if driver is being unloaded 2487 * or if the crash happens during FW probing 2488 */ 2489 ath10k_warn(ar, "cannot restart a device that hasn't been started\n"); 2490 break; 2491 case ATH10K_STATE_RESTARTING: 2492 /* hw restart might be requested from multiple places */ 2493 break; 2494 case ATH10K_STATE_RESTARTED: 2495 ar->state = ATH10K_STATE_WEDGED; 2496 fallthrough; 2497 case ATH10K_STATE_WEDGED: 2498 ath10k_warn(ar, "device is wedged, will not restart\n"); 2499 break; 2500 case ATH10K_STATE_UTF: 2501 ath10k_warn(ar, "firmware restart in UTF mode not supported\n"); 2502 break; 2503 } 2504 2505 mutex_unlock(&ar->conf_mutex); 2506 2507 ret = ath10k_coredump_submit(ar); 2508 if (ret) 2509 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d", 2510 ret); 2511 2512 complete(&ar->driver_recovery); 2513 } 2514 2515 static void ath10k_core_set_coverage_class_work(struct work_struct *work) 2516 { 2517 struct ath10k *ar = container_of(work, struct ath10k, 2518 set_coverage_class_work); 2519 2520 if (ar->hw_params.hw_ops->set_coverage_class) 2521 ar->hw_params.hw_ops->set_coverage_class(ar, -1); 2522 } 2523 2524 static int ath10k_core_init_firmware_features(struct ath10k *ar) 2525 { 2526 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2527 int max_num_peers; 2528 2529 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) && 2530 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2531 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well"); 2532 return -EINVAL; 2533 } 2534 2535 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { 2536 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", 2537 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version); 2538 return -EINVAL; 2539 } 2540 2541 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 2542 switch (ath10k_cryptmode_param) { 2543 case ATH10K_CRYPT_MODE_HW: 2544 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2545 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2546 break; 2547 case ATH10K_CRYPT_MODE_SW: 2548 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2549 fw_file->fw_features)) { 2550 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware"); 2551 return -EINVAL; 2552 } 2553 2554 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2555 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2556 break; 2557 default: 2558 ath10k_info(ar, "invalid cryptmode: %d\n", 2559 ath10k_cryptmode_param); 2560 return -EINVAL; 2561 } 2562 2563 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT; 2564 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT; 2565 2566 if (rawmode) { 2567 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2568 fw_file->fw_features)) { 2569 ath10k_err(ar, "rawmode = 1 requires support from firmware"); 2570 return -EINVAL; 2571 } 2572 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2573 } 2574 2575 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 2576 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW; 2577 2578 /* Workaround: 2579 * 2580 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode 2581 * and causes enormous performance issues (malformed frames, 2582 * etc). 2583 * 2584 * Disabling A-MSDU makes RAW mode stable with heavy traffic 2585 * albeit a bit slower compared to regular operation. 2586 */ 2587 ar->htt.max_num_amsdu = 1; 2588 } 2589 2590 /* Backwards compatibility for firmwares without 2591 * ATH10K_FW_IE_WMI_OP_VERSION. 2592 */ 2593 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { 2594 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2595 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, 2596 fw_file->fw_features)) 2597 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2; 2598 else 2599 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1; 2600 } else { 2601 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; 2602 } 2603 } 2604 2605 switch (fw_file->wmi_op_version) { 2606 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2607 max_num_peers = TARGET_NUM_PEERS; 2608 ar->max_num_stations = TARGET_NUM_STATIONS; 2609 ar->max_num_vdevs = TARGET_NUM_VDEVS; 2610 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC; 2611 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | 2612 WMI_STAT_PEER; 2613 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2614 break; 2615 case ATH10K_FW_WMI_OP_VERSION_10_1: 2616 case ATH10K_FW_WMI_OP_VERSION_10_2: 2617 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2618 if (ath10k_peer_stats_enabled(ar)) { 2619 max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS; 2620 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS; 2621 } else { 2622 max_num_peers = TARGET_10X_NUM_PEERS; 2623 ar->max_num_stations = TARGET_10X_NUM_STATIONS; 2624 } 2625 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS; 2626 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC; 2627 ar->fw_stats_req_mask = WMI_STAT_PEER; 2628 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2629 break; 2630 case ATH10K_FW_WMI_OP_VERSION_TLV: 2631 max_num_peers = TARGET_TLV_NUM_PEERS; 2632 ar->max_num_stations = TARGET_TLV_NUM_STATIONS; 2633 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS; 2634 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS; 2635 if (ar->hif.bus == ATH10K_BUS_SDIO) 2636 ar->htt.max_num_pending_tx = 2637 TARGET_TLV_NUM_MSDU_DESC_HL; 2638 else 2639 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC; 2640 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS; 2641 ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV | 2642 WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD; 2643 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2644 ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC; 2645 break; 2646 case ATH10K_FW_WMI_OP_VERSION_10_4: 2647 max_num_peers = TARGET_10_4_NUM_PEERS; 2648 ar->max_num_stations = TARGET_10_4_NUM_STATIONS; 2649 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS; 2650 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS; 2651 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS; 2652 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER | 2653 WMI_10_4_STAT_PEER_EXTD | 2654 WMI_10_4_STAT_VDEV_EXTD; 2655 ar->max_spatial_stream = ar->hw_params.max_spatial_stream; 2656 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS; 2657 2658 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 2659 fw_file->fw_features)) 2660 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC; 2661 else 2662 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC; 2663 break; 2664 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2665 case ATH10K_FW_WMI_OP_VERSION_MAX: 2666 default: 2667 WARN_ON(1); 2668 return -EINVAL; 2669 } 2670 2671 if (ar->hw_params.num_peers) 2672 ar->max_num_peers = ar->hw_params.num_peers; 2673 else 2674 ar->max_num_peers = max_num_peers; 2675 2676 /* Backwards compatibility for firmwares without 2677 * ATH10K_FW_IE_HTT_OP_VERSION. 2678 */ 2679 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { 2680 switch (fw_file->wmi_op_version) { 2681 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2682 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; 2683 break; 2684 case ATH10K_FW_WMI_OP_VERSION_10_1: 2685 case ATH10K_FW_WMI_OP_VERSION_10_2: 2686 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2687 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1; 2688 break; 2689 case ATH10K_FW_WMI_OP_VERSION_TLV: 2690 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV; 2691 break; 2692 case ATH10K_FW_WMI_OP_VERSION_10_4: 2693 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2694 case ATH10K_FW_WMI_OP_VERSION_MAX: 2695 ath10k_err(ar, "htt op version not found from fw meta data"); 2696 return -EINVAL; 2697 } 2698 } 2699 2700 return 0; 2701 } 2702 2703 static int ath10k_core_reset_rx_filter(struct ath10k *ar) 2704 { 2705 int ret; 2706 int vdev_id; 2707 int vdev_type; 2708 int vdev_subtype; 2709 const u8 *vdev_addr; 2710 2711 vdev_id = 0; 2712 vdev_type = WMI_VDEV_TYPE_STA; 2713 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE); 2714 vdev_addr = ar->mac_addr; 2715 2716 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype, 2717 vdev_addr); 2718 if (ret) { 2719 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret); 2720 return ret; 2721 } 2722 2723 ret = ath10k_wmi_vdev_delete(ar, vdev_id); 2724 if (ret) { 2725 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret); 2726 return ret; 2727 } 2728 2729 /* WMI and HTT may use separate HIF pipes and are not guaranteed to be 2730 * serialized properly implicitly. 2731 * 2732 * Moreover (most) WMI commands have no explicit acknowledges. It is 2733 * possible to infer it implicitly by poking firmware with echo 2734 * command - getting a reply means all preceding comments have been 2735 * (mostly) processed. 2736 * 2737 * In case of vdev create/delete this is sufficient. 2738 * 2739 * Without this it's possible to end up with a race when HTT Rx ring is 2740 * started before vdev create/delete hack is complete allowing a short 2741 * window of opportunity to receive (and Tx ACK) a bunch of frames. 2742 */ 2743 ret = ath10k_wmi_barrier(ar); 2744 if (ret) { 2745 ath10k_err(ar, "failed to ping firmware: %d\n", ret); 2746 return ret; 2747 } 2748 2749 return 0; 2750 } 2751 2752 static int ath10k_core_compat_services(struct ath10k *ar) 2753 { 2754 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2755 2756 /* all 10.x firmware versions support thermal throttling but don't 2757 * advertise the support via service flags so we have to hardcode 2758 * it here 2759 */ 2760 switch (fw_file->wmi_op_version) { 2761 case ATH10K_FW_WMI_OP_VERSION_10_1: 2762 case ATH10K_FW_WMI_OP_VERSION_10_2: 2763 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2764 case ATH10K_FW_WMI_OP_VERSION_10_4: 2765 set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map); 2766 break; 2767 default: 2768 break; 2769 } 2770 2771 return 0; 2772 } 2773 2774 #define TGT_IRAM_READ_PER_ITR (8 * 1024) 2775 2776 static int ath10k_core_copy_target_iram(struct ath10k *ar) 2777 { 2778 const struct ath10k_hw_mem_layout *hw_mem; 2779 const struct ath10k_mem_region *tmp, *mem_region = NULL; 2780 dma_addr_t paddr; 2781 void *vaddr = NULL; 2782 u8 num_read_itr; 2783 int i, ret; 2784 u32 len, remaining_len; 2785 2786 /* copy target iram feature must work also when 2787 * ATH10K_FW_CRASH_DUMP_RAM_DATA is disabled, so 2788 * _ath10k_coredump_get_mem_layout() to accomplist that 2789 */ 2790 hw_mem = _ath10k_coredump_get_mem_layout(ar); 2791 if (!hw_mem) 2792 /* if CONFIG_DEV_COREDUMP is disabled we get NULL, then 2793 * just silently disable the feature by doing nothing 2794 */ 2795 return 0; 2796 2797 for (i = 0; i < hw_mem->region_table.size; i++) { 2798 tmp = &hw_mem->region_table.regions[i]; 2799 if (tmp->type == ATH10K_MEM_REGION_TYPE_REG) { 2800 mem_region = tmp; 2801 break; 2802 } 2803 } 2804 2805 if (!mem_region) 2806 return -ENOMEM; 2807 2808 for (i = 0; i < ar->wmi.num_mem_chunks; i++) { 2809 if (ar->wmi.mem_chunks[i].req_id == 2810 WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID) { 2811 vaddr = ar->wmi.mem_chunks[i].vaddr; 2812 len = ar->wmi.mem_chunks[i].len; 2813 break; 2814 } 2815 } 2816 2817 if (!vaddr || !len) { 2818 ath10k_warn(ar, "No allocated memory for IRAM back up"); 2819 return -ENOMEM; 2820 } 2821 2822 len = (len < mem_region->len) ? len : mem_region->len; 2823 paddr = mem_region->start; 2824 num_read_itr = len / TGT_IRAM_READ_PER_ITR; 2825 remaining_len = len % TGT_IRAM_READ_PER_ITR; 2826 for (i = 0; i < num_read_itr; i++) { 2827 ret = ath10k_hif_diag_read(ar, paddr, vaddr, 2828 TGT_IRAM_READ_PER_ITR); 2829 if (ret) { 2830 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2831 ret); 2832 return ret; 2833 } 2834 2835 paddr += TGT_IRAM_READ_PER_ITR; 2836 vaddr += TGT_IRAM_READ_PER_ITR; 2837 } 2838 2839 if (remaining_len) { 2840 ret = ath10k_hif_diag_read(ar, paddr, vaddr, remaining_len); 2841 if (ret) { 2842 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2843 ret); 2844 return ret; 2845 } 2846 } 2847 2848 ath10k_dbg(ar, ATH10K_DBG_BOOT, "target IRAM back up completed\n"); 2849 2850 return 0; 2851 } 2852 2853 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, 2854 const struct ath10k_fw_components *fw) 2855 { 2856 int status; 2857 u32 val; 2858 2859 lockdep_assert_held(&ar->conf_mutex); 2860 2861 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2862 2863 ar->running_fw = fw; 2864 2865 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2866 ar->running_fw->fw_file.fw_features)) { 2867 ath10k_bmi_start(ar); 2868 2869 /* Enable hardware clock to speed up firmware download */ 2870 if (ar->hw_params.hw_ops->enable_pll_clk) { 2871 status = ar->hw_params.hw_ops->enable_pll_clk(ar); 2872 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n", 2873 status); 2874 } 2875 2876 if (ath10k_init_configure_target(ar)) { 2877 status = -EINVAL; 2878 goto err; 2879 } 2880 2881 status = ath10k_download_cal_data(ar); 2882 if (status) 2883 goto err; 2884 2885 /* Some of qca988x solutions are having global reset issue 2886 * during target initialization. Bypassing PLL setting before 2887 * downloading firmware and letting the SoC run on REF_CLK is 2888 * fixing the problem. Corresponding firmware change is also 2889 * needed to set the clock source once the target is 2890 * initialized. 2891 */ 2892 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, 2893 ar->running_fw->fw_file.fw_features)) { 2894 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); 2895 if (status) { 2896 ath10k_err(ar, "could not write to skip_clock_init: %d\n", 2897 status); 2898 goto err; 2899 } 2900 } 2901 2902 status = ath10k_download_fw(ar); 2903 if (status) 2904 goto err; 2905 2906 status = ath10k_init_uart(ar); 2907 if (status) 2908 goto err; 2909 2910 if (ar->hif.bus == ATH10K_BUS_SDIO) { 2911 status = ath10k_init_sdio(ar, mode); 2912 if (status) { 2913 ath10k_err(ar, "failed to init SDIO: %d\n", status); 2914 goto err; 2915 } 2916 } 2917 } 2918 2919 ar->htc.htc_ops.target_send_suspend_complete = 2920 ath10k_send_suspend_complete; 2921 2922 status = ath10k_htc_init(ar); 2923 if (status) { 2924 ath10k_err(ar, "could not init HTC (%d)\n", status); 2925 goto err; 2926 } 2927 2928 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2929 ar->running_fw->fw_file.fw_features)) { 2930 status = ath10k_bmi_done(ar); 2931 if (status) 2932 goto err; 2933 } 2934 2935 status = ath10k_wmi_attach(ar); 2936 if (status) { 2937 ath10k_err(ar, "WMI attach failed: %d\n", status); 2938 goto err; 2939 } 2940 2941 status = ath10k_htt_init(ar); 2942 if (status) { 2943 ath10k_err(ar, "failed to init htt: %d\n", status); 2944 goto err_wmi_detach; 2945 } 2946 2947 status = ath10k_htt_tx_start(&ar->htt); 2948 if (status) { 2949 ath10k_err(ar, "failed to alloc htt tx: %d\n", status); 2950 goto err_wmi_detach; 2951 } 2952 2953 /* If firmware indicates Full Rx Reorder support it must be used in a 2954 * slightly different manner. Let HTT code know. 2955 */ 2956 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER, 2957 ar->wmi.svc_map)); 2958 2959 status = ath10k_htt_rx_alloc(&ar->htt); 2960 if (status) { 2961 ath10k_err(ar, "failed to alloc htt rx: %d\n", status); 2962 goto err_htt_tx_detach; 2963 } 2964 2965 status = ath10k_hif_start(ar); 2966 if (status) { 2967 ath10k_err(ar, "could not start HIF: %d\n", status); 2968 goto err_htt_rx_detach; 2969 } 2970 2971 status = ath10k_htc_wait_target(&ar->htc); 2972 if (status) { 2973 ath10k_err(ar, "failed to connect to HTC: %d\n", status); 2974 goto err_hif_stop; 2975 } 2976 2977 status = ath10k_hif_start_post(ar); 2978 if (status) { 2979 ath10k_err(ar, "failed to swap mailbox: %d\n", status); 2980 goto err_hif_stop; 2981 } 2982 2983 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 2984 status = ath10k_htt_connect(&ar->htt); 2985 if (status) { 2986 ath10k_err(ar, "failed to connect htt (%d)\n", status); 2987 goto err_hif_stop; 2988 } 2989 } 2990 2991 status = ath10k_wmi_connect(ar); 2992 if (status) { 2993 ath10k_err(ar, "could not connect wmi: %d\n", status); 2994 goto err_hif_stop; 2995 } 2996 2997 status = ath10k_htc_start(&ar->htc); 2998 if (status) { 2999 ath10k_err(ar, "failed to start htc: %d\n", status); 3000 goto err_hif_stop; 3001 } 3002 3003 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3004 status = ath10k_wmi_wait_for_service_ready(ar); 3005 if (status) { 3006 ath10k_warn(ar, "wmi service ready event not received"); 3007 goto err_hif_stop; 3008 } 3009 } 3010 3011 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n", 3012 ar->hw->wiphy->fw_version); 3013 3014 if (test_bit(ATH10K_FW_FEATURE_IRAM_RECOVERY, 3015 ar->running_fw->fw_file.fw_features)) { 3016 status = ath10k_core_copy_target_iram(ar); 3017 if (status) { 3018 ath10k_warn(ar, "failed to copy target iram contents: %d", 3019 status); 3020 goto err_hif_stop; 3021 } 3022 } 3023 3024 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) && 3025 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3026 val = 0; 3027 if (ath10k_peer_stats_enabled(ar)) 3028 val = WMI_10_4_PEER_STATS; 3029 3030 /* Enable vdev stats by default */ 3031 val |= WMI_10_4_VDEV_STATS; 3032 3033 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map)) 3034 val |= WMI_10_4_BSS_CHANNEL_INFO_64; 3035 3036 ath10k_core_fetch_btcoex_dt(ar); 3037 3038 /* 10.4 firmware supports BT-Coex without reloading firmware 3039 * via pdev param. To support Bluetooth coexistence pdev param, 3040 * WMI_COEX_GPIO_SUPPORT of extended resource config should be 3041 * enabled always. 3042 * 3043 * We can still enable BTCOEX if firmware has the support 3044 * eventhough btceox_support value is 3045 * ATH10K_DT_BTCOEX_NOT_FOUND 3046 */ 3047 3048 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) && 3049 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM, 3050 ar->running_fw->fw_file.fw_features) && 3051 ar->coex_support) 3052 val |= WMI_10_4_COEX_GPIO_SUPPORT; 3053 3054 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY, 3055 ar->wmi.svc_map)) 3056 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY; 3057 3058 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA, 3059 ar->wmi.svc_map)) 3060 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA; 3061 3062 if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI, 3063 ar->wmi.svc_map)) 3064 val |= WMI_10_4_TX_DATA_ACK_RSSI; 3065 3066 if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map)) 3067 val |= WMI_10_4_REPORT_AIRTIME; 3068 3069 if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT, 3070 ar->wmi.svc_map)) 3071 val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT; 3072 3073 status = ath10k_mac_ext_resource_config(ar, val); 3074 if (status) { 3075 ath10k_err(ar, 3076 "failed to send ext resource cfg command : %d\n", 3077 status); 3078 goto err_hif_stop; 3079 } 3080 } 3081 3082 status = ath10k_wmi_cmd_init(ar); 3083 if (status) { 3084 ath10k_err(ar, "could not send WMI init command (%d)\n", 3085 status); 3086 goto err_hif_stop; 3087 } 3088 3089 status = ath10k_wmi_wait_for_unified_ready(ar); 3090 if (status) { 3091 ath10k_err(ar, "wmi unified ready event not received\n"); 3092 goto err_hif_stop; 3093 } 3094 3095 status = ath10k_core_compat_services(ar); 3096 if (status) { 3097 ath10k_err(ar, "compat services failed: %d\n", status); 3098 goto err_hif_stop; 3099 } 3100 3101 status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr); 3102 if (status && status != -EOPNOTSUPP) { 3103 ath10k_err(ar, 3104 "failed to set base mac address: %d\n", status); 3105 goto err_hif_stop; 3106 } 3107 3108 /* Some firmware revisions do not properly set up hardware rx filter 3109 * registers. 3110 * 3111 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK 3112 * is filled with 0s instead of 1s allowing HW to respond with ACKs to 3113 * any frames that matches MAC_PCU_RX_FILTER which is also 3114 * misconfigured to accept anything. 3115 * 3116 * The ADDR1 is programmed using internal firmware structure field and 3117 * can't be (easily/sanely) reached from the driver explicitly. It is 3118 * possible to implicitly make it correct by creating a dummy vdev and 3119 * then deleting it. 3120 */ 3121 if (ar->hw_params.hw_filter_reset_required && 3122 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3123 status = ath10k_core_reset_rx_filter(ar); 3124 if (status) { 3125 ath10k_err(ar, 3126 "failed to reset rx filter: %d\n", status); 3127 goto err_hif_stop; 3128 } 3129 } 3130 3131 status = ath10k_htt_rx_ring_refill(ar); 3132 if (status) { 3133 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status); 3134 goto err_hif_stop; 3135 } 3136 3137 if (ar->max_num_vdevs >= 64) 3138 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL; 3139 else 3140 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1; 3141 3142 INIT_LIST_HEAD(&ar->arvifs); 3143 3144 /* we don't care about HTT in UTF mode */ 3145 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3146 status = ath10k_htt_setup(&ar->htt); 3147 if (status) { 3148 ath10k_err(ar, "failed to setup htt: %d\n", status); 3149 goto err_hif_stop; 3150 } 3151 } 3152 3153 status = ath10k_debug_start(ar); 3154 if (status) 3155 goto err_hif_stop; 3156 3157 status = ath10k_hif_set_target_log_mode(ar, fw_diag_log); 3158 if (status && status != -EOPNOTSUPP) { 3159 ath10k_warn(ar, "set target log mode failed: %d\n", status); 3160 goto err_hif_stop; 3161 } 3162 3163 return 0; 3164 3165 err_hif_stop: 3166 ath10k_hif_stop(ar); 3167 err_htt_rx_detach: 3168 ath10k_htt_rx_free(&ar->htt); 3169 err_htt_tx_detach: 3170 ath10k_htt_tx_free(&ar->htt); 3171 err_wmi_detach: 3172 ath10k_wmi_detach(ar); 3173 err: 3174 return status; 3175 } 3176 EXPORT_SYMBOL(ath10k_core_start); 3177 3178 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt) 3179 { 3180 int ret; 3181 unsigned long time_left; 3182 3183 reinit_completion(&ar->target_suspend); 3184 3185 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt); 3186 if (ret) { 3187 ath10k_warn(ar, "could not suspend target (%d)\n", ret); 3188 return ret; 3189 } 3190 3191 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ); 3192 3193 if (!time_left) { 3194 ath10k_warn(ar, "suspend timed out - target pause event never came\n"); 3195 return -ETIMEDOUT; 3196 } 3197 3198 return 0; 3199 } 3200 3201 void ath10k_core_stop(struct ath10k *ar) 3202 { 3203 lockdep_assert_held(&ar->conf_mutex); 3204 ath10k_debug_stop(ar); 3205 3206 /* try to suspend target */ 3207 if (ar->state != ATH10K_STATE_RESTARTING && 3208 ar->state != ATH10K_STATE_UTF) 3209 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); 3210 3211 ath10k_hif_stop(ar); 3212 ath10k_htt_tx_stop(&ar->htt); 3213 ath10k_htt_rx_free(&ar->htt); 3214 ath10k_wmi_detach(ar); 3215 3216 ar->id.bmi_ids_valid = false; 3217 } 3218 EXPORT_SYMBOL(ath10k_core_stop); 3219 3220 /* mac80211 manages fw/hw initialization through start/stop hooks. However in 3221 * order to know what hw capabilities should be advertised to mac80211 it is 3222 * necessary to load the firmware (and tear it down immediately since start 3223 * hook will try to init it again) before registering 3224 */ 3225 static int ath10k_core_probe_fw(struct ath10k *ar) 3226 { 3227 struct bmi_target_info target_info; 3228 int ret = 0; 3229 3230 ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL); 3231 if (ret) { 3232 ath10k_err(ar, "could not power on hif bus (%d)\n", ret); 3233 return ret; 3234 } 3235 3236 switch (ar->hif.bus) { 3237 case ATH10K_BUS_SDIO: 3238 memset(&target_info, 0, sizeof(target_info)); 3239 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info); 3240 if (ret) { 3241 ath10k_err(ar, "could not get target info (%d)\n", ret); 3242 goto err_power_down; 3243 } 3244 ar->target_version = target_info.version; 3245 ar->hw->wiphy->hw_version = target_info.version; 3246 break; 3247 case ATH10K_BUS_PCI: 3248 case ATH10K_BUS_AHB: 3249 case ATH10K_BUS_USB: 3250 memset(&target_info, 0, sizeof(target_info)); 3251 ret = ath10k_bmi_get_target_info(ar, &target_info); 3252 if (ret) { 3253 ath10k_err(ar, "could not get target info (%d)\n", ret); 3254 goto err_power_down; 3255 } 3256 ar->target_version = target_info.version; 3257 ar->hw->wiphy->hw_version = target_info.version; 3258 break; 3259 case ATH10K_BUS_SNOC: 3260 memset(&target_info, 0, sizeof(target_info)); 3261 ret = ath10k_hif_get_target_info(ar, &target_info); 3262 if (ret) { 3263 ath10k_err(ar, "could not get target info (%d)\n", ret); 3264 goto err_power_down; 3265 } 3266 ar->target_version = target_info.version; 3267 ar->hw->wiphy->hw_version = target_info.version; 3268 break; 3269 default: 3270 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus); 3271 } 3272 3273 ret = ath10k_init_hw_params(ar); 3274 if (ret) { 3275 ath10k_err(ar, "could not get hw params (%d)\n", ret); 3276 goto err_power_down; 3277 } 3278 3279 ret = ath10k_core_fetch_firmware_files(ar); 3280 if (ret) { 3281 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret); 3282 goto err_power_down; 3283 } 3284 3285 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) != 3286 sizeof(ar->normal_mode_fw.fw_file.fw_version)); 3287 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version, 3288 sizeof(ar->hw->wiphy->fw_version)); 3289 3290 ath10k_debug_print_hwfw_info(ar); 3291 3292 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3293 ar->normal_mode_fw.fw_file.fw_features)) { 3294 ret = ath10k_core_pre_cal_download(ar); 3295 if (ret) { 3296 /* pre calibration data download is not necessary 3297 * for all the chipsets. Ignore failures and continue. 3298 */ 3299 ath10k_dbg(ar, ATH10K_DBG_BOOT, 3300 "could not load pre cal data: %d\n", ret); 3301 } 3302 3303 ret = ath10k_core_get_board_id_from_otp(ar); 3304 if (ret && ret != -EOPNOTSUPP) { 3305 ath10k_err(ar, "failed to get board id from otp: %d\n", 3306 ret); 3307 goto err_free_firmware_files; 3308 } 3309 3310 ret = ath10k_core_check_smbios(ar); 3311 if (ret) 3312 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n"); 3313 3314 ret = ath10k_core_check_dt(ar); 3315 if (ret) 3316 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n"); 3317 3318 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD); 3319 if (ret) { 3320 ath10k_err(ar, "failed to fetch board file: %d\n", ret); 3321 goto err_free_firmware_files; 3322 } 3323 3324 ath10k_debug_print_board_info(ar); 3325 } 3326 3327 device_get_mac_address(ar->dev, ar->mac_addr); 3328 3329 ret = ath10k_core_init_firmware_features(ar); 3330 if (ret) { 3331 ath10k_err(ar, "fatal problem with firmware features: %d\n", 3332 ret); 3333 goto err_free_firmware_files; 3334 } 3335 3336 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3337 ar->normal_mode_fw.fw_file.fw_features)) { 3338 ret = ath10k_swap_code_seg_init(ar, 3339 &ar->normal_mode_fw.fw_file); 3340 if (ret) { 3341 ath10k_err(ar, "failed to initialize code swap segment: %d\n", 3342 ret); 3343 goto err_free_firmware_files; 3344 } 3345 } 3346 3347 mutex_lock(&ar->conf_mutex); 3348 3349 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, 3350 &ar->normal_mode_fw); 3351 if (ret) { 3352 ath10k_err(ar, "could not init core (%d)\n", ret); 3353 goto err_unlock; 3354 } 3355 3356 ath10k_debug_print_boot_info(ar); 3357 ath10k_core_stop(ar); 3358 3359 mutex_unlock(&ar->conf_mutex); 3360 3361 ath10k_hif_power_down(ar); 3362 return 0; 3363 3364 err_unlock: 3365 mutex_unlock(&ar->conf_mutex); 3366 3367 err_free_firmware_files: 3368 ath10k_core_free_firmware_files(ar); 3369 3370 err_power_down: 3371 ath10k_hif_power_down(ar); 3372 3373 return ret; 3374 } 3375 3376 static void ath10k_core_register_work(struct work_struct *work) 3377 { 3378 struct ath10k *ar = container_of(work, struct ath10k, register_work); 3379 int status; 3380 3381 /* peer stats are enabled by default */ 3382 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags); 3383 3384 status = ath10k_core_probe_fw(ar); 3385 if (status) { 3386 ath10k_err(ar, "could not probe fw (%d)\n", status); 3387 goto err; 3388 } 3389 3390 status = ath10k_mac_register(ar); 3391 if (status) { 3392 ath10k_err(ar, "could not register to mac80211 (%d)\n", status); 3393 goto err_release_fw; 3394 } 3395 3396 status = ath10k_coredump_register(ar); 3397 if (status) { 3398 ath10k_err(ar, "unable to register coredump\n"); 3399 goto err_unregister_mac; 3400 } 3401 3402 status = ath10k_debug_register(ar); 3403 if (status) { 3404 ath10k_err(ar, "unable to initialize debugfs\n"); 3405 goto err_unregister_coredump; 3406 } 3407 3408 status = ath10k_spectral_create(ar); 3409 if (status) { 3410 ath10k_err(ar, "failed to initialize spectral\n"); 3411 goto err_debug_destroy; 3412 } 3413 3414 status = ath10k_thermal_register(ar); 3415 if (status) { 3416 ath10k_err(ar, "could not register thermal device: %d\n", 3417 status); 3418 goto err_spectral_destroy; 3419 } 3420 3421 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags); 3422 return; 3423 3424 err_spectral_destroy: 3425 ath10k_spectral_destroy(ar); 3426 err_debug_destroy: 3427 ath10k_debug_destroy(ar); 3428 err_unregister_coredump: 3429 ath10k_coredump_unregister(ar); 3430 err_unregister_mac: 3431 ath10k_mac_unregister(ar); 3432 err_release_fw: 3433 ath10k_core_free_firmware_files(ar); 3434 err: 3435 /* TODO: It's probably a good idea to release device from the driver 3436 * but calling device_release_driver() here will cause a deadlock. 3437 */ 3438 return; 3439 } 3440 3441 int ath10k_core_register(struct ath10k *ar, 3442 const struct ath10k_bus_params *bus_params) 3443 { 3444 ar->bus_param = *bus_params; 3445 3446 queue_work(ar->workqueue, &ar->register_work); 3447 3448 return 0; 3449 } 3450 EXPORT_SYMBOL(ath10k_core_register); 3451 3452 void ath10k_core_unregister(struct ath10k *ar) 3453 { 3454 cancel_work_sync(&ar->register_work); 3455 3456 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) 3457 return; 3458 3459 ath10k_thermal_unregister(ar); 3460 /* Stop spectral before unregistering from mac80211 to remove the 3461 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree 3462 * would be already be free'd recursively, leading to a double free. 3463 */ 3464 ath10k_spectral_destroy(ar); 3465 3466 /* We must unregister from mac80211 before we stop HTC and HIF. 3467 * Otherwise we will fail to submit commands to FW and mac80211 will be 3468 * unhappy about callback failures. 3469 */ 3470 ath10k_mac_unregister(ar); 3471 3472 ath10k_testmode_destroy(ar); 3473 3474 ath10k_core_free_firmware_files(ar); 3475 ath10k_core_free_board_files(ar); 3476 3477 ath10k_debug_unregister(ar); 3478 } 3479 EXPORT_SYMBOL(ath10k_core_unregister); 3480 3481 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, 3482 enum ath10k_bus bus, 3483 enum ath10k_hw_rev hw_rev, 3484 const struct ath10k_hif_ops *hif_ops) 3485 { 3486 struct ath10k *ar; 3487 int ret; 3488 3489 ar = ath10k_mac_create(priv_size); 3490 if (!ar) 3491 return NULL; 3492 3493 ar->ath_common.priv = ar; 3494 ar->ath_common.hw = ar->hw; 3495 ar->dev = dev; 3496 ar->hw_rev = hw_rev; 3497 ar->hif.ops = hif_ops; 3498 ar->hif.bus = bus; 3499 3500 switch (hw_rev) { 3501 case ATH10K_HW_QCA988X: 3502 case ATH10K_HW_QCA9887: 3503 ar->regs = &qca988x_regs; 3504 ar->hw_ce_regs = &qcax_ce_regs; 3505 ar->hw_values = &qca988x_values; 3506 break; 3507 case ATH10K_HW_QCA6174: 3508 case ATH10K_HW_QCA9377: 3509 ar->regs = &qca6174_regs; 3510 ar->hw_ce_regs = &qcax_ce_regs; 3511 ar->hw_values = &qca6174_values; 3512 break; 3513 case ATH10K_HW_QCA99X0: 3514 case ATH10K_HW_QCA9984: 3515 ar->regs = &qca99x0_regs; 3516 ar->hw_ce_regs = &qcax_ce_regs; 3517 ar->hw_values = &qca99x0_values; 3518 break; 3519 case ATH10K_HW_QCA9888: 3520 ar->regs = &qca99x0_regs; 3521 ar->hw_ce_regs = &qcax_ce_regs; 3522 ar->hw_values = &qca9888_values; 3523 break; 3524 case ATH10K_HW_QCA4019: 3525 ar->regs = &qca4019_regs; 3526 ar->hw_ce_regs = &qcax_ce_regs; 3527 ar->hw_values = &qca4019_values; 3528 break; 3529 case ATH10K_HW_WCN3990: 3530 ar->regs = &wcn3990_regs; 3531 ar->hw_ce_regs = &wcn3990_ce_regs; 3532 ar->hw_values = &wcn3990_values; 3533 break; 3534 default: 3535 ath10k_err(ar, "unsupported core hardware revision %d\n", 3536 hw_rev); 3537 ret = -ENOTSUPP; 3538 goto err_free_mac; 3539 } 3540 3541 init_completion(&ar->scan.started); 3542 init_completion(&ar->scan.completed); 3543 init_completion(&ar->scan.on_channel); 3544 init_completion(&ar->target_suspend); 3545 init_completion(&ar->driver_recovery); 3546 init_completion(&ar->wow.wakeup_completed); 3547 3548 init_completion(&ar->install_key_done); 3549 init_completion(&ar->vdev_setup_done); 3550 init_completion(&ar->vdev_delete_done); 3551 init_completion(&ar->thermal.wmi_sync); 3552 init_completion(&ar->bss_survey_done); 3553 init_completion(&ar->peer_delete_done); 3554 init_completion(&ar->peer_stats_info_complete); 3555 3556 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work); 3557 3558 ar->workqueue = create_singlethread_workqueue("ath10k_wq"); 3559 if (!ar->workqueue) 3560 goto err_free_mac; 3561 3562 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq"); 3563 if (!ar->workqueue_aux) 3564 goto err_free_wq; 3565 3566 ar->workqueue_tx_complete = 3567 create_singlethread_workqueue("ath10k_tx_complete_wq"); 3568 if (!ar->workqueue_tx_complete) 3569 goto err_free_aux_wq; 3570 3571 mutex_init(&ar->conf_mutex); 3572 mutex_init(&ar->dump_mutex); 3573 spin_lock_init(&ar->data_lock); 3574 3575 INIT_LIST_HEAD(&ar->peers); 3576 init_waitqueue_head(&ar->peer_mapping_wq); 3577 init_waitqueue_head(&ar->htt.empty_tx_wq); 3578 init_waitqueue_head(&ar->wmi.tx_credits_wq); 3579 3580 skb_queue_head_init(&ar->htt.rx_indication_head); 3581 3582 init_completion(&ar->offchan_tx_completed); 3583 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work); 3584 skb_queue_head_init(&ar->offchan_tx_queue); 3585 3586 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work); 3587 skb_queue_head_init(&ar->wmi_mgmt_tx_queue); 3588 3589 INIT_WORK(&ar->register_work, ath10k_core_register_work); 3590 INIT_WORK(&ar->restart_work, ath10k_core_restart); 3591 INIT_WORK(&ar->set_coverage_class_work, 3592 ath10k_core_set_coverage_class_work); 3593 3594 init_dummy_netdev(&ar->napi_dev); 3595 3596 ret = ath10k_coredump_create(ar); 3597 if (ret) 3598 goto err_free_tx_complete; 3599 3600 ret = ath10k_debug_create(ar); 3601 if (ret) 3602 goto err_free_coredump; 3603 3604 return ar; 3605 3606 err_free_coredump: 3607 ath10k_coredump_destroy(ar); 3608 err_free_tx_complete: 3609 destroy_workqueue(ar->workqueue_tx_complete); 3610 err_free_aux_wq: 3611 destroy_workqueue(ar->workqueue_aux); 3612 err_free_wq: 3613 destroy_workqueue(ar->workqueue); 3614 err_free_mac: 3615 ath10k_mac_destroy(ar); 3616 3617 return NULL; 3618 } 3619 EXPORT_SYMBOL(ath10k_core_create); 3620 3621 void ath10k_core_destroy(struct ath10k *ar) 3622 { 3623 destroy_workqueue(ar->workqueue); 3624 3625 destroy_workqueue(ar->workqueue_aux); 3626 3627 destroy_workqueue(ar->workqueue_tx_complete); 3628 3629 ath10k_debug_destroy(ar); 3630 ath10k_coredump_destroy(ar); 3631 ath10k_htt_tx_destroy(&ar->htt); 3632 ath10k_wmi_free_host_mem(ar); 3633 ath10k_mac_destroy(ar); 3634 } 3635 EXPORT_SYMBOL(ath10k_core_destroy); 3636 3637 MODULE_AUTHOR("Qualcomm Atheros"); 3638 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards."); 3639 MODULE_LICENSE("Dual BSD/GPL"); 3640