1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 */ 6 7 #include <linux/etherdevice.h> 8 #include "htt.h" 9 #include "mac.h" 10 #include "hif.h" 11 #include "txrx.h" 12 #include "debug.h" 13 14 static u8 ath10k_htt_tx_txq_calc_size(size_t count) 15 { 16 int exp; 17 int factor; 18 19 exp = 0; 20 factor = count >> 7; 21 22 while (factor >= 64 && exp < 4) { 23 factor >>= 3; 24 exp++; 25 } 26 27 if (exp == 4) 28 return 0xff; 29 30 if (count > 0) 31 factor = max(1, factor); 32 33 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) | 34 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR); 35 } 36 37 static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 38 struct ieee80211_txq *txq) 39 { 40 struct ath10k *ar = hw->priv; 41 struct ath10k_sta *arsta; 42 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv; 43 unsigned long frame_cnt; 44 unsigned long byte_cnt; 45 int idx; 46 u32 bit; 47 u16 peer_id; 48 u8 tid; 49 u8 count; 50 51 lockdep_assert_held(&ar->htt.tx_lock); 52 53 if (!ar->htt.tx_q_state.enabled) 54 return; 55 56 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 57 return; 58 59 if (txq->sta) { 60 arsta = (void *)txq->sta->drv_priv; 61 peer_id = arsta->peer_id; 62 } else { 63 peer_id = arvif->peer_id; 64 } 65 66 tid = txq->tid; 67 bit = BIT(peer_id % 32); 68 idx = peer_id / 32; 69 70 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 71 count = ath10k_htt_tx_txq_calc_size(byte_cnt); 72 73 if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) || 74 unlikely(tid >= ar->htt.tx_q_state.num_tids)) { 75 ath10k_warn(ar, "refusing to update txq for peer_id %hu tid %hhu due to out of bounds\n", 76 peer_id, tid); 77 return; 78 } 79 80 ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count; 81 ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit; 82 ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0; 83 84 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %hu tid %hhu count %hhu\n", 85 peer_id, tid, count); 86 } 87 88 static void __ath10k_htt_tx_txq_sync(struct ath10k *ar) 89 { 90 u32 seq; 91 size_t size; 92 93 lockdep_assert_held(&ar->htt.tx_lock); 94 95 if (!ar->htt.tx_q_state.enabled) 96 return; 97 98 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 99 return; 100 101 seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq); 102 seq++; 103 ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq); 104 105 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n", 106 seq); 107 108 size = sizeof(*ar->htt.tx_q_state.vaddr); 109 dma_sync_single_for_device(ar->dev, 110 ar->htt.tx_q_state.paddr, 111 size, 112 DMA_TO_DEVICE); 113 } 114 115 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 116 struct ieee80211_txq *txq) 117 { 118 struct ath10k *ar = hw->priv; 119 120 spin_lock_bh(&ar->htt.tx_lock); 121 __ath10k_htt_tx_txq_recalc(hw, txq); 122 spin_unlock_bh(&ar->htt.tx_lock); 123 } 124 125 void ath10k_htt_tx_txq_sync(struct ath10k *ar) 126 { 127 spin_lock_bh(&ar->htt.tx_lock); 128 __ath10k_htt_tx_txq_sync(ar); 129 spin_unlock_bh(&ar->htt.tx_lock); 130 } 131 132 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 133 struct ieee80211_txq *txq) 134 { 135 struct ath10k *ar = hw->priv; 136 137 spin_lock_bh(&ar->htt.tx_lock); 138 __ath10k_htt_tx_txq_recalc(hw, txq); 139 __ath10k_htt_tx_txq_sync(ar); 140 spin_unlock_bh(&ar->htt.tx_lock); 141 } 142 143 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt) 144 { 145 lockdep_assert_held(&htt->tx_lock); 146 147 htt->num_pending_tx--; 148 if (htt->num_pending_tx == htt->max_num_pending_tx - 1) 149 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 150 } 151 152 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt) 153 { 154 lockdep_assert_held(&htt->tx_lock); 155 156 if (htt->num_pending_tx >= htt->max_num_pending_tx) 157 return -EBUSY; 158 159 htt->num_pending_tx++; 160 if (htt->num_pending_tx == htt->max_num_pending_tx) 161 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 162 163 return 0; 164 } 165 166 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 167 bool is_presp) 168 { 169 struct ath10k *ar = htt->ar; 170 171 lockdep_assert_held(&htt->tx_lock); 172 173 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres) 174 return 0; 175 176 if (is_presp && 177 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx) 178 return -EBUSY; 179 180 htt->num_pending_mgmt_tx++; 181 182 return 0; 183 } 184 185 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt) 186 { 187 lockdep_assert_held(&htt->tx_lock); 188 189 if (!htt->ar->hw_params.max_probe_resp_desc_thres) 190 return; 191 192 htt->num_pending_mgmt_tx--; 193 } 194 195 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb) 196 { 197 struct ath10k *ar = htt->ar; 198 int ret; 199 200 spin_lock_bh(&htt->tx_lock); 201 ret = idr_alloc(&htt->pending_tx, skb, 0, 202 htt->max_num_pending_tx, GFP_ATOMIC); 203 spin_unlock_bh(&htt->tx_lock); 204 205 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret); 206 207 return ret; 208 } 209 210 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id) 211 { 212 struct ath10k *ar = htt->ar; 213 214 lockdep_assert_held(&htt->tx_lock); 215 216 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id); 217 218 idr_remove(&htt->pending_tx, msdu_id); 219 } 220 221 static void ath10k_htt_tx_free_cont_txbuf_32(struct ath10k_htt *htt) 222 { 223 struct ath10k *ar = htt->ar; 224 size_t size; 225 226 if (!htt->txbuf.vaddr_txbuff_32) 227 return; 228 229 size = htt->txbuf.size; 230 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_32, 231 htt->txbuf.paddr); 232 htt->txbuf.vaddr_txbuff_32 = NULL; 233 } 234 235 static int ath10k_htt_tx_alloc_cont_txbuf_32(struct ath10k_htt *htt) 236 { 237 struct ath10k *ar = htt->ar; 238 size_t size; 239 240 size = htt->max_num_pending_tx * 241 sizeof(struct ath10k_htt_txbuf_32); 242 243 htt->txbuf.vaddr_txbuff_32 = dma_alloc_coherent(ar->dev, size, 244 &htt->txbuf.paddr, 245 GFP_KERNEL); 246 if (!htt->txbuf.vaddr_txbuff_32) 247 return -ENOMEM; 248 249 htt->txbuf.size = size; 250 251 return 0; 252 } 253 254 static void ath10k_htt_tx_free_cont_txbuf_64(struct ath10k_htt *htt) 255 { 256 struct ath10k *ar = htt->ar; 257 size_t size; 258 259 if (!htt->txbuf.vaddr_txbuff_64) 260 return; 261 262 size = htt->txbuf.size; 263 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_64, 264 htt->txbuf.paddr); 265 htt->txbuf.vaddr_txbuff_64 = NULL; 266 } 267 268 static int ath10k_htt_tx_alloc_cont_txbuf_64(struct ath10k_htt *htt) 269 { 270 struct ath10k *ar = htt->ar; 271 size_t size; 272 273 size = htt->max_num_pending_tx * 274 sizeof(struct ath10k_htt_txbuf_64); 275 276 htt->txbuf.vaddr_txbuff_64 = dma_alloc_coherent(ar->dev, size, 277 &htt->txbuf.paddr, 278 GFP_KERNEL); 279 if (!htt->txbuf.vaddr_txbuff_64) 280 return -ENOMEM; 281 282 htt->txbuf.size = size; 283 284 return 0; 285 } 286 287 static void ath10k_htt_tx_free_cont_frag_desc_32(struct ath10k_htt *htt) 288 { 289 size_t size; 290 291 if (!htt->frag_desc.vaddr_desc_32) 292 return; 293 294 size = htt->max_num_pending_tx * 295 sizeof(struct htt_msdu_ext_desc); 296 297 dma_free_coherent(htt->ar->dev, 298 size, 299 htt->frag_desc.vaddr_desc_32, 300 htt->frag_desc.paddr); 301 302 htt->frag_desc.vaddr_desc_32 = NULL; 303 } 304 305 static int ath10k_htt_tx_alloc_cont_frag_desc_32(struct ath10k_htt *htt) 306 { 307 struct ath10k *ar = htt->ar; 308 size_t size; 309 310 if (!ar->hw_params.continuous_frag_desc) 311 return 0; 312 313 size = htt->max_num_pending_tx * 314 sizeof(struct htt_msdu_ext_desc); 315 htt->frag_desc.vaddr_desc_32 = dma_alloc_coherent(ar->dev, size, 316 &htt->frag_desc.paddr, 317 GFP_KERNEL); 318 if (!htt->frag_desc.vaddr_desc_32) { 319 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 320 return -ENOMEM; 321 } 322 htt->frag_desc.size = size; 323 324 return 0; 325 } 326 327 static void ath10k_htt_tx_free_cont_frag_desc_64(struct ath10k_htt *htt) 328 { 329 size_t size; 330 331 if (!htt->frag_desc.vaddr_desc_64) 332 return; 333 334 size = htt->max_num_pending_tx * 335 sizeof(struct htt_msdu_ext_desc_64); 336 337 dma_free_coherent(htt->ar->dev, 338 size, 339 htt->frag_desc.vaddr_desc_64, 340 htt->frag_desc.paddr); 341 342 htt->frag_desc.vaddr_desc_64 = NULL; 343 } 344 345 static int ath10k_htt_tx_alloc_cont_frag_desc_64(struct ath10k_htt *htt) 346 { 347 struct ath10k *ar = htt->ar; 348 size_t size; 349 350 if (!ar->hw_params.continuous_frag_desc) 351 return 0; 352 353 size = htt->max_num_pending_tx * 354 sizeof(struct htt_msdu_ext_desc_64); 355 356 htt->frag_desc.vaddr_desc_64 = dma_alloc_coherent(ar->dev, size, 357 &htt->frag_desc.paddr, 358 GFP_KERNEL); 359 if (!htt->frag_desc.vaddr_desc_64) { 360 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 361 return -ENOMEM; 362 } 363 htt->frag_desc.size = size; 364 365 return 0; 366 } 367 368 static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt) 369 { 370 struct ath10k *ar = htt->ar; 371 size_t size; 372 373 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 374 ar->running_fw->fw_file.fw_features)) 375 return; 376 377 size = sizeof(*htt->tx_q_state.vaddr); 378 379 dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE); 380 kfree(htt->tx_q_state.vaddr); 381 } 382 383 static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt) 384 { 385 struct ath10k *ar = htt->ar; 386 size_t size; 387 int ret; 388 389 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 390 ar->running_fw->fw_file.fw_features)) 391 return 0; 392 393 htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS; 394 htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS; 395 htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES; 396 397 size = sizeof(*htt->tx_q_state.vaddr); 398 htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL); 399 if (!htt->tx_q_state.vaddr) 400 return -ENOMEM; 401 402 htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr, 403 size, DMA_TO_DEVICE); 404 ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr); 405 if (ret) { 406 ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret); 407 kfree(htt->tx_q_state.vaddr); 408 return -EIO; 409 } 410 411 return 0; 412 } 413 414 static void ath10k_htt_tx_free_txdone_fifo(struct ath10k_htt *htt) 415 { 416 WARN_ON(!kfifo_is_empty(&htt->txdone_fifo)); 417 kfifo_free(&htt->txdone_fifo); 418 } 419 420 static int ath10k_htt_tx_alloc_txdone_fifo(struct ath10k_htt *htt) 421 { 422 int ret; 423 size_t size; 424 425 size = roundup_pow_of_two(htt->max_num_pending_tx); 426 ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL); 427 return ret; 428 } 429 430 static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt) 431 { 432 struct ath10k *ar = htt->ar; 433 int ret; 434 435 ret = ath10k_htt_alloc_txbuff(htt); 436 if (ret) { 437 ath10k_err(ar, "failed to alloc cont tx buffer: %d\n", ret); 438 return ret; 439 } 440 441 ret = ath10k_htt_alloc_frag_desc(htt); 442 if (ret) { 443 ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret); 444 goto free_txbuf; 445 } 446 447 ret = ath10k_htt_tx_alloc_txq(htt); 448 if (ret) { 449 ath10k_err(ar, "failed to alloc txq: %d\n", ret); 450 goto free_frag_desc; 451 } 452 453 ret = ath10k_htt_tx_alloc_txdone_fifo(htt); 454 if (ret) { 455 ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret); 456 goto free_txq; 457 } 458 459 return 0; 460 461 free_txq: 462 ath10k_htt_tx_free_txq(htt); 463 464 free_frag_desc: 465 ath10k_htt_free_frag_desc(htt); 466 467 free_txbuf: 468 ath10k_htt_free_txbuff(htt); 469 470 return ret; 471 } 472 473 int ath10k_htt_tx_start(struct ath10k_htt *htt) 474 { 475 struct ath10k *ar = htt->ar; 476 int ret; 477 478 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n", 479 htt->max_num_pending_tx); 480 481 spin_lock_init(&htt->tx_lock); 482 idr_init(&htt->pending_tx); 483 484 if (htt->tx_mem_allocated) 485 return 0; 486 487 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) 488 return 0; 489 490 ret = ath10k_htt_tx_alloc_buf(htt); 491 if (ret) 492 goto free_idr_pending_tx; 493 494 htt->tx_mem_allocated = true; 495 496 return 0; 497 498 free_idr_pending_tx: 499 idr_destroy(&htt->pending_tx); 500 501 return ret; 502 } 503 504 static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx) 505 { 506 struct ath10k *ar = ctx; 507 struct ath10k_htt *htt = &ar->htt; 508 struct htt_tx_done tx_done = {0}; 509 510 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n", msdu_id); 511 512 tx_done.msdu_id = msdu_id; 513 tx_done.status = HTT_TX_COMPL_STATE_DISCARD; 514 515 ath10k_txrx_tx_unref(htt, &tx_done); 516 517 return 0; 518 } 519 520 void ath10k_htt_tx_destroy(struct ath10k_htt *htt) 521 { 522 if (!htt->tx_mem_allocated) 523 return; 524 525 ath10k_htt_free_txbuff(htt); 526 ath10k_htt_tx_free_txq(htt); 527 ath10k_htt_free_frag_desc(htt); 528 ath10k_htt_tx_free_txdone_fifo(htt); 529 htt->tx_mem_allocated = false; 530 } 531 532 void ath10k_htt_tx_stop(struct ath10k_htt *htt) 533 { 534 idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar); 535 idr_destroy(&htt->pending_tx); 536 } 537 538 void ath10k_htt_tx_free(struct ath10k_htt *htt) 539 { 540 ath10k_htt_tx_stop(htt); 541 ath10k_htt_tx_destroy(htt); 542 } 543 544 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb) 545 { 546 dev_kfree_skb_any(skb); 547 } 548 549 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb) 550 { 551 dev_kfree_skb_any(skb); 552 } 553 EXPORT_SYMBOL(ath10k_htt_hif_tx_complete); 554 555 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt) 556 { 557 struct ath10k *ar = htt->ar; 558 struct sk_buff *skb; 559 struct htt_cmd *cmd; 560 int len = 0; 561 int ret; 562 563 len += sizeof(cmd->hdr); 564 len += sizeof(cmd->ver_req); 565 566 skb = ath10k_htc_alloc_skb(ar, len); 567 if (!skb) 568 return -ENOMEM; 569 570 skb_put(skb, len); 571 cmd = (struct htt_cmd *)skb->data; 572 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ; 573 574 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 575 if (ret) { 576 dev_kfree_skb_any(skb); 577 return ret; 578 } 579 580 return 0; 581 } 582 583 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie) 584 { 585 struct ath10k *ar = htt->ar; 586 struct htt_stats_req *req; 587 struct sk_buff *skb; 588 struct htt_cmd *cmd; 589 int len = 0, ret; 590 591 len += sizeof(cmd->hdr); 592 len += sizeof(cmd->stats_req); 593 594 skb = ath10k_htc_alloc_skb(ar, len); 595 if (!skb) 596 return -ENOMEM; 597 598 skb_put(skb, len); 599 cmd = (struct htt_cmd *)skb->data; 600 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ; 601 602 req = &cmd->stats_req; 603 604 memset(req, 0, sizeof(*req)); 605 606 /* currently we support only max 8 bit masks so no need to worry 607 * about endian support 608 */ 609 req->upload_types[0] = mask; 610 req->reset_types[0] = mask; 611 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID; 612 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff); 613 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32); 614 615 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 616 if (ret) { 617 ath10k_warn(ar, "failed to send htt type stats request: %d", 618 ret); 619 dev_kfree_skb_any(skb); 620 return ret; 621 } 622 623 return 0; 624 } 625 626 static int ath10k_htt_send_frag_desc_bank_cfg_32(struct ath10k_htt *htt) 627 { 628 struct ath10k *ar = htt->ar; 629 struct sk_buff *skb; 630 struct htt_cmd *cmd; 631 struct htt_frag_desc_bank_cfg32 *cfg; 632 int ret, size; 633 u8 info; 634 635 if (!ar->hw_params.continuous_frag_desc) 636 return 0; 637 638 if (!htt->frag_desc.paddr) { 639 ath10k_warn(ar, "invalid frag desc memory\n"); 640 return -EINVAL; 641 } 642 643 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg32); 644 skb = ath10k_htc_alloc_skb(ar, size); 645 if (!skb) 646 return -ENOMEM; 647 648 skb_put(skb, size); 649 cmd = (struct htt_cmd *)skb->data; 650 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 651 652 info = 0; 653 info |= SM(htt->tx_q_state.type, 654 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 655 656 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 657 ar->running_fw->fw_file.fw_features)) 658 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 659 660 cfg = &cmd->frag_desc_bank_cfg32; 661 cfg->info = info; 662 cfg->num_banks = 1; 663 cfg->desc_size = sizeof(struct htt_msdu_ext_desc); 664 cfg->bank_base_addrs[0] = __cpu_to_le32(htt->frag_desc.paddr); 665 cfg->bank_id[0].bank_min_id = 0; 666 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 667 1); 668 669 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 670 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 671 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 672 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 673 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 674 675 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 676 677 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 678 if (ret) { 679 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 680 ret); 681 dev_kfree_skb_any(skb); 682 return ret; 683 } 684 685 return 0; 686 } 687 688 static int ath10k_htt_send_frag_desc_bank_cfg_64(struct ath10k_htt *htt) 689 { 690 struct ath10k *ar = htt->ar; 691 struct sk_buff *skb; 692 struct htt_cmd *cmd; 693 struct htt_frag_desc_bank_cfg64 *cfg; 694 int ret, size; 695 u8 info; 696 697 if (!ar->hw_params.continuous_frag_desc) 698 return 0; 699 700 if (!htt->frag_desc.paddr) { 701 ath10k_warn(ar, "invalid frag desc memory\n"); 702 return -EINVAL; 703 } 704 705 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg64); 706 skb = ath10k_htc_alloc_skb(ar, size); 707 if (!skb) 708 return -ENOMEM; 709 710 skb_put(skb, size); 711 cmd = (struct htt_cmd *)skb->data; 712 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 713 714 info = 0; 715 info |= SM(htt->tx_q_state.type, 716 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 717 718 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 719 ar->running_fw->fw_file.fw_features)) 720 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 721 722 cfg = &cmd->frag_desc_bank_cfg64; 723 cfg->info = info; 724 cfg->num_banks = 1; 725 cfg->desc_size = sizeof(struct htt_msdu_ext_desc_64); 726 cfg->bank_base_addrs[0] = __cpu_to_le64(htt->frag_desc.paddr); 727 cfg->bank_id[0].bank_min_id = 0; 728 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 729 1); 730 731 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 732 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 733 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 734 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 735 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 736 737 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 738 739 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 740 if (ret) { 741 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 742 ret); 743 dev_kfree_skb_any(skb); 744 return ret; 745 } 746 747 return 0; 748 } 749 750 static void ath10k_htt_fill_rx_desc_offset_32(void *rx_ring) 751 { 752 struct htt_rx_ring_setup_ring32 *ring = 753 (struct htt_rx_ring_setup_ring32 *)rx_ring; 754 755 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4) 756 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status)); 757 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload)); 758 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start)); 759 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end)); 760 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start)); 761 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end)); 762 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start)); 763 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end)); 764 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention)); 765 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info)); 766 #undef desc_offset 767 } 768 769 static void ath10k_htt_fill_rx_desc_offset_64(void *rx_ring) 770 { 771 struct htt_rx_ring_setup_ring64 *ring = 772 (struct htt_rx_ring_setup_ring64 *)rx_ring; 773 774 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4) 775 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status)); 776 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload)); 777 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start)); 778 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end)); 779 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start)); 780 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end)); 781 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start)); 782 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end)); 783 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention)); 784 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info)); 785 #undef desc_offset 786 } 787 788 static int ath10k_htt_send_rx_ring_cfg_32(struct ath10k_htt *htt) 789 { 790 struct ath10k *ar = htt->ar; 791 struct sk_buff *skb; 792 struct htt_cmd *cmd; 793 struct htt_rx_ring_setup_ring32 *ring; 794 const int num_rx_ring = 1; 795 u16 flags; 796 u32 fw_idx; 797 int len; 798 int ret; 799 800 /* 801 * the HW expects the buffer to be an integral number of 4-byte 802 * "words" 803 */ 804 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 805 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 806 807 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr) 808 + (sizeof(*ring) * num_rx_ring); 809 skb = ath10k_htc_alloc_skb(ar, len); 810 if (!skb) 811 return -ENOMEM; 812 813 skb_put(skb, len); 814 815 cmd = (struct htt_cmd *)skb->data; 816 ring = &cmd->rx_setup_32.rings[0]; 817 818 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 819 cmd->rx_setup_32.hdr.num_rings = 1; 820 821 /* FIXME: do we need all of this? */ 822 flags = 0; 823 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 824 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 825 flags |= HTT_RX_RING_FLAGS_PPDU_START; 826 flags |= HTT_RX_RING_FLAGS_PPDU_END; 827 flags |= HTT_RX_RING_FLAGS_MPDU_START; 828 flags |= HTT_RX_RING_FLAGS_MPDU_END; 829 flags |= HTT_RX_RING_FLAGS_MSDU_START; 830 flags |= HTT_RX_RING_FLAGS_MSDU_END; 831 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 832 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 833 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 834 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 835 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 836 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 837 flags |= HTT_RX_RING_FLAGS_NULL_RX; 838 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 839 840 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 841 842 ring->fw_idx_shadow_reg_paddr = 843 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr); 844 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr); 845 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 846 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 847 ring->flags = __cpu_to_le16(flags); 848 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 849 850 ath10k_htt_fill_rx_desc_offset_32(ring); 851 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 852 if (ret) { 853 dev_kfree_skb_any(skb); 854 return ret; 855 } 856 857 return 0; 858 } 859 860 static int ath10k_htt_send_rx_ring_cfg_64(struct ath10k_htt *htt) 861 { 862 struct ath10k *ar = htt->ar; 863 struct sk_buff *skb; 864 struct htt_cmd *cmd; 865 struct htt_rx_ring_setup_ring64 *ring; 866 const int num_rx_ring = 1; 867 u16 flags; 868 u32 fw_idx; 869 int len; 870 int ret; 871 872 /* HW expects the buffer to be an integral number of 4-byte 873 * "words" 874 */ 875 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 876 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 877 878 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_64.hdr) 879 + (sizeof(*ring) * num_rx_ring); 880 skb = ath10k_htc_alloc_skb(ar, len); 881 if (!skb) 882 return -ENOMEM; 883 884 skb_put(skb, len); 885 886 cmd = (struct htt_cmd *)skb->data; 887 ring = &cmd->rx_setup_64.rings[0]; 888 889 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 890 cmd->rx_setup_64.hdr.num_rings = 1; 891 892 flags = 0; 893 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 894 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 895 flags |= HTT_RX_RING_FLAGS_PPDU_START; 896 flags |= HTT_RX_RING_FLAGS_PPDU_END; 897 flags |= HTT_RX_RING_FLAGS_MPDU_START; 898 flags |= HTT_RX_RING_FLAGS_MPDU_END; 899 flags |= HTT_RX_RING_FLAGS_MSDU_START; 900 flags |= HTT_RX_RING_FLAGS_MSDU_END; 901 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 902 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 903 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 904 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 905 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 906 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 907 flags |= HTT_RX_RING_FLAGS_NULL_RX; 908 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 909 910 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 911 912 ring->fw_idx_shadow_reg_paddr = __cpu_to_le64(htt->rx_ring.alloc_idx.paddr); 913 ring->rx_ring_base_paddr = __cpu_to_le64(htt->rx_ring.base_paddr); 914 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 915 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 916 ring->flags = __cpu_to_le16(flags); 917 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 918 919 ath10k_htt_fill_rx_desc_offset_64(ring); 920 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 921 if (ret) { 922 dev_kfree_skb_any(skb); 923 return ret; 924 } 925 926 return 0; 927 } 928 929 static int ath10k_htt_send_rx_ring_cfg_hl(struct ath10k_htt *htt) 930 { 931 struct ath10k *ar = htt->ar; 932 struct sk_buff *skb; 933 struct htt_cmd *cmd; 934 struct htt_rx_ring_setup_ring32 *ring; 935 const int num_rx_ring = 1; 936 u16 flags; 937 int len; 938 int ret; 939 940 /* 941 * the HW expects the buffer to be an integral number of 4-byte 942 * "words" 943 */ 944 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 945 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 946 947 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr) 948 + (sizeof(*ring) * num_rx_ring); 949 skb = ath10k_htc_alloc_skb(ar, len); 950 if (!skb) 951 return -ENOMEM; 952 953 skb_put(skb, len); 954 955 cmd = (struct htt_cmd *)skb->data; 956 ring = &cmd->rx_setup_32.rings[0]; 957 958 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 959 cmd->rx_setup_32.hdr.num_rings = 1; 960 961 flags = 0; 962 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 963 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 964 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 965 966 memset(ring, 0, sizeof(*ring)); 967 ring->rx_ring_len = __cpu_to_le16(HTT_RX_RING_SIZE_MIN); 968 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 969 ring->flags = __cpu_to_le16(flags); 970 971 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 972 if (ret) { 973 dev_kfree_skb_any(skb); 974 return ret; 975 } 976 977 return 0; 978 } 979 980 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 981 u8 max_subfrms_ampdu, 982 u8 max_subfrms_amsdu) 983 { 984 struct ath10k *ar = htt->ar; 985 struct htt_aggr_conf *aggr_conf; 986 struct sk_buff *skb; 987 struct htt_cmd *cmd; 988 int len; 989 int ret; 990 991 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 992 993 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 994 return -EINVAL; 995 996 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 997 return -EINVAL; 998 999 len = sizeof(cmd->hdr); 1000 len += sizeof(cmd->aggr_conf); 1001 1002 skb = ath10k_htc_alloc_skb(ar, len); 1003 if (!skb) 1004 return -ENOMEM; 1005 1006 skb_put(skb, len); 1007 cmd = (struct htt_cmd *)skb->data; 1008 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 1009 1010 aggr_conf = &cmd->aggr_conf; 1011 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 1012 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 1013 1014 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 1015 aggr_conf->max_num_amsdu_subframes, 1016 aggr_conf->max_num_ampdu_subframes); 1017 1018 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1019 if (ret) { 1020 dev_kfree_skb_any(skb); 1021 return ret; 1022 } 1023 1024 return 0; 1025 } 1026 1027 static int ath10k_htt_h2t_aggr_cfg_msg_v2(struct ath10k_htt *htt, 1028 u8 max_subfrms_ampdu, 1029 u8 max_subfrms_amsdu) 1030 { 1031 struct ath10k *ar = htt->ar; 1032 struct htt_aggr_conf_v2 *aggr_conf; 1033 struct sk_buff *skb; 1034 struct htt_cmd *cmd; 1035 int len; 1036 int ret; 1037 1038 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 1039 1040 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 1041 return -EINVAL; 1042 1043 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 1044 return -EINVAL; 1045 1046 len = sizeof(cmd->hdr); 1047 len += sizeof(cmd->aggr_conf_v2); 1048 1049 skb = ath10k_htc_alloc_skb(ar, len); 1050 if (!skb) 1051 return -ENOMEM; 1052 1053 skb_put(skb, len); 1054 cmd = (struct htt_cmd *)skb->data; 1055 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 1056 1057 aggr_conf = &cmd->aggr_conf_v2; 1058 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 1059 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 1060 1061 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 1062 aggr_conf->max_num_amsdu_subframes, 1063 aggr_conf->max_num_ampdu_subframes); 1064 1065 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1066 if (ret) { 1067 dev_kfree_skb_any(skb); 1068 return ret; 1069 } 1070 1071 return 0; 1072 } 1073 1074 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 1075 __le32 token, 1076 __le16 fetch_seq_num, 1077 struct htt_tx_fetch_record *records, 1078 size_t num_records) 1079 { 1080 struct sk_buff *skb; 1081 struct htt_cmd *cmd; 1082 const u16 resp_id = 0; 1083 int len = 0; 1084 int ret; 1085 1086 /* Response IDs are echo-ed back only for host driver convienence 1087 * purposes. They aren't used for anything in the driver yet so use 0. 1088 */ 1089 1090 len += sizeof(cmd->hdr); 1091 len += sizeof(cmd->tx_fetch_resp); 1092 len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records; 1093 1094 skb = ath10k_htc_alloc_skb(ar, len); 1095 if (!skb) 1096 return -ENOMEM; 1097 1098 skb_put(skb, len); 1099 cmd = (struct htt_cmd *)skb->data; 1100 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP; 1101 cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id); 1102 cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num; 1103 cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records); 1104 cmd->tx_fetch_resp.token = token; 1105 1106 memcpy(cmd->tx_fetch_resp.records, records, 1107 sizeof(records[0]) * num_records); 1108 1109 ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb); 1110 if (ret) { 1111 ath10k_warn(ar, "failed to submit htc command: %d\n", ret); 1112 goto err_free_skb; 1113 } 1114 1115 return 0; 1116 1117 err_free_skb: 1118 dev_kfree_skb_any(skb); 1119 1120 return ret; 1121 } 1122 1123 static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb) 1124 { 1125 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1126 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1127 struct ath10k_vif *arvif; 1128 1129 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) { 1130 return ar->scan.vdev_id; 1131 } else if (cb->vif) { 1132 arvif = (void *)cb->vif->drv_priv; 1133 return arvif->vdev_id; 1134 } else if (ar->monitor_started) { 1135 return ar->monitor_vdev_id; 1136 } else { 1137 return 0; 1138 } 1139 } 1140 1141 static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth) 1142 { 1143 struct ieee80211_hdr *hdr = (void *)skb->data; 1144 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1145 1146 if (!is_eth && ieee80211_is_mgmt(hdr->frame_control)) 1147 return HTT_DATA_TX_EXT_TID_MGMT; 1148 else if (cb->flags & ATH10K_SKB_F_QOS) 1149 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 1150 else 1151 return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST; 1152 } 1153 1154 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu) 1155 { 1156 struct ath10k *ar = htt->ar; 1157 struct device *dev = ar->dev; 1158 struct sk_buff *txdesc = NULL; 1159 struct htt_cmd *cmd; 1160 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1161 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1162 int len = 0; 1163 int msdu_id = -1; 1164 int res; 1165 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1166 1167 len += sizeof(cmd->hdr); 1168 len += sizeof(cmd->mgmt_tx); 1169 1170 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1171 if (res < 0) 1172 goto err; 1173 1174 msdu_id = res; 1175 1176 if ((ieee80211_is_action(hdr->frame_control) || 1177 ieee80211_is_deauth(hdr->frame_control) || 1178 ieee80211_is_disassoc(hdr->frame_control)) && 1179 ieee80211_has_protected(hdr->frame_control)) { 1180 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1181 } 1182 1183 txdesc = ath10k_htc_alloc_skb(ar, len); 1184 if (!txdesc) { 1185 res = -ENOMEM; 1186 goto err_free_msdu_id; 1187 } 1188 1189 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1190 DMA_TO_DEVICE); 1191 res = dma_mapping_error(dev, skb_cb->paddr); 1192 if (res) { 1193 res = -EIO; 1194 goto err_free_txdesc; 1195 } 1196 1197 skb_put(txdesc, len); 1198 cmd = (struct htt_cmd *)txdesc->data; 1199 memset(cmd, 0, len); 1200 1201 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX; 1202 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr); 1203 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len); 1204 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id); 1205 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id); 1206 memcpy(cmd->mgmt_tx.hdr, msdu->data, 1207 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN)); 1208 1209 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc); 1210 if (res) 1211 goto err_unmap_msdu; 1212 1213 return 0; 1214 1215 err_unmap_msdu: 1216 if (ar->bus_param.dev_type != ATH10K_DEV_TYPE_HL) 1217 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1218 err_free_txdesc: 1219 dev_kfree_skb_any(txdesc); 1220 err_free_msdu_id: 1221 spin_lock_bh(&htt->tx_lock); 1222 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1223 spin_unlock_bh(&htt->tx_lock); 1224 err: 1225 return res; 1226 } 1227 1228 #define HTT_TX_HL_NEEDED_HEADROOM \ 1229 (unsigned int)(sizeof(struct htt_cmd_hdr) + \ 1230 sizeof(struct htt_data_tx_desc) + \ 1231 sizeof(struct ath10k_htc_hdr)) 1232 1233 static int ath10k_htt_tx_hl(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 1234 struct sk_buff *msdu) 1235 { 1236 struct ath10k *ar = htt->ar; 1237 int res, data_len; 1238 struct htt_cmd_hdr *cmd_hdr; 1239 struct htt_data_tx_desc *tx_desc; 1240 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1241 struct sk_buff *tmp_skb; 1242 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1243 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1244 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1245 u8 flags0 = 0; 1246 u16 flags1 = 0; 1247 1248 data_len = msdu->len; 1249 1250 switch (txmode) { 1251 case ATH10K_HW_TXRX_RAW: 1252 case ATH10K_HW_TXRX_NATIVE_WIFI: 1253 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1254 /* fall through */ 1255 case ATH10K_HW_TXRX_ETHERNET: 1256 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1257 break; 1258 case ATH10K_HW_TXRX_MGMT: 1259 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1260 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1261 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1262 break; 1263 } 1264 1265 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1266 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1267 1268 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1269 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1270 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1271 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1272 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1273 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1274 } 1275 1276 /* Prepend the HTT header and TX desc struct to the data message 1277 * and realloc the skb if it does not have enough headroom. 1278 */ 1279 if (skb_headroom(msdu) < HTT_TX_HL_NEEDED_HEADROOM) { 1280 tmp_skb = msdu; 1281 1282 ath10k_dbg(htt->ar, ATH10K_DBG_HTT, 1283 "Not enough headroom in skb. Current headroom: %u, needed: %u. Reallocating...\n", 1284 skb_headroom(msdu), HTT_TX_HL_NEEDED_HEADROOM); 1285 msdu = skb_realloc_headroom(msdu, HTT_TX_HL_NEEDED_HEADROOM); 1286 kfree_skb(tmp_skb); 1287 if (!msdu) { 1288 ath10k_warn(htt->ar, "htt hl tx: Unable to realloc skb!\n"); 1289 res = -ENOMEM; 1290 goto out; 1291 } 1292 } 1293 1294 skb_push(msdu, sizeof(*cmd_hdr)); 1295 skb_push(msdu, sizeof(*tx_desc)); 1296 cmd_hdr = (struct htt_cmd_hdr *)msdu->data; 1297 tx_desc = (struct htt_data_tx_desc *)(msdu->data + sizeof(*cmd_hdr)); 1298 1299 cmd_hdr->msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1300 tx_desc->flags0 = flags0; 1301 tx_desc->flags1 = __cpu_to_le16(flags1); 1302 tx_desc->len = __cpu_to_le16(data_len); 1303 tx_desc->id = 0; 1304 tx_desc->frags_paddr = 0; /* always zero */ 1305 /* Initialize peer_id to INVALID_PEER because this is NOT 1306 * Reinjection path 1307 */ 1308 tx_desc->peerid = __cpu_to_le32(HTT_INVALID_PEERID); 1309 1310 res = ath10k_htc_send(&htt->ar->htc, htt->eid, msdu); 1311 1312 out: 1313 return res; 1314 } 1315 1316 static int ath10k_htt_tx_32(struct ath10k_htt *htt, 1317 enum ath10k_hw_txrx_mode txmode, 1318 struct sk_buff *msdu) 1319 { 1320 struct ath10k *ar = htt->ar; 1321 struct device *dev = ar->dev; 1322 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1323 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1324 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1325 struct ath10k_hif_sg_item sg_items[2]; 1326 struct ath10k_htt_txbuf_32 *txbuf; 1327 struct htt_data_tx_desc_frag *frags; 1328 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1329 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1330 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1331 int prefetch_len; 1332 int res; 1333 u8 flags0 = 0; 1334 u16 msdu_id, flags1 = 0; 1335 u16 freq = 0; 1336 u32 frags_paddr = 0; 1337 u32 txbuf_paddr; 1338 struct htt_msdu_ext_desc *ext_desc = NULL; 1339 struct htt_msdu_ext_desc *ext_desc_t = NULL; 1340 1341 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1342 if (res < 0) 1343 goto err; 1344 1345 msdu_id = res; 1346 1347 prefetch_len = min(htt->prefetch_len, msdu->len); 1348 prefetch_len = roundup(prefetch_len, 4); 1349 1350 txbuf = htt->txbuf.vaddr_txbuff_32 + msdu_id; 1351 txbuf_paddr = htt->txbuf.paddr + 1352 (sizeof(struct ath10k_htt_txbuf_32) * msdu_id); 1353 1354 if ((ieee80211_is_action(hdr->frame_control) || 1355 ieee80211_is_deauth(hdr->frame_control) || 1356 ieee80211_is_disassoc(hdr->frame_control)) && 1357 ieee80211_has_protected(hdr->frame_control)) { 1358 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1359 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1360 txmode == ATH10K_HW_TXRX_RAW && 1361 ieee80211_has_protected(hdr->frame_control)) { 1362 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1363 } 1364 1365 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1366 DMA_TO_DEVICE); 1367 res = dma_mapping_error(dev, skb_cb->paddr); 1368 if (res) { 1369 res = -EIO; 1370 goto err_free_msdu_id; 1371 } 1372 1373 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1374 freq = ar->scan.roc_freq; 1375 1376 switch (txmode) { 1377 case ATH10K_HW_TXRX_RAW: 1378 case ATH10K_HW_TXRX_NATIVE_WIFI: 1379 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1380 /* fall through */ 1381 case ATH10K_HW_TXRX_ETHERNET: 1382 if (ar->hw_params.continuous_frag_desc) { 1383 ext_desc_t = htt->frag_desc.vaddr_desc_32; 1384 memset(&ext_desc_t[msdu_id], 0, 1385 sizeof(struct htt_msdu_ext_desc)); 1386 frags = (struct htt_data_tx_desc_frag *) 1387 &ext_desc_t[msdu_id].frags; 1388 ext_desc = &ext_desc_t[msdu_id]; 1389 frags[0].tword_addr.paddr_lo = 1390 __cpu_to_le32(skb_cb->paddr); 1391 frags[0].tword_addr.paddr_hi = 0; 1392 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1393 1394 frags_paddr = htt->frag_desc.paddr + 1395 (sizeof(struct htt_msdu_ext_desc) * msdu_id); 1396 } else { 1397 frags = txbuf->frags; 1398 frags[0].dword_addr.paddr = 1399 __cpu_to_le32(skb_cb->paddr); 1400 frags[0].dword_addr.len = __cpu_to_le32(msdu->len); 1401 frags[1].dword_addr.paddr = 0; 1402 frags[1].dword_addr.len = 0; 1403 1404 frags_paddr = txbuf_paddr; 1405 } 1406 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1407 break; 1408 case ATH10K_HW_TXRX_MGMT: 1409 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1410 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1411 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1412 1413 frags_paddr = skb_cb->paddr; 1414 break; 1415 } 1416 1417 /* Normally all commands go through HTC which manages tx credits for 1418 * each endpoint and notifies when tx is completed. 1419 * 1420 * HTT endpoint is creditless so there's no need to care about HTC 1421 * flags. In that case it is trivial to fill the HTC header here. 1422 * 1423 * MSDU transmission is considered completed upon HTT event. This 1424 * implies no relevant resources can be freed until after the event is 1425 * received. That's why HTC tx completion handler itself is ignored by 1426 * setting NULL to transfer_context for all sg items. 1427 * 1428 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1429 * as it's a waste of resources. By bypassing HTC it is possible to 1430 * avoid extra memory allocations, compress data structures and thus 1431 * improve performance. 1432 */ 1433 1434 txbuf->htc_hdr.eid = htt->eid; 1435 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1436 sizeof(txbuf->cmd_tx) + 1437 prefetch_len); 1438 txbuf->htc_hdr.flags = 0; 1439 1440 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1441 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1442 1443 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1444 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1445 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1446 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1447 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1448 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1449 if (ar->hw_params.continuous_frag_desc) 1450 ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE; 1451 } 1452 1453 /* Prevent firmware from sending up tx inspection requests. There's 1454 * nothing ath10k can do with frames requested for inspection so force 1455 * it to simply rely a regular tx completion with discard status. 1456 */ 1457 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1458 1459 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1460 txbuf->cmd_tx.flags0 = flags0; 1461 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1462 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1463 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1464 txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr); 1465 if (ath10k_mac_tx_frm_has_freq(ar)) { 1466 txbuf->cmd_tx.offchan_tx.peerid = 1467 __cpu_to_le16(HTT_INVALID_PEERID); 1468 txbuf->cmd_tx.offchan_tx.freq = 1469 __cpu_to_le16(freq); 1470 } else { 1471 txbuf->cmd_tx.peerid = 1472 __cpu_to_le32(HTT_INVALID_PEERID); 1473 } 1474 1475 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1476 ath10k_dbg(ar, ATH10K_DBG_HTT, 1477 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %pad, msdu_paddr %pad vdev %hhu tid %hhu freq %hu\n", 1478 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1479 &skb_cb->paddr, vdev_id, tid, freq); 1480 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1481 msdu->data, msdu->len); 1482 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1483 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1484 1485 sg_items[0].transfer_id = 0; 1486 sg_items[0].transfer_context = NULL; 1487 sg_items[0].vaddr = &txbuf->htc_hdr; 1488 sg_items[0].paddr = txbuf_paddr + 1489 sizeof(txbuf->frags); 1490 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1491 sizeof(txbuf->cmd_hdr) + 1492 sizeof(txbuf->cmd_tx); 1493 1494 sg_items[1].transfer_id = 0; 1495 sg_items[1].transfer_context = NULL; 1496 sg_items[1].vaddr = msdu->data; 1497 sg_items[1].paddr = skb_cb->paddr; 1498 sg_items[1].len = prefetch_len; 1499 1500 res = ath10k_hif_tx_sg(htt->ar, 1501 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1502 sg_items, ARRAY_SIZE(sg_items)); 1503 if (res) 1504 goto err_unmap_msdu; 1505 1506 return 0; 1507 1508 err_unmap_msdu: 1509 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1510 err_free_msdu_id: 1511 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1512 err: 1513 return res; 1514 } 1515 1516 static int ath10k_htt_tx_64(struct ath10k_htt *htt, 1517 enum ath10k_hw_txrx_mode txmode, 1518 struct sk_buff *msdu) 1519 { 1520 struct ath10k *ar = htt->ar; 1521 struct device *dev = ar->dev; 1522 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1523 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1524 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1525 struct ath10k_hif_sg_item sg_items[2]; 1526 struct ath10k_htt_txbuf_64 *txbuf; 1527 struct htt_data_tx_desc_frag *frags; 1528 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1529 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1530 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1531 int prefetch_len; 1532 int res; 1533 u8 flags0 = 0; 1534 u16 msdu_id, flags1 = 0; 1535 u16 freq = 0; 1536 dma_addr_t frags_paddr = 0; 1537 dma_addr_t txbuf_paddr; 1538 struct htt_msdu_ext_desc_64 *ext_desc = NULL; 1539 struct htt_msdu_ext_desc_64 *ext_desc_t = NULL; 1540 1541 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1542 if (res < 0) 1543 goto err; 1544 1545 msdu_id = res; 1546 1547 prefetch_len = min(htt->prefetch_len, msdu->len); 1548 prefetch_len = roundup(prefetch_len, 4); 1549 1550 txbuf = htt->txbuf.vaddr_txbuff_64 + msdu_id; 1551 txbuf_paddr = htt->txbuf.paddr + 1552 (sizeof(struct ath10k_htt_txbuf_64) * msdu_id); 1553 1554 if ((ieee80211_is_action(hdr->frame_control) || 1555 ieee80211_is_deauth(hdr->frame_control) || 1556 ieee80211_is_disassoc(hdr->frame_control)) && 1557 ieee80211_has_protected(hdr->frame_control)) { 1558 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1559 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1560 txmode == ATH10K_HW_TXRX_RAW && 1561 ieee80211_has_protected(hdr->frame_control)) { 1562 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1563 } 1564 1565 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1566 DMA_TO_DEVICE); 1567 res = dma_mapping_error(dev, skb_cb->paddr); 1568 if (res) { 1569 res = -EIO; 1570 goto err_free_msdu_id; 1571 } 1572 1573 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1574 freq = ar->scan.roc_freq; 1575 1576 switch (txmode) { 1577 case ATH10K_HW_TXRX_RAW: 1578 case ATH10K_HW_TXRX_NATIVE_WIFI: 1579 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1580 /* fall through */ 1581 case ATH10K_HW_TXRX_ETHERNET: 1582 if (ar->hw_params.continuous_frag_desc) { 1583 ext_desc_t = htt->frag_desc.vaddr_desc_64; 1584 memset(&ext_desc_t[msdu_id], 0, 1585 sizeof(struct htt_msdu_ext_desc_64)); 1586 frags = (struct htt_data_tx_desc_frag *) 1587 &ext_desc_t[msdu_id].frags; 1588 ext_desc = &ext_desc_t[msdu_id]; 1589 frags[0].tword_addr.paddr_lo = 1590 __cpu_to_le32(skb_cb->paddr); 1591 frags[0].tword_addr.paddr_hi = 1592 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1593 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1594 1595 frags_paddr = htt->frag_desc.paddr + 1596 (sizeof(struct htt_msdu_ext_desc_64) * msdu_id); 1597 } else { 1598 frags = txbuf->frags; 1599 frags[0].tword_addr.paddr_lo = 1600 __cpu_to_le32(skb_cb->paddr); 1601 frags[0].tword_addr.paddr_hi = 1602 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1603 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1604 frags[1].tword_addr.paddr_lo = 0; 1605 frags[1].tword_addr.paddr_hi = 0; 1606 frags[1].tword_addr.len_16 = 0; 1607 } 1608 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1609 break; 1610 case ATH10K_HW_TXRX_MGMT: 1611 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1612 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1613 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1614 1615 frags_paddr = skb_cb->paddr; 1616 break; 1617 } 1618 1619 /* Normally all commands go through HTC which manages tx credits for 1620 * each endpoint and notifies when tx is completed. 1621 * 1622 * HTT endpoint is creditless so there's no need to care about HTC 1623 * flags. In that case it is trivial to fill the HTC header here. 1624 * 1625 * MSDU transmission is considered completed upon HTT event. This 1626 * implies no relevant resources can be freed until after the event is 1627 * received. That's why HTC tx completion handler itself is ignored by 1628 * setting NULL to transfer_context for all sg items. 1629 * 1630 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1631 * as it's a waste of resources. By bypassing HTC it is possible to 1632 * avoid extra memory allocations, compress data structures and thus 1633 * improve performance. 1634 */ 1635 1636 txbuf->htc_hdr.eid = htt->eid; 1637 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1638 sizeof(txbuf->cmd_tx) + 1639 prefetch_len); 1640 txbuf->htc_hdr.flags = 0; 1641 1642 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1643 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1644 1645 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1646 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1647 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1648 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1649 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1650 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1651 if (ar->hw_params.continuous_frag_desc) { 1652 memset(ext_desc->tso_flag, 0, sizeof(ext_desc->tso_flag)); 1653 ext_desc->tso_flag[3] |= 1654 __cpu_to_le32(HTT_MSDU_CHECKSUM_ENABLE_64); 1655 } 1656 } 1657 1658 /* Prevent firmware from sending up tx inspection requests. There's 1659 * nothing ath10k can do with frames requested for inspection so force 1660 * it to simply rely a regular tx completion with discard status. 1661 */ 1662 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1663 1664 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1665 txbuf->cmd_tx.flags0 = flags0; 1666 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1667 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1668 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1669 1670 /* fill fragment descriptor */ 1671 txbuf->cmd_tx.frags_paddr = __cpu_to_le64(frags_paddr); 1672 if (ath10k_mac_tx_frm_has_freq(ar)) { 1673 txbuf->cmd_tx.offchan_tx.peerid = 1674 __cpu_to_le16(HTT_INVALID_PEERID); 1675 txbuf->cmd_tx.offchan_tx.freq = 1676 __cpu_to_le16(freq); 1677 } else { 1678 txbuf->cmd_tx.peerid = 1679 __cpu_to_le32(HTT_INVALID_PEERID); 1680 } 1681 1682 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1683 ath10k_dbg(ar, ATH10K_DBG_HTT, 1684 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %pad, msdu_paddr %pad vdev %hhu tid %hhu freq %hu\n", 1685 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1686 &skb_cb->paddr, vdev_id, tid, freq); 1687 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1688 msdu->data, msdu->len); 1689 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1690 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1691 1692 sg_items[0].transfer_id = 0; 1693 sg_items[0].transfer_context = NULL; 1694 sg_items[0].vaddr = &txbuf->htc_hdr; 1695 sg_items[0].paddr = txbuf_paddr + 1696 sizeof(txbuf->frags); 1697 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1698 sizeof(txbuf->cmd_hdr) + 1699 sizeof(txbuf->cmd_tx); 1700 1701 sg_items[1].transfer_id = 0; 1702 sg_items[1].transfer_context = NULL; 1703 sg_items[1].vaddr = msdu->data; 1704 sg_items[1].paddr = skb_cb->paddr; 1705 sg_items[1].len = prefetch_len; 1706 1707 res = ath10k_hif_tx_sg(htt->ar, 1708 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1709 sg_items, ARRAY_SIZE(sg_items)); 1710 if (res) 1711 goto err_unmap_msdu; 1712 1713 return 0; 1714 1715 err_unmap_msdu: 1716 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1717 err_free_msdu_id: 1718 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1719 err: 1720 return res; 1721 } 1722 1723 static const struct ath10k_htt_tx_ops htt_tx_ops_32 = { 1724 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_32, 1725 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32, 1726 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_32, 1727 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_32, 1728 .htt_tx = ath10k_htt_tx_32, 1729 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_32, 1730 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_32, 1731 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg, 1732 }; 1733 1734 static const struct ath10k_htt_tx_ops htt_tx_ops_64 = { 1735 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_64, 1736 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_64, 1737 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_64, 1738 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_64, 1739 .htt_tx = ath10k_htt_tx_64, 1740 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_64, 1741 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_64, 1742 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_v2, 1743 }; 1744 1745 static const struct ath10k_htt_tx_ops htt_tx_ops_hl = { 1746 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_hl, 1747 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32, 1748 .htt_tx = ath10k_htt_tx_hl, 1749 }; 1750 1751 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt) 1752 { 1753 struct ath10k *ar = htt->ar; 1754 1755 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) 1756 htt->tx_ops = &htt_tx_ops_hl; 1757 else if (ar->hw_params.target_64bit) 1758 htt->tx_ops = &htt_tx_ops_64; 1759 else 1760 htt->tx_ops = &htt_tx_ops_32; 1761 } 1762