1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/slab.h> 9 #include <linux/remoteproc.h> 10 #include <linux/firmware.h> 11 #include <linux/of.h> 12 13 #include "core.h" 14 #include "dp_tx.h" 15 #include "dp_rx.h" 16 #include "debug.h" 17 #include "hif.h" 18 #include "wow.h" 19 20 unsigned int ath11k_debug_mask; 21 EXPORT_SYMBOL(ath11k_debug_mask); 22 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644); 23 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 24 25 static unsigned int ath11k_crypto_mode; 26 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644); 27 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software"); 28 29 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */ 30 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI; 31 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644); 32 MODULE_PARM_DESC(frame_mode, 33 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 34 35 static const struct ath11k_hw_params ath11k_hw_params[] = { 36 { 37 .hw_rev = ATH11K_HW_IPQ8074, 38 .name = "ipq8074 hw2.0", 39 .fw = { 40 .dir = "IPQ8074/hw2.0", 41 .board_size = 256 * 1024, 42 .cal_offset = 128 * 1024, 43 }, 44 .max_radios = 3, 45 .bdf_addr = 0x4B0C0000, 46 .hw_ops = &ipq8074_ops, 47 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 48 .internal_sleep_clock = false, 49 .regs = &ipq8074_regs, 50 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 51 .host_ce_config = ath11k_host_ce_config_ipq8074, 52 .ce_count = 12, 53 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 54 .target_ce_count = 11, 55 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074, 56 .svc_to_ce_map_len = 21, 57 .single_pdev_only = false, 58 .rxdma1_enable = true, 59 .num_rxmda_per_pdev = 1, 60 .rx_mac_buf_ring = false, 61 .vdev_start_delay = false, 62 .htt_peer_map_v2 = true, 63 64 .spectral = { 65 .fft_sz = 2, 66 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes. 67 * so added pad size as 2 bytes to compensate the BIN size 68 */ 69 .fft_pad_sz = 2, 70 .summary_pad_sz = 0, 71 .fft_hdr_len = 16, 72 .max_fft_bins = 512, 73 .fragment_160mhz = true, 74 }, 75 76 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 77 BIT(NL80211_IFTYPE_AP) | 78 BIT(NL80211_IFTYPE_MESH_POINT), 79 .supports_monitor = true, 80 .full_monitor_mode = false, 81 .supports_shadow_regs = false, 82 .idle_ps = false, 83 .supports_sta_ps = false, 84 .cold_boot_calib = true, 85 .cbcal_restart_fw = true, 86 .fw_mem_mode = 0, 87 .num_vdevs = 16 + 1, 88 .num_peers = 512, 89 .supports_suspend = false, 90 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 91 .supports_regdb = false, 92 .fix_l1ss = true, 93 .credit_flow = false, 94 .max_tx_ring = DP_TCL_NUM_RING_MAX, 95 .hal_params = &ath11k_hw_hal_params_ipq8074, 96 .supports_dynamic_smps_6ghz = false, 97 .alloc_cacheable_memory = true, 98 .supports_rssi_stats = false, 99 .fw_wmi_diag_event = false, 100 .current_cc_support = false, 101 .dbr_debug_support = true, 102 .global_reset = false, 103 .bios_sar_capa = NULL, 104 .m3_fw_support = false, 105 .fixed_bdf_addr = true, 106 .fixed_mem_region = true, 107 .static_window_map = false, 108 .hybrid_bus_type = false, 109 .fixed_fw_mem = false, 110 .support_off_channel_tx = false, 111 .supports_multi_bssid = false, 112 113 .sram_dump = {}, 114 115 .tcl_ring_retry = true, 116 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 117 .smp2p_wow_exit = false, 118 }, 119 { 120 .hw_rev = ATH11K_HW_IPQ6018_HW10, 121 .name = "ipq6018 hw1.0", 122 .fw = { 123 .dir = "IPQ6018/hw1.0", 124 .board_size = 256 * 1024, 125 .cal_offset = 128 * 1024, 126 }, 127 .max_radios = 2, 128 .bdf_addr = 0x4ABC0000, 129 .hw_ops = &ipq6018_ops, 130 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 131 .internal_sleep_clock = false, 132 .regs = &ipq8074_regs, 133 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 134 .host_ce_config = ath11k_host_ce_config_ipq8074, 135 .ce_count = 12, 136 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 137 .target_ce_count = 11, 138 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018, 139 .svc_to_ce_map_len = 19, 140 .single_pdev_only = false, 141 .rxdma1_enable = true, 142 .num_rxmda_per_pdev = 1, 143 .rx_mac_buf_ring = false, 144 .vdev_start_delay = false, 145 .htt_peer_map_v2 = true, 146 147 .spectral = { 148 .fft_sz = 4, 149 .fft_pad_sz = 0, 150 .summary_pad_sz = 0, 151 .fft_hdr_len = 16, 152 .max_fft_bins = 512, 153 .fragment_160mhz = true, 154 }, 155 156 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 157 BIT(NL80211_IFTYPE_AP) | 158 BIT(NL80211_IFTYPE_MESH_POINT), 159 .supports_monitor = true, 160 .full_monitor_mode = false, 161 .supports_shadow_regs = false, 162 .idle_ps = false, 163 .supports_sta_ps = false, 164 .cold_boot_calib = true, 165 .cbcal_restart_fw = true, 166 .fw_mem_mode = 0, 167 .num_vdevs = 16 + 1, 168 .num_peers = 512, 169 .supports_suspend = false, 170 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 171 .supports_regdb = false, 172 .fix_l1ss = true, 173 .credit_flow = false, 174 .max_tx_ring = DP_TCL_NUM_RING_MAX, 175 .hal_params = &ath11k_hw_hal_params_ipq8074, 176 .supports_dynamic_smps_6ghz = false, 177 .alloc_cacheable_memory = true, 178 .supports_rssi_stats = false, 179 .fw_wmi_diag_event = false, 180 .current_cc_support = false, 181 .dbr_debug_support = true, 182 .global_reset = false, 183 .bios_sar_capa = NULL, 184 .m3_fw_support = false, 185 .fixed_bdf_addr = true, 186 .fixed_mem_region = true, 187 .static_window_map = false, 188 .hybrid_bus_type = false, 189 .fixed_fw_mem = false, 190 .support_off_channel_tx = false, 191 .supports_multi_bssid = false, 192 193 .sram_dump = {}, 194 195 .tcl_ring_retry = true, 196 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 197 .smp2p_wow_exit = false, 198 }, 199 { 200 .name = "qca6390 hw2.0", 201 .hw_rev = ATH11K_HW_QCA6390_HW20, 202 .fw = { 203 .dir = "QCA6390/hw2.0", 204 .board_size = 256 * 1024, 205 .cal_offset = 128 * 1024, 206 }, 207 .max_radios = 3, 208 .bdf_addr = 0x4B0C0000, 209 .hw_ops = &qca6390_ops, 210 .ring_mask = &ath11k_hw_ring_mask_qca6390, 211 .internal_sleep_clock = true, 212 .regs = &qca6390_regs, 213 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 214 .host_ce_config = ath11k_host_ce_config_qca6390, 215 .ce_count = 9, 216 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 217 .target_ce_count = 9, 218 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 219 .svc_to_ce_map_len = 14, 220 .single_pdev_only = true, 221 .rxdma1_enable = false, 222 .num_rxmda_per_pdev = 2, 223 .rx_mac_buf_ring = true, 224 .vdev_start_delay = true, 225 .htt_peer_map_v2 = false, 226 227 .spectral = { 228 .fft_sz = 0, 229 .fft_pad_sz = 0, 230 .summary_pad_sz = 0, 231 .fft_hdr_len = 0, 232 .max_fft_bins = 0, 233 .fragment_160mhz = false, 234 }, 235 236 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 237 BIT(NL80211_IFTYPE_AP), 238 .supports_monitor = false, 239 .full_monitor_mode = false, 240 .supports_shadow_regs = true, 241 .idle_ps = true, 242 .supports_sta_ps = true, 243 .cold_boot_calib = false, 244 .cbcal_restart_fw = false, 245 .fw_mem_mode = 0, 246 .num_vdevs = 16 + 1, 247 .num_peers = 512, 248 .supports_suspend = true, 249 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 250 .supports_regdb = false, 251 .fix_l1ss = true, 252 .credit_flow = true, 253 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 254 .hal_params = &ath11k_hw_hal_params_qca6390, 255 .supports_dynamic_smps_6ghz = false, 256 .alloc_cacheable_memory = false, 257 .supports_rssi_stats = true, 258 .fw_wmi_diag_event = true, 259 .current_cc_support = true, 260 .dbr_debug_support = false, 261 .global_reset = true, 262 .bios_sar_capa = NULL, 263 .m3_fw_support = true, 264 .fixed_bdf_addr = false, 265 .fixed_mem_region = false, 266 .static_window_map = false, 267 .hybrid_bus_type = false, 268 .fixed_fw_mem = false, 269 .support_off_channel_tx = true, 270 .supports_multi_bssid = true, 271 272 .sram_dump = { 273 .start = 0x01400000, 274 .end = 0x0171ffff, 275 }, 276 277 .tcl_ring_retry = true, 278 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 279 .smp2p_wow_exit = false, 280 }, 281 { 282 .name = "qcn9074 hw1.0", 283 .hw_rev = ATH11K_HW_QCN9074_HW10, 284 .fw = { 285 .dir = "QCN9074/hw1.0", 286 .board_size = 256 * 1024, 287 .cal_offset = 128 * 1024, 288 }, 289 .max_radios = 1, 290 .single_pdev_only = false, 291 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074, 292 .hw_ops = &qcn9074_ops, 293 .ring_mask = &ath11k_hw_ring_mask_qcn9074, 294 .internal_sleep_clock = false, 295 .regs = &qcn9074_regs, 296 .host_ce_config = ath11k_host_ce_config_qcn9074, 297 .ce_count = 6, 298 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074, 299 .target_ce_count = 9, 300 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074, 301 .svc_to_ce_map_len = 18, 302 .rxdma1_enable = true, 303 .num_rxmda_per_pdev = 1, 304 .rx_mac_buf_ring = false, 305 .vdev_start_delay = false, 306 .htt_peer_map_v2 = true, 307 308 .spectral = { 309 .fft_sz = 2, 310 .fft_pad_sz = 0, 311 .summary_pad_sz = 16, 312 .fft_hdr_len = 24, 313 .max_fft_bins = 1024, 314 .fragment_160mhz = false, 315 }, 316 317 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 318 BIT(NL80211_IFTYPE_AP) | 319 BIT(NL80211_IFTYPE_MESH_POINT), 320 .supports_monitor = true, 321 .full_monitor_mode = true, 322 .supports_shadow_regs = false, 323 .idle_ps = false, 324 .supports_sta_ps = false, 325 .cold_boot_calib = false, 326 .cbcal_restart_fw = false, 327 .fw_mem_mode = 2, 328 .num_vdevs = 8, 329 .num_peers = 128, 330 .supports_suspend = false, 331 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 332 .supports_regdb = false, 333 .fix_l1ss = true, 334 .credit_flow = false, 335 .max_tx_ring = DP_TCL_NUM_RING_MAX, 336 .hal_params = &ath11k_hw_hal_params_ipq8074, 337 .supports_dynamic_smps_6ghz = true, 338 .alloc_cacheable_memory = true, 339 .supports_rssi_stats = false, 340 .fw_wmi_diag_event = false, 341 .current_cc_support = false, 342 .dbr_debug_support = true, 343 .global_reset = false, 344 .bios_sar_capa = NULL, 345 .m3_fw_support = true, 346 .fixed_bdf_addr = false, 347 .fixed_mem_region = false, 348 .static_window_map = true, 349 .hybrid_bus_type = false, 350 .fixed_fw_mem = false, 351 .support_off_channel_tx = false, 352 .supports_multi_bssid = false, 353 354 .sram_dump = {}, 355 356 .tcl_ring_retry = true, 357 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 358 .smp2p_wow_exit = false, 359 }, 360 { 361 .name = "wcn6855 hw2.0", 362 .hw_rev = ATH11K_HW_WCN6855_HW20, 363 .fw = { 364 .dir = "WCN6855/hw2.0", 365 .board_size = 256 * 1024, 366 .cal_offset = 128 * 1024, 367 }, 368 .max_radios = 3, 369 .bdf_addr = 0x4B0C0000, 370 .hw_ops = &wcn6855_ops, 371 .ring_mask = &ath11k_hw_ring_mask_qca6390, 372 .internal_sleep_clock = true, 373 .regs = &wcn6855_regs, 374 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 375 .host_ce_config = ath11k_host_ce_config_qca6390, 376 .ce_count = 9, 377 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 378 .target_ce_count = 9, 379 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 380 .svc_to_ce_map_len = 14, 381 .single_pdev_only = true, 382 .rxdma1_enable = false, 383 .num_rxmda_per_pdev = 2, 384 .rx_mac_buf_ring = true, 385 .vdev_start_delay = true, 386 .htt_peer_map_v2 = false, 387 388 .spectral = { 389 .fft_sz = 0, 390 .fft_pad_sz = 0, 391 .summary_pad_sz = 0, 392 .fft_hdr_len = 0, 393 .max_fft_bins = 0, 394 .fragment_160mhz = false, 395 }, 396 397 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 398 BIT(NL80211_IFTYPE_AP), 399 .supports_monitor = false, 400 .full_monitor_mode = false, 401 .supports_shadow_regs = true, 402 .idle_ps = true, 403 .supports_sta_ps = true, 404 .cold_boot_calib = false, 405 .cbcal_restart_fw = false, 406 .fw_mem_mode = 0, 407 .num_vdevs = 16 + 1, 408 .num_peers = 512, 409 .supports_suspend = true, 410 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 411 .supports_regdb = true, 412 .fix_l1ss = false, 413 .credit_flow = true, 414 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 415 .hal_params = &ath11k_hw_hal_params_qca6390, 416 .supports_dynamic_smps_6ghz = false, 417 .alloc_cacheable_memory = false, 418 .supports_rssi_stats = true, 419 .fw_wmi_diag_event = true, 420 .current_cc_support = true, 421 .dbr_debug_support = false, 422 .global_reset = true, 423 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 424 .m3_fw_support = true, 425 .fixed_bdf_addr = false, 426 .fixed_mem_region = false, 427 .static_window_map = false, 428 .hybrid_bus_type = false, 429 .fixed_fw_mem = false, 430 .support_off_channel_tx = true, 431 .supports_multi_bssid = true, 432 433 .sram_dump = { 434 .start = 0x01400000, 435 .end = 0x0177ffff, 436 }, 437 438 .tcl_ring_retry = true, 439 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 440 .smp2p_wow_exit = false, 441 }, 442 { 443 .name = "wcn6855 hw2.1", 444 .hw_rev = ATH11K_HW_WCN6855_HW21, 445 .fw = { 446 .dir = "WCN6855/hw2.1", 447 .board_size = 256 * 1024, 448 .cal_offset = 128 * 1024, 449 }, 450 .max_radios = 3, 451 .bdf_addr = 0x4B0C0000, 452 .hw_ops = &wcn6855_ops, 453 .ring_mask = &ath11k_hw_ring_mask_qca6390, 454 .internal_sleep_clock = true, 455 .regs = &wcn6855_regs, 456 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 457 .host_ce_config = ath11k_host_ce_config_qca6390, 458 .ce_count = 9, 459 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 460 .target_ce_count = 9, 461 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 462 .svc_to_ce_map_len = 14, 463 .single_pdev_only = true, 464 .rxdma1_enable = false, 465 .num_rxmda_per_pdev = 2, 466 .rx_mac_buf_ring = true, 467 .vdev_start_delay = true, 468 .htt_peer_map_v2 = false, 469 470 .spectral = { 471 .fft_sz = 0, 472 .fft_pad_sz = 0, 473 .summary_pad_sz = 0, 474 .fft_hdr_len = 0, 475 .max_fft_bins = 0, 476 .fragment_160mhz = false, 477 }, 478 479 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 480 BIT(NL80211_IFTYPE_AP), 481 .supports_monitor = false, 482 .supports_shadow_regs = true, 483 .idle_ps = true, 484 .supports_sta_ps = true, 485 .cold_boot_calib = false, 486 .cbcal_restart_fw = false, 487 .fw_mem_mode = 0, 488 .num_vdevs = 16 + 1, 489 .num_peers = 512, 490 .supports_suspend = true, 491 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 492 .supports_regdb = true, 493 .fix_l1ss = false, 494 .credit_flow = true, 495 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 496 .hal_params = &ath11k_hw_hal_params_qca6390, 497 .supports_dynamic_smps_6ghz = false, 498 .alloc_cacheable_memory = false, 499 .supports_rssi_stats = true, 500 .fw_wmi_diag_event = true, 501 .current_cc_support = true, 502 .dbr_debug_support = false, 503 .global_reset = true, 504 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 505 .m3_fw_support = true, 506 .fixed_bdf_addr = false, 507 .fixed_mem_region = false, 508 .static_window_map = false, 509 .hybrid_bus_type = false, 510 .fixed_fw_mem = false, 511 .support_off_channel_tx = true, 512 .supports_multi_bssid = true, 513 514 .sram_dump = { 515 .start = 0x01400000, 516 .end = 0x0177ffff, 517 }, 518 519 .tcl_ring_retry = true, 520 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 521 .smp2p_wow_exit = false, 522 }, 523 { 524 .name = "wcn6750 hw1.0", 525 .hw_rev = ATH11K_HW_WCN6750_HW10, 526 .fw = { 527 .dir = "WCN6750/hw1.0", 528 .board_size = 256 * 1024, 529 .cal_offset = 128 * 1024, 530 }, 531 .max_radios = 1, 532 .bdf_addr = 0x4B0C0000, 533 .hw_ops = &wcn6750_ops, 534 .ring_mask = &ath11k_hw_ring_mask_wcn6750, 535 .internal_sleep_clock = false, 536 .regs = &wcn6750_regs, 537 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750, 538 .host_ce_config = ath11k_host_ce_config_qca6390, 539 .ce_count = 9, 540 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 541 .target_ce_count = 9, 542 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 543 .svc_to_ce_map_len = 14, 544 .single_pdev_only = true, 545 .rxdma1_enable = false, 546 .num_rxmda_per_pdev = 1, 547 .rx_mac_buf_ring = true, 548 .vdev_start_delay = true, 549 .htt_peer_map_v2 = false, 550 551 .spectral = { 552 .fft_sz = 0, 553 .fft_pad_sz = 0, 554 .summary_pad_sz = 0, 555 .fft_hdr_len = 0, 556 .max_fft_bins = 0, 557 .fragment_160mhz = false, 558 }, 559 560 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 561 BIT(NL80211_IFTYPE_AP), 562 .supports_monitor = false, 563 .supports_shadow_regs = true, 564 .idle_ps = true, 565 .supports_sta_ps = true, 566 .cold_boot_calib = true, 567 .cbcal_restart_fw = false, 568 .fw_mem_mode = 0, 569 .num_vdevs = 16 + 1, 570 .num_peers = 512, 571 .supports_suspend = false, 572 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 573 .supports_regdb = true, 574 .fix_l1ss = false, 575 .credit_flow = true, 576 .max_tx_ring = DP_TCL_NUM_RING_MAX, 577 .hal_params = &ath11k_hw_hal_params_wcn6750, 578 .supports_dynamic_smps_6ghz = false, 579 .alloc_cacheable_memory = false, 580 .supports_rssi_stats = true, 581 .fw_wmi_diag_event = false, 582 .current_cc_support = true, 583 .dbr_debug_support = false, 584 .global_reset = false, 585 .bios_sar_capa = NULL, 586 .m3_fw_support = false, 587 .fixed_bdf_addr = false, 588 .fixed_mem_region = false, 589 .static_window_map = true, 590 .hybrid_bus_type = true, 591 .fixed_fw_mem = true, 592 .support_off_channel_tx = true, 593 .supports_multi_bssid = true, 594 595 .sram_dump = {}, 596 597 .tcl_ring_retry = false, 598 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750, 599 .smp2p_wow_exit = true, 600 }, 601 }; 602 603 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab) 604 { 605 WARN_ON(!ab->hw_params.single_pdev_only); 606 607 return &ab->pdevs[0]; 608 } 609 610 void ath11k_fw_stats_pdevs_free(struct list_head *head) 611 { 612 struct ath11k_fw_stats_pdev *i, *tmp; 613 614 list_for_each_entry_safe(i, tmp, head, list) { 615 list_del(&i->list); 616 kfree(i); 617 } 618 } 619 620 void ath11k_fw_stats_vdevs_free(struct list_head *head) 621 { 622 struct ath11k_fw_stats_vdev *i, *tmp; 623 624 list_for_each_entry_safe(i, tmp, head, list) { 625 list_del(&i->list); 626 kfree(i); 627 } 628 } 629 630 void ath11k_fw_stats_bcn_free(struct list_head *head) 631 { 632 struct ath11k_fw_stats_bcn *i, *tmp; 633 634 list_for_each_entry_safe(i, tmp, head, list) { 635 list_del(&i->list); 636 kfree(i); 637 } 638 } 639 640 void ath11k_fw_stats_init(struct ath11k *ar) 641 { 642 INIT_LIST_HEAD(&ar->fw_stats.pdevs); 643 INIT_LIST_HEAD(&ar->fw_stats.vdevs); 644 INIT_LIST_HEAD(&ar->fw_stats.bcn); 645 646 init_completion(&ar->fw_stats_complete); 647 } 648 649 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats) 650 { 651 ath11k_fw_stats_pdevs_free(&stats->pdevs); 652 ath11k_fw_stats_vdevs_free(&stats->vdevs); 653 ath11k_fw_stats_bcn_free(&stats->bcn); 654 } 655 656 int ath11k_core_suspend(struct ath11k_base *ab) 657 { 658 int ret; 659 struct ath11k_pdev *pdev; 660 struct ath11k *ar; 661 662 if (!ab->hw_params.supports_suspend) 663 return -EOPNOTSUPP; 664 665 /* so far single_pdev_only chips have supports_suspend as true 666 * and only the first pdev is valid. 667 */ 668 pdev = ath11k_core_get_single_pdev(ab); 669 ar = pdev->ar; 670 if (!ar || ar->state != ATH11K_STATE_OFF) 671 return 0; 672 673 ret = ath11k_dp_rx_pktlog_stop(ab, true); 674 if (ret) { 675 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n", 676 ret); 677 return ret; 678 } 679 680 ret = ath11k_mac_wait_tx_complete(ar); 681 if (ret) { 682 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret); 683 return ret; 684 } 685 686 ret = ath11k_wow_enable(ab); 687 if (ret) { 688 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret); 689 return ret; 690 } 691 692 ret = ath11k_dp_rx_pktlog_stop(ab, false); 693 if (ret) { 694 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n", 695 ret); 696 return ret; 697 } 698 699 ath11k_ce_stop_shadow_timers(ab); 700 ath11k_dp_stop_shadow_timers(ab); 701 702 ath11k_hif_irq_disable(ab); 703 ath11k_hif_ce_irq_disable(ab); 704 705 ret = ath11k_hif_suspend(ab); 706 if (ret) { 707 ath11k_warn(ab, "failed to suspend hif: %d\n", ret); 708 return ret; 709 } 710 711 return 0; 712 } 713 EXPORT_SYMBOL(ath11k_core_suspend); 714 715 int ath11k_core_resume(struct ath11k_base *ab) 716 { 717 int ret; 718 struct ath11k_pdev *pdev; 719 struct ath11k *ar; 720 721 if (!ab->hw_params.supports_suspend) 722 return -EOPNOTSUPP; 723 724 /* so far signle_pdev_only chips have supports_suspend as true 725 * and only the first pdev is valid. 726 */ 727 pdev = ath11k_core_get_single_pdev(ab); 728 ar = pdev->ar; 729 if (!ar || ar->state != ATH11K_STATE_OFF) 730 return 0; 731 732 ret = ath11k_hif_resume(ab); 733 if (ret) { 734 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret); 735 return ret; 736 } 737 738 ath11k_hif_ce_irq_enable(ab); 739 ath11k_hif_irq_enable(ab); 740 741 ret = ath11k_dp_rx_pktlog_start(ab); 742 if (ret) { 743 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n", 744 ret); 745 return ret; 746 } 747 748 ret = ath11k_wow_wakeup(ab); 749 if (ret) { 750 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret); 751 return ret; 752 } 753 754 return 0; 755 } 756 EXPORT_SYMBOL(ath11k_core_resume); 757 758 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data) 759 { 760 struct ath11k_base *ab = data; 761 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC; 762 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr; 763 ssize_t copied; 764 size_t len; 765 int i; 766 767 if (ab->qmi.target.bdf_ext[0] != '\0') 768 return; 769 770 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE) 771 return; 772 773 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) { 774 ath11k_dbg(ab, ATH11K_DBG_BOOT, 775 "wrong smbios bdf ext type length (%d).\n", 776 hdr->length); 777 return; 778 } 779 780 spin_lock_bh(&ab->base_lock); 781 782 switch (smbios->country_code_flag) { 783 case ATH11K_SMBIOS_CC_ISO: 784 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff; 785 ab->new_alpha2[1] = smbios->cc_code & 0xff; 786 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios cc_code %c%c\n", 787 ab->new_alpha2[0], ab->new_alpha2[1]); 788 break; 789 case ATH11K_SMBIOS_CC_WW: 790 ab->new_alpha2[0] = '0'; 791 ab->new_alpha2[1] = '0'; 792 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios worldwide regdomain\n"); 793 break; 794 default: 795 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot ignore smbios country code setting %d\n", 796 smbios->country_code_flag); 797 break; 798 } 799 800 spin_unlock_bh(&ab->base_lock); 801 802 if (!smbios->bdf_enabled) { 803 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n"); 804 return; 805 } 806 807 /* Only one string exists (per spec) */ 808 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) { 809 ath11k_dbg(ab, ATH11K_DBG_BOOT, 810 "bdf variant magic does not match.\n"); 811 return; 812 } 813 814 len = min_t(size_t, 815 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext)); 816 for (i = 0; i < len; i++) { 817 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) { 818 ath11k_dbg(ab, ATH11K_DBG_BOOT, 819 "bdf variant name contains non ascii chars.\n"); 820 return; 821 } 822 } 823 824 /* Copy extension name without magic prefix */ 825 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic), 826 sizeof(ab->qmi.target.bdf_ext)); 827 if (copied < 0) { 828 ath11k_dbg(ab, ATH11K_DBG_BOOT, 829 "bdf variant string is longer than the buffer can accommodate\n"); 830 return; 831 } 832 833 ath11k_dbg(ab, ATH11K_DBG_BOOT, 834 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 835 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext); 836 } 837 838 int ath11k_core_check_smbios(struct ath11k_base *ab) 839 { 840 ab->qmi.target.bdf_ext[0] = '\0'; 841 dmi_walk(ath11k_core_check_cc_code_bdfext, ab); 842 843 if (ab->qmi.target.bdf_ext[0] == '\0') 844 return -ENODATA; 845 846 return 0; 847 } 848 849 int ath11k_core_check_dt(struct ath11k_base *ab) 850 { 851 size_t max_len = sizeof(ab->qmi.target.bdf_ext); 852 const char *variant = NULL; 853 struct device_node *node; 854 855 node = ab->dev->of_node; 856 if (!node) 857 return -ENOENT; 858 859 of_property_read_string(node, "qcom,ath11k-calibration-variant", 860 &variant); 861 if (!variant) 862 return -ENODATA; 863 864 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0) 865 ath11k_dbg(ab, ATH11K_DBG_BOOT, 866 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 867 variant); 868 869 return 0; 870 } 871 872 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 873 size_t name_len, bool with_variant) 874 { 875 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ 876 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; 877 878 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0') 879 scnprintf(variant, sizeof(variant), ",variant=%s", 880 ab->qmi.target.bdf_ext); 881 882 switch (ab->id.bdf_search) { 883 case ATH11K_BDF_SEARCH_BUS_AND_BOARD: 884 scnprintf(name, name_len, 885 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", 886 ath11k_bus_str(ab->hif.bus), 887 ab->id.vendor, ab->id.device, 888 ab->id.subsystem_vendor, 889 ab->id.subsystem_device, 890 ab->qmi.target.chip_id, 891 ab->qmi.target.board_id, 892 variant); 893 break; 894 default: 895 scnprintf(name, name_len, 896 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s", 897 ath11k_bus_str(ab->hif.bus), 898 ab->qmi.target.chip_id, 899 ab->qmi.target.board_id, variant); 900 break; 901 } 902 903 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot using board name '%s'\n", name); 904 905 return 0; 906 } 907 908 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 909 size_t name_len) 910 { 911 return __ath11k_core_create_board_name(ab, name, name_len, true); 912 } 913 914 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name, 915 size_t name_len) 916 { 917 return __ath11k_core_create_board_name(ab, name, name_len, false); 918 } 919 920 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, 921 const char *file) 922 { 923 const struct firmware *fw; 924 char path[100]; 925 int ret; 926 927 if (file == NULL) 928 return ERR_PTR(-ENOENT); 929 930 ath11k_core_create_firmware_path(ab, file, path, sizeof(path)); 931 932 ret = firmware_request_nowarn(&fw, path, ab->dev); 933 if (ret) 934 return ERR_PTR(ret); 935 936 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot firmware request %s size %zu\n", 937 path, fw->size); 938 939 return fw; 940 } 941 942 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 943 { 944 if (!IS_ERR(bd->fw)) 945 release_firmware(bd->fw); 946 947 memset(bd, 0, sizeof(*bd)); 948 } 949 950 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab, 951 struct ath11k_board_data *bd, 952 const void *buf, size_t buf_len, 953 const char *boardname, 954 int ie_id, 955 int name_id, 956 int data_id) 957 { 958 const struct ath11k_fw_ie *hdr; 959 bool name_match_found; 960 int ret, board_ie_id; 961 size_t board_ie_len; 962 const void *board_ie_data; 963 964 name_match_found = false; 965 966 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */ 967 while (buf_len > sizeof(struct ath11k_fw_ie)) { 968 hdr = buf; 969 board_ie_id = le32_to_cpu(hdr->id); 970 board_ie_len = le32_to_cpu(hdr->len); 971 board_ie_data = hdr->data; 972 973 buf_len -= sizeof(*hdr); 974 buf += sizeof(*hdr); 975 976 if (buf_len < ALIGN(board_ie_len, 4)) { 977 ath11k_err(ab, "invalid %s length: %zu < %zu\n", 978 ath11k_bd_ie_type_str(ie_id), 979 buf_len, ALIGN(board_ie_len, 4)); 980 ret = -EINVAL; 981 goto out; 982 } 983 984 if (board_ie_id == name_id) { 985 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "", 986 board_ie_data, board_ie_len); 987 988 if (board_ie_len != strlen(boardname)) 989 goto next; 990 991 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 992 if (ret) 993 goto next; 994 995 name_match_found = true; 996 ath11k_dbg(ab, ATH11K_DBG_BOOT, 997 "boot found match %s for name '%s'", 998 ath11k_bd_ie_type_str(ie_id), 999 boardname); 1000 } else if (board_ie_id == data_id) { 1001 if (!name_match_found) 1002 /* no match found */ 1003 goto next; 1004 1005 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1006 "boot found %s for '%s'", 1007 ath11k_bd_ie_type_str(ie_id), 1008 boardname); 1009 1010 bd->data = board_ie_data; 1011 bd->len = board_ie_len; 1012 1013 ret = 0; 1014 goto out; 1015 } else { 1016 ath11k_warn(ab, "unknown %s id found: %d\n", 1017 ath11k_bd_ie_type_str(ie_id), 1018 board_ie_id); 1019 } 1020 next: 1021 /* jump over the padding */ 1022 board_ie_len = ALIGN(board_ie_len, 4); 1023 1024 buf_len -= board_ie_len; 1025 buf += board_ie_len; 1026 } 1027 1028 /* no match found */ 1029 ret = -ENOENT; 1030 1031 out: 1032 return ret; 1033 } 1034 1035 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab, 1036 struct ath11k_board_data *bd, 1037 const char *boardname, 1038 int ie_id_match, 1039 int name_id, 1040 int data_id) 1041 { 1042 size_t len, magic_len; 1043 const u8 *data; 1044 char *filename, filepath[100]; 1045 size_t ie_len; 1046 struct ath11k_fw_ie *hdr; 1047 int ret, ie_id; 1048 1049 filename = ATH11K_BOARD_API2_FILE; 1050 1051 if (!bd->fw) 1052 bd->fw = ath11k_core_firmware_request(ab, filename); 1053 1054 if (IS_ERR(bd->fw)) 1055 return PTR_ERR(bd->fw); 1056 1057 data = bd->fw->data; 1058 len = bd->fw->size; 1059 1060 ath11k_core_create_firmware_path(ab, filename, 1061 filepath, sizeof(filepath)); 1062 1063 /* magic has extra null byte padded */ 1064 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1; 1065 if (len < magic_len) { 1066 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n", 1067 filepath, len); 1068 ret = -EINVAL; 1069 goto err; 1070 } 1071 1072 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) { 1073 ath11k_err(ab, "found invalid board magic\n"); 1074 ret = -EINVAL; 1075 goto err; 1076 } 1077 1078 /* magic is padded to 4 bytes */ 1079 magic_len = ALIGN(magic_len, 4); 1080 if (len < magic_len) { 1081 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n", 1082 filepath, len); 1083 ret = -EINVAL; 1084 goto err; 1085 } 1086 1087 data += magic_len; 1088 len -= magic_len; 1089 1090 while (len > sizeof(struct ath11k_fw_ie)) { 1091 hdr = (struct ath11k_fw_ie *)data; 1092 ie_id = le32_to_cpu(hdr->id); 1093 ie_len = le32_to_cpu(hdr->len); 1094 1095 len -= sizeof(*hdr); 1096 data = hdr->data; 1097 1098 if (len < ALIGN(ie_len, 4)) { 1099 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1100 ie_id, ie_len, len); 1101 ret = -EINVAL; 1102 goto err; 1103 } 1104 1105 if (ie_id == ie_id_match) { 1106 ret = ath11k_core_parse_bd_ie_board(ab, bd, data, 1107 ie_len, 1108 boardname, 1109 ie_id_match, 1110 name_id, 1111 data_id); 1112 if (ret == -ENOENT) 1113 /* no match found, continue */ 1114 goto next; 1115 else if (ret) 1116 /* there was an error, bail out */ 1117 goto err; 1118 /* either found or error, so stop searching */ 1119 goto out; 1120 } 1121 next: 1122 /* jump over the padding */ 1123 ie_len = ALIGN(ie_len, 4); 1124 1125 len -= ie_len; 1126 data += ie_len; 1127 } 1128 1129 out: 1130 if (!bd->data || !bd->len) { 1131 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1132 "failed to fetch %s for %s from %s\n", 1133 ath11k_bd_ie_type_str(ie_id_match), 1134 boardname, filepath); 1135 ret = -ENODATA; 1136 goto err; 1137 } 1138 1139 return 0; 1140 1141 err: 1142 ath11k_core_free_bdf(ab, bd); 1143 return ret; 1144 } 1145 1146 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab, 1147 struct ath11k_board_data *bd, 1148 const char *name) 1149 { 1150 bd->fw = ath11k_core_firmware_request(ab, name); 1151 1152 if (IS_ERR(bd->fw)) 1153 return PTR_ERR(bd->fw); 1154 1155 bd->data = bd->fw->data; 1156 bd->len = bd->fw->size; 1157 1158 return 0; 1159 } 1160 1161 #define BOARD_NAME_SIZE 200 1162 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1163 { 1164 char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE]; 1165 char *filename, filepath[100]; 1166 int ret; 1167 1168 filename = ATH11K_BOARD_API2_FILE; 1169 1170 ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname)); 1171 if (ret) { 1172 ath11k_err(ab, "failed to create board name: %d", ret); 1173 return ret; 1174 } 1175 1176 ab->bd_api = 2; 1177 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1178 ATH11K_BD_IE_BOARD, 1179 ATH11K_BD_IE_BOARD_NAME, 1180 ATH11K_BD_IE_BOARD_DATA); 1181 if (!ret) 1182 goto success; 1183 1184 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname, 1185 sizeof(fallback_boardname)); 1186 if (ret) { 1187 ath11k_err(ab, "failed to create fallback board name: %d", ret); 1188 return ret; 1189 } 1190 1191 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname, 1192 ATH11K_BD_IE_BOARD, 1193 ATH11K_BD_IE_BOARD_NAME, 1194 ATH11K_BD_IE_BOARD_DATA); 1195 if (!ret) 1196 goto success; 1197 1198 ab->bd_api = 1; 1199 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE); 1200 if (ret) { 1201 ath11k_core_create_firmware_path(ab, filename, 1202 filepath, sizeof(filepath)); 1203 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1204 boardname, filepath); 1205 if (memcmp(boardname, fallback_boardname, strlen(boardname))) 1206 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1207 fallback_boardname, filepath); 1208 1209 ath11k_err(ab, "failed to fetch board.bin from %s\n", 1210 ab->hw_params.fw.dir); 1211 return ret; 1212 } 1213 1214 success: 1215 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api); 1216 return 0; 1217 } 1218 1219 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd) 1220 { 1221 char boardname[BOARD_NAME_SIZE]; 1222 int ret; 1223 1224 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1225 if (ret) { 1226 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1227 "failed to create board name for regdb: %d", ret); 1228 goto exit; 1229 } 1230 1231 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1232 ATH11K_BD_IE_REGDB, 1233 ATH11K_BD_IE_REGDB_NAME, 1234 ATH11K_BD_IE_REGDB_DATA); 1235 if (!ret) 1236 goto exit; 1237 1238 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME); 1239 if (ret) 1240 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n", 1241 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir); 1242 1243 exit: 1244 if (!ret) 1245 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n"); 1246 1247 return ret; 1248 } 1249 1250 static void ath11k_core_stop(struct ath11k_base *ab) 1251 { 1252 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 1253 ath11k_qmi_firmware_stop(ab); 1254 1255 ath11k_hif_stop(ab); 1256 ath11k_wmi_detach(ab); 1257 ath11k_dp_pdev_reo_cleanup(ab); 1258 1259 /* De-Init of components as needed */ 1260 } 1261 1262 static int ath11k_core_soc_create(struct ath11k_base *ab) 1263 { 1264 int ret; 1265 1266 ret = ath11k_qmi_init_service(ab); 1267 if (ret) { 1268 ath11k_err(ab, "failed to initialize qmi :%d\n", ret); 1269 return ret; 1270 } 1271 1272 ret = ath11k_debugfs_soc_create(ab); 1273 if (ret) { 1274 ath11k_err(ab, "failed to create ath11k debugfs\n"); 1275 goto err_qmi_deinit; 1276 } 1277 1278 ret = ath11k_hif_power_up(ab); 1279 if (ret) { 1280 ath11k_err(ab, "failed to power up :%d\n", ret); 1281 goto err_debugfs_reg; 1282 } 1283 1284 return 0; 1285 1286 err_debugfs_reg: 1287 ath11k_debugfs_soc_destroy(ab); 1288 err_qmi_deinit: 1289 ath11k_qmi_deinit_service(ab); 1290 return ret; 1291 } 1292 1293 static void ath11k_core_soc_destroy(struct ath11k_base *ab) 1294 { 1295 ath11k_debugfs_soc_destroy(ab); 1296 ath11k_dp_free(ab); 1297 ath11k_reg_free(ab); 1298 ath11k_qmi_deinit_service(ab); 1299 } 1300 1301 static int ath11k_core_pdev_create(struct ath11k_base *ab) 1302 { 1303 int ret; 1304 1305 ret = ath11k_debugfs_pdev_create(ab); 1306 if (ret) { 1307 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret); 1308 return ret; 1309 } 1310 1311 ret = ath11k_dp_pdev_alloc(ab); 1312 if (ret) { 1313 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret); 1314 goto err_pdev_debug; 1315 } 1316 1317 ret = ath11k_mac_register(ab); 1318 if (ret) { 1319 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret); 1320 goto err_dp_pdev_free; 1321 } 1322 1323 ret = ath11k_thermal_register(ab); 1324 if (ret) { 1325 ath11k_err(ab, "could not register thermal device: %d\n", 1326 ret); 1327 goto err_mac_unregister; 1328 } 1329 1330 ret = ath11k_spectral_init(ab); 1331 if (ret) { 1332 ath11k_err(ab, "failed to init spectral %d\n", ret); 1333 goto err_thermal_unregister; 1334 } 1335 1336 return 0; 1337 1338 err_thermal_unregister: 1339 ath11k_thermal_unregister(ab); 1340 err_mac_unregister: 1341 ath11k_mac_unregister(ab); 1342 err_dp_pdev_free: 1343 ath11k_dp_pdev_free(ab); 1344 err_pdev_debug: 1345 ath11k_debugfs_pdev_destroy(ab); 1346 1347 return ret; 1348 } 1349 1350 static void ath11k_core_pdev_destroy(struct ath11k_base *ab) 1351 { 1352 ath11k_spectral_deinit(ab); 1353 ath11k_thermal_unregister(ab); 1354 ath11k_mac_unregister(ab); 1355 ath11k_hif_irq_disable(ab); 1356 ath11k_dp_pdev_free(ab); 1357 ath11k_debugfs_pdev_destroy(ab); 1358 } 1359 1360 static int ath11k_core_start(struct ath11k_base *ab) 1361 { 1362 int ret; 1363 1364 ret = ath11k_wmi_attach(ab); 1365 if (ret) { 1366 ath11k_err(ab, "failed to attach wmi: %d\n", ret); 1367 return ret; 1368 } 1369 1370 ret = ath11k_htc_init(ab); 1371 if (ret) { 1372 ath11k_err(ab, "failed to init htc: %d\n", ret); 1373 goto err_wmi_detach; 1374 } 1375 1376 ret = ath11k_hif_start(ab); 1377 if (ret) { 1378 ath11k_err(ab, "failed to start HIF: %d\n", ret); 1379 goto err_wmi_detach; 1380 } 1381 1382 ret = ath11k_htc_wait_target(&ab->htc); 1383 if (ret) { 1384 ath11k_err(ab, "failed to connect to HTC: %d\n", ret); 1385 goto err_hif_stop; 1386 } 1387 1388 ret = ath11k_dp_htt_connect(&ab->dp); 1389 if (ret) { 1390 ath11k_err(ab, "failed to connect to HTT: %d\n", ret); 1391 goto err_hif_stop; 1392 } 1393 1394 ret = ath11k_wmi_connect(ab); 1395 if (ret) { 1396 ath11k_err(ab, "failed to connect wmi: %d\n", ret); 1397 goto err_hif_stop; 1398 } 1399 1400 ret = ath11k_htc_start(&ab->htc); 1401 if (ret) { 1402 ath11k_err(ab, "failed to start HTC: %d\n", ret); 1403 goto err_hif_stop; 1404 } 1405 1406 ret = ath11k_wmi_wait_for_service_ready(ab); 1407 if (ret) { 1408 ath11k_err(ab, "failed to receive wmi service ready event: %d\n", 1409 ret); 1410 goto err_hif_stop; 1411 } 1412 1413 ret = ath11k_mac_allocate(ab); 1414 if (ret) { 1415 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n", 1416 ret); 1417 goto err_hif_stop; 1418 } 1419 1420 ath11k_dp_pdev_pre_alloc(ab); 1421 1422 ret = ath11k_dp_pdev_reo_setup(ab); 1423 if (ret) { 1424 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret); 1425 goto err_mac_destroy; 1426 } 1427 1428 ret = ath11k_wmi_cmd_init(ab); 1429 if (ret) { 1430 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret); 1431 goto err_reo_cleanup; 1432 } 1433 1434 ret = ath11k_wmi_wait_for_unified_ready(ab); 1435 if (ret) { 1436 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n", 1437 ret); 1438 goto err_reo_cleanup; 1439 } 1440 1441 /* put hardware to DBS mode */ 1442 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) { 1443 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS); 1444 if (ret) { 1445 ath11k_err(ab, "failed to send dbs mode: %d\n", ret); 1446 goto err_hif_stop; 1447 } 1448 } 1449 1450 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab); 1451 if (ret) { 1452 ath11k_err(ab, "failed to send htt version request message: %d\n", 1453 ret); 1454 goto err_reo_cleanup; 1455 } 1456 1457 return 0; 1458 1459 err_reo_cleanup: 1460 ath11k_dp_pdev_reo_cleanup(ab); 1461 err_mac_destroy: 1462 ath11k_mac_destroy(ab); 1463 err_hif_stop: 1464 ath11k_hif_stop(ab); 1465 err_wmi_detach: 1466 ath11k_wmi_detach(ab); 1467 1468 return ret; 1469 } 1470 1471 static int ath11k_core_start_firmware(struct ath11k_base *ab, 1472 enum ath11k_firmware_mode mode) 1473 { 1474 int ret; 1475 1476 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2, 1477 &ab->qmi.ce_cfg.shadow_reg_v2_len); 1478 1479 ret = ath11k_qmi_firmware_start(ab, mode); 1480 if (ret) { 1481 ath11k_err(ab, "failed to send firmware start: %d\n", ret); 1482 return ret; 1483 } 1484 1485 return ret; 1486 } 1487 1488 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab) 1489 { 1490 int ret; 1491 1492 ret = ath11k_core_start_firmware(ab, ATH11K_FIRMWARE_MODE_NORMAL); 1493 if (ret) { 1494 ath11k_err(ab, "failed to start firmware: %d\n", ret); 1495 return ret; 1496 } 1497 1498 ret = ath11k_ce_init_pipes(ab); 1499 if (ret) { 1500 ath11k_err(ab, "failed to initialize CE: %d\n", ret); 1501 goto err_firmware_stop; 1502 } 1503 1504 ret = ath11k_dp_alloc(ab); 1505 if (ret) { 1506 ath11k_err(ab, "failed to init DP: %d\n", ret); 1507 goto err_firmware_stop; 1508 } 1509 1510 switch (ath11k_crypto_mode) { 1511 case ATH11K_CRYPT_MODE_SW: 1512 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1513 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1514 break; 1515 case ATH11K_CRYPT_MODE_HW: 1516 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1517 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1518 break; 1519 default: 1520 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode); 1521 return -EINVAL; 1522 } 1523 1524 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW) 1525 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1526 1527 mutex_lock(&ab->core_lock); 1528 ret = ath11k_core_start(ab); 1529 if (ret) { 1530 ath11k_err(ab, "failed to start core: %d\n", ret); 1531 goto err_dp_free; 1532 } 1533 1534 ret = ath11k_core_pdev_create(ab); 1535 if (ret) { 1536 ath11k_err(ab, "failed to create pdev core: %d\n", ret); 1537 goto err_core_stop; 1538 } 1539 ath11k_hif_irq_enable(ab); 1540 mutex_unlock(&ab->core_lock); 1541 1542 return 0; 1543 1544 err_core_stop: 1545 ath11k_core_stop(ab); 1546 ath11k_mac_destroy(ab); 1547 err_dp_free: 1548 ath11k_dp_free(ab); 1549 mutex_unlock(&ab->core_lock); 1550 err_firmware_stop: 1551 ath11k_qmi_firmware_stop(ab); 1552 1553 return ret; 1554 } 1555 1556 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab) 1557 { 1558 int ret; 1559 1560 mutex_lock(&ab->core_lock); 1561 ath11k_thermal_unregister(ab); 1562 ath11k_hif_irq_disable(ab); 1563 ath11k_dp_pdev_free(ab); 1564 ath11k_spectral_deinit(ab); 1565 ath11k_hif_stop(ab); 1566 ath11k_wmi_detach(ab); 1567 ath11k_dp_pdev_reo_cleanup(ab); 1568 mutex_unlock(&ab->core_lock); 1569 1570 ath11k_dp_free(ab); 1571 ath11k_hal_srng_deinit(ab); 1572 1573 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1; 1574 1575 ret = ath11k_hal_srng_init(ab); 1576 if (ret) 1577 return ret; 1578 1579 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags); 1580 1581 ret = ath11k_core_qmi_firmware_ready(ab); 1582 if (ret) 1583 goto err_hal_srng_deinit; 1584 1585 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags); 1586 1587 return 0; 1588 1589 err_hal_srng_deinit: 1590 ath11k_hal_srng_deinit(ab); 1591 return ret; 1592 } 1593 1594 void ath11k_core_halt(struct ath11k *ar) 1595 { 1596 struct ath11k_base *ab = ar->ab; 1597 1598 lockdep_assert_held(&ar->conf_mutex); 1599 1600 ar->num_created_vdevs = 0; 1601 ar->allocated_vdev_map = 0; 1602 1603 ath11k_mac_scan_finish(ar); 1604 ath11k_mac_peer_cleanup_all(ar); 1605 cancel_delayed_work_sync(&ar->scan.timeout); 1606 cancel_work_sync(&ar->regd_update_work); 1607 cancel_work_sync(&ab->update_11d_work); 1608 1609 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL); 1610 synchronize_rcu(); 1611 INIT_LIST_HEAD(&ar->arvifs); 1612 idr_init(&ar->txmgmt_idr); 1613 } 1614 1615 static void ath11k_update_11d(struct work_struct *work) 1616 { 1617 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work); 1618 struct ath11k *ar; 1619 struct ath11k_pdev *pdev; 1620 struct wmi_set_current_country_params set_current_param = {}; 1621 int ret, i; 1622 1623 spin_lock_bh(&ab->base_lock); 1624 memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2); 1625 spin_unlock_bh(&ab->base_lock); 1626 1627 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n", 1628 set_current_param.alpha2[0], 1629 set_current_param.alpha2[1]); 1630 1631 for (i = 0; i < ab->num_radios; i++) { 1632 pdev = &ab->pdevs[i]; 1633 ar = pdev->ar; 1634 1635 memcpy(&ar->alpha2, &set_current_param.alpha2, 2); 1636 ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param); 1637 if (ret) 1638 ath11k_warn(ar->ab, 1639 "pdev id %d failed set current country code: %d\n", 1640 i, ret); 1641 } 1642 } 1643 1644 static void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab) 1645 { 1646 struct ath11k *ar; 1647 struct ath11k_pdev *pdev; 1648 int i; 1649 1650 spin_lock_bh(&ab->base_lock); 1651 ab->stats.fw_crash_counter++; 1652 spin_unlock_bh(&ab->base_lock); 1653 1654 for (i = 0; i < ab->num_radios; i++) { 1655 pdev = &ab->pdevs[i]; 1656 ar = pdev->ar; 1657 if (!ar || ar->state == ATH11K_STATE_OFF) 1658 continue; 1659 1660 ieee80211_stop_queues(ar->hw); 1661 ath11k_mac_drain_tx(ar); 1662 ar->state_11d = ATH11K_11D_IDLE; 1663 complete(&ar->completed_11d_scan); 1664 complete(&ar->scan.started); 1665 complete_all(&ar->scan.completed); 1666 complete(&ar->scan.on_channel); 1667 complete(&ar->peer_assoc_done); 1668 complete(&ar->peer_delete_done); 1669 complete(&ar->install_key_done); 1670 complete(&ar->vdev_setup_done); 1671 complete(&ar->vdev_delete_done); 1672 complete(&ar->bss_survey_done); 1673 complete(&ar->thermal.wmi_sync); 1674 1675 wake_up(&ar->dp.tx_empty_waitq); 1676 idr_for_each(&ar->txmgmt_idr, 1677 ath11k_mac_tx_mgmt_pending_free, ar); 1678 idr_destroy(&ar->txmgmt_idr); 1679 wake_up(&ar->txmgmt_empty_waitq); 1680 } 1681 1682 wake_up(&ab->wmi_ab.tx_credits_wq); 1683 wake_up(&ab->peer_mapping_wq); 1684 1685 reinit_completion(&ab->driver_recovery); 1686 } 1687 1688 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab) 1689 { 1690 struct ath11k *ar; 1691 struct ath11k_pdev *pdev; 1692 int i; 1693 1694 for (i = 0; i < ab->num_radios; i++) { 1695 pdev = &ab->pdevs[i]; 1696 ar = pdev->ar; 1697 if (!ar || ar->state == ATH11K_STATE_OFF) 1698 continue; 1699 1700 mutex_lock(&ar->conf_mutex); 1701 1702 switch (ar->state) { 1703 case ATH11K_STATE_ON: 1704 ar->state = ATH11K_STATE_RESTARTING; 1705 ath11k_core_halt(ar); 1706 ieee80211_restart_hw(ar->hw); 1707 break; 1708 case ATH11K_STATE_OFF: 1709 ath11k_warn(ab, 1710 "cannot restart radio %d that hasn't been started\n", 1711 i); 1712 break; 1713 case ATH11K_STATE_RESTARTING: 1714 break; 1715 case ATH11K_STATE_RESTARTED: 1716 ar->state = ATH11K_STATE_WEDGED; 1717 fallthrough; 1718 case ATH11K_STATE_WEDGED: 1719 ath11k_warn(ab, 1720 "device is wedged, will not restart radio %d\n", i); 1721 break; 1722 } 1723 mutex_unlock(&ar->conf_mutex); 1724 } 1725 complete(&ab->driver_recovery); 1726 } 1727 1728 static void ath11k_core_restart(struct work_struct *work) 1729 { 1730 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work); 1731 int ret; 1732 1733 if (!ab->is_reset) 1734 ath11k_core_pre_reconfigure_recovery(ab); 1735 1736 ret = ath11k_core_reconfigure_on_crash(ab); 1737 if (ret) { 1738 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n"); 1739 return; 1740 } 1741 1742 if (ab->is_reset) 1743 complete_all(&ab->reconfigure_complete); 1744 1745 if (!ab->is_reset) 1746 ath11k_core_post_reconfigure_recovery(ab); 1747 } 1748 1749 static void ath11k_core_reset(struct work_struct *work) 1750 { 1751 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work); 1752 int reset_count, fail_cont_count; 1753 long time_left; 1754 1755 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) { 1756 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags); 1757 return; 1758 } 1759 1760 /* Sometimes the recovery will fail and then the next all recovery fail, 1761 * this is to avoid infinite recovery since it can not recovery success. 1762 */ 1763 fail_cont_count = atomic_read(&ab->fail_cont_count); 1764 1765 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL) 1766 return; 1767 1768 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST && 1769 time_before(jiffies, ab->reset_fail_timeout)) 1770 return; 1771 1772 reset_count = atomic_inc_return(&ab->reset_count); 1773 1774 if (reset_count > 1) { 1775 /* Sometimes it happened another reset worker before the previous one 1776 * completed, then the second reset worker will destroy the previous one, 1777 * thus below is to avoid that. 1778 */ 1779 ath11k_warn(ab, "already resetting count %d\n", reset_count); 1780 1781 reinit_completion(&ab->reset_complete); 1782 time_left = wait_for_completion_timeout(&ab->reset_complete, 1783 ATH11K_RESET_TIMEOUT_HZ); 1784 1785 if (time_left) { 1786 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n"); 1787 atomic_dec(&ab->reset_count); 1788 return; 1789 } 1790 1791 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ; 1792 /* Record the continuous recovery fail count when recovery failed*/ 1793 atomic_inc(&ab->fail_cont_count); 1794 } 1795 1796 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n"); 1797 1798 ab->is_reset = true; 1799 atomic_set(&ab->recovery_count, 0); 1800 reinit_completion(&ab->recovery_start); 1801 atomic_set(&ab->recovery_start_count, 0); 1802 1803 ath11k_core_pre_reconfigure_recovery(ab); 1804 1805 reinit_completion(&ab->reconfigure_complete); 1806 ath11k_core_post_reconfigure_recovery(ab); 1807 1808 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n"); 1809 1810 time_left = wait_for_completion_timeout(&ab->recovery_start, 1811 ATH11K_RECOVER_START_TIMEOUT_HZ); 1812 1813 ath11k_hif_power_down(ab); 1814 ath11k_hif_power_up(ab); 1815 1816 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n"); 1817 } 1818 1819 static int ath11k_init_hw_params(struct ath11k_base *ab) 1820 { 1821 const struct ath11k_hw_params *hw_params = NULL; 1822 int i; 1823 1824 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) { 1825 hw_params = &ath11k_hw_params[i]; 1826 1827 if (hw_params->hw_rev == ab->hw_rev) 1828 break; 1829 } 1830 1831 if (i == ARRAY_SIZE(ath11k_hw_params)) { 1832 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 1833 return -EINVAL; 1834 } 1835 1836 ab->hw_params = *hw_params; 1837 1838 ath11k_info(ab, "%s\n", ab->hw_params.name); 1839 1840 return 0; 1841 } 1842 1843 int ath11k_core_pre_init(struct ath11k_base *ab) 1844 { 1845 int ret; 1846 1847 ret = ath11k_init_hw_params(ab); 1848 if (ret) { 1849 ath11k_err(ab, "failed to get hw params: %d\n", ret); 1850 return ret; 1851 } 1852 1853 return 0; 1854 } 1855 EXPORT_SYMBOL(ath11k_core_pre_init); 1856 1857 int ath11k_core_init(struct ath11k_base *ab) 1858 { 1859 int ret; 1860 1861 ret = ath11k_core_soc_create(ab); 1862 if (ret) { 1863 ath11k_err(ab, "failed to create soc core: %d\n", ret); 1864 return ret; 1865 } 1866 1867 return 0; 1868 } 1869 EXPORT_SYMBOL(ath11k_core_init); 1870 1871 void ath11k_core_deinit(struct ath11k_base *ab) 1872 { 1873 mutex_lock(&ab->core_lock); 1874 1875 ath11k_core_pdev_destroy(ab); 1876 ath11k_core_stop(ab); 1877 1878 mutex_unlock(&ab->core_lock); 1879 1880 ath11k_hif_power_down(ab); 1881 ath11k_mac_destroy(ab); 1882 ath11k_core_soc_destroy(ab); 1883 } 1884 EXPORT_SYMBOL(ath11k_core_deinit); 1885 1886 void ath11k_core_free(struct ath11k_base *ab) 1887 { 1888 destroy_workqueue(ab->workqueue_aux); 1889 destroy_workqueue(ab->workqueue); 1890 1891 kfree(ab); 1892 } 1893 EXPORT_SYMBOL(ath11k_core_free); 1894 1895 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size, 1896 enum ath11k_bus bus) 1897 { 1898 struct ath11k_base *ab; 1899 1900 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL); 1901 if (!ab) 1902 return NULL; 1903 1904 init_completion(&ab->driver_recovery); 1905 1906 ab->workqueue = create_singlethread_workqueue("ath11k_wq"); 1907 if (!ab->workqueue) 1908 goto err_sc_free; 1909 1910 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq"); 1911 if (!ab->workqueue_aux) 1912 goto err_free_wq; 1913 1914 mutex_init(&ab->core_lock); 1915 mutex_init(&ab->tbl_mtx_lock); 1916 spin_lock_init(&ab->base_lock); 1917 mutex_init(&ab->vdev_id_11d_lock); 1918 init_completion(&ab->reset_complete); 1919 init_completion(&ab->reconfigure_complete); 1920 init_completion(&ab->recovery_start); 1921 1922 INIT_LIST_HEAD(&ab->peers); 1923 init_waitqueue_head(&ab->peer_mapping_wq); 1924 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq); 1925 init_waitqueue_head(&ab->qmi.cold_boot_waitq); 1926 INIT_WORK(&ab->restart_work, ath11k_core_restart); 1927 INIT_WORK(&ab->update_11d_work, ath11k_update_11d); 1928 INIT_WORK(&ab->reset_work, ath11k_core_reset); 1929 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0); 1930 init_completion(&ab->htc_suspend); 1931 init_completion(&ab->wow.wakeup_completed); 1932 1933 ab->dev = dev; 1934 ab->hif.bus = bus; 1935 1936 return ab; 1937 1938 err_free_wq: 1939 destroy_workqueue(ab->workqueue); 1940 err_sc_free: 1941 kfree(ab); 1942 return NULL; 1943 } 1944 EXPORT_SYMBOL(ath11k_core_alloc); 1945 1946 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards."); 1947 MODULE_LICENSE("Dual BSD/GPL"); 1948