1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/types.h> 8 #include <linux/bitops.h> 9 #include <linux/bitfield.h> 10 11 #include "core.h" 12 #include "ce.h" 13 #include "hif.h" 14 #include "hal.h" 15 #include "hw.h" 16 17 /* Map from pdev index to hw mac index */ 18 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 19 { 20 switch (pdev_idx) { 21 case 0: 22 return 0; 23 case 1: 24 return 2; 25 case 2: 26 return 1; 27 default: 28 return ATH11K_INVALID_HW_MAC_ID; 29 } 30 } 31 32 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 33 { 34 return pdev_idx; 35 } 36 37 static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab, 38 struct hal_tcl_data_cmd *tcl_cmd) 39 { 40 tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE, 41 true); 42 } 43 44 static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab, 45 struct hal_tcl_data_cmd *tcl_cmd) 46 { 47 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 48 true); 49 } 50 51 static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab, 52 struct hal_tcl_data_cmd *tcl_cmd) 53 { 54 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 55 true); 56 } 57 58 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 59 struct target_resource_config *config) 60 { 61 config->num_vdevs = 4; 62 config->num_peers = 16; 63 config->num_tids = 32; 64 65 config->num_offload_peers = 3; 66 config->num_offload_reorder_buffs = 3; 67 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 68 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 69 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 70 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 71 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 72 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 73 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 74 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 75 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 76 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 77 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 78 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 79 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 80 config->num_mcast_groups = 0; 81 config->num_mcast_table_elems = 0; 82 config->mcast2ucast_mode = 0; 83 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 84 config->num_wds_entries = 0; 85 config->dma_burst_size = 0; 86 config->rx_skip_defrag_timeout_dup_detection_check = 0; 87 config->vow_config = TARGET_VOW_CONFIG; 88 config->gtk_offload_max_vdev = 2; 89 config->num_msdu_desc = 0x400; 90 config->beacon_tx_offload_max_vdev = 2; 91 config->rx_batchmode = TARGET_RX_BATCHMODE; 92 93 config->peer_map_unmap_v2_support = 0; 94 config->use_pdev_id = 1; 95 config->max_frag_entries = 0xa; 96 config->num_tdls_vdevs = 0x1; 97 config->num_tdls_conn_table_entries = 8; 98 config->beacon_tx_offload_max_vdev = 0x2; 99 config->num_multicast_filter_entries = 0x20; 100 config->num_wow_filters = 0x16; 101 config->num_keep_alive_pattern = 0; 102 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 103 } 104 105 static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab) 106 { 107 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 108 u32 val; 109 /* Each hash entry uses three bits to map to a particular ring. */ 110 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 111 HAL_HASH_ROUTING_RING_SW2 << 3 | 112 HAL_HASH_ROUTING_RING_SW3 << 6 | 113 HAL_HASH_ROUTING_RING_SW4 << 9 | 114 HAL_HASH_ROUTING_RING_SW1 << 12 | 115 HAL_HASH_ROUTING_RING_SW2 << 15 | 116 HAL_HASH_ROUTING_RING_SW3 << 18 | 117 HAL_HASH_ROUTING_RING_SW4 << 21; 118 119 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 120 121 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; 122 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, 123 HAL_SRNG_RING_ID_REO2SW1) | 124 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 125 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 126 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 127 128 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 129 HAL_DEFAULT_REO_TIMEOUT_USEC); 130 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 131 HAL_DEFAULT_REO_TIMEOUT_USEC); 132 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 133 HAL_DEFAULT_REO_TIMEOUT_USEC); 134 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 135 HAL_DEFAULT_REO_TIMEOUT_USEC); 136 137 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, 138 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 139 ring_hash_map)); 140 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, 141 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 142 ring_hash_map)); 143 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 144 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 145 ring_hash_map)); 146 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 147 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 148 ring_hash_map)); 149 } 150 151 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 152 struct target_resource_config *config) 153 { 154 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS(ab); 155 156 if (ab->num_radios == 2) { 157 config->num_peers = TARGET_NUM_PEERS(ab, DBS); 158 config->num_tids = TARGET_NUM_TIDS(ab, DBS); 159 } else if (ab->num_radios == 3) { 160 config->num_peers = TARGET_NUM_PEERS(ab, DBS_SBS); 161 config->num_tids = TARGET_NUM_TIDS(ab, DBS_SBS); 162 } else { 163 /* Control should not reach here */ 164 config->num_peers = TARGET_NUM_PEERS(ab, SINGLE); 165 config->num_tids = TARGET_NUM_TIDS(ab, SINGLE); 166 } 167 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 168 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 169 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 170 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 171 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 172 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 173 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 174 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 175 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 176 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 177 178 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 179 config->rx_decap_mode = TARGET_DECAP_MODE_RAW; 180 else 181 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 182 183 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 184 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 185 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 186 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 187 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 188 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 189 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 190 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 191 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 192 config->dma_burst_size = TARGET_DMA_BURST_SIZE; 193 config->rx_skip_defrag_timeout_dup_detection_check = 194 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 195 config->vow_config = TARGET_VOW_CONFIG; 196 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 197 config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 198 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 199 config->rx_batchmode = TARGET_RX_BATCHMODE; 200 config->peer_map_unmap_v2_support = 1; 201 config->twt_ap_pdev_count = ab->num_radios; 202 config->twt_ap_sta_count = 1000; 203 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 204 } 205 206 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 207 int mac_id) 208 { 209 return mac_id; 210 } 211 212 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 213 int mac_id) 214 { 215 return 0; 216 } 217 218 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 219 int mac_id) 220 { 221 return 0; 222 } 223 224 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 225 int mac_id) 226 { 227 return mac_id; 228 } 229 230 static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 231 { 232 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, 233 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 234 } 235 236 static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 237 { 238 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU, 239 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 240 } 241 242 static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 243 { 244 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 245 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 246 } 247 248 static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 249 { 250 return desc->u.ipq8074.hdr_status; 251 } 252 253 static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 254 { 255 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 256 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 257 } 258 259 static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 260 { 261 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 262 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 263 } 264 265 static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 266 { 267 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 268 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 269 } 270 271 static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 272 { 273 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 274 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 275 } 276 277 static bool ath11k_hw_ipq8074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 278 { 279 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 280 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 281 } 282 283 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 284 { 285 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 286 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 287 } 288 289 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 290 { 291 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 292 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 293 } 294 295 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 296 { 297 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 298 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 299 } 300 301 static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 302 { 303 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 304 __le32_to_cpu(desc->u.ipq8074.msdu_start.info1)); 305 } 306 307 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 308 { 309 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 310 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 311 } 312 313 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 314 { 315 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 316 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 317 } 318 319 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 320 { 321 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 322 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 323 } 324 325 static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 326 { 327 return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data); 328 } 329 330 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 331 { 332 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 333 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 334 } 335 336 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 337 { 338 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 339 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 340 } 341 342 static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 343 { 344 return FIELD_GET(RX_MPDU_START_INFO2_TID, 345 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 346 } 347 348 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 349 { 350 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id); 351 } 352 353 static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 354 struct hal_rx_desc *ldesc) 355 { 356 memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end, 357 sizeof(struct rx_msdu_end_ipq8074)); 358 memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention, 359 sizeof(struct rx_attention)); 360 memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end, 361 sizeof(struct rx_mpdu_end)); 362 } 363 364 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 365 { 366 return FIELD_GET(HAL_TLV_HDR_TAG, 367 __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag)); 368 } 369 370 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 371 { 372 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id); 373 } 374 375 static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 376 { 377 u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1); 378 379 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 380 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 381 382 desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info); 383 } 384 385 static bool ath11k_hw_ipq8074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 386 { 387 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 388 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 389 } 390 391 static u8 *ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 392 { 393 return desc->u.ipq8074.mpdu_start.addr2; 394 } 395 396 static 397 struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc) 398 { 399 return &desc->u.ipq8074.attention; 400 } 401 402 static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 403 { 404 return &desc->u.ipq8074.msdu_payload[0]; 405 } 406 407 static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 408 { 409 return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU, 410 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 411 } 412 413 static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 414 { 415 return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU, 416 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 417 } 418 419 static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 420 { 421 return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING, 422 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 423 } 424 425 static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 426 { 427 return desc->u.qcn9074.hdr_status; 428 } 429 430 static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 431 { 432 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 433 RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID; 434 } 435 436 static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 437 { 438 return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE, 439 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 440 } 441 442 static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 443 { 444 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 445 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 446 } 447 448 static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 449 { 450 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 451 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 452 } 453 454 static bool ath11k_hw_qcn9074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 455 { 456 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 457 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 458 } 459 460 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 461 { 462 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID, 463 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 464 } 465 466 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 467 { 468 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID, 469 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 470 } 471 472 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 473 { 474 return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM, 475 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 476 } 477 478 static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 479 { 480 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 481 __le32_to_cpu(desc->u.qcn9074.msdu_start.info1)); 482 } 483 484 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 485 { 486 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 487 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 488 } 489 490 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 491 { 492 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 493 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 494 } 495 496 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 497 { 498 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 499 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 500 } 501 502 static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 503 { 504 return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data); 505 } 506 507 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 508 { 509 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 510 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 511 } 512 513 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 514 { 515 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 516 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 517 } 518 519 static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 520 { 521 return FIELD_GET(RX_MPDU_START_INFO9_TID, 522 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 523 } 524 525 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 526 { 527 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id); 528 } 529 530 static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 531 struct hal_rx_desc *ldesc) 532 { 533 memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end, 534 sizeof(struct rx_msdu_end_qcn9074)); 535 memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention, 536 sizeof(struct rx_attention)); 537 memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end, 538 sizeof(struct rx_mpdu_end)); 539 } 540 541 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 542 { 543 return FIELD_GET(HAL_TLV_HDR_TAG, 544 __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag)); 545 } 546 547 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 548 { 549 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id); 550 } 551 552 static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 553 { 554 u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1); 555 556 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 557 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 558 559 desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info); 560 } 561 562 static 563 struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc) 564 { 565 return &desc->u.qcn9074.attention; 566 } 567 568 static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 569 { 570 return &desc->u.qcn9074.msdu_payload[0]; 571 } 572 573 static bool ath11k_hw_ipq9074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 574 { 575 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 576 RX_MPDU_START_INFO11_MAC_ADDR2_VALID; 577 } 578 579 static u8 *ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 580 { 581 return desc->u.qcn9074.mpdu_start.addr2; 582 } 583 584 static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 585 { 586 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855, 587 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 588 } 589 590 static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 591 { 592 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855, 593 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 594 } 595 596 static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 597 { 598 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 599 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 600 } 601 602 static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 603 { 604 return desc->u.wcn6855.hdr_status; 605 } 606 607 static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 608 { 609 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 610 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 611 } 612 613 static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 614 { 615 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 616 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 617 } 618 619 static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc) 620 { 621 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 622 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 623 } 624 625 static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 626 { 627 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 628 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 629 } 630 631 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 632 { 633 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 634 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 635 } 636 637 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 638 { 639 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 640 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 641 } 642 643 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 644 { 645 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 646 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 647 } 648 649 static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 650 { 651 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 652 __le32_to_cpu(desc->u.wcn6855.msdu_start.info1)); 653 } 654 655 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 656 { 657 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 658 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 659 } 660 661 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 662 { 663 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 664 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 665 } 666 667 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 668 { 669 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 670 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 671 } 672 673 static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 674 { 675 return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data); 676 } 677 678 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 679 { 680 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 681 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 682 } 683 684 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 685 { 686 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 687 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 688 } 689 690 static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 691 { 692 return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855, 693 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 694 } 695 696 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 697 { 698 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id); 699 } 700 701 static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 702 struct hal_rx_desc *ldesc) 703 { 704 memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end, 705 sizeof(struct rx_msdu_end_wcn6855)); 706 memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention, 707 sizeof(struct rx_attention)); 708 memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end, 709 sizeof(struct rx_mpdu_end)); 710 } 711 712 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 713 { 714 return FIELD_GET(HAL_TLV_HDR_TAG, 715 __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag)); 716 } 717 718 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 719 { 720 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id); 721 } 722 723 static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 724 { 725 u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1); 726 727 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 728 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 729 730 desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info); 731 } 732 733 static 734 struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc) 735 { 736 return &desc->u.wcn6855.attention; 737 } 738 739 static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 740 { 741 return &desc->u.wcn6855.msdu_payload[0]; 742 } 743 744 static bool ath11k_hw_wcn6855_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 745 { 746 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 747 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 748 } 749 750 static u8 *ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 751 { 752 return desc->u.wcn6855.mpdu_start.addr2; 753 } 754 755 static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab) 756 { 757 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 758 u32 val; 759 /* Each hash entry uses four bits to map to a particular ring. */ 760 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 761 HAL_HASH_ROUTING_RING_SW2 << 4 | 762 HAL_HASH_ROUTING_RING_SW3 << 8 | 763 HAL_HASH_ROUTING_RING_SW4 << 12 | 764 HAL_HASH_ROUTING_RING_SW1 << 16 | 765 HAL_HASH_ROUTING_RING_SW2 << 20 | 766 HAL_HASH_ROUTING_RING_SW3 << 24 | 767 HAL_HASH_ROUTING_RING_SW4 << 28; 768 769 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 770 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 771 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 772 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 773 774 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL(ab)); 775 val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING; 776 val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1); 777 ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL(ab), val); 778 779 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 780 HAL_DEFAULT_REO_TIMEOUT_USEC); 781 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 782 HAL_DEFAULT_REO_TIMEOUT_USEC); 783 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 784 HAL_DEFAULT_REO_TIMEOUT_USEC); 785 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 786 HAL_DEFAULT_REO_TIMEOUT_USEC); 787 788 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 789 ring_hash_map); 790 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 791 ring_hash_map); 792 } 793 794 static void ath11k_hw_ipq5018_reo_setup(struct ath11k_base *ab) 795 { 796 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 797 u32 val; 798 799 /* Each hash entry uses three bits to map to a particular ring. */ 800 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 801 HAL_HASH_ROUTING_RING_SW2 << 4 | 802 HAL_HASH_ROUTING_RING_SW3 << 8 | 803 HAL_HASH_ROUTING_RING_SW4 << 12 | 804 HAL_HASH_ROUTING_RING_SW1 << 16 | 805 HAL_HASH_ROUTING_RING_SW2 << 20 | 806 HAL_HASH_ROUTING_RING_SW3 << 24 | 807 HAL_HASH_ROUTING_RING_SW4 << 28; 808 809 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 810 811 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; 812 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, 813 HAL_SRNG_RING_ID_REO2SW1) | 814 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 815 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 816 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 817 818 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 819 HAL_DEFAULT_REO_TIMEOUT_USEC); 820 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 821 HAL_DEFAULT_REO_TIMEOUT_USEC); 822 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 823 HAL_DEFAULT_REO_TIMEOUT_USEC); 824 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 825 HAL_DEFAULT_REO_TIMEOUT_USEC); 826 827 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, 828 ring_hash_map); 829 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, 830 ring_hash_map); 831 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 832 ring_hash_map); 833 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 834 ring_hash_map); 835 } 836 837 static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data) 838 { 839 u16 peer_id = 0; 840 struct hal_rx_mpdu_info *mpdu_info = 841 (struct hal_rx_mpdu_info *)tlv_data; 842 843 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID, 844 __le32_to_cpu(mpdu_info->info0)); 845 846 return peer_id; 847 } 848 849 static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data) 850 { 851 u16 peer_id = 0; 852 struct hal_rx_mpdu_info_wcn6855 *mpdu_info = 853 (struct hal_rx_mpdu_info_wcn6855 *)tlv_data; 854 855 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855, 856 __le32_to_cpu(mpdu_info->info0)); 857 return peer_id; 858 } 859 860 static bool ath11k_hw_wcn6855_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 861 { 862 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 863 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 864 } 865 866 static u32 ath11k_hw_ipq8074_get_tcl_ring_selector(struct sk_buff *skb) 867 { 868 /* Let the default ring selection be based on current processor 869 * number, where one of the 3 tcl rings are selected based on 870 * the smp_processor_id(). In case that ring 871 * is full/busy, we resort to other available rings. 872 * If all rings are full, we drop the packet. 873 * 874 * TODO: Add throttling logic when all rings are full 875 */ 876 return smp_processor_id(); 877 } 878 879 static u32 ath11k_hw_wcn6750_get_tcl_ring_selector(struct sk_buff *skb) 880 { 881 /* Select the TCL ring based on the flow hash of the SKB instead 882 * of CPU ID. Since applications pumping the traffic can be scheduled 883 * on multiple CPUs, there is a chance that packets of the same flow 884 * could end on different TCL rings, this could sometimes results in 885 * an out of order arrival of the packets at the receiver. 886 */ 887 return skb_get_hash(skb); 888 } 889 890 const struct ath11k_hw_ops ipq8074_ops = { 891 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 892 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 893 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 894 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 895 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 896 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 897 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 898 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 899 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 900 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 901 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 902 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 903 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 904 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 905 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 906 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 907 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 908 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 909 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 910 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 911 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 912 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 913 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 914 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 915 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 916 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 917 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 918 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 919 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 920 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 921 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 922 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 923 .reo_setup = ath11k_hw_ipq8074_reo_setup, 924 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 925 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 926 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 927 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 928 }; 929 930 const struct ath11k_hw_ops ipq6018_ops = { 931 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 932 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 933 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 934 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 935 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 936 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 937 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 938 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 939 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 940 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 941 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 942 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 943 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 944 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 945 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 946 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 947 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 948 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 949 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 950 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 951 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 952 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 953 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 954 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 955 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 956 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 957 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 958 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 959 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 960 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 961 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 962 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 963 .reo_setup = ath11k_hw_ipq8074_reo_setup, 964 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 965 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 966 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 967 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 968 }; 969 970 const struct ath11k_hw_ops qca6390_ops = { 971 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 972 .wmi_init_config = ath11k_init_wmi_config_qca6390, 973 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 974 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 975 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 976 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 977 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 978 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 979 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 980 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 981 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 982 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 983 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 984 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 985 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 986 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 987 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 988 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 989 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 990 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 991 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 992 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 993 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 994 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 995 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 996 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 997 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 998 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 999 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 1000 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 1001 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 1002 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 1003 .reo_setup = ath11k_hw_ipq8074_reo_setup, 1004 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 1005 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 1006 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 1007 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 1008 }; 1009 1010 const struct ath11k_hw_ops qcn9074_ops = { 1011 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 1012 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 1013 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 1014 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 1015 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 1016 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 1017 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 1018 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 1019 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 1020 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 1021 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 1022 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 1023 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 1024 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 1025 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 1026 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 1027 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 1028 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 1029 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 1030 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 1031 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 1032 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 1033 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 1034 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 1035 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 1036 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 1037 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 1038 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 1039 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 1040 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 1041 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 1042 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 1043 .reo_setup = ath11k_hw_ipq8074_reo_setup, 1044 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 1045 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 1046 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 1047 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 1048 }; 1049 1050 const struct ath11k_hw_ops wcn6855_ops = { 1051 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 1052 .wmi_init_config = ath11k_init_wmi_config_qca6390, 1053 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 1054 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 1055 .tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable, 1056 .rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu, 1057 .rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu, 1058 .rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes, 1059 .rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status, 1060 .rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid, 1061 .rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type, 1062 .rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type, 1063 .rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl, 1064 .rx_desc_get_ldpc_support = ath11k_hw_wcn6855_rx_desc_get_ldpc_support, 1065 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld, 1066 .rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid, 1067 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no, 1068 .rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len, 1069 .rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi, 1070 .rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs, 1071 .rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw, 1072 .rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq, 1073 .rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type, 1074 .rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss, 1075 .rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid, 1076 .rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id, 1077 .rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end, 1078 .rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag, 1079 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id, 1080 .rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len, 1081 .rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention, 1082 .rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload, 1083 .reo_setup = ath11k_hw_wcn6855_reo_setup, 1084 .mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid, 1085 .rx_desc_mac_addr2_valid = ath11k_hw_wcn6855_rx_desc_mac_addr2_valid, 1086 .rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2, 1087 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 1088 }; 1089 1090 const struct ath11k_hw_ops wcn6750_ops = { 1091 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 1092 .wmi_init_config = ath11k_init_wmi_config_qca6390, 1093 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 1094 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 1095 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 1096 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 1097 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 1098 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 1099 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 1100 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 1101 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 1102 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 1103 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 1104 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 1105 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 1106 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 1107 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 1108 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 1109 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 1110 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 1111 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 1112 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 1113 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 1114 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 1115 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 1116 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 1117 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 1118 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 1119 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 1120 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 1121 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 1122 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 1123 .reo_setup = ath11k_hw_wcn6855_reo_setup, 1124 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 1125 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 1126 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 1127 .get_ring_selector = ath11k_hw_wcn6750_get_tcl_ring_selector, 1128 }; 1129 1130 /* IPQ5018 hw ops is similar to QCN9074 except for the dest ring remap */ 1131 const struct ath11k_hw_ops ipq5018_ops = { 1132 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 1133 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 1134 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 1135 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 1136 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 1137 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 1138 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 1139 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 1140 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 1141 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 1142 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 1143 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 1144 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 1145 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 1146 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 1147 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 1148 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 1149 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 1150 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 1151 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 1152 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 1153 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 1154 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 1155 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 1156 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 1157 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 1158 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 1159 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 1160 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 1161 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 1162 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 1163 .reo_setup = ath11k_hw_ipq5018_reo_setup, 1164 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 1165 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 1166 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 1167 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 1168 1169 }; 1170 1171 #define ATH11K_TX_RING_MASK_0 BIT(0) 1172 #define ATH11K_TX_RING_MASK_1 BIT(1) 1173 #define ATH11K_TX_RING_MASK_2 BIT(2) 1174 #define ATH11K_TX_RING_MASK_3 BIT(3) 1175 #define ATH11K_TX_RING_MASK_4 BIT(4) 1176 1177 #define ATH11K_RX_RING_MASK_0 0x1 1178 #define ATH11K_RX_RING_MASK_1 0x2 1179 #define ATH11K_RX_RING_MASK_2 0x4 1180 #define ATH11K_RX_RING_MASK_3 0x8 1181 1182 #define ATH11K_RX_ERR_RING_MASK_0 0x1 1183 1184 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 1185 1186 #define ATH11K_REO_STATUS_RING_MASK_0 0x1 1187 1188 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 1189 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 1190 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 1191 1192 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 1193 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 1194 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 1195 1196 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 1197 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 1198 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 1199 1200 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 1201 .tx = { 1202 ATH11K_TX_RING_MASK_0, 1203 ATH11K_TX_RING_MASK_1, 1204 ATH11K_TX_RING_MASK_2, 1205 }, 1206 .rx_mon_status = { 1207 0, 0, 0, 0, 1208 ATH11K_RX_MON_STATUS_RING_MASK_0, 1209 ATH11K_RX_MON_STATUS_RING_MASK_1, 1210 ATH11K_RX_MON_STATUS_RING_MASK_2, 1211 }, 1212 .rx = { 1213 0, 0, 0, 0, 0, 0, 0, 1214 ATH11K_RX_RING_MASK_0, 1215 ATH11K_RX_RING_MASK_1, 1216 ATH11K_RX_RING_MASK_2, 1217 ATH11K_RX_RING_MASK_3, 1218 }, 1219 .rx_err = { 1220 ATH11K_RX_ERR_RING_MASK_0, 1221 }, 1222 .rx_wbm_rel = { 1223 ATH11K_RX_WBM_REL_RING_MASK_0, 1224 }, 1225 .reo_status = { 1226 ATH11K_REO_STATUS_RING_MASK_0, 1227 }, 1228 .rxdma2host = { 1229 ATH11K_RXDMA2HOST_RING_MASK_0, 1230 ATH11K_RXDMA2HOST_RING_MASK_1, 1231 ATH11K_RXDMA2HOST_RING_MASK_2, 1232 }, 1233 .host2rxdma = { 1234 ATH11K_HOST2RXDMA_RING_MASK_0, 1235 ATH11K_HOST2RXDMA_RING_MASK_1, 1236 ATH11K_HOST2RXDMA_RING_MASK_2, 1237 }, 1238 }; 1239 1240 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 1241 .tx = { 1242 ATH11K_TX_RING_MASK_0, 1243 }, 1244 .rx_mon_status = { 1245 0, 0, 0, 0, 1246 ATH11K_RX_MON_STATUS_RING_MASK_0, 1247 ATH11K_RX_MON_STATUS_RING_MASK_1, 1248 ATH11K_RX_MON_STATUS_RING_MASK_2, 1249 }, 1250 .rx = { 1251 0, 0, 0, 0, 0, 0, 0, 1252 ATH11K_RX_RING_MASK_0, 1253 ATH11K_RX_RING_MASK_1, 1254 ATH11K_RX_RING_MASK_2, 1255 ATH11K_RX_RING_MASK_3, 1256 }, 1257 .rx_err = { 1258 ATH11K_RX_ERR_RING_MASK_0, 1259 }, 1260 .rx_wbm_rel = { 1261 ATH11K_RX_WBM_REL_RING_MASK_0, 1262 }, 1263 .reo_status = { 1264 ATH11K_REO_STATUS_RING_MASK_0, 1265 }, 1266 .rxdma2host = { 1267 ATH11K_RXDMA2HOST_RING_MASK_0, 1268 ATH11K_RXDMA2HOST_RING_MASK_1, 1269 ATH11K_RXDMA2HOST_RING_MASK_2, 1270 }, 1271 .host2rxdma = { 1272 }, 1273 }; 1274 1275 /* Target firmware's Copy Engine configuration. */ 1276 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = { 1277 /* CE0: host->target HTC control and raw streams */ 1278 { 1279 .pipenum = __cpu_to_le32(0), 1280 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1281 .nentries = __cpu_to_le32(32), 1282 .nbytes_max = __cpu_to_le32(2048), 1283 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1284 .reserved = __cpu_to_le32(0), 1285 }, 1286 1287 /* CE1: target->host HTT + HTC control */ 1288 { 1289 .pipenum = __cpu_to_le32(1), 1290 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1291 .nentries = __cpu_to_le32(32), 1292 .nbytes_max = __cpu_to_le32(2048), 1293 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1294 .reserved = __cpu_to_le32(0), 1295 }, 1296 1297 /* CE2: target->host WMI */ 1298 { 1299 .pipenum = __cpu_to_le32(2), 1300 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1301 .nentries = __cpu_to_le32(32), 1302 .nbytes_max = __cpu_to_le32(2048), 1303 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1304 .reserved = __cpu_to_le32(0), 1305 }, 1306 1307 /* CE3: host->target WMI */ 1308 { 1309 .pipenum = __cpu_to_le32(3), 1310 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1311 .nentries = __cpu_to_le32(32), 1312 .nbytes_max = __cpu_to_le32(2048), 1313 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1314 .reserved = __cpu_to_le32(0), 1315 }, 1316 1317 /* CE4: host->target HTT */ 1318 { 1319 .pipenum = __cpu_to_le32(4), 1320 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1321 .nentries = __cpu_to_le32(256), 1322 .nbytes_max = __cpu_to_le32(256), 1323 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1324 .reserved = __cpu_to_le32(0), 1325 }, 1326 1327 /* CE5: target->host Pktlog */ 1328 { 1329 .pipenum = __cpu_to_le32(5), 1330 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1331 .nentries = __cpu_to_le32(32), 1332 .nbytes_max = __cpu_to_le32(2048), 1333 .flags = __cpu_to_le32(0), 1334 .reserved = __cpu_to_le32(0), 1335 }, 1336 1337 /* CE6: Reserved for target autonomous hif_memcpy */ 1338 { 1339 .pipenum = __cpu_to_le32(6), 1340 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1341 .nentries = __cpu_to_le32(32), 1342 .nbytes_max = __cpu_to_le32(65535), 1343 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1344 .reserved = __cpu_to_le32(0), 1345 }, 1346 1347 /* CE7 used only by Host */ 1348 { 1349 .pipenum = __cpu_to_le32(7), 1350 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1351 .nentries = __cpu_to_le32(32), 1352 .nbytes_max = __cpu_to_le32(2048), 1353 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1354 .reserved = __cpu_to_le32(0), 1355 }, 1356 1357 /* CE8 target->host used only by IPA */ 1358 { 1359 .pipenum = __cpu_to_le32(8), 1360 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1361 .nentries = __cpu_to_le32(32), 1362 .nbytes_max = __cpu_to_le32(65535), 1363 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1364 .reserved = __cpu_to_le32(0), 1365 }, 1366 1367 /* CE9 host->target HTT */ 1368 { 1369 .pipenum = __cpu_to_le32(9), 1370 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1371 .nentries = __cpu_to_le32(32), 1372 .nbytes_max = __cpu_to_le32(2048), 1373 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1374 .reserved = __cpu_to_le32(0), 1375 }, 1376 1377 /* CE10 target->host HTT */ 1378 { 1379 .pipenum = __cpu_to_le32(10), 1380 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1381 .nentries = __cpu_to_le32(0), 1382 .nbytes_max = __cpu_to_le32(0), 1383 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1384 .reserved = __cpu_to_le32(0), 1385 }, 1386 1387 /* CE11 Not used */ 1388 }; 1389 1390 /* Map from service/endpoint to Copy Engine. 1391 * This table is derived from the CE_PCI TABLE, above. 1392 * It is passed to the Target at startup for use by firmware. 1393 */ 1394 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = { 1395 { 1396 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1397 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1398 .pipenum = __cpu_to_le32(3), 1399 }, 1400 { 1401 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1402 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1403 .pipenum = __cpu_to_le32(2), 1404 }, 1405 { 1406 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1407 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1408 .pipenum = __cpu_to_le32(3), 1409 }, 1410 { 1411 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1412 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1413 .pipenum = __cpu_to_le32(2), 1414 }, 1415 { 1416 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1417 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1418 .pipenum = __cpu_to_le32(3), 1419 }, 1420 { 1421 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1422 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1423 .pipenum = __cpu_to_le32(2), 1424 }, 1425 { 1426 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1427 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1428 .pipenum = __cpu_to_le32(3), 1429 }, 1430 { 1431 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1432 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1433 .pipenum = __cpu_to_le32(2), 1434 }, 1435 { 1436 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1437 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1438 .pipenum = __cpu_to_le32(3), 1439 }, 1440 { 1441 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1442 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1443 .pipenum = __cpu_to_le32(2), 1444 }, 1445 { 1446 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1447 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1448 .pipenum = __cpu_to_le32(7), 1449 }, 1450 { 1451 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1452 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1453 .pipenum = __cpu_to_le32(2), 1454 }, 1455 { 1456 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1457 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1458 .pipenum = __cpu_to_le32(9), 1459 }, 1460 { 1461 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1462 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1463 .pipenum = __cpu_to_le32(2), 1464 }, 1465 { 1466 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1467 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1468 .pipenum = __cpu_to_le32(0), 1469 }, 1470 { 1471 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1472 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1473 .pipenum = __cpu_to_le32(1), 1474 }, 1475 { /* not used */ 1476 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1477 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1478 .pipenum = __cpu_to_le32(0), 1479 }, 1480 { /* not used */ 1481 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1482 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1483 .pipenum = __cpu_to_le32(1), 1484 }, 1485 { 1486 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1487 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1488 .pipenum = __cpu_to_le32(4), 1489 }, 1490 { 1491 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1492 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1493 .pipenum = __cpu_to_le32(1), 1494 }, 1495 { 1496 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1497 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1498 .pipenum = __cpu_to_le32(5), 1499 }, 1500 1501 /* (Additions here) */ 1502 1503 { /* terminator entry */ } 1504 }; 1505 1506 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = { 1507 { 1508 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1509 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1510 .pipenum = __cpu_to_le32(3), 1511 }, 1512 { 1513 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1514 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1515 .pipenum = __cpu_to_le32(2), 1516 }, 1517 { 1518 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1519 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1520 .pipenum = __cpu_to_le32(3), 1521 }, 1522 { 1523 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1524 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1525 .pipenum = __cpu_to_le32(2), 1526 }, 1527 { 1528 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1529 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1530 .pipenum = __cpu_to_le32(3), 1531 }, 1532 { 1533 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1534 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1535 .pipenum = __cpu_to_le32(2), 1536 }, 1537 { 1538 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1539 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1540 .pipenum = __cpu_to_le32(3), 1541 }, 1542 { 1543 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1544 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1545 .pipenum = __cpu_to_le32(2), 1546 }, 1547 { 1548 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1549 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1550 .pipenum = __cpu_to_le32(3), 1551 }, 1552 { 1553 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1554 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1555 .pipenum = __cpu_to_le32(2), 1556 }, 1557 { 1558 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1559 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1560 .pipenum = __cpu_to_le32(7), 1561 }, 1562 { 1563 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1564 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1565 .pipenum = __cpu_to_le32(2), 1566 }, 1567 { 1568 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1569 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1570 .pipenum = __cpu_to_le32(0), 1571 }, 1572 { 1573 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1574 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1575 .pipenum = __cpu_to_le32(1), 1576 }, 1577 { /* not used */ 1578 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1579 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1580 .pipenum = __cpu_to_le32(0), 1581 }, 1582 { /* not used */ 1583 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1584 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1585 .pipenum = __cpu_to_le32(1), 1586 }, 1587 { 1588 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1589 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1590 .pipenum = __cpu_to_le32(4), 1591 }, 1592 { 1593 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1594 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1595 .pipenum = __cpu_to_le32(1), 1596 }, 1597 { 1598 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1599 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1600 .pipenum = __cpu_to_le32(5), 1601 }, 1602 1603 /* (Additions here) */ 1604 1605 { /* terminator entry */ } 1606 }; 1607 1608 /* Target firmware's Copy Engine configuration. */ 1609 const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = { 1610 /* CE0: host->target HTC control and raw streams */ 1611 { 1612 .pipenum = __cpu_to_le32(0), 1613 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1614 .nentries = __cpu_to_le32(32), 1615 .nbytes_max = __cpu_to_le32(2048), 1616 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1617 .reserved = __cpu_to_le32(0), 1618 }, 1619 1620 /* CE1: target->host HTT + HTC control */ 1621 { 1622 .pipenum = __cpu_to_le32(1), 1623 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1624 .nentries = __cpu_to_le32(32), 1625 .nbytes_max = __cpu_to_le32(2048), 1626 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1627 .reserved = __cpu_to_le32(0), 1628 }, 1629 1630 /* CE2: target->host WMI */ 1631 { 1632 .pipenum = __cpu_to_le32(2), 1633 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1634 .nentries = __cpu_to_le32(32), 1635 .nbytes_max = __cpu_to_le32(2048), 1636 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1637 .reserved = __cpu_to_le32(0), 1638 }, 1639 1640 /* CE3: host->target WMI */ 1641 { 1642 .pipenum = __cpu_to_le32(3), 1643 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1644 .nentries = __cpu_to_le32(32), 1645 .nbytes_max = __cpu_to_le32(2048), 1646 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1647 .reserved = __cpu_to_le32(0), 1648 }, 1649 1650 /* CE4: host->target HTT */ 1651 { 1652 .pipenum = __cpu_to_le32(4), 1653 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1654 .nentries = __cpu_to_le32(256), 1655 .nbytes_max = __cpu_to_le32(256), 1656 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1657 .reserved = __cpu_to_le32(0), 1658 }, 1659 1660 /* CE5: target->host Pktlog */ 1661 { 1662 .pipenum = __cpu_to_le32(5), 1663 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1664 .nentries = __cpu_to_le32(32), 1665 .nbytes_max = __cpu_to_le32(2048), 1666 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1667 .reserved = __cpu_to_le32(0), 1668 }, 1669 1670 /* CE6: Reserved for target autonomous hif_memcpy */ 1671 { 1672 .pipenum = __cpu_to_le32(6), 1673 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1674 .nentries = __cpu_to_le32(32), 1675 .nbytes_max = __cpu_to_le32(16384), 1676 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1677 .reserved = __cpu_to_le32(0), 1678 }, 1679 1680 /* CE7 used only by Host */ 1681 { 1682 .pipenum = __cpu_to_le32(7), 1683 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1684 .nentries = __cpu_to_le32(0), 1685 .nbytes_max = __cpu_to_le32(0), 1686 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1687 .reserved = __cpu_to_le32(0), 1688 }, 1689 1690 /* CE8 target->host used only by IPA */ 1691 { 1692 .pipenum = __cpu_to_le32(8), 1693 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1694 .nentries = __cpu_to_le32(32), 1695 .nbytes_max = __cpu_to_le32(16384), 1696 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1697 .reserved = __cpu_to_le32(0), 1698 }, 1699 /* CE 9, 10, 11 are used by MHI driver */ 1700 }; 1701 1702 /* Map from service/endpoint to Copy Engine. 1703 * This table is derived from the CE_PCI TABLE, above. 1704 * It is passed to the Target at startup for use by firmware. 1705 */ 1706 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = { 1707 { 1708 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1709 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1710 __cpu_to_le32(3), 1711 }, 1712 { 1713 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1714 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1715 __cpu_to_le32(2), 1716 }, 1717 { 1718 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1719 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1720 __cpu_to_le32(3), 1721 }, 1722 { 1723 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1724 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1725 __cpu_to_le32(2), 1726 }, 1727 { 1728 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1729 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1730 __cpu_to_le32(3), 1731 }, 1732 { 1733 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1734 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1735 __cpu_to_le32(2), 1736 }, 1737 { 1738 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1739 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1740 __cpu_to_le32(3), 1741 }, 1742 { 1743 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1744 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1745 __cpu_to_le32(2), 1746 }, 1747 { 1748 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1749 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1750 __cpu_to_le32(3), 1751 }, 1752 { 1753 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1754 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1755 __cpu_to_le32(2), 1756 }, 1757 { 1758 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1759 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1760 __cpu_to_le32(0), 1761 }, 1762 { 1763 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1764 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1765 __cpu_to_le32(2), 1766 }, 1767 { 1768 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1769 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1770 __cpu_to_le32(4), 1771 }, 1772 { 1773 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1774 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1775 __cpu_to_le32(1), 1776 }, 1777 1778 /* (Additions here) */ 1779 1780 { /* must be last */ 1781 __cpu_to_le32(0), 1782 __cpu_to_le32(0), 1783 __cpu_to_le32(0), 1784 }, 1785 }; 1786 1787 /* Target firmware's Copy Engine configuration. */ 1788 const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = { 1789 /* CE0: host->target HTC control and raw streams */ 1790 { 1791 .pipenum = __cpu_to_le32(0), 1792 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1793 .nentries = __cpu_to_le32(32), 1794 .nbytes_max = __cpu_to_le32(2048), 1795 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1796 .reserved = __cpu_to_le32(0), 1797 }, 1798 1799 /* CE1: target->host HTT + HTC control */ 1800 { 1801 .pipenum = __cpu_to_le32(1), 1802 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1803 .nentries = __cpu_to_le32(32), 1804 .nbytes_max = __cpu_to_le32(2048), 1805 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1806 .reserved = __cpu_to_le32(0), 1807 }, 1808 1809 /* CE2: target->host WMI */ 1810 { 1811 .pipenum = __cpu_to_le32(2), 1812 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1813 .nentries = __cpu_to_le32(32), 1814 .nbytes_max = __cpu_to_le32(2048), 1815 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1816 .reserved = __cpu_to_le32(0), 1817 }, 1818 1819 /* CE3: host->target WMI */ 1820 { 1821 .pipenum = __cpu_to_le32(3), 1822 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1823 .nentries = __cpu_to_le32(32), 1824 .nbytes_max = __cpu_to_le32(2048), 1825 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1826 .reserved = __cpu_to_le32(0), 1827 }, 1828 1829 /* CE4: host->target HTT */ 1830 { 1831 .pipenum = __cpu_to_le32(4), 1832 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1833 .nentries = __cpu_to_le32(256), 1834 .nbytes_max = __cpu_to_le32(256), 1835 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1836 .reserved = __cpu_to_le32(0), 1837 }, 1838 1839 /* CE5: target->host Pktlog */ 1840 { 1841 .pipenum = __cpu_to_le32(5), 1842 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1843 .nentries = __cpu_to_le32(32), 1844 .nbytes_max = __cpu_to_le32(2048), 1845 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1846 .reserved = __cpu_to_le32(0), 1847 }, 1848 1849 /* CE6: Reserved for target autonomous hif_memcpy */ 1850 { 1851 .pipenum = __cpu_to_le32(6), 1852 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1853 .nentries = __cpu_to_le32(32), 1854 .nbytes_max = __cpu_to_le32(16384), 1855 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1856 .reserved = __cpu_to_le32(0), 1857 }, 1858 1859 /* CE7 used only by Host */ 1860 { 1861 .pipenum = __cpu_to_le32(7), 1862 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1863 .nentries = __cpu_to_le32(0), 1864 .nbytes_max = __cpu_to_le32(0), 1865 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1866 .reserved = __cpu_to_le32(0), 1867 }, 1868 1869 /* CE8 target->host used only by IPA */ 1870 { 1871 .pipenum = __cpu_to_le32(8), 1872 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1873 .nentries = __cpu_to_le32(32), 1874 .nbytes_max = __cpu_to_le32(16384), 1875 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1876 .reserved = __cpu_to_le32(0), 1877 }, 1878 /* CE 9, 10, 11 are used by MHI driver */ 1879 }; 1880 1881 /* Map from service/endpoint to Copy Engine. 1882 * This table is derived from the CE_PCI TABLE, above. 1883 * It is passed to the Target at startup for use by firmware. 1884 */ 1885 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = { 1886 { 1887 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1888 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1889 __cpu_to_le32(3), 1890 }, 1891 { 1892 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1893 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1894 __cpu_to_le32(2), 1895 }, 1896 { 1897 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1898 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1899 __cpu_to_le32(3), 1900 }, 1901 { 1902 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1903 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1904 __cpu_to_le32(2), 1905 }, 1906 { 1907 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1908 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1909 __cpu_to_le32(3), 1910 }, 1911 { 1912 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1913 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1914 __cpu_to_le32(2), 1915 }, 1916 { 1917 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1918 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1919 __cpu_to_le32(3), 1920 }, 1921 { 1922 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1923 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1924 __cpu_to_le32(2), 1925 }, 1926 { 1927 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1928 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1929 __cpu_to_le32(3), 1930 }, 1931 { 1932 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1933 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1934 __cpu_to_le32(2), 1935 }, 1936 { 1937 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1938 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1939 __cpu_to_le32(0), 1940 }, 1941 { 1942 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1943 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1944 __cpu_to_le32(1), 1945 }, 1946 { 1947 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1948 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1949 __cpu_to_le32(0), 1950 }, 1951 { 1952 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1953 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1954 __cpu_to_le32(1), 1955 }, 1956 { 1957 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1958 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1959 __cpu_to_le32(4), 1960 }, 1961 { 1962 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1963 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1964 __cpu_to_le32(1), 1965 }, 1966 { 1967 __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1968 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1969 __cpu_to_le32(5), 1970 }, 1971 1972 /* (Additions here) */ 1973 1974 { /* must be last */ 1975 __cpu_to_le32(0), 1976 __cpu_to_le32(0), 1977 __cpu_to_le32(0), 1978 }, 1979 }; 1980 1981 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = { 1982 .tx = { 1983 ATH11K_TX_RING_MASK_0, 1984 ATH11K_TX_RING_MASK_1, 1985 ATH11K_TX_RING_MASK_2, 1986 }, 1987 .rx_mon_status = { 1988 0, 0, 0, 1989 ATH11K_RX_MON_STATUS_RING_MASK_0, 1990 ATH11K_RX_MON_STATUS_RING_MASK_1, 1991 ATH11K_RX_MON_STATUS_RING_MASK_2, 1992 }, 1993 .rx = { 1994 0, 0, 0, 0, 1995 ATH11K_RX_RING_MASK_0, 1996 ATH11K_RX_RING_MASK_1, 1997 ATH11K_RX_RING_MASK_2, 1998 ATH11K_RX_RING_MASK_3, 1999 }, 2000 .rx_err = { 2001 0, 0, 0, 2002 ATH11K_RX_ERR_RING_MASK_0, 2003 }, 2004 .rx_wbm_rel = { 2005 0, 0, 0, 2006 ATH11K_RX_WBM_REL_RING_MASK_0, 2007 }, 2008 .reo_status = { 2009 0, 0, 0, 2010 ATH11K_REO_STATUS_RING_MASK_0, 2011 }, 2012 .rxdma2host = { 2013 0, 0, 0, 2014 ATH11K_RXDMA2HOST_RING_MASK_0, 2015 }, 2016 .host2rxdma = { 2017 0, 0, 0, 2018 ATH11K_HOST2RXDMA_RING_MASK_0, 2019 }, 2020 }; 2021 2022 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_wcn6750 = { 2023 .tx = { 2024 ATH11K_TX_RING_MASK_0, 2025 0, 2026 ATH11K_TX_RING_MASK_2, 2027 0, 2028 ATH11K_TX_RING_MASK_4, 2029 }, 2030 .rx_mon_status = { 2031 0, 0, 0, 0, 0, 0, 2032 ATH11K_RX_MON_STATUS_RING_MASK_0, 2033 }, 2034 .rx = { 2035 0, 0, 0, 0, 0, 0, 0, 2036 ATH11K_RX_RING_MASK_0, 2037 ATH11K_RX_RING_MASK_1, 2038 ATH11K_RX_RING_MASK_2, 2039 ATH11K_RX_RING_MASK_3, 2040 }, 2041 .rx_err = { 2042 0, ATH11K_RX_ERR_RING_MASK_0, 2043 }, 2044 .rx_wbm_rel = { 2045 0, ATH11K_RX_WBM_REL_RING_MASK_0, 2046 }, 2047 .reo_status = { 2048 0, ATH11K_REO_STATUS_RING_MASK_0, 2049 }, 2050 .rxdma2host = { 2051 ATH11K_RXDMA2HOST_RING_MASK_0, 2052 ATH11K_RXDMA2HOST_RING_MASK_1, 2053 ATH11K_RXDMA2HOST_RING_MASK_2, 2054 }, 2055 .host2rxdma = { 2056 }, 2057 }; 2058 2059 /* Target firmware's Copy Engine configuration for IPQ5018 */ 2060 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[] = { 2061 /* CE0: host->target HTC control and raw streams */ 2062 { 2063 .pipenum = __cpu_to_le32(0), 2064 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 2065 .nentries = __cpu_to_le32(32), 2066 .nbytes_max = __cpu_to_le32(2048), 2067 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2068 .reserved = __cpu_to_le32(0), 2069 }, 2070 2071 /* CE1: target->host HTT + HTC control */ 2072 { 2073 .pipenum = __cpu_to_le32(1), 2074 .pipedir = __cpu_to_le32(PIPEDIR_IN), 2075 .nentries = __cpu_to_le32(32), 2076 .nbytes_max = __cpu_to_le32(2048), 2077 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2078 .reserved = __cpu_to_le32(0), 2079 }, 2080 2081 /* CE2: target->host WMI */ 2082 { 2083 .pipenum = __cpu_to_le32(2), 2084 .pipedir = __cpu_to_le32(PIPEDIR_IN), 2085 .nentries = __cpu_to_le32(32), 2086 .nbytes_max = __cpu_to_le32(2048), 2087 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2088 .reserved = __cpu_to_le32(0), 2089 }, 2090 2091 /* CE3: host->target WMI */ 2092 { 2093 .pipenum = __cpu_to_le32(3), 2094 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 2095 .nentries = __cpu_to_le32(32), 2096 .nbytes_max = __cpu_to_le32(2048), 2097 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2098 .reserved = __cpu_to_le32(0), 2099 }, 2100 2101 /* CE4: host->target HTT */ 2102 { 2103 .pipenum = __cpu_to_le32(4), 2104 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 2105 .nentries = __cpu_to_le32(256), 2106 .nbytes_max = __cpu_to_le32(256), 2107 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 2108 .reserved = __cpu_to_le32(0), 2109 }, 2110 2111 /* CE5: target->host Pktlog */ 2112 { 2113 .pipenum = __cpu_to_le32(5), 2114 .pipedir = __cpu_to_le32(PIPEDIR_IN), 2115 .nentries = __cpu_to_le32(32), 2116 .nbytes_max = __cpu_to_le32(2048), 2117 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2118 .reserved = __cpu_to_le32(0), 2119 }, 2120 2121 /* CE6: Reserved for target autonomous hif_memcpy */ 2122 { 2123 .pipenum = __cpu_to_le32(6), 2124 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 2125 .nentries = __cpu_to_le32(32), 2126 .nbytes_max = __cpu_to_le32(16384), 2127 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2128 .reserved = __cpu_to_le32(0), 2129 }, 2130 2131 /* CE7 used only by Host */ 2132 { 2133 .pipenum = __cpu_to_le32(7), 2134 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 2135 .nentries = __cpu_to_le32(32), 2136 .nbytes_max = __cpu_to_le32(2048), 2137 .flags = __cpu_to_le32(0x2000), 2138 .reserved = __cpu_to_le32(0), 2139 }, 2140 2141 /* CE8 target->host used only by IPA */ 2142 { 2143 .pipenum = __cpu_to_le32(8), 2144 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 2145 .nentries = __cpu_to_le32(32), 2146 .nbytes_max = __cpu_to_le32(16384), 2147 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2148 .reserved = __cpu_to_le32(0), 2149 }, 2150 }; 2151 2152 /* Map from service/endpoint to Copy Engine for IPQ5018. 2153 * This table is derived from the CE TABLE, above. 2154 * It is passed to the Target at startup for use by firmware. 2155 */ 2156 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[] = { 2157 { 2158 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 2159 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2160 .pipenum = __cpu_to_le32(3), 2161 }, 2162 { 2163 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 2164 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2165 .pipenum = __cpu_to_le32(2), 2166 }, 2167 { 2168 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 2169 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2170 .pipenum = __cpu_to_le32(3), 2171 }, 2172 { 2173 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 2174 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2175 .pipenum = __cpu_to_le32(2), 2176 }, 2177 { 2178 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 2179 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2180 .pipenum = __cpu_to_le32(3), 2181 }, 2182 { 2183 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 2184 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2185 .pipenum = __cpu_to_le32(2), 2186 }, 2187 { 2188 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 2189 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2190 .pipenum = __cpu_to_le32(3), 2191 }, 2192 { 2193 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 2194 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2195 .pipenum = __cpu_to_le32(2), 2196 }, 2197 { 2198 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 2199 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2200 .pipenum = __cpu_to_le32(3), 2201 }, 2202 { 2203 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 2204 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2205 .pipenum = __cpu_to_le32(2), 2206 }, 2207 2208 { 2209 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 2210 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2211 .pipenum = __cpu_to_le32(0), 2212 }, 2213 { 2214 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 2215 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2216 .pipenum = __cpu_to_le32(1), 2217 }, 2218 2219 { 2220 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 2221 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2222 .pipenum = __cpu_to_le32(0), 2223 }, 2224 { 2225 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 2226 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2227 .pipenum = __cpu_to_le32(1), 2228 }, 2229 { 2230 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 2231 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2232 .pipenum = __cpu_to_le32(4), 2233 }, 2234 { 2235 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 2236 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2237 .pipenum = __cpu_to_le32(1), 2238 }, 2239 { 2240 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 2241 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2242 .pipenum = __cpu_to_le32(5), 2243 }, 2244 2245 /* (Additions here) */ 2246 2247 { /* terminator entry */ } 2248 }; 2249 2250 const struct ce_ie_addr ath11k_ce_ie_addr_ipq8074 = { 2251 .ie1_reg_addr = CE_HOST_IE_ADDRESS, 2252 .ie2_reg_addr = CE_HOST_IE_2_ADDRESS, 2253 .ie3_reg_addr = CE_HOST_IE_3_ADDRESS, 2254 }; 2255 2256 const struct ce_ie_addr ath11k_ce_ie_addr_ipq5018 = { 2257 .ie1_reg_addr = CE_HOST_IPQ5018_IE_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, 2258 .ie2_reg_addr = CE_HOST_IPQ5018_IE_2_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, 2259 .ie3_reg_addr = CE_HOST_IPQ5018_IE_3_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, 2260 }; 2261 2262 const struct ce_remap ath11k_ce_remap_ipq5018 = { 2263 .base = HAL_IPQ5018_CE_WFSS_REG_BASE, 2264 .size = HAL_IPQ5018_CE_SIZE, 2265 }; 2266 2267 const struct ath11k_hw_regs ipq8074_regs = { 2268 /* SW2TCL(x) R0 ring configuration address */ 2269 .hal_tcl1_ring_base_lsb = 0x00000510, 2270 .hal_tcl1_ring_base_msb = 0x00000514, 2271 .hal_tcl1_ring_id = 0x00000518, 2272 .hal_tcl1_ring_misc = 0x00000520, 2273 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 2274 .hal_tcl1_ring_tp_addr_msb = 0x00000530, 2275 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 2276 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 2277 .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 2278 .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 2279 .hal_tcl1_ring_msi1_data = 0x00000560, 2280 .hal_tcl2_ring_base_lsb = 0x00000568, 2281 .hal_tcl_ring_base_lsb = 0x00000618, 2282 2283 /* TCL STATUS ring address */ 2284 .hal_tcl_status_ring_base_lsb = 0x00000720, 2285 2286 /* REO2SW(x) R0 ring configuration address */ 2287 .hal_reo1_ring_base_lsb = 0x0000029c, 2288 .hal_reo1_ring_base_msb = 0x000002a0, 2289 .hal_reo1_ring_id = 0x000002a4, 2290 .hal_reo1_ring_misc = 0x000002ac, 2291 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 2292 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 2293 .hal_reo1_ring_producer_int_setup = 0x000002c0, 2294 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 2295 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 2296 .hal_reo1_ring_msi1_data = 0x000002ec, 2297 .hal_reo2_ring_base_lsb = 0x000002f4, 2298 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2299 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2300 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2301 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2302 2303 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2304 .hal_reo1_ring_hp = 0x00003038, 2305 .hal_reo1_ring_tp = 0x0000303c, 2306 .hal_reo2_ring_hp = 0x00003040, 2307 2308 /* REO2TCL R0 ring configuration address */ 2309 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2310 .hal_reo_tcl_ring_hp = 0x00003058, 2311 2312 /* REO CMD ring address */ 2313 .hal_reo_cmd_ring_base_lsb = 0x00000194, 2314 .hal_reo_cmd_ring_hp = 0x00003020, 2315 2316 /* REO status address */ 2317 .hal_reo_status_ring_base_lsb = 0x00000504, 2318 .hal_reo_status_hp = 0x00003070, 2319 2320 /* SW2REO ring address */ 2321 .hal_sw2reo_ring_base_lsb = 0x000001ec, 2322 .hal_sw2reo_ring_hp = 0x00003028, 2323 2324 /* WCSS relative address */ 2325 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 2326 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 2327 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 2328 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 2329 2330 /* WBM Idle address */ 2331 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 2332 .hal_wbm_idle_link_ring_misc = 0x00000870, 2333 2334 /* SW2WBM release address */ 2335 .hal_wbm_release_ring_base_lsb = 0x000001d8, 2336 2337 /* WBM2SW release address */ 2338 .hal_wbm0_release_ring_base_lsb = 0x00000910, 2339 .hal_wbm1_release_ring_base_lsb = 0x00000968, 2340 2341 /* PCIe base address */ 2342 .pcie_qserdes_sysclk_en_sel = 0x0, 2343 .pcie_pcs_osc_dtct_config_base = 0x0, 2344 2345 /* Shadow register area */ 2346 .hal_shadow_base_addr = 0x0, 2347 2348 /* REO misc control register, not used in IPQ8074 */ 2349 .hal_reo1_misc_ctl = 0x0, 2350 }; 2351 2352 const struct ath11k_hw_regs qca6390_regs = { 2353 /* SW2TCL(x) R0 ring configuration address */ 2354 .hal_tcl1_ring_base_lsb = 0x00000684, 2355 .hal_tcl1_ring_base_msb = 0x00000688, 2356 .hal_tcl1_ring_id = 0x0000068c, 2357 .hal_tcl1_ring_misc = 0x00000694, 2358 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 2359 .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 2360 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 2361 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 2362 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 2363 .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 2364 .hal_tcl1_ring_msi1_data = 0x000006d4, 2365 .hal_tcl2_ring_base_lsb = 0x000006dc, 2366 .hal_tcl_ring_base_lsb = 0x0000078c, 2367 2368 /* TCL STATUS ring address */ 2369 .hal_tcl_status_ring_base_lsb = 0x00000894, 2370 2371 /* REO2SW(x) R0 ring configuration address */ 2372 .hal_reo1_ring_base_lsb = 0x00000244, 2373 .hal_reo1_ring_base_msb = 0x00000248, 2374 .hal_reo1_ring_id = 0x0000024c, 2375 .hal_reo1_ring_misc = 0x00000254, 2376 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 2377 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 2378 .hal_reo1_ring_producer_int_setup = 0x00000268, 2379 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 2380 .hal_reo1_ring_msi1_base_msb = 0x00000290, 2381 .hal_reo1_ring_msi1_data = 0x00000294, 2382 .hal_reo2_ring_base_lsb = 0x0000029c, 2383 .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 2384 .hal_reo1_aging_thresh_ix_1 = 0x00000510, 2385 .hal_reo1_aging_thresh_ix_2 = 0x00000514, 2386 .hal_reo1_aging_thresh_ix_3 = 0x00000518, 2387 2388 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2389 .hal_reo1_ring_hp = 0x00003030, 2390 .hal_reo1_ring_tp = 0x00003034, 2391 .hal_reo2_ring_hp = 0x00003038, 2392 2393 /* REO2TCL R0 ring configuration address */ 2394 .hal_reo_tcl_ring_base_lsb = 0x000003a4, 2395 .hal_reo_tcl_ring_hp = 0x00003050, 2396 2397 /* REO CMD ring address */ 2398 .hal_reo_cmd_ring_base_lsb = 0x00000194, 2399 .hal_reo_cmd_ring_hp = 0x00003020, 2400 2401 /* REO status address */ 2402 .hal_reo_status_ring_base_lsb = 0x000004ac, 2403 .hal_reo_status_hp = 0x00003068, 2404 2405 /* SW2REO ring address */ 2406 .hal_sw2reo_ring_base_lsb = 0x000001ec, 2407 .hal_sw2reo_ring_hp = 0x00003028, 2408 2409 /* WCSS relative address */ 2410 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 2411 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 2412 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 2413 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 2414 2415 /* WBM Idle address */ 2416 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 2417 .hal_wbm_idle_link_ring_misc = 0x00000870, 2418 2419 /* SW2WBM release address */ 2420 .hal_wbm_release_ring_base_lsb = 0x000001d8, 2421 2422 /* WBM2SW release address */ 2423 .hal_wbm0_release_ring_base_lsb = 0x00000910, 2424 .hal_wbm1_release_ring_base_lsb = 0x00000968, 2425 2426 /* PCIe base address */ 2427 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 2428 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 2429 2430 /* Shadow register area */ 2431 .hal_shadow_base_addr = 0x000008fc, 2432 2433 /* REO misc control register, not used in QCA6390 */ 2434 .hal_reo1_misc_ctl = 0x0, 2435 }; 2436 2437 const struct ath11k_hw_regs qcn9074_regs = { 2438 /* SW2TCL(x) R0 ring configuration address */ 2439 .hal_tcl1_ring_base_lsb = 0x000004f0, 2440 .hal_tcl1_ring_base_msb = 0x000004f4, 2441 .hal_tcl1_ring_id = 0x000004f8, 2442 .hal_tcl1_ring_misc = 0x00000500, 2443 .hal_tcl1_ring_tp_addr_lsb = 0x0000050c, 2444 .hal_tcl1_ring_tp_addr_msb = 0x00000510, 2445 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520, 2446 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524, 2447 .hal_tcl1_ring_msi1_base_lsb = 0x00000538, 2448 .hal_tcl1_ring_msi1_base_msb = 0x0000053c, 2449 .hal_tcl1_ring_msi1_data = 0x00000540, 2450 .hal_tcl2_ring_base_lsb = 0x00000548, 2451 .hal_tcl_ring_base_lsb = 0x000005f8, 2452 2453 /* TCL STATUS ring address */ 2454 .hal_tcl_status_ring_base_lsb = 0x00000700, 2455 2456 /* REO2SW(x) R0 ring configuration address */ 2457 .hal_reo1_ring_base_lsb = 0x0000029c, 2458 .hal_reo1_ring_base_msb = 0x000002a0, 2459 .hal_reo1_ring_id = 0x000002a4, 2460 .hal_reo1_ring_misc = 0x000002ac, 2461 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 2462 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 2463 .hal_reo1_ring_producer_int_setup = 0x000002c0, 2464 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 2465 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 2466 .hal_reo1_ring_msi1_data = 0x000002ec, 2467 .hal_reo2_ring_base_lsb = 0x000002f4, 2468 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2469 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2470 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2471 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2472 2473 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2474 .hal_reo1_ring_hp = 0x00003038, 2475 .hal_reo1_ring_tp = 0x0000303c, 2476 .hal_reo2_ring_hp = 0x00003040, 2477 2478 /* REO2TCL R0 ring configuration address */ 2479 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2480 .hal_reo_tcl_ring_hp = 0x00003058, 2481 2482 /* REO CMD ring address */ 2483 .hal_reo_cmd_ring_base_lsb = 0x00000194, 2484 .hal_reo_cmd_ring_hp = 0x00003020, 2485 2486 /* REO status address */ 2487 .hal_reo_status_ring_base_lsb = 0x00000504, 2488 .hal_reo_status_hp = 0x00003070, 2489 2490 /* SW2REO ring address */ 2491 .hal_sw2reo_ring_base_lsb = 0x000001ec, 2492 .hal_sw2reo_ring_hp = 0x00003028, 2493 2494 /* WCSS relative address */ 2495 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 2496 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 2497 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 2498 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 2499 2500 /* WBM Idle address */ 2501 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2502 .hal_wbm_idle_link_ring_misc = 0x00000884, 2503 2504 /* SW2WBM release address */ 2505 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2506 2507 /* WBM2SW release address */ 2508 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2509 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2510 2511 /* PCIe base address */ 2512 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 2513 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 2514 2515 /* Shadow register area */ 2516 .hal_shadow_base_addr = 0x0, 2517 2518 /* REO misc control register, not used in QCN9074 */ 2519 .hal_reo1_misc_ctl = 0x0, 2520 }; 2521 2522 const struct ath11k_hw_regs wcn6855_regs = { 2523 /* SW2TCL(x) R0 ring configuration address */ 2524 .hal_tcl1_ring_base_lsb = 0x00000690, 2525 .hal_tcl1_ring_base_msb = 0x00000694, 2526 .hal_tcl1_ring_id = 0x00000698, 2527 .hal_tcl1_ring_misc = 0x000006a0, 2528 .hal_tcl1_ring_tp_addr_lsb = 0x000006ac, 2529 .hal_tcl1_ring_tp_addr_msb = 0x000006b0, 2530 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0, 2531 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4, 2532 .hal_tcl1_ring_msi1_base_lsb = 0x000006d8, 2533 .hal_tcl1_ring_msi1_base_msb = 0x000006dc, 2534 .hal_tcl1_ring_msi1_data = 0x000006e0, 2535 .hal_tcl2_ring_base_lsb = 0x000006e8, 2536 .hal_tcl_ring_base_lsb = 0x00000798, 2537 2538 /* TCL STATUS ring address */ 2539 .hal_tcl_status_ring_base_lsb = 0x000008a0, 2540 2541 /* REO2SW(x) R0 ring configuration address */ 2542 .hal_reo1_ring_base_lsb = 0x00000244, 2543 .hal_reo1_ring_base_msb = 0x00000248, 2544 .hal_reo1_ring_id = 0x0000024c, 2545 .hal_reo1_ring_misc = 0x00000254, 2546 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 2547 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 2548 .hal_reo1_ring_producer_int_setup = 0x00000268, 2549 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 2550 .hal_reo1_ring_msi1_base_msb = 0x00000290, 2551 .hal_reo1_ring_msi1_data = 0x00000294, 2552 .hal_reo2_ring_base_lsb = 0x0000029c, 2553 .hal_reo1_aging_thresh_ix_0 = 0x000005bc, 2554 .hal_reo1_aging_thresh_ix_1 = 0x000005c0, 2555 .hal_reo1_aging_thresh_ix_2 = 0x000005c4, 2556 .hal_reo1_aging_thresh_ix_3 = 0x000005c8, 2557 2558 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2559 .hal_reo1_ring_hp = 0x00003030, 2560 .hal_reo1_ring_tp = 0x00003034, 2561 .hal_reo2_ring_hp = 0x00003038, 2562 2563 /* REO2TCL R0 ring configuration address */ 2564 .hal_reo_tcl_ring_base_lsb = 0x00000454, 2565 .hal_reo_tcl_ring_hp = 0x00003060, 2566 2567 /* REO CMD ring address */ 2568 .hal_reo_cmd_ring_base_lsb = 0x00000194, 2569 .hal_reo_cmd_ring_hp = 0x00003020, 2570 2571 /* REO status address */ 2572 .hal_reo_status_ring_base_lsb = 0x0000055c, 2573 .hal_reo_status_hp = 0x00003078, 2574 2575 /* SW2REO ring address */ 2576 .hal_sw2reo_ring_base_lsb = 0x000001ec, 2577 .hal_sw2reo_ring_hp = 0x00003028, 2578 2579 /* WCSS relative address */ 2580 .hal_seq_wcss_umac_ce0_src_reg = 0x1b80000, 2581 .hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000, 2582 .hal_seq_wcss_umac_ce1_src_reg = 0x1b82000, 2583 .hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000, 2584 2585 /* WBM Idle address */ 2586 .hal_wbm_idle_link_ring_base_lsb = 0x00000870, 2587 .hal_wbm_idle_link_ring_misc = 0x00000880, 2588 2589 /* SW2WBM release address */ 2590 .hal_wbm_release_ring_base_lsb = 0x000001e8, 2591 2592 /* WBM2SW release address */ 2593 .hal_wbm0_release_ring_base_lsb = 0x00000920, 2594 .hal_wbm1_release_ring_base_lsb = 0x00000978, 2595 2596 /* PCIe base address */ 2597 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 2598 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 2599 2600 /* Shadow register area */ 2601 .hal_shadow_base_addr = 0x000008fc, 2602 2603 /* REO misc control register, used for fragment 2604 * destination ring config in WCN6855. 2605 */ 2606 .hal_reo1_misc_ctl = 0x00000630, 2607 }; 2608 2609 const struct ath11k_hw_regs wcn6750_regs = { 2610 /* SW2TCL(x) R0 ring configuration address */ 2611 .hal_tcl1_ring_base_lsb = 0x00000694, 2612 .hal_tcl1_ring_base_msb = 0x00000698, 2613 .hal_tcl1_ring_id = 0x0000069c, 2614 .hal_tcl1_ring_misc = 0x000006a4, 2615 .hal_tcl1_ring_tp_addr_lsb = 0x000006b0, 2616 .hal_tcl1_ring_tp_addr_msb = 0x000006b4, 2617 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4, 2618 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8, 2619 .hal_tcl1_ring_msi1_base_lsb = 0x000006dc, 2620 .hal_tcl1_ring_msi1_base_msb = 0x000006e0, 2621 .hal_tcl1_ring_msi1_data = 0x000006e4, 2622 .hal_tcl2_ring_base_lsb = 0x000006ec, 2623 .hal_tcl_ring_base_lsb = 0x0000079c, 2624 2625 /* TCL STATUS ring address */ 2626 .hal_tcl_status_ring_base_lsb = 0x000008a4, 2627 2628 /* REO2SW(x) R0 ring configuration address */ 2629 .hal_reo1_ring_base_lsb = 0x000001ec, 2630 .hal_reo1_ring_base_msb = 0x000001f0, 2631 .hal_reo1_ring_id = 0x000001f4, 2632 .hal_reo1_ring_misc = 0x000001fc, 2633 .hal_reo1_ring_hp_addr_lsb = 0x00000200, 2634 .hal_reo1_ring_hp_addr_msb = 0x00000204, 2635 .hal_reo1_ring_producer_int_setup = 0x00000210, 2636 .hal_reo1_ring_msi1_base_lsb = 0x00000234, 2637 .hal_reo1_ring_msi1_base_msb = 0x00000238, 2638 .hal_reo1_ring_msi1_data = 0x0000023c, 2639 .hal_reo2_ring_base_lsb = 0x00000244, 2640 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2641 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2642 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2643 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2644 2645 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2646 .hal_reo1_ring_hp = 0x00003028, 2647 .hal_reo1_ring_tp = 0x0000302c, 2648 .hal_reo2_ring_hp = 0x00003030, 2649 2650 /* REO2TCL R0 ring configuration address */ 2651 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2652 .hal_reo_tcl_ring_hp = 0x00003058, 2653 2654 /* REO CMD ring address */ 2655 .hal_reo_cmd_ring_base_lsb = 0x000000e4, 2656 .hal_reo_cmd_ring_hp = 0x00003010, 2657 2658 /* REO status address */ 2659 .hal_reo_status_ring_base_lsb = 0x00000504, 2660 .hal_reo_status_hp = 0x00003070, 2661 2662 /* SW2REO ring address */ 2663 .hal_sw2reo_ring_base_lsb = 0x0000013c, 2664 .hal_sw2reo_ring_hp = 0x00003018, 2665 2666 /* WCSS relative address */ 2667 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 2668 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 2669 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 2670 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 2671 2672 /* WBM Idle address */ 2673 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2674 .hal_wbm_idle_link_ring_misc = 0x00000884, 2675 2676 /* SW2WBM release address */ 2677 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2678 2679 /* WBM2SW release address */ 2680 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2681 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2682 2683 /* PCIe base address */ 2684 .pcie_qserdes_sysclk_en_sel = 0x0, 2685 .pcie_pcs_osc_dtct_config_base = 0x0, 2686 2687 /* Shadow register area */ 2688 .hal_shadow_base_addr = 0x00000504, 2689 2690 /* REO misc control register, used for fragment 2691 * destination ring config in WCN6750. 2692 */ 2693 .hal_reo1_misc_ctl = 0x000005d8, 2694 }; 2695 2696 static const struct ath11k_hw_tcl2wbm_rbm_map ath11k_hw_tcl2wbm_rbm_map_ipq8074[] = { 2697 { 2698 .tcl_ring_num = 0, 2699 .wbm_ring_num = 0, 2700 .rbm_id = HAL_RX_BUF_RBM_SW0_BM, 2701 }, 2702 { 2703 .tcl_ring_num = 1, 2704 .wbm_ring_num = 1, 2705 .rbm_id = HAL_RX_BUF_RBM_SW1_BM, 2706 }, 2707 { 2708 .tcl_ring_num = 2, 2709 .wbm_ring_num = 2, 2710 .rbm_id = HAL_RX_BUF_RBM_SW2_BM, 2711 }, 2712 }; 2713 2714 static const struct ath11k_hw_tcl2wbm_rbm_map ath11k_hw_tcl2wbm_rbm_map_wcn6750[] = { 2715 { 2716 .tcl_ring_num = 0, 2717 .wbm_ring_num = 0, 2718 .rbm_id = HAL_RX_BUF_RBM_SW0_BM, 2719 }, 2720 { 2721 .tcl_ring_num = 1, 2722 .wbm_ring_num = 4, 2723 .rbm_id = HAL_RX_BUF_RBM_SW4_BM, 2724 }, 2725 { 2726 .tcl_ring_num = 2, 2727 .wbm_ring_num = 2, 2728 .rbm_id = HAL_RX_BUF_RBM_SW2_BM, 2729 }, 2730 }; 2731 2732 const struct ath11k_hw_regs ipq5018_regs = { 2733 /* SW2TCL(x) R0 ring configuration address */ 2734 .hal_tcl1_ring_base_lsb = 0x00000694, 2735 .hal_tcl1_ring_base_msb = 0x00000698, 2736 .hal_tcl1_ring_id = 0x0000069c, 2737 .hal_tcl1_ring_misc = 0x000006a4, 2738 .hal_tcl1_ring_tp_addr_lsb = 0x000006b0, 2739 .hal_tcl1_ring_tp_addr_msb = 0x000006b4, 2740 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4, 2741 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8, 2742 .hal_tcl1_ring_msi1_base_lsb = 0x000006dc, 2743 .hal_tcl1_ring_msi1_base_msb = 0x000006e0, 2744 .hal_tcl1_ring_msi1_data = 0x000006e4, 2745 .hal_tcl2_ring_base_lsb = 0x000006ec, 2746 .hal_tcl_ring_base_lsb = 0x0000079c, 2747 2748 /* TCL STATUS ring address */ 2749 .hal_tcl_status_ring_base_lsb = 0x000008a4, 2750 2751 /* REO2SW(x) R0 ring configuration address */ 2752 .hal_reo1_ring_base_lsb = 0x000001ec, 2753 .hal_reo1_ring_base_msb = 0x000001f0, 2754 .hal_reo1_ring_id = 0x000001f4, 2755 .hal_reo1_ring_misc = 0x000001fc, 2756 .hal_reo1_ring_hp_addr_lsb = 0x00000200, 2757 .hal_reo1_ring_hp_addr_msb = 0x00000204, 2758 .hal_reo1_ring_producer_int_setup = 0x00000210, 2759 .hal_reo1_ring_msi1_base_lsb = 0x00000234, 2760 .hal_reo1_ring_msi1_base_msb = 0x00000238, 2761 .hal_reo1_ring_msi1_data = 0x0000023c, 2762 .hal_reo2_ring_base_lsb = 0x00000244, 2763 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2764 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2765 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2766 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2767 2768 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2769 .hal_reo1_ring_hp = 0x00003028, 2770 .hal_reo1_ring_tp = 0x0000302c, 2771 .hal_reo2_ring_hp = 0x00003030, 2772 2773 /* REO2TCL R0 ring configuration address */ 2774 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2775 .hal_reo_tcl_ring_hp = 0x00003058, 2776 2777 /* SW2REO ring address */ 2778 .hal_sw2reo_ring_base_lsb = 0x0000013c, 2779 .hal_sw2reo_ring_hp = 0x00003018, 2780 2781 /* REO CMD ring address */ 2782 .hal_reo_cmd_ring_base_lsb = 0x000000e4, 2783 .hal_reo_cmd_ring_hp = 0x00003010, 2784 2785 /* REO status address */ 2786 .hal_reo_status_ring_base_lsb = 0x00000504, 2787 .hal_reo_status_hp = 0x00003070, 2788 2789 /* WCSS relative address */ 2790 .hal_seq_wcss_umac_ce0_src_reg = 0x08400000 2791 - HAL_IPQ5018_CE_WFSS_REG_BASE, 2792 .hal_seq_wcss_umac_ce0_dst_reg = 0x08401000 2793 - HAL_IPQ5018_CE_WFSS_REG_BASE, 2794 .hal_seq_wcss_umac_ce1_src_reg = 0x08402000 2795 - HAL_IPQ5018_CE_WFSS_REG_BASE, 2796 .hal_seq_wcss_umac_ce1_dst_reg = 0x08403000 2797 - HAL_IPQ5018_CE_WFSS_REG_BASE, 2798 2799 /* WBM Idle address */ 2800 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2801 .hal_wbm_idle_link_ring_misc = 0x00000884, 2802 2803 /* SW2WBM release address */ 2804 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2805 2806 /* WBM2SW release address */ 2807 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2808 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2809 }; 2810 2811 const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = { 2812 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 2813 .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074, 2814 }; 2815 2816 const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390 = { 2817 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 2818 .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074, 2819 }; 2820 2821 const struct ath11k_hw_hal_params ath11k_hw_hal_params_wcn6750 = { 2822 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 2823 .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_wcn6750, 2824 }; 2825 2826 static const struct cfg80211_sar_freq_ranges ath11k_hw_sar_freq_ranges_wcn6855[] = { 2827 {.start_freq = 2402, .end_freq = 2482 }, /* 2G ch1~ch13 */ 2828 {.start_freq = 5150, .end_freq = 5250 }, /* 5G UNII-1 ch32~ch48 */ 2829 {.start_freq = 5250, .end_freq = 5725 }, /* 5G UNII-2 ch50~ch144 */ 2830 {.start_freq = 5725, .end_freq = 5810 }, /* 5G UNII-3 ch149~ch161 */ 2831 {.start_freq = 5815, .end_freq = 5895 }, /* 5G UNII-4 ch163~ch177 */ 2832 {.start_freq = 5925, .end_freq = 6165 }, /* 6G UNII-5 Ch1, Ch2 ~ Ch41 */ 2833 {.start_freq = 6165, .end_freq = 6425 }, /* 6G UNII-5 ch45~ch93 */ 2834 {.start_freq = 6425, .end_freq = 6525 }, /* 6G UNII-6 ch97~ch113 */ 2835 {.start_freq = 6525, .end_freq = 6705 }, /* 6G UNII-7 ch117~ch149 */ 2836 {.start_freq = 6705, .end_freq = 6875 }, /* 6G UNII-7 ch153~ch185 */ 2837 {.start_freq = 6875, .end_freq = 7125 }, /* 6G UNII-8 ch189~ch233 */ 2838 }; 2839 2840 const struct cfg80211_sar_capa ath11k_hw_sar_capa_wcn6855 = { 2841 .type = NL80211_SAR_TYPE_POWER, 2842 .num_freq_ranges = (ARRAY_SIZE(ath11k_hw_sar_freq_ranges_wcn6855)), 2843 .freq_ranges = ath11k_hw_sar_freq_ranges_wcn6855, 2844 }; 2845