1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/msi.h> 8 #include <linux/pci.h> 9 #include <linux/of.h> 10 11 #include "pci.h" 12 #include "core.h" 13 #include "hif.h" 14 #include "mhi.h" 15 #include "debug.h" 16 17 #define ATH11K_PCI_BAR_NUM 0 18 #define ATH11K_PCI_DMA_MASK 32 19 20 #define ATH11K_PCI_IRQ_CE0_OFFSET 3 21 #define ATH11K_PCI_IRQ_DP_OFFSET 14 22 23 #define WINDOW_ENABLE_BIT 0x40000000 24 #define WINDOW_REG_ADDRESS 0x310c 25 #define WINDOW_VALUE_MASK GENMASK(24, 19) 26 #define WINDOW_START 0x80000 27 #define WINDOW_RANGE_MASK GENMASK(18, 0) 28 29 #define TCSR_SOC_HW_VERSION 0x0224 30 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8) 31 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0) 32 33 /* BAR0 + 4k is always accessible, and no 34 * need to force wakeup. 35 * 4K - 32 = 0xFE0 36 */ 37 #define ACCESS_ALWAYS_OFF 0xFE0 38 39 #define QCA6390_DEVICE_ID 0x1101 40 #define QCN9074_DEVICE_ID 0x1104 41 #define WCN6855_DEVICE_ID 0x1103 42 43 static const struct pci_device_id ath11k_pci_id_table[] = { 44 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) }, 45 { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) }, 46 { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) }, 47 {0} 48 }; 49 50 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table); 51 52 static const struct ath11k_bus_params ath11k_pci_bus_params = { 53 .mhi_support = true, 54 .m3_fw_support = true, 55 .fixed_bdf_addr = false, 56 .fixed_mem_region = false, 57 }; 58 59 static const struct ath11k_msi_config ath11k_msi_config[] = { 60 { 61 .total_vectors = 32, 62 .total_users = 4, 63 .users = (struct ath11k_msi_user[]) { 64 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 65 { .name = "CE", .num_vectors = 10, .base_vector = 3 }, 66 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 }, 67 { .name = "DP", .num_vectors = 18, .base_vector = 14 }, 68 }, 69 }, 70 { 71 .total_vectors = 16, 72 .total_users = 3, 73 .users = (struct ath11k_msi_user[]) { 74 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 75 { .name = "CE", .num_vectors = 5, .base_vector = 3 }, 76 { .name = "DP", .num_vectors = 8, .base_vector = 8 }, 77 }, 78 }, 79 }; 80 81 static const struct ath11k_msi_config msi_config_one_msi = { 82 .total_vectors = 1, 83 .total_users = 4, 84 .users = (struct ath11k_msi_user[]) { 85 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 86 { .name = "CE", .num_vectors = 1, .base_vector = 0 }, 87 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 }, 88 { .name = "DP", .num_vectors = 1, .base_vector = 0 }, 89 }, 90 }; 91 92 static const char *irq_name[ATH11K_IRQ_NUM_MAX] = { 93 "bhi", 94 "mhi-er0", 95 "mhi-er1", 96 "ce0", 97 "ce1", 98 "ce2", 99 "ce3", 100 "ce4", 101 "ce5", 102 "ce6", 103 "ce7", 104 "ce8", 105 "ce9", 106 "ce10", 107 "ce11", 108 "host2wbm-desc-feed", 109 "host2reo-re-injection", 110 "host2reo-command", 111 "host2rxdma-monitor-ring3", 112 "host2rxdma-monitor-ring2", 113 "host2rxdma-monitor-ring1", 114 "reo2ost-exception", 115 "wbm2host-rx-release", 116 "reo2host-status", 117 "reo2host-destination-ring4", 118 "reo2host-destination-ring3", 119 "reo2host-destination-ring2", 120 "reo2host-destination-ring1", 121 "rxdma2host-monitor-destination-mac3", 122 "rxdma2host-monitor-destination-mac2", 123 "rxdma2host-monitor-destination-mac1", 124 "ppdu-end-interrupts-mac3", 125 "ppdu-end-interrupts-mac2", 126 "ppdu-end-interrupts-mac1", 127 "rxdma2host-monitor-status-ring-mac3", 128 "rxdma2host-monitor-status-ring-mac2", 129 "rxdma2host-monitor-status-ring-mac1", 130 "host2rxdma-host-buf-ring-mac3", 131 "host2rxdma-host-buf-ring-mac2", 132 "host2rxdma-host-buf-ring-mac1", 133 "rxdma2host-destination-ring-mac3", 134 "rxdma2host-destination-ring-mac2", 135 "rxdma2host-destination-ring-mac1", 136 "host2tcl-input-ring4", 137 "host2tcl-input-ring3", 138 "host2tcl-input-ring2", 139 "host2tcl-input-ring1", 140 "wbm2host-tx-completions-ring3", 141 "wbm2host-tx-completions-ring2", 142 "wbm2host-tx-completions-ring1", 143 "tcl2host-status-ring", 144 }; 145 146 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset) 147 { 148 struct ath11k_base *ab = ab_pci->ab; 149 150 u32 window = FIELD_GET(WINDOW_VALUE_MASK, offset); 151 152 lockdep_assert_held(&ab_pci->window_lock); 153 154 if (window != ab_pci->register_window) { 155 iowrite32(WINDOW_ENABLE_BIT | window, 156 ab->mem + WINDOW_REG_ADDRESS); 157 ioread32(ab->mem + WINDOW_REG_ADDRESS); 158 ab_pci->register_window = window; 159 } 160 } 161 162 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci) 163 { 164 u32 umac_window = FIELD_GET(WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET); 165 u32 ce_window = FIELD_GET(WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE); 166 u32 window; 167 168 window = (umac_window << 12) | (ce_window << 6); 169 170 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS); 171 } 172 173 static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab, 174 u32 offset) 175 { 176 u32 window_start; 177 178 /* If offset lies within DP register range, use 3rd window */ 179 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) 180 window_start = 3 * WINDOW_START; 181 /* If offset lies within CE register range, use 2nd window */ 182 else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) 183 window_start = 2 * WINDOW_START; 184 else 185 window_start = WINDOW_START; 186 187 return window_start; 188 } 189 190 void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value) 191 { 192 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 193 u32 window_start; 194 195 /* for offset beyond BAR + 4K - 32, may 196 * need to wakeup MHI to access. 197 */ 198 if (ab->hw_params.wakeup_mhi && 199 test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 200 offset >= ACCESS_ALWAYS_OFF) 201 mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 202 203 if (offset < WINDOW_START) { 204 iowrite32(value, ab->mem + offset); 205 } else { 206 if (ab->bus_params.static_window_map) 207 window_start = ath11k_pci_get_window_start(ab, offset); 208 else 209 window_start = WINDOW_START; 210 211 if (window_start == WINDOW_START) { 212 spin_lock_bh(&ab_pci->window_lock); 213 ath11k_pci_select_window(ab_pci, offset); 214 iowrite32(value, ab->mem + window_start + 215 (offset & WINDOW_RANGE_MASK)); 216 spin_unlock_bh(&ab_pci->window_lock); 217 } else { 218 iowrite32(value, ab->mem + window_start + 219 (offset & WINDOW_RANGE_MASK)); 220 } 221 } 222 223 if (ab->hw_params.wakeup_mhi && 224 test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 225 offset >= ACCESS_ALWAYS_OFF) 226 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 227 } 228 229 u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset) 230 { 231 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 232 u32 val, window_start; 233 234 /* for offset beyond BAR + 4K - 32, may 235 * need to wakeup MHI to access. 236 */ 237 if (ab->hw_params.wakeup_mhi && 238 test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 239 offset >= ACCESS_ALWAYS_OFF) 240 mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 241 242 if (offset < WINDOW_START) { 243 val = ioread32(ab->mem + offset); 244 } else { 245 if (ab->bus_params.static_window_map) 246 window_start = ath11k_pci_get_window_start(ab, offset); 247 else 248 window_start = WINDOW_START; 249 250 if (window_start == WINDOW_START) { 251 spin_lock_bh(&ab_pci->window_lock); 252 ath11k_pci_select_window(ab_pci, offset); 253 val = ioread32(ab->mem + window_start + 254 (offset & WINDOW_RANGE_MASK)); 255 spin_unlock_bh(&ab_pci->window_lock); 256 } else { 257 val = ioread32(ab->mem + window_start + 258 (offset & WINDOW_RANGE_MASK)); 259 } 260 } 261 262 if (ab->hw_params.wakeup_mhi && 263 test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 264 offset >= ACCESS_ALWAYS_OFF) 265 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 266 267 return val; 268 } 269 270 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab) 271 { 272 u32 val, delay; 273 274 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 275 276 val |= PCIE_SOC_GLOBAL_RESET_V; 277 278 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 279 280 /* TODO: exact time to sleep is uncertain */ 281 delay = 10; 282 mdelay(delay); 283 284 /* Need to toggle V bit back otherwise stuck in reset status */ 285 val &= ~PCIE_SOC_GLOBAL_RESET_V; 286 287 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 288 289 mdelay(delay); 290 291 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 292 if (val == 0xffffffff) 293 ath11k_warn(ab, "link down error during global reset\n"); 294 } 295 296 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab) 297 { 298 u32 val; 299 300 /* read cookie */ 301 val = ath11k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR); 302 ath11k_dbg(ab, ATH11K_DBG_PCI, "cookie:0x%x\n", val); 303 304 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 305 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 306 307 /* TODO: exact time to sleep is uncertain */ 308 mdelay(10); 309 310 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 311 * continuing warm path and entering dead loop. 312 */ 313 ath11k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0); 314 mdelay(10); 315 316 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 317 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 318 319 /* A read clear register. clear the register to prevent 320 * Q6 from entering wrong code path. 321 */ 322 val = ath11k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 323 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause:%d\n", val); 324 } 325 326 static int ath11k_pci_set_link_reg(struct ath11k_base *ab, 327 u32 offset, u32 value, u32 mask) 328 { 329 u32 v; 330 int i; 331 332 v = ath11k_pci_read32(ab, offset); 333 if ((v & mask) == value) 334 return 0; 335 336 for (i = 0; i < 10; i++) { 337 ath11k_pci_write32(ab, offset, (v & ~mask) | value); 338 339 v = ath11k_pci_read32(ab, offset); 340 if ((v & mask) == value) 341 return 0; 342 343 mdelay(2); 344 } 345 346 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n", 347 offset, v & mask, value); 348 349 return -ETIMEDOUT; 350 } 351 352 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab) 353 { 354 int ret; 355 356 ret = ath11k_pci_set_link_reg(ab, 357 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab), 358 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL, 359 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK); 360 if (ret) { 361 ath11k_warn(ab, "failed to set sysclk: %d\n", ret); 362 return ret; 363 } 364 365 ret = ath11k_pci_set_link_reg(ab, 366 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab), 367 PCIE_PCS_OSC_DTCT_CONFIG1_VAL, 368 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 369 if (ret) { 370 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret); 371 return ret; 372 } 373 374 ret = ath11k_pci_set_link_reg(ab, 375 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab), 376 PCIE_PCS_OSC_DTCT_CONFIG2_VAL, 377 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 378 if (ret) { 379 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret); 380 return ret; 381 } 382 383 ret = ath11k_pci_set_link_reg(ab, 384 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab), 385 PCIE_PCS_OSC_DTCT_CONFIG4_VAL, 386 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 387 if (ret) { 388 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret); 389 return ret; 390 } 391 392 return 0; 393 } 394 395 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab) 396 { 397 u32 val; 398 int i; 399 400 val = ath11k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 401 402 /* PCIE link seems very unstable after the Hot Reset*/ 403 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) { 404 if (val == 0xffffffff) 405 mdelay(5); 406 407 ath11k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE); 408 val = ath11k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 409 } 410 411 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci ltssm 0x%x\n", val); 412 413 val = ath11k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST); 414 val |= GCC_GCC_PCIE_HOT_RST_VAL; 415 ath11k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val); 416 val = ath11k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST); 417 418 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val); 419 420 mdelay(5); 421 } 422 423 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab) 424 { 425 /* This is a WAR for PCIE Hotreset. 426 * When target receive Hotreset, but will set the interrupt. 427 * So when download SBL again, SBL will open Interrupt and 428 * receive it, and crash immediately. 429 */ 430 ath11k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL); 431 } 432 433 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab) 434 { 435 u32 val; 436 437 val = ath11k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG); 438 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK; 439 ath11k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val); 440 } 441 442 static void ath11k_pci_force_wake(struct ath11k_base *ab) 443 { 444 ath11k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 445 mdelay(5); 446 } 447 448 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on) 449 { 450 mdelay(100); 451 452 if (power_on) { 453 ath11k_pci_enable_ltssm(ab); 454 ath11k_pci_clear_all_intrs(ab); 455 ath11k_pci_set_wlaon_pwr_ctrl(ab); 456 if (ab->hw_params.fix_l1ss) 457 ath11k_pci_fix_l1ss(ab); 458 } 459 460 ath11k_mhi_clear_vector(ab); 461 ath11k_pci_clear_dbg_registers(ab); 462 ath11k_pci_soc_global_reset(ab); 463 ath11k_mhi_set_mhictrl_reset(ab); 464 } 465 466 int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector) 467 { 468 struct pci_dev *pci_dev = to_pci_dev(dev); 469 470 return pci_irq_vector(pci_dev, vector); 471 } 472 473 static void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo, 474 u32 *msi_addr_hi) 475 { 476 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 477 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 478 479 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 480 msi_addr_lo); 481 482 if (test_bit(ATH11K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) { 483 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 484 msi_addr_hi); 485 } else { 486 *msi_addr_hi = 0; 487 } 488 } 489 490 int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ab_pci, char *user_name, 491 int *num_vectors, u32 *user_base_data, 492 u32 *base_vector) 493 { 494 struct ath11k_base *ab = ab_pci->ab; 495 const struct ath11k_msi_config *msi_config = ab_pci->msi_config; 496 int idx; 497 498 for (idx = 0; idx < msi_config->total_users; idx++) { 499 if (strcmp(user_name, msi_config->users[idx].name) == 0) { 500 *num_vectors = msi_config->users[idx].num_vectors; 501 *base_vector = msi_config->users[idx].base_vector; 502 *user_base_data = *base_vector + ab_pci->msi_ep_base_data; 503 504 ath11k_dbg(ab, ATH11K_DBG_PCI, 505 "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n", 506 user_name, *num_vectors, *user_base_data, 507 *base_vector); 508 509 return 0; 510 } 511 } 512 513 ath11k_err(ab, "Failed to find MSI assignment for %s!\n", user_name); 514 515 return -EINVAL; 516 } 517 518 static void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, 519 u32 *msi_idx) 520 { 521 u32 i, msi_data_idx; 522 523 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) { 524 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 525 continue; 526 527 if (ce_id == i) 528 break; 529 530 msi_data_idx++; 531 } 532 *msi_idx = msi_data_idx; 533 } 534 535 static int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name, 536 int *num_vectors, u32 *user_base_data, 537 u32 *base_vector) 538 { 539 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 540 541 return ath11k_pci_get_user_msi_assignment(ab_pci, user_name, 542 num_vectors, user_base_data, 543 base_vector); 544 } 545 546 static void ath11k_pci_free_ext_irq(struct ath11k_base *ab) 547 { 548 int i, j; 549 550 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 551 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 552 553 for (j = 0; j < irq_grp->num_irq; j++) 554 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); 555 556 netif_napi_del(&irq_grp->napi); 557 } 558 } 559 560 static void ath11k_pci_free_irq(struct ath11k_base *ab) 561 { 562 int i, irq_idx; 563 564 for (i = 0; i < ab->hw_params.ce_count; i++) { 565 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 566 continue; 567 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 568 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); 569 } 570 571 ath11k_pci_free_ext_irq(ab); 572 } 573 574 static void ath11k_pci_ce_irq_enable(struct ath11k_base *ab, u16 ce_id) 575 { 576 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 577 u32 irq_idx; 578 579 /* In case of one MSI vector, we handle irq enable/disable in a 580 * uniform way since we only have one irq 581 */ 582 if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 583 return; 584 585 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id; 586 enable_irq(ab->irq_num[irq_idx]); 587 } 588 589 static void ath11k_pci_ce_irq_disable(struct ath11k_base *ab, u16 ce_id) 590 { 591 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 592 u32 irq_idx; 593 594 /* In case of one MSI vector, we handle irq enable/disable in a 595 * uniform way since we only have one irq 596 */ 597 if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 598 return; 599 600 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id; 601 disable_irq_nosync(ab->irq_num[irq_idx]); 602 } 603 604 static void ath11k_pci_ce_irqs_disable(struct ath11k_base *ab) 605 { 606 int i; 607 608 clear_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); 609 610 for (i = 0; i < ab->hw_params.ce_count; i++) { 611 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 612 continue; 613 ath11k_pci_ce_irq_disable(ab, i); 614 } 615 } 616 617 static void ath11k_pci_sync_ce_irqs(struct ath11k_base *ab) 618 { 619 int i; 620 int irq_idx; 621 622 for (i = 0; i < ab->hw_params.ce_count; i++) { 623 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 624 continue; 625 626 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 627 synchronize_irq(ab->irq_num[irq_idx]); 628 } 629 } 630 631 static void ath11k_pci_ce_tasklet(struct tasklet_struct *t) 632 { 633 struct ath11k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq); 634 int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; 635 636 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); 637 638 enable_irq(ce_pipe->ab->irq_num[irq_idx]); 639 } 640 641 static irqreturn_t ath11k_pci_ce_interrupt_handler(int irq, void *arg) 642 { 643 struct ath11k_ce_pipe *ce_pipe = arg; 644 struct ath11k_base *ab = ce_pipe->ab; 645 int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; 646 647 if (!test_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags)) 648 return IRQ_HANDLED; 649 650 /* last interrupt received for this CE */ 651 ce_pipe->timestamp = jiffies; 652 653 disable_irq_nosync(ab->irq_num[irq_idx]); 654 655 tasklet_schedule(&ce_pipe->intr_tq); 656 657 return IRQ_HANDLED; 658 } 659 660 static void ath11k_pci_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp) 661 { 662 struct ath11k_pci *ab_pci = ath11k_pci_priv(irq_grp->ab); 663 int i; 664 665 /* In case of one MSI vector, we handle irq enable/disable 666 * in a uniform way since we only have one irq 667 */ 668 if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 669 return; 670 671 for (i = 0; i < irq_grp->num_irq; i++) 672 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 673 } 674 675 static void __ath11k_pci_ext_irq_disable(struct ath11k_base *sc) 676 { 677 int i; 678 679 clear_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &sc->dev_flags); 680 681 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 682 struct ath11k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i]; 683 684 ath11k_pci_ext_grp_disable(irq_grp); 685 686 if (irq_grp->napi_enabled) { 687 napi_synchronize(&irq_grp->napi); 688 napi_disable(&irq_grp->napi); 689 irq_grp->napi_enabled = false; 690 } 691 } 692 } 693 694 static void ath11k_pci_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp) 695 { 696 struct ath11k_pci *ab_pci = ath11k_pci_priv(irq_grp->ab); 697 int i; 698 699 /* In case of one MSI vector, we handle irq enable/disable in a 700 * uniform way since we only have one irq 701 */ 702 if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 703 return; 704 705 for (i = 0; i < irq_grp->num_irq; i++) 706 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 707 } 708 709 static void ath11k_pci_ext_irq_enable(struct ath11k_base *ab) 710 { 711 int i; 712 713 set_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags); 714 715 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 716 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 717 718 if (!irq_grp->napi_enabled) { 719 napi_enable(&irq_grp->napi); 720 irq_grp->napi_enabled = true; 721 } 722 ath11k_pci_ext_grp_enable(irq_grp); 723 } 724 } 725 726 static void ath11k_pci_sync_ext_irqs(struct ath11k_base *ab) 727 { 728 int i, j, irq_idx; 729 730 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 731 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 732 733 for (j = 0; j < irq_grp->num_irq; j++) { 734 irq_idx = irq_grp->irqs[j]; 735 synchronize_irq(ab->irq_num[irq_idx]); 736 } 737 } 738 } 739 740 static void ath11k_pci_ext_irq_disable(struct ath11k_base *ab) 741 { 742 __ath11k_pci_ext_irq_disable(ab); 743 ath11k_pci_sync_ext_irqs(ab); 744 } 745 746 static int ath11k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget) 747 { 748 struct ath11k_ext_irq_grp *irq_grp = container_of(napi, 749 struct ath11k_ext_irq_grp, 750 napi); 751 struct ath11k_base *ab = irq_grp->ab; 752 int work_done; 753 int i; 754 755 work_done = ath11k_dp_service_srng(ab, irq_grp, budget); 756 if (work_done < budget) { 757 napi_complete_done(napi, work_done); 758 for (i = 0; i < irq_grp->num_irq; i++) 759 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 760 } 761 762 if (work_done > budget) 763 work_done = budget; 764 765 return work_done; 766 } 767 768 static irqreturn_t ath11k_pci_ext_interrupt_handler(int irq, void *arg) 769 { 770 struct ath11k_ext_irq_grp *irq_grp = arg; 771 struct ath11k_base *ab = irq_grp->ab; 772 int i; 773 774 if (!test_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) 775 return IRQ_HANDLED; 776 777 ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq:%d\n", irq); 778 779 /* last interrupt received for this group */ 780 irq_grp->timestamp = jiffies; 781 782 for (i = 0; i < irq_grp->num_irq; i++) 783 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 784 785 napi_schedule(&irq_grp->napi); 786 787 return IRQ_HANDLED; 788 } 789 790 static int ath11k_pci_ext_irq_config(struct ath11k_base *ab) 791 { 792 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 793 int i, j, ret, num_vectors = 0; 794 u32 user_base_data = 0, base_vector = 0; 795 796 ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), "DP", 797 &num_vectors, 798 &user_base_data, 799 &base_vector); 800 if (ret < 0) 801 return ret; 802 803 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 804 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 805 u32 num_irq = 0; 806 807 irq_grp->ab = ab; 808 irq_grp->grp_id = i; 809 init_dummy_netdev(&irq_grp->napi_ndev); 810 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, 811 ath11k_pci_ext_grp_napi_poll, NAPI_POLL_WEIGHT); 812 813 if (ab->hw_params.ring_mask->tx[i] || 814 ab->hw_params.ring_mask->rx[i] || 815 ab->hw_params.ring_mask->rx_err[i] || 816 ab->hw_params.ring_mask->rx_wbm_rel[i] || 817 ab->hw_params.ring_mask->reo_status[i] || 818 ab->hw_params.ring_mask->rxdma2host[i] || 819 ab->hw_params.ring_mask->host2rxdma[i] || 820 ab->hw_params.ring_mask->rx_mon_status[i]) { 821 num_irq = 1; 822 } 823 824 irq_grp->num_irq = num_irq; 825 irq_grp->irqs[0] = ATH11K_PCI_IRQ_DP_OFFSET + i; 826 827 for (j = 0; j < irq_grp->num_irq; j++) { 828 int irq_idx = irq_grp->irqs[j]; 829 int vector = (i % num_vectors) + base_vector; 830 int irq = ath11k_pci_get_msi_irq(ab->dev, vector); 831 832 ab->irq_num[irq_idx] = irq; 833 834 ath11k_dbg(ab, ATH11K_DBG_PCI, 835 "irq:%d group:%d\n", irq, i); 836 837 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); 838 ret = request_irq(irq, ath11k_pci_ext_interrupt_handler, 839 ab_pci->irq_flags, 840 "DP_EXT_IRQ", irq_grp); 841 if (ret) { 842 ath11k_err(ab, "failed request irq %d: %d\n", 843 vector, ret); 844 return ret; 845 } 846 } 847 ath11k_pci_ext_grp_disable(irq_grp); 848 } 849 850 return 0; 851 } 852 853 static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci, 854 const struct cpumask *m) 855 { 856 if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 857 return 0; 858 859 return irq_set_affinity_hint(ab_pci->pdev->irq, m); 860 } 861 862 static int ath11k_pci_config_irq(struct ath11k_base *ab) 863 { 864 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 865 struct ath11k_ce_pipe *ce_pipe; 866 u32 msi_data_start; 867 u32 msi_data_count, msi_data_idx; 868 u32 msi_irq_start; 869 unsigned int msi_data; 870 int irq, i, ret, irq_idx; 871 872 ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), 873 "CE", &msi_data_count, 874 &msi_data_start, &msi_irq_start); 875 if (ret) 876 return ret; 877 878 ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0)); 879 if (ret) { 880 ath11k_err(ab, "failed to set irq affinity %d\n", ret); 881 return ret; 882 } 883 884 /* Configure CE irqs */ 885 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) { 886 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 887 continue; 888 889 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start; 890 irq = ath11k_pci_get_msi_irq(ab->dev, msi_data); 891 ce_pipe = &ab->ce.ce_pipe[i]; 892 893 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 894 895 tasklet_setup(&ce_pipe->intr_tq, ath11k_pci_ce_tasklet); 896 897 ret = request_irq(irq, ath11k_pci_ce_interrupt_handler, 898 ab_pci->irq_flags, irq_name[irq_idx], 899 ce_pipe); 900 if (ret) { 901 ath11k_err(ab, "failed to request irq %d: %d\n", 902 irq_idx, ret); 903 goto err_irq_affinity_cleanup; 904 } 905 906 ab->irq_num[irq_idx] = irq; 907 msi_data_idx++; 908 909 ath11k_pci_ce_irq_disable(ab, i); 910 } 911 912 ret = ath11k_pci_ext_irq_config(ab); 913 if (ret) 914 goto err_irq_affinity_cleanup; 915 916 return 0; 917 918 err_irq_affinity_cleanup: 919 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 920 return ret; 921 } 922 923 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab) 924 { 925 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 926 927 cfg->tgt_ce = ab->hw_params.target_ce_config; 928 cfg->tgt_ce_len = ab->hw_params.target_ce_count; 929 930 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map; 931 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len; 932 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id; 933 934 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2, 935 &cfg->shadow_reg_v2_len); 936 } 937 938 static void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab) 939 { 940 int i; 941 942 set_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); 943 944 for (i = 0; i < ab->hw_params.ce_count; i++) { 945 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 946 continue; 947 ath11k_pci_ce_irq_enable(ab, i); 948 } 949 } 950 951 static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable) 952 { 953 struct pci_dev *dev = ab_pci->pdev; 954 u16 control; 955 956 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 957 958 if (enable) 959 control |= PCI_MSI_FLAGS_ENABLE; 960 else 961 control &= ~PCI_MSI_FLAGS_ENABLE; 962 963 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 964 } 965 966 static void ath11k_pci_msi_enable(struct ath11k_pci *ab_pci) 967 { 968 ath11k_pci_msi_config(ab_pci, true); 969 } 970 971 static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci) 972 { 973 ath11k_pci_msi_config(ab_pci, false); 974 } 975 976 static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci) 977 { 978 struct ath11k_base *ab = ab_pci->ab; 979 const struct ath11k_msi_config *msi_config = ab_pci->msi_config; 980 struct msi_desc *msi_desc; 981 int num_vectors; 982 int ret; 983 984 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 985 msi_config->total_vectors, 986 msi_config->total_vectors, 987 PCI_IRQ_MSI); 988 if (num_vectors == msi_config->total_vectors) { 989 set_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags); 990 ab_pci->irq_flags = IRQF_SHARED; 991 } else { 992 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 993 1, 994 1, 995 PCI_IRQ_MSI); 996 if (num_vectors < 0) { 997 ret = -EINVAL; 998 goto reset_msi_config; 999 } 1000 clear_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags); 1001 ab_pci->msi_config = &msi_config_one_msi; 1002 ab_pci->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 1003 ath11k_dbg(ab, ATH11K_DBG_PCI, "request MSI one vector\n"); 1004 } 1005 ath11k_info(ab, "MSI vectors: %d\n", num_vectors); 1006 1007 ath11k_pci_msi_disable(ab_pci); 1008 1009 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 1010 if (!msi_desc) { 1011 ath11k_err(ab, "msi_desc is NULL!\n"); 1012 ret = -EINVAL; 1013 goto free_msi_vector; 1014 } 1015 1016 ab_pci->msi_ep_base_data = msi_desc->msg.data; 1017 if (msi_desc->pci.msi_attrib.is_64) 1018 set_bit(ATH11K_PCI_FLAG_IS_MSI_64, &ab_pci->flags); 1019 1020 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); 1021 1022 return 0; 1023 1024 free_msi_vector: 1025 pci_free_irq_vectors(ab_pci->pdev); 1026 1027 reset_msi_config: 1028 return ret; 1029 } 1030 1031 static void ath11k_pci_free_msi(struct ath11k_pci *ab_pci) 1032 { 1033 pci_free_irq_vectors(ab_pci->pdev); 1034 } 1035 1036 static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci) 1037 { 1038 struct msi_desc *msi_desc; 1039 1040 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 1041 if (!msi_desc) { 1042 ath11k_err(ab_pci->ab, "msi_desc is NULL!\n"); 1043 pci_free_irq_vectors(ab_pci->pdev); 1044 return -EINVAL; 1045 } 1046 1047 ab_pci->msi_ep_base_data = msi_desc->msg.data; 1048 1049 ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n", 1050 ab_pci->msi_ep_base_data); 1051 1052 return 0; 1053 } 1054 1055 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev) 1056 { 1057 struct ath11k_base *ab = ab_pci->ab; 1058 u16 device_id; 1059 int ret = 0; 1060 1061 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 1062 if (device_id != ab_pci->dev_id) { 1063 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 1064 device_id, ab_pci->dev_id); 1065 ret = -EIO; 1066 goto out; 1067 } 1068 1069 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM); 1070 if (ret) { 1071 ath11k_err(ab, "failed to assign pci resource: %d\n", ret); 1072 goto out; 1073 } 1074 1075 ret = pci_enable_device(pdev); 1076 if (ret) { 1077 ath11k_err(ab, "failed to enable pci device: %d\n", ret); 1078 goto out; 1079 } 1080 1081 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci"); 1082 if (ret) { 1083 ath11k_err(ab, "failed to request pci region: %d\n", ret); 1084 goto disable_device; 1085 } 1086 1087 ret = dma_set_mask_and_coherent(&pdev->dev, 1088 DMA_BIT_MASK(ATH11K_PCI_DMA_MASK)); 1089 if (ret) { 1090 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n", 1091 ATH11K_PCI_DMA_MASK, ret); 1092 goto release_region; 1093 } 1094 1095 pci_set_master(pdev); 1096 1097 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM); 1098 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0); 1099 if (!ab->mem) { 1100 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM); 1101 ret = -EIO; 1102 goto clear_master; 1103 } 1104 1105 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem); 1106 return 0; 1107 1108 clear_master: 1109 pci_clear_master(pdev); 1110 release_region: 1111 pci_release_region(pdev, ATH11K_PCI_BAR_NUM); 1112 disable_device: 1113 pci_disable_device(pdev); 1114 out: 1115 return ret; 1116 } 1117 1118 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci) 1119 { 1120 struct ath11k_base *ab = ab_pci->ab; 1121 struct pci_dev *pci_dev = ab_pci->pdev; 1122 1123 pci_iounmap(pci_dev, ab->mem); 1124 ab->mem = NULL; 1125 pci_clear_master(pci_dev); 1126 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM); 1127 if (pci_is_enabled(pci_dev)) 1128 pci_disable_device(pci_dev); 1129 } 1130 1131 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci) 1132 { 1133 struct ath11k_base *ab = ab_pci->ab; 1134 1135 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, 1136 &ab_pci->link_ctl); 1137 1138 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n", 1139 ab_pci->link_ctl, 1140 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), 1141 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); 1142 1143 /* disable L0s and L1 */ 1144 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, 1145 ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); 1146 1147 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags); 1148 } 1149 1150 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci) 1151 { 1152 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags)) 1153 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, 1154 ab_pci->link_ctl); 1155 } 1156 1157 static int ath11k_pci_power_up(struct ath11k_base *ab) 1158 { 1159 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1160 int ret; 1161 1162 ab_pci->register_window = 0; 1163 clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1164 ath11k_pci_sw_reset(ab_pci->ab, true); 1165 1166 /* Disable ASPM during firmware download due to problems switching 1167 * to AMSS state. 1168 */ 1169 ath11k_pci_aspm_disable(ab_pci); 1170 1171 ath11k_pci_msi_enable(ab_pci); 1172 1173 ret = ath11k_mhi_start(ab_pci); 1174 if (ret) { 1175 ath11k_err(ab, "failed to start mhi: %d\n", ret); 1176 return ret; 1177 } 1178 1179 if (ab->bus_params.static_window_map) 1180 ath11k_pci_select_static_window(ab_pci); 1181 1182 return 0; 1183 } 1184 1185 static void ath11k_pci_power_down(struct ath11k_base *ab) 1186 { 1187 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1188 1189 /* restore aspm in case firmware bootup fails */ 1190 ath11k_pci_aspm_restore(ab_pci); 1191 1192 ath11k_pci_force_wake(ab_pci->ab); 1193 1194 ath11k_pci_msi_disable(ab_pci); 1195 1196 ath11k_mhi_stop(ab_pci); 1197 clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1198 ath11k_pci_sw_reset(ab_pci->ab, false); 1199 } 1200 1201 static int ath11k_pci_hif_suspend(struct ath11k_base *ab) 1202 { 1203 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 1204 1205 ath11k_mhi_suspend(ar_pci); 1206 1207 return 0; 1208 } 1209 1210 static int ath11k_pci_hif_resume(struct ath11k_base *ab) 1211 { 1212 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 1213 1214 ath11k_mhi_resume(ar_pci); 1215 1216 return 0; 1217 } 1218 1219 static void ath11k_pci_kill_tasklets(struct ath11k_base *ab) 1220 { 1221 int i; 1222 1223 for (i = 0; i < ab->hw_params.ce_count; i++) { 1224 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 1225 1226 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 1227 continue; 1228 1229 tasklet_kill(&ce_pipe->intr_tq); 1230 } 1231 } 1232 1233 static void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab) 1234 { 1235 ath11k_pci_ce_irqs_disable(ab); 1236 ath11k_pci_sync_ce_irqs(ab); 1237 ath11k_pci_kill_tasklets(ab); 1238 } 1239 1240 static void ath11k_pci_stop(struct ath11k_base *ab) 1241 { 1242 ath11k_pci_ce_irq_disable_sync(ab); 1243 ath11k_ce_cleanup_pipes(ab); 1244 } 1245 1246 static int ath11k_pci_start(struct ath11k_base *ab) 1247 { 1248 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1249 1250 set_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1251 1252 /* TODO: for now don't restore ASPM in case of single MSI 1253 * vector as MHI register reading in M2 causes system hang. 1254 */ 1255 if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 1256 ath11k_pci_aspm_restore(ab_pci); 1257 else 1258 ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n"); 1259 1260 ath11k_pci_ce_irqs_enable(ab); 1261 ath11k_ce_rx_post_buf(ab); 1262 1263 return 0; 1264 } 1265 1266 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab) 1267 { 1268 ath11k_pci_ce_irqs_enable(ab); 1269 } 1270 1271 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab) 1272 { 1273 ath11k_pci_ce_irq_disable_sync(ab); 1274 } 1275 1276 static int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, 1277 u8 *ul_pipe, u8 *dl_pipe) 1278 { 1279 const struct service_to_pipe *entry; 1280 bool ul_set = false, dl_set = false; 1281 int i; 1282 1283 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) { 1284 entry = &ab->hw_params.svc_to_ce_map[i]; 1285 1286 if (__le32_to_cpu(entry->service_id) != service_id) 1287 continue; 1288 1289 switch (__le32_to_cpu(entry->pipedir)) { 1290 case PIPEDIR_NONE: 1291 break; 1292 case PIPEDIR_IN: 1293 WARN_ON(dl_set); 1294 *dl_pipe = __le32_to_cpu(entry->pipenum); 1295 dl_set = true; 1296 break; 1297 case PIPEDIR_OUT: 1298 WARN_ON(ul_set); 1299 *ul_pipe = __le32_to_cpu(entry->pipenum); 1300 ul_set = true; 1301 break; 1302 case PIPEDIR_INOUT: 1303 WARN_ON(dl_set); 1304 WARN_ON(ul_set); 1305 *dl_pipe = __le32_to_cpu(entry->pipenum); 1306 *ul_pipe = __le32_to_cpu(entry->pipenum); 1307 dl_set = true; 1308 ul_set = true; 1309 break; 1310 } 1311 } 1312 1313 if (WARN_ON(!ul_set || !dl_set)) 1314 return -ENOENT; 1315 1316 return 0; 1317 } 1318 1319 static const struct ath11k_hif_ops ath11k_pci_hif_ops = { 1320 .start = ath11k_pci_start, 1321 .stop = ath11k_pci_stop, 1322 .read32 = ath11k_pci_read32, 1323 .write32 = ath11k_pci_write32, 1324 .power_down = ath11k_pci_power_down, 1325 .power_up = ath11k_pci_power_up, 1326 .suspend = ath11k_pci_hif_suspend, 1327 .resume = ath11k_pci_hif_resume, 1328 .irq_enable = ath11k_pci_ext_irq_enable, 1329 .irq_disable = ath11k_pci_ext_irq_disable, 1330 .get_msi_address = ath11k_pci_get_msi_address, 1331 .get_user_msi_vector = ath11k_get_user_msi_assignment, 1332 .map_service_to_pipe = ath11k_pci_map_service_to_pipe, 1333 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable, 1334 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable, 1335 .get_ce_msi_idx = ath11k_pci_get_ce_msi_idx, 1336 }; 1337 1338 static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor) 1339 { 1340 u32 soc_hw_version; 1341 1342 soc_hw_version = ath11k_pci_read32(ab, TCSR_SOC_HW_VERSION); 1343 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, 1344 soc_hw_version); 1345 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, 1346 soc_hw_version); 1347 1348 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n", 1349 *major, *minor); 1350 } 1351 1352 static int ath11k_pci_probe(struct pci_dev *pdev, 1353 const struct pci_device_id *pci_dev) 1354 { 1355 struct ath11k_base *ab; 1356 struct ath11k_pci *ab_pci; 1357 u32 soc_hw_version_major, soc_hw_version_minor, addr; 1358 int ret; 1359 1360 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI, 1361 &ath11k_pci_bus_params); 1362 if (!ab) { 1363 dev_err(&pdev->dev, "failed to allocate ath11k base\n"); 1364 return -ENOMEM; 1365 } 1366 1367 ab->dev = &pdev->dev; 1368 pci_set_drvdata(pdev, ab); 1369 ab_pci = ath11k_pci_priv(ab); 1370 ab_pci->dev_id = pci_dev->device; 1371 ab_pci->ab = ab; 1372 ab_pci->pdev = pdev; 1373 ab->hif.ops = &ath11k_pci_hif_ops; 1374 pci_set_drvdata(pdev, ab); 1375 spin_lock_init(&ab_pci->window_lock); 1376 1377 /* Set fixed_mem_region to true for platforms support reserved memory 1378 * from DT. If memory is reserved from DT for FW, ath11k driver need not 1379 * allocate memory. 1380 */ 1381 ret = of_property_read_u32(ab->dev->of_node, "memory-region", &addr); 1382 if (!ret) 1383 set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags); 1384 1385 ret = ath11k_pci_claim(ab_pci, pdev); 1386 if (ret) { 1387 ath11k_err(ab, "failed to claim device: %d\n", ret); 1388 goto err_free_core; 1389 } 1390 1391 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 1392 pdev->vendor, pdev->device, 1393 pdev->subsystem_vendor, pdev->subsystem_device); 1394 1395 ab->id.vendor = pdev->vendor; 1396 ab->id.device = pdev->device; 1397 ab->id.subsystem_vendor = pdev->subsystem_vendor; 1398 ab->id.subsystem_device = pdev->subsystem_device; 1399 1400 switch (pci_dev->device) { 1401 case QCA6390_DEVICE_ID: 1402 ath11k_pci_read_hw_version(ab, &soc_hw_version_major, 1403 &soc_hw_version_minor); 1404 switch (soc_hw_version_major) { 1405 case 2: 1406 ab->hw_rev = ATH11K_HW_QCA6390_HW20; 1407 break; 1408 default: 1409 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n", 1410 soc_hw_version_major, soc_hw_version_minor); 1411 ret = -EOPNOTSUPP; 1412 goto err_pci_free_region; 1413 } 1414 ab_pci->msi_config = &ath11k_msi_config[0]; 1415 break; 1416 case QCN9074_DEVICE_ID: 1417 ab_pci->msi_config = &ath11k_msi_config[1]; 1418 ab->bus_params.static_window_map = true; 1419 ab->hw_rev = ATH11K_HW_QCN9074_HW10; 1420 break; 1421 case WCN6855_DEVICE_ID: 1422 ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD; 1423 ath11k_pci_read_hw_version(ab, &soc_hw_version_major, 1424 &soc_hw_version_minor); 1425 switch (soc_hw_version_major) { 1426 case 2: 1427 switch (soc_hw_version_minor) { 1428 case 0x00: 1429 case 0x01: 1430 ab->hw_rev = ATH11K_HW_WCN6855_HW20; 1431 break; 1432 case 0x10: 1433 case 0x11: 1434 ab->hw_rev = ATH11K_HW_WCN6855_HW21; 1435 break; 1436 default: 1437 goto unsupported_wcn6855_soc; 1438 } 1439 break; 1440 default: 1441 unsupported_wcn6855_soc: 1442 dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n", 1443 soc_hw_version_major, soc_hw_version_minor); 1444 ret = -EOPNOTSUPP; 1445 goto err_pci_free_region; 1446 } 1447 ab_pci->msi_config = &ath11k_msi_config[0]; 1448 break; 1449 default: 1450 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", 1451 pci_dev->device); 1452 ret = -EOPNOTSUPP; 1453 goto err_pci_free_region; 1454 } 1455 1456 ret = ath11k_pci_alloc_msi(ab_pci); 1457 if (ret) { 1458 ath11k_err(ab, "failed to enable msi: %d\n", ret); 1459 goto err_pci_free_region; 1460 } 1461 1462 ret = ath11k_core_pre_init(ab); 1463 if (ret) 1464 goto err_pci_disable_msi; 1465 1466 ret = ath11k_mhi_register(ab_pci); 1467 if (ret) { 1468 ath11k_err(ab, "failed to register mhi: %d\n", ret); 1469 goto err_pci_disable_msi; 1470 } 1471 1472 ret = ath11k_hal_srng_init(ab); 1473 if (ret) 1474 goto err_mhi_unregister; 1475 1476 ret = ath11k_ce_alloc_pipes(ab); 1477 if (ret) { 1478 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret); 1479 goto err_hal_srng_deinit; 1480 } 1481 1482 ath11k_pci_init_qmi_ce_config(ab); 1483 1484 ret = ath11k_pci_config_irq(ab); 1485 if (ret) { 1486 ath11k_err(ab, "failed to config irq: %d\n", ret); 1487 goto err_ce_free; 1488 } 1489 1490 /* kernel may allocate a dummy vector before request_irq and 1491 * then allocate a real vector when request_irq is called. 1492 * So get msi_data here again to avoid spurious interrupt 1493 * as msi_data will configured to srngs. 1494 */ 1495 ret = ath11k_pci_config_msi_data(ab_pci); 1496 if (ret) { 1497 ath11k_err(ab, "failed to config msi_data: %d\n", ret); 1498 goto err_free_irq; 1499 } 1500 1501 ret = ath11k_core_init(ab); 1502 if (ret) { 1503 ath11k_err(ab, "failed to init core: %d\n", ret); 1504 goto err_free_irq; 1505 } 1506 return 0; 1507 1508 err_free_irq: 1509 ath11k_pci_free_irq(ab); 1510 1511 err_ce_free: 1512 ath11k_ce_free_pipes(ab); 1513 1514 err_hal_srng_deinit: 1515 ath11k_hal_srng_deinit(ab); 1516 1517 err_mhi_unregister: 1518 ath11k_mhi_unregister(ab_pci); 1519 1520 err_pci_disable_msi: 1521 ath11k_pci_free_msi(ab_pci); 1522 1523 err_pci_free_region: 1524 ath11k_pci_free_region(ab_pci); 1525 1526 err_free_core: 1527 ath11k_core_free(ab); 1528 1529 return ret; 1530 } 1531 1532 static void ath11k_pci_remove(struct pci_dev *pdev) 1533 { 1534 struct ath11k_base *ab = pci_get_drvdata(pdev); 1535 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1536 1537 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 1538 1539 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1540 ath11k_pci_power_down(ab); 1541 ath11k_debugfs_soc_destroy(ab); 1542 ath11k_qmi_deinit_service(ab); 1543 goto qmi_fail; 1544 } 1545 1546 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags); 1547 1548 ath11k_core_deinit(ab); 1549 1550 qmi_fail: 1551 ath11k_mhi_unregister(ab_pci); 1552 1553 ath11k_pci_free_irq(ab); 1554 ath11k_pci_free_msi(ab_pci); 1555 ath11k_pci_free_region(ab_pci); 1556 1557 ath11k_hal_srng_deinit(ab); 1558 ath11k_ce_free_pipes(ab); 1559 ath11k_core_free(ab); 1560 } 1561 1562 static void ath11k_pci_shutdown(struct pci_dev *pdev) 1563 { 1564 struct ath11k_base *ab = pci_get_drvdata(pdev); 1565 1566 ath11k_pci_power_down(ab); 1567 } 1568 1569 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev) 1570 { 1571 struct ath11k_base *ab = dev_get_drvdata(dev); 1572 int ret; 1573 1574 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1575 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci suspend as qmi is not initialised\n"); 1576 return 0; 1577 } 1578 1579 ret = ath11k_core_suspend(ab); 1580 if (ret) 1581 ath11k_warn(ab, "failed to suspend core: %d\n", ret); 1582 1583 return ret; 1584 } 1585 1586 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev) 1587 { 1588 struct ath11k_base *ab = dev_get_drvdata(dev); 1589 int ret; 1590 1591 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1592 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci resume as qmi is not initialised\n"); 1593 return 0; 1594 } 1595 1596 ret = ath11k_core_resume(ab); 1597 if (ret) 1598 ath11k_warn(ab, "failed to resume core: %d\n", ret); 1599 1600 return ret; 1601 } 1602 1603 static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops, 1604 ath11k_pci_pm_suspend, 1605 ath11k_pci_pm_resume); 1606 1607 static struct pci_driver ath11k_pci_driver = { 1608 .name = "ath11k_pci", 1609 .id_table = ath11k_pci_id_table, 1610 .probe = ath11k_pci_probe, 1611 .remove = ath11k_pci_remove, 1612 .shutdown = ath11k_pci_shutdown, 1613 #ifdef CONFIG_PM 1614 .driver.pm = &ath11k_pci_pm_ops, 1615 #endif 1616 }; 1617 1618 static int ath11k_pci_init(void) 1619 { 1620 int ret; 1621 1622 ret = pci_register_driver(&ath11k_pci_driver); 1623 if (ret) 1624 pr_err("failed to register ath11k pci driver: %d\n", 1625 ret); 1626 1627 return ret; 1628 } 1629 module_init(ath11k_pci_init); 1630 1631 static void ath11k_pci_exit(void) 1632 { 1633 pci_unregister_driver(&ath11k_pci_driver); 1634 } 1635 1636 module_exit(ath11k_pci_exit); 1637 1638 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices"); 1639 MODULE_LICENSE("Dual BSD/GPL"); 1640 1641 /* QCA639x 2.0 firmware files */ 1642 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_BOARD_API2_FILE); 1643 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_AMSS_FILE); 1644 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_M3_FILE); 1645