1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 */ 18 19 /*************************************\ 20 * DMA and interrupt masking functions * 21 \*************************************/ 22 23 /* 24 * dma.c - DMA and interrupt masking functions 25 * 26 * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and 27 * handle queue setup for 5210 chipset (rest are handled on qcu.c). 28 * Also we setup interrupt mask register (IMR) and read the various interrupt 29 * status registers (ISR). 30 * 31 * TODO: Handle SISR on 5211+ and introduce a function to return the queue 32 * number that resulted the interrupt. 33 */ 34 35 #include "ath5k.h" 36 #include "reg.h" 37 #include "debug.h" 38 #include "base.h" 39 40 41 /*********\ 42 * Receive * 43 \*********/ 44 45 /** 46 * ath5k_hw_start_rx_dma - Start DMA receive 47 * 48 * @ah: The &struct ath5k_hw 49 */ 50 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah) 51 { 52 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR); 53 ath5k_hw_reg_read(ah, AR5K_CR); 54 } 55 56 /** 57 * ath5k_hw_stop_rx_dma - Stop DMA receive 58 * 59 * @ah: The &struct ath5k_hw 60 */ 61 static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah) 62 { 63 unsigned int i; 64 65 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR); 66 67 /* 68 * It may take some time to disable the DMA receive unit 69 */ 70 for (i = 1000; i > 0 && 71 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0; 72 i--) 73 udelay(100); 74 75 if (!i) 76 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, 77 "failed to stop RX DMA !\n"); 78 79 return i ? 0 : -EBUSY; 80 } 81 82 /** 83 * ath5k_hw_get_rxdp - Get RX Descriptor's address 84 * 85 * @ah: The &struct ath5k_hw 86 */ 87 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah) 88 { 89 return ath5k_hw_reg_read(ah, AR5K_RXDP); 90 } 91 92 /** 93 * ath5k_hw_set_rxdp - Set RX Descriptor's address 94 * 95 * @ah: The &struct ath5k_hw 96 * @phys_addr: RX descriptor address 97 * 98 * Returns -EIO if rx is active 99 */ 100 int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr) 101 { 102 if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) { 103 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, 104 "tried to set RXDP while rx was active !\n"); 105 return -EIO; 106 } 107 108 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP); 109 return 0; 110 } 111 112 113 /**********\ 114 * Transmit * 115 \**********/ 116 117 /** 118 * ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue 119 * 120 * @ah: The &struct ath5k_hw 121 * @queue: The hw queue number 122 * 123 * Start DMA transmit for a specific queue and since 5210 doesn't have 124 * QCU/DCU, set up queue parameters for 5210 here based on queue type (one 125 * queue for normal data and one queue for beacons). For queue setup 126 * on newer chips check out qcu.c. Returns -EINVAL if queue number is out 127 * of range or if queue is already disabled. 128 * 129 * NOTE: Must be called after setting up tx control descriptor for that 130 * queue (see below). 131 */ 132 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue) 133 { 134 u32 tx_queue; 135 136 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); 137 138 /* Return if queue is declared inactive */ 139 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) 140 return -EINVAL; 141 142 if (ah->ah_version == AR5K_AR5210) { 143 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); 144 145 /* 146 * Set the queue by type on 5210 147 */ 148 switch (ah->ah_txq[queue].tqi_type) { 149 case AR5K_TX_QUEUE_DATA: 150 tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0; 151 break; 152 case AR5K_TX_QUEUE_BEACON: 153 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; 154 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, 155 AR5K_BSR); 156 break; 157 case AR5K_TX_QUEUE_CAB: 158 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; 159 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V | 160 AR5K_BCR_BDMAE, AR5K_BSR); 161 break; 162 default: 163 return -EINVAL; 164 } 165 /* Start queue */ 166 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); 167 ath5k_hw_reg_read(ah, AR5K_CR); 168 } else { 169 /* Return if queue is disabled */ 170 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue)) 171 return -EIO; 172 173 /* Start queue */ 174 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue); 175 } 176 177 return 0; 178 } 179 180 /** 181 * ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue 182 * 183 * @ah: The &struct ath5k_hw 184 * @queue: The hw queue number 185 * 186 * Stop DMA transmit on a specific hw queue and drain queue so we don't 187 * have any pending frames. Returns -EBUSY if we still have pending frames, 188 * -EINVAL if queue number is out of range or inactive. 189 * 190 */ 191 static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue) 192 { 193 unsigned int i = 40; 194 u32 tx_queue, pending; 195 196 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); 197 198 /* Return if queue is declared inactive */ 199 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) 200 return -EINVAL; 201 202 if (ah->ah_version == AR5K_AR5210) { 203 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); 204 205 /* 206 * Set by queue type 207 */ 208 switch (ah->ah_txq[queue].tqi_type) { 209 case AR5K_TX_QUEUE_DATA: 210 tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0; 211 break; 212 case AR5K_TX_QUEUE_BEACON: 213 case AR5K_TX_QUEUE_CAB: 214 /* XXX Fix me... */ 215 tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1; 216 ath5k_hw_reg_write(ah, 0, AR5K_BSR); 217 break; 218 default: 219 return -EINVAL; 220 } 221 222 /* Stop queue */ 223 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); 224 ath5k_hw_reg_read(ah, AR5K_CR); 225 } else { 226 227 /* 228 * Enable DCU early termination to quickly 229 * flush any pending frames from QCU 230 */ 231 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), 232 AR5K_QCU_MISC_DCU_EARLY); 233 234 /* 235 * Schedule TX disable and wait until queue is empty 236 */ 237 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue); 238 239 /* Wait for queue to stop */ 240 for (i = 1000; i > 0 && 241 (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue) != 0); 242 i--) 243 udelay(100); 244 245 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) 246 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, 247 "queue %i didn't stop !\n", queue); 248 249 /* Check for pending frames */ 250 i = 1000; 251 do { 252 pending = ath5k_hw_reg_read(ah, 253 AR5K_QUEUE_STATUS(queue)) & 254 AR5K_QCU_STS_FRMPENDCNT; 255 udelay(100); 256 } while (--i && pending); 257 258 /* For 2413+ order PCU to drop packets using 259 * QUIET mechanism */ 260 if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) && 261 pending) { 262 /* Set periodicity and duration */ 263 ath5k_hw_reg_write(ah, 264 AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)| 265 AR5K_REG_SM(10, AR5K_QUIET_CTL2_QT_DUR), 266 AR5K_QUIET_CTL2); 267 268 /* Enable quiet period for current TSF */ 269 ath5k_hw_reg_write(ah, 270 AR5K_QUIET_CTL1_QT_EN | 271 AR5K_REG_SM(ath5k_hw_reg_read(ah, 272 AR5K_TSF_L32_5211) >> 10, 273 AR5K_QUIET_CTL1_NEXT_QT_TSF), 274 AR5K_QUIET_CTL1); 275 276 /* Force channel idle high */ 277 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, 278 AR5K_DIAG_SW_CHANNEL_IDLE_HIGH); 279 280 /* Wait a while and disable mechanism */ 281 udelay(400); 282 AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1, 283 AR5K_QUIET_CTL1_QT_EN); 284 285 /* Re-check for pending frames */ 286 i = 100; 287 do { 288 pending = ath5k_hw_reg_read(ah, 289 AR5K_QUEUE_STATUS(queue)) & 290 AR5K_QCU_STS_FRMPENDCNT; 291 udelay(100); 292 } while (--i && pending); 293 294 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211, 295 AR5K_DIAG_SW_CHANNEL_IDLE_HIGH); 296 297 if (pending) 298 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, 299 "quiet mechanism didn't work q:%i !\n", 300 queue); 301 } 302 303 /* 304 * Disable DCU early termination 305 */ 306 AR5K_REG_DISABLE_BITS(ah, AR5K_QUEUE_MISC(queue), 307 AR5K_QCU_MISC_DCU_EARLY); 308 309 /* Clear register */ 310 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD); 311 if (pending) { 312 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, 313 "tx dma didn't stop (q:%i, frm:%i) !\n", 314 queue, pending); 315 return -EBUSY; 316 } 317 } 318 319 /* TODO: Check for success on 5210 else return error */ 320 return 0; 321 } 322 323 /** 324 * ath5k_hw_stop_beacon_queue - Stop beacon queue 325 * 326 * @ah The &struct ath5k_hw 327 * @queue The queue number 328 * 329 * Returns -EIO if queue didn't stop 330 */ 331 int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue) 332 { 333 int ret; 334 ret = ath5k_hw_stop_tx_dma(ah, queue); 335 if (ret) { 336 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, 337 "beacon queue didn't stop !\n"); 338 return -EIO; 339 } 340 return 0; 341 } 342 343 /** 344 * ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue 345 * 346 * @ah: The &struct ath5k_hw 347 * @queue: The hw queue number 348 * 349 * Get TX descriptor's address for a specific queue. For 5210 we ignore 350 * the queue number and use tx queue type since we only have 2 queues. 351 * We use TXDP0 for normal data queue and TXDP1 for beacon queue. 352 * For newer chips with QCU/DCU we just read the corresponding TXDP register. 353 * 354 * XXX: Is TXDP read and clear ? 355 */ 356 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue) 357 { 358 u16 tx_reg; 359 360 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); 361 362 /* 363 * Get the transmit queue descriptor pointer from the selected queue 364 */ 365 /*5210 doesn't have QCU*/ 366 if (ah->ah_version == AR5K_AR5210) { 367 switch (ah->ah_txq[queue].tqi_type) { 368 case AR5K_TX_QUEUE_DATA: 369 tx_reg = AR5K_NOQCU_TXDP0; 370 break; 371 case AR5K_TX_QUEUE_BEACON: 372 case AR5K_TX_QUEUE_CAB: 373 tx_reg = AR5K_NOQCU_TXDP1; 374 break; 375 default: 376 return 0xffffffff; 377 } 378 } else { 379 tx_reg = AR5K_QUEUE_TXDP(queue); 380 } 381 382 return ath5k_hw_reg_read(ah, tx_reg); 383 } 384 385 /** 386 * ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue 387 * 388 * @ah: The &struct ath5k_hw 389 * @queue: The hw queue number 390 * 391 * Set TX descriptor's address for a specific queue. For 5210 we ignore 392 * the queue number and we use tx queue type since we only have 2 queues 393 * so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue. 394 * For newer chips with QCU/DCU we just set the corresponding TXDP register. 395 * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still 396 * active. 397 */ 398 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr) 399 { 400 u16 tx_reg; 401 402 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); 403 404 /* 405 * Set the transmit queue descriptor pointer register by type 406 * on 5210 407 */ 408 if (ah->ah_version == AR5K_AR5210) { 409 switch (ah->ah_txq[queue].tqi_type) { 410 case AR5K_TX_QUEUE_DATA: 411 tx_reg = AR5K_NOQCU_TXDP0; 412 break; 413 case AR5K_TX_QUEUE_BEACON: 414 case AR5K_TX_QUEUE_CAB: 415 tx_reg = AR5K_NOQCU_TXDP1; 416 break; 417 default: 418 return -EINVAL; 419 } 420 } else { 421 /* 422 * Set the transmit queue descriptor pointer for 423 * the selected queue on QCU for 5211+ 424 * (this won't work if the queue is still active) 425 */ 426 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) 427 return -EIO; 428 429 tx_reg = AR5K_QUEUE_TXDP(queue); 430 } 431 432 /* Set descriptor pointer */ 433 ath5k_hw_reg_write(ah, phys_addr, tx_reg); 434 435 return 0; 436 } 437 438 /** 439 * ath5k_hw_update_tx_triglevel - Update tx trigger level 440 * 441 * @ah: The &struct ath5k_hw 442 * @increase: Flag to force increase of trigger level 443 * 444 * This function increases/decreases the tx trigger level for the tx fifo 445 * buffer (aka FIFO threshold) that is used to indicate when PCU flushes 446 * the buffer and transmits its data. Lowering this results sending small 447 * frames more quickly but can lead to tx underruns, raising it a lot can 448 * result other problems (i think bmiss is related). Right now we start with 449 * the lowest possible (64Bytes) and if we get tx underrun we increase it using 450 * the increase flag. Returns -EIO if we have reached maximum/minimum. 451 * 452 * XXX: Link this with tx DMA size ? 453 * XXX: Use it to save interrupts ? 454 * TODO: Needs testing, i think it's related to bmiss... 455 */ 456 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase) 457 { 458 u32 trigger_level, imr; 459 int ret = -EIO; 460 461 /* 462 * Disable interrupts by setting the mask 463 */ 464 imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL); 465 466 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG), 467 AR5K_TXCFG_TXFULL); 468 469 if (!increase) { 470 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) 471 goto done; 472 } else 473 trigger_level += 474 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); 475 476 /* 477 * Update trigger level on success 478 */ 479 if (ah->ah_version == AR5K_AR5210) 480 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL); 481 else 482 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, 483 AR5K_TXCFG_TXFULL, trigger_level); 484 485 ret = 0; 486 487 done: 488 /* 489 * Restore interrupt mask 490 */ 491 ath5k_hw_set_imr(ah, imr); 492 493 return ret; 494 } 495 496 497 /*******************\ 498 * Interrupt masking * 499 \*******************/ 500 501 /** 502 * ath5k_hw_is_intr_pending - Check if we have pending interrupts 503 * 504 * @ah: The &struct ath5k_hw 505 * 506 * Check if we have pending interrupts to process. Returns 1 if we 507 * have pending interrupts and 0 if we haven't. 508 */ 509 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah) 510 { 511 return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0; 512 } 513 514 /** 515 * ath5k_hw_get_isr - Get interrupt status 516 * 517 * @ah: The @struct ath5k_hw 518 * @interrupt_mask: Driver's interrupt mask used to filter out 519 * interrupts in sw. 520 * 521 * This function is used inside our interrupt handler to determine the reason 522 * for the interrupt by reading Primary Interrupt Status Register. Returns an 523 * abstract interrupt status mask which is mostly ISR with some uncommon bits 524 * being mapped on some standard non hw-specific positions 525 * (check out &ath5k_int). 526 * 527 * NOTE: We use read-and-clear register, so after this function is called ISR 528 * is zeroed. 529 */ 530 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask) 531 { 532 u32 data; 533 534 /* 535 * Read interrupt status from the Interrupt Status register 536 * on 5210 537 */ 538 if (ah->ah_version == AR5K_AR5210) { 539 data = ath5k_hw_reg_read(ah, AR5K_ISR); 540 if (unlikely(data == AR5K_INT_NOCARD)) { 541 *interrupt_mask = data; 542 return -ENODEV; 543 } 544 } else { 545 /* 546 * Read interrupt status from Interrupt 547 * Status Register shadow copy (Read And Clear) 548 * 549 * Note: PISR/SISR Not available on 5210 550 */ 551 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR); 552 if (unlikely(data == AR5K_INT_NOCARD)) { 553 *interrupt_mask = data; 554 return -ENODEV; 555 } 556 } 557 558 /* 559 * Get abstract interrupt mask (driver-compatible) 560 */ 561 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr; 562 563 if (ah->ah_version != AR5K_AR5210) { 564 u32 sisr2 = ath5k_hw_reg_read(ah, AR5K_RAC_SISR2); 565 566 /*HIU = Host Interface Unit (PCI etc)*/ 567 if (unlikely(data & (AR5K_ISR_HIUERR))) 568 *interrupt_mask |= AR5K_INT_FATAL; 569 570 /*Beacon Not Ready*/ 571 if (unlikely(data & (AR5K_ISR_BNR))) 572 *interrupt_mask |= AR5K_INT_BNR; 573 574 if (unlikely(sisr2 & (AR5K_SISR2_SSERR | 575 AR5K_SISR2_DPERR | 576 AR5K_SISR2_MCABT))) 577 *interrupt_mask |= AR5K_INT_FATAL; 578 579 if (data & AR5K_ISR_TIM) 580 *interrupt_mask |= AR5K_INT_TIM; 581 582 if (data & AR5K_ISR_BCNMISC) { 583 if (sisr2 & AR5K_SISR2_TIM) 584 *interrupt_mask |= AR5K_INT_TIM; 585 if (sisr2 & AR5K_SISR2_DTIM) 586 *interrupt_mask |= AR5K_INT_DTIM; 587 if (sisr2 & AR5K_SISR2_DTIM_SYNC) 588 *interrupt_mask |= AR5K_INT_DTIM_SYNC; 589 if (sisr2 & AR5K_SISR2_BCN_TIMEOUT) 590 *interrupt_mask |= AR5K_INT_BCN_TIMEOUT; 591 if (sisr2 & AR5K_SISR2_CAB_TIMEOUT) 592 *interrupt_mask |= AR5K_INT_CAB_TIMEOUT; 593 } 594 595 if (data & AR5K_ISR_RXDOPPLER) 596 *interrupt_mask |= AR5K_INT_RX_DOPPLER; 597 if (data & AR5K_ISR_QCBRORN) { 598 *interrupt_mask |= AR5K_INT_QCBRORN; 599 ah->ah_txq_isr |= AR5K_REG_MS( 600 ath5k_hw_reg_read(ah, AR5K_RAC_SISR3), 601 AR5K_SISR3_QCBRORN); 602 } 603 if (data & AR5K_ISR_QCBRURN) { 604 *interrupt_mask |= AR5K_INT_QCBRURN; 605 ah->ah_txq_isr |= AR5K_REG_MS( 606 ath5k_hw_reg_read(ah, AR5K_RAC_SISR3), 607 AR5K_SISR3_QCBRURN); 608 } 609 if (data & AR5K_ISR_QTRIG) { 610 *interrupt_mask |= AR5K_INT_QTRIG; 611 ah->ah_txq_isr |= AR5K_REG_MS( 612 ath5k_hw_reg_read(ah, AR5K_RAC_SISR4), 613 AR5K_SISR4_QTRIG); 614 } 615 616 if (data & AR5K_ISR_TXOK) 617 ah->ah_txq_isr |= AR5K_REG_MS( 618 ath5k_hw_reg_read(ah, AR5K_RAC_SISR0), 619 AR5K_SISR0_QCU_TXOK); 620 621 if (data & AR5K_ISR_TXDESC) 622 ah->ah_txq_isr |= AR5K_REG_MS( 623 ath5k_hw_reg_read(ah, AR5K_RAC_SISR0), 624 AR5K_SISR0_QCU_TXDESC); 625 626 if (data & AR5K_ISR_TXERR) 627 ah->ah_txq_isr |= AR5K_REG_MS( 628 ath5k_hw_reg_read(ah, AR5K_RAC_SISR1), 629 AR5K_SISR1_QCU_TXERR); 630 631 if (data & AR5K_ISR_TXEOL) 632 ah->ah_txq_isr |= AR5K_REG_MS( 633 ath5k_hw_reg_read(ah, AR5K_RAC_SISR1), 634 AR5K_SISR1_QCU_TXEOL); 635 636 if (data & AR5K_ISR_TXURN) 637 ah->ah_txq_isr |= AR5K_REG_MS( 638 ath5k_hw_reg_read(ah, AR5K_RAC_SISR2), 639 AR5K_SISR2_QCU_TXURN); 640 } else { 641 if (unlikely(data & (AR5K_ISR_SSERR | AR5K_ISR_MCABT 642 | AR5K_ISR_HIUERR | AR5K_ISR_DPERR))) 643 *interrupt_mask |= AR5K_INT_FATAL; 644 645 /* 646 * XXX: BMISS interrupts may occur after association. 647 * I found this on 5210 code but it needs testing. If this is 648 * true we should disable them before assoc and re-enable them 649 * after a successful assoc + some jiffies. 650 interrupt_mask &= ~AR5K_INT_BMISS; 651 */ 652 } 653 654 /* 655 * In case we didn't handle anything, 656 * print the register value. 657 */ 658 if (unlikely(*interrupt_mask == 0 && net_ratelimit())) 659 ATH5K_PRINTF("ISR: 0x%08x IMR: 0x%08x\n", data, ah->ah_imr); 660 661 return 0; 662 } 663 664 /** 665 * ath5k_hw_set_imr - Set interrupt mask 666 * 667 * @ah: The &struct ath5k_hw 668 * @new_mask: The new interrupt mask to be set 669 * 670 * Set the interrupt mask in hw to save interrupts. We do that by mapping 671 * ath5k_int bits to hw-specific bits to remove abstraction and writing 672 * Interrupt Mask Register. 673 */ 674 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask) 675 { 676 enum ath5k_int old_mask, int_mask; 677 678 old_mask = ah->ah_imr; 679 680 /* 681 * Disable card interrupts to prevent any race conditions 682 * (they will be re-enabled afterwards if AR5K_INT GLOBAL 683 * is set again on the new mask). 684 */ 685 if (old_mask & AR5K_INT_GLOBAL) { 686 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER); 687 ath5k_hw_reg_read(ah, AR5K_IER); 688 } 689 690 /* 691 * Add additional, chipset-dependent interrupt mask flags 692 * and write them to the IMR (interrupt mask register). 693 */ 694 int_mask = new_mask & AR5K_INT_COMMON; 695 696 if (ah->ah_version != AR5K_AR5210) { 697 /* Preserve per queue TXURN interrupt mask */ 698 u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2) 699 & AR5K_SIMR2_QCU_TXURN; 700 701 if (new_mask & AR5K_INT_FATAL) { 702 int_mask |= AR5K_IMR_HIUERR; 703 simr2 |= (AR5K_SIMR2_MCABT | AR5K_SIMR2_SSERR 704 | AR5K_SIMR2_DPERR); 705 } 706 707 /*Beacon Not Ready*/ 708 if (new_mask & AR5K_INT_BNR) 709 int_mask |= AR5K_INT_BNR; 710 711 if (new_mask & AR5K_INT_TIM) 712 int_mask |= AR5K_IMR_TIM; 713 714 if (new_mask & AR5K_INT_TIM) 715 simr2 |= AR5K_SISR2_TIM; 716 if (new_mask & AR5K_INT_DTIM) 717 simr2 |= AR5K_SISR2_DTIM; 718 if (new_mask & AR5K_INT_DTIM_SYNC) 719 simr2 |= AR5K_SISR2_DTIM_SYNC; 720 if (new_mask & AR5K_INT_BCN_TIMEOUT) 721 simr2 |= AR5K_SISR2_BCN_TIMEOUT; 722 if (new_mask & AR5K_INT_CAB_TIMEOUT) 723 simr2 |= AR5K_SISR2_CAB_TIMEOUT; 724 725 if (new_mask & AR5K_INT_RX_DOPPLER) 726 int_mask |= AR5K_IMR_RXDOPPLER; 727 728 /* Note: Per queue interrupt masks 729 * are set via ath5k_hw_reset_tx_queue() (qcu.c) */ 730 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR); 731 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2); 732 733 } else { 734 if (new_mask & AR5K_INT_FATAL) 735 int_mask |= (AR5K_IMR_SSERR | AR5K_IMR_MCABT 736 | AR5K_IMR_HIUERR | AR5K_IMR_DPERR); 737 738 ath5k_hw_reg_write(ah, int_mask, AR5K_IMR); 739 } 740 741 /* If RXNOFRM interrupt is masked disable it 742 * by setting AR5K_RXNOFRM to zero */ 743 if (!(new_mask & AR5K_INT_RXNOFRM)) 744 ath5k_hw_reg_write(ah, 0, AR5K_RXNOFRM); 745 746 /* Store new interrupt mask */ 747 ah->ah_imr = new_mask; 748 749 /* ..re-enable interrupts if AR5K_INT_GLOBAL is set */ 750 if (new_mask & AR5K_INT_GLOBAL) { 751 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER); 752 ath5k_hw_reg_read(ah, AR5K_IER); 753 } 754 755 return old_mask; 756 } 757 758 759 /********************\ 760 Init/Stop functions 761 \********************/ 762 763 /** 764 * ath5k_hw_dma_init - Initialize DMA unit 765 * 766 * @ah: The &struct ath5k_hw 767 * 768 * Set DMA size and pre-enable interrupts 769 * (driver handles tx/rx buffer setup and 770 * dma start/stop) 771 * 772 * XXX: Save/restore RXDP/TXDP registers ? 773 */ 774 void ath5k_hw_dma_init(struct ath5k_hw *ah) 775 { 776 /* 777 * Set Rx/Tx DMA Configuration 778 * 779 * Set standard DMA size (128). Note that 780 * a DMA size of 512 causes rx overruns and tx errors 781 * on pci-e cards (tested on 5424 but since rx overruns 782 * also occur on 5416/5418 with madwifi we set 128 783 * for all PCI-E cards to be safe). 784 * 785 * XXX: need to check 5210 for this 786 * TODO: Check out tx trigger level, it's always 64 on dumps but I 787 * guess we can tweak it and see how it goes ;-) 788 */ 789 if (ah->ah_version != AR5K_AR5210) { 790 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, 791 AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B); 792 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, 793 AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B); 794 } 795 796 /* Pre-enable interrupts on 5211/5212*/ 797 if (ah->ah_version != AR5K_AR5210) 798 ath5k_hw_set_imr(ah, ah->ah_imr); 799 800 } 801 802 /** 803 * ath5k_hw_dma_stop - stop DMA unit 804 * 805 * @ah: The &struct ath5k_hw 806 * 807 * Stop tx/rx DMA and interrupts. Returns 808 * -EBUSY if tx or rx dma failed to stop. 809 * 810 * XXX: Sometimes DMA unit hangs and we have 811 * stuck frames on tx queues, only a reset 812 * can fix that. 813 */ 814 int ath5k_hw_dma_stop(struct ath5k_hw *ah) 815 { 816 int i, qmax, err; 817 err = 0; 818 819 /* Disable interrupts */ 820 ath5k_hw_set_imr(ah, 0); 821 822 /* Stop rx dma */ 823 err = ath5k_hw_stop_rx_dma(ah); 824 if (err) 825 return err; 826 827 /* Clear any pending interrupts 828 * and disable tx dma */ 829 if (ah->ah_version != AR5K_AR5210) { 830 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR); 831 qmax = AR5K_NUM_TX_QUEUES; 832 } else { 833 /* PISR/SISR Not available on 5210 */ 834 ath5k_hw_reg_read(ah, AR5K_ISR); 835 qmax = AR5K_NUM_TX_QUEUES_NOQCU; 836 } 837 838 for (i = 0; i < qmax; i++) { 839 err = ath5k_hw_stop_tx_dma(ah, i); 840 /* -EINVAL -> queue inactive */ 841 if (err && err != -EINVAL) 842 return err; 843 } 844 845 return 0; 846 } 847