1 /*
2  * Copyright (c) 2010-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include <linux/export.h>
18 #include "hw.h"
19 #include "ar9003_phy.h"
20 #include "ar9003_eeprom.h"
21 
22 #define AR9300_OFDM_RATES	8
23 #define AR9300_HT_SS_RATES	8
24 #define AR9300_HT_DS_RATES	8
25 #define AR9300_HT_TS_RATES	8
26 
27 #define AR9300_11NA_OFDM_SHIFT		0
28 #define AR9300_11NA_HT_SS_SHIFT		8
29 #define AR9300_11NA_HT_DS_SHIFT		16
30 #define AR9300_11NA_HT_TS_SHIFT		24
31 
32 #define AR9300_11NG_OFDM_SHIFT		4
33 #define AR9300_11NG_HT_SS_SHIFT		12
34 #define AR9300_11NG_HT_DS_SHIFT		20
35 #define AR9300_11NG_HT_TS_SHIFT		28
36 
37 static const int firstep_table[] =
38 /* level:  0   1   2   3   4   5   6   7   8  */
39 	{ -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
40 
41 static const int cycpwrThr1_table[] =
42 /* level:  0   1   2   3   4   5   6   7   8  */
43 	{ -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
44 
45 /*
46  * register values to turn OFDM weak signal detection OFF
47  */
48 static const int m1ThreshLow_off = 127;
49 static const int m2ThreshLow_off = 127;
50 static const int m1Thresh_off = 127;
51 static const int m2Thresh_off = 127;
52 static const int m2CountThr_off =  31;
53 static const int m2CountThrLow_off =  63;
54 static const int m1ThreshLowExt_off = 127;
55 static const int m2ThreshLowExt_off = 127;
56 static const int m1ThreshExt_off = 127;
57 static const int m2ThreshExt_off = 127;
58 
59 static const u8 ofdm2pwr[] = {
60 	ALL_TARGET_LEGACY_6_24,
61 	ALL_TARGET_LEGACY_6_24,
62 	ALL_TARGET_LEGACY_6_24,
63 	ALL_TARGET_LEGACY_6_24,
64 	ALL_TARGET_LEGACY_6_24,
65 	ALL_TARGET_LEGACY_36,
66 	ALL_TARGET_LEGACY_48,
67 	ALL_TARGET_LEGACY_54
68 };
69 
70 static const u8 mcs2pwr_ht20[] = {
71 	ALL_TARGET_HT20_0_8_16,
72 	ALL_TARGET_HT20_1_3_9_11_17_19,
73 	ALL_TARGET_HT20_1_3_9_11_17_19,
74 	ALL_TARGET_HT20_1_3_9_11_17_19,
75 	ALL_TARGET_HT20_4,
76 	ALL_TARGET_HT20_5,
77 	ALL_TARGET_HT20_6,
78 	ALL_TARGET_HT20_7,
79 	ALL_TARGET_HT20_0_8_16,
80 	ALL_TARGET_HT20_1_3_9_11_17_19,
81 	ALL_TARGET_HT20_1_3_9_11_17_19,
82 	ALL_TARGET_HT20_1_3_9_11_17_19,
83 	ALL_TARGET_HT20_12,
84 	ALL_TARGET_HT20_13,
85 	ALL_TARGET_HT20_14,
86 	ALL_TARGET_HT20_15,
87 	ALL_TARGET_HT20_0_8_16,
88 	ALL_TARGET_HT20_1_3_9_11_17_19,
89 	ALL_TARGET_HT20_1_3_9_11_17_19,
90 	ALL_TARGET_HT20_1_3_9_11_17_19,
91 	ALL_TARGET_HT20_20,
92 	ALL_TARGET_HT20_21,
93 	ALL_TARGET_HT20_22,
94 	ALL_TARGET_HT20_23
95 };
96 
97 static const u8 mcs2pwr_ht40[] = {
98 	ALL_TARGET_HT40_0_8_16,
99 	ALL_TARGET_HT40_1_3_9_11_17_19,
100 	ALL_TARGET_HT40_1_3_9_11_17_19,
101 	ALL_TARGET_HT40_1_3_9_11_17_19,
102 	ALL_TARGET_HT40_4,
103 	ALL_TARGET_HT40_5,
104 	ALL_TARGET_HT40_6,
105 	ALL_TARGET_HT40_7,
106 	ALL_TARGET_HT40_0_8_16,
107 	ALL_TARGET_HT40_1_3_9_11_17_19,
108 	ALL_TARGET_HT40_1_3_9_11_17_19,
109 	ALL_TARGET_HT40_1_3_9_11_17_19,
110 	ALL_TARGET_HT40_12,
111 	ALL_TARGET_HT40_13,
112 	ALL_TARGET_HT40_14,
113 	ALL_TARGET_HT40_15,
114 	ALL_TARGET_HT40_0_8_16,
115 	ALL_TARGET_HT40_1_3_9_11_17_19,
116 	ALL_TARGET_HT40_1_3_9_11_17_19,
117 	ALL_TARGET_HT40_1_3_9_11_17_19,
118 	ALL_TARGET_HT40_20,
119 	ALL_TARGET_HT40_21,
120 	ALL_TARGET_HT40_22,
121 	ALL_TARGET_HT40_23,
122 };
123 
124 /**
125  * ar9003_hw_set_channel - set channel on single-chip device
126  * @ah: atheros hardware structure
127  * @chan:
128  *
129  * This is the function to change channel on single-chip devices, that is
130  * for AR9300 family of chipsets.
131  *
132  * This function takes the channel value in MHz and sets
133  * hardware channel value. Assumes writes have been enabled to analog bus.
134  *
135  * Actual Expression,
136  *
137  * For 2GHz channel,
138  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
139  * (freq_ref = 40MHz)
140  *
141  * For 5GHz channel,
142  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
143  * (freq_ref = 40MHz/(24>>amodeRefSel))
144  *
145  * For 5GHz channels which are 5MHz spaced,
146  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
147  * (freq_ref = 40MHz)
148  */
149 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
150 {
151 	u16 bMode, fracMode = 0, aModeRefSel = 0;
152 	u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
153 	struct chan_centers centers;
154 	int loadSynthChannel;
155 
156 	ath9k_hw_get_channel_centers(ah, chan, &centers);
157 	freq = centers.synth_center;
158 
159 	if (freq < 4800) {     /* 2 GHz, fractional mode */
160 		if (AR_SREV_9330(ah) || AR_SREV_9485(ah) ||
161 		    AR_SREV_9531(ah) || AR_SREV_9550(ah) ||
162 		    AR_SREV_9561(ah) || AR_SREV_9565(ah)) {
163 			if (ah->is_clk_25mhz)
164 				div = 75;
165 			else
166 				div = 120;
167 
168 			channelSel = (freq * 4) / div;
169 			chan_frac = (((freq * 4) % div) * 0x20000) / div;
170 			channelSel = (channelSel << 17) | chan_frac;
171 		} else if (AR_SREV_9340(ah)) {
172 			if (ah->is_clk_25mhz) {
173 				channelSel = (freq * 2) / 75;
174 				chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
175 				channelSel = (channelSel << 17) | chan_frac;
176 			} else {
177 				channelSel = CHANSEL_2G(freq) >> 1;
178 			}
179 		} else {
180 			channelSel = CHANSEL_2G(freq);
181 		}
182 		/* Set to 2G mode */
183 		bMode = 1;
184 	} else {
185 		if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) ||
186 		     AR_SREV_9531(ah) || AR_SREV_9561(ah)) &&
187 		    ah->is_clk_25mhz) {
188 			channelSel = freq / 75;
189 			chan_frac = ((freq % 75) * 0x20000) / 75;
190 			channelSel = (channelSel << 17) | chan_frac;
191 		} else {
192 			channelSel = CHANSEL_5G(freq);
193 			/* Doubler is ON, so, divide channelSel by 2. */
194 			channelSel >>= 1;
195 		}
196 		/* Set to 5G mode */
197 		bMode = 0;
198 	}
199 
200 	/* Enable fractional mode for all channels */
201 	fracMode = 1;
202 	aModeRefSel = 0;
203 	loadSynthChannel = 0;
204 
205 	reg32 = (bMode << 29);
206 	REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
207 
208 	/* Enable Long shift Select for Synthesizer */
209 	REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
210 		      AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
211 
212 	/* Program Synth. setting */
213 	reg32 = (channelSel << 2) | (fracMode << 30) |
214 		(aModeRefSel << 28) | (loadSynthChannel << 31);
215 	REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
216 
217 	/* Toggle Load Synth channel bit */
218 	loadSynthChannel = 1;
219 	reg32 = (channelSel << 2) | (fracMode << 30) |
220 		(aModeRefSel << 28) | (loadSynthChannel << 31);
221 	REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
222 
223 	ah->curchan = chan;
224 
225 	return 0;
226 }
227 
228 /**
229  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
230  * @ah: atheros hardware structure
231  * @chan:
232  *
233  * For single-chip solutions. Converts to baseband spur frequency given the
234  * input channel frequency and compute register settings below.
235  *
236  * Spur mitigation for MRC CCK
237  */
238 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
239 					    struct ath9k_channel *chan)
240 {
241 	static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
242 	int cur_bb_spur, negative = 0, cck_spur_freq;
243 	int i;
244 	int range, max_spur_cnts, synth_freq;
245 	u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
246 
247 	/*
248 	 * Need to verify range +/- 10 MHz in control channel, otherwise spur
249 	 * is out-of-band and can be ignored.
250 	 */
251 
252 	if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
253 	    AR_SREV_9550(ah) || AR_SREV_9561(ah)) {
254 		if (spur_fbin_ptr[0] == 0) /* No spur */
255 			return;
256 		max_spur_cnts = 5;
257 		if (IS_CHAN_HT40(chan)) {
258 			range = 19;
259 			if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
260 					   AR_PHY_GC_DYN2040_PRI_CH) == 0)
261 				synth_freq = chan->channel + 10;
262 			else
263 				synth_freq = chan->channel - 10;
264 		} else {
265 			range = 10;
266 			synth_freq = chan->channel;
267 		}
268 	} else {
269 		range = AR_SREV_9462(ah) ? 5 : 10;
270 		max_spur_cnts = 4;
271 		synth_freq = chan->channel;
272 	}
273 
274 	for (i = 0; i < max_spur_cnts; i++) {
275 		if (AR_SREV_9462(ah) && (i == 0 || i == 3))
276 			continue;
277 
278 		negative = 0;
279 		if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
280 		    AR_SREV_9550(ah) || AR_SREV_9561(ah))
281 			cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
282 							 IS_CHAN_2GHZ(chan));
283 		else
284 			cur_bb_spur = spur_freq[i];
285 
286 		cur_bb_spur -= synth_freq;
287 		if (cur_bb_spur < 0) {
288 			negative = 1;
289 			cur_bb_spur = -cur_bb_spur;
290 		}
291 		if (cur_bb_spur < range) {
292 			cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
293 
294 			if (negative == 1)
295 				cck_spur_freq = -cck_spur_freq;
296 
297 			cck_spur_freq = cck_spur_freq & 0xfffff;
298 
299 			REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL(ah),
300 				      AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
301 			REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
302 				      AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
303 			REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
304 				      AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
305 				      0x2);
306 			REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
307 				      AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
308 				      0x1);
309 			REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
310 				      AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
311 				      cck_spur_freq);
312 
313 			return;
314 		}
315 	}
316 
317 	REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL(ah),
318 		      AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
319 	REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
320 		      AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
321 	REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
322 		      AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
323 }
324 
325 /* Clean all spur register fields */
326 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
327 {
328 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
329 		      AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
330 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
331 		      AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
332 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
333 		      AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
334 	REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
335 		      AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
336 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
337 		      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
338 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
339 		      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
340 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
341 		      AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
342 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
343 		      AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
344 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
345 		      AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
346 
347 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
348 		      AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
349 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
350 		      AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
351 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
352 		      AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
353 	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
354 		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
355 	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah),
356 		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
357 	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
358 		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
359 	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
360 		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
361 	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
362 		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
363 	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah),
364 		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
365 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
366 		      AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
367 }
368 
369 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
370 				int freq_offset,
371 				int spur_freq_sd,
372 				int spur_delta_phase,
373 				int spur_subchannel_sd,
374 				int range,
375 				int synth_freq)
376 {
377 	int mask_index = 0;
378 
379 	/* OFDM Spur mitigation */
380 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
381 		 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
382 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
383 		      AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
384 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
385 		      AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
386 	REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
387 		      AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
388 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
389 		      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
390 
391 	if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
392 		REG_RMW_FIELD(ah, AR_PHY_TIMING11,
393 			      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
394 
395 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
396 		      AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
397 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
398 		      AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
399 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
400 		      AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
401 
402 	if (!AR_SREV_9340(ah) &&
403 	    REG_READ_FIELD(ah, AR_PHY_MODE,
404 			   AR_PHY_MODE_DYNAMIC) == 0x1)
405 		REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
406 			      AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
407 
408 	mask_index = (freq_offset << 4) / 5;
409 	if (mask_index < 0)
410 		mask_index = mask_index - 1;
411 
412 	mask_index = mask_index & 0x7f;
413 
414 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
415 		      AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
416 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
417 		      AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
418 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
419 		      AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
420 	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
421 		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
422 	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah),
423 		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
424 	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
425 		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
426 	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
427 		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
428 	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
429 		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
430 	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah),
431 		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
432 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
433 		      AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
434 }
435 
436 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
437 				     int freq_offset)
438 {
439 	int mask_index = 0;
440 
441 	mask_index = (freq_offset << 4) / 5;
442 	if (mask_index < 0)
443 		mask_index = mask_index - 1;
444 
445 	mask_index = mask_index & 0x7f;
446 
447 	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
448 		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
449 		      mask_index);
450 
451 	/* A == B */
452 	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B(ah),
453 		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
454 		      mask_index);
455 
456 	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
457 		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
458 		      mask_index);
459 	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
460 		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
461 	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
462 		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
463 
464 	/* A == B */
465 	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B(ah),
466 		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
467 }
468 
469 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
470 				     struct ath9k_channel *chan,
471 				     int freq_offset,
472 				     int range,
473 				     int synth_freq)
474 {
475 	int spur_freq_sd = 0;
476 	int spur_subchannel_sd = 0;
477 	int spur_delta_phase = 0;
478 
479 	if (IS_CHAN_HT40(chan)) {
480 		if (freq_offset < 0) {
481 			if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
482 					   AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
483 				spur_subchannel_sd = 1;
484 			else
485 				spur_subchannel_sd = 0;
486 
487 			spur_freq_sd = ((freq_offset + 10) << 9) / 11;
488 
489 		} else {
490 			if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
491 			    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
492 				spur_subchannel_sd = 0;
493 			else
494 				spur_subchannel_sd = 1;
495 
496 			spur_freq_sd = ((freq_offset - 10) << 9) / 11;
497 
498 		}
499 
500 		spur_delta_phase = (freq_offset << 17) / 5;
501 
502 	} else {
503 		spur_subchannel_sd = 0;
504 		spur_freq_sd = (freq_offset << 9) /11;
505 		spur_delta_phase = (freq_offset << 18) / 5;
506 	}
507 
508 	spur_freq_sd = spur_freq_sd & 0x3ff;
509 	spur_delta_phase = spur_delta_phase & 0xfffff;
510 
511 	ar9003_hw_spur_ofdm(ah,
512 			    freq_offset,
513 			    spur_freq_sd,
514 			    spur_delta_phase,
515 			    spur_subchannel_sd,
516 			    range, synth_freq);
517 }
518 
519 /* Spur mitigation for OFDM */
520 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
521 					 struct ath9k_channel *chan)
522 {
523 	int synth_freq;
524 	int range = 10;
525 	int freq_offset = 0;
526 	u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
527 	unsigned int i;
528 
529 	if (spur_fbin_ptr[0] == 0)
530 		return; /* No spur in the mode */
531 
532 	if (IS_CHAN_HT40(chan)) {
533 		range = 19;
534 		if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
535 				   AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
536 			synth_freq = chan->channel - 10;
537 		else
538 			synth_freq = chan->channel + 10;
539 	} else {
540 		range = 10;
541 		synth_freq = chan->channel;
542 	}
543 
544 	ar9003_hw_spur_ofdm_clear(ah);
545 
546 	for (i = 0; i < AR_EEPROM_MODAL_SPURS && spur_fbin_ptr[i]; i++) {
547 		freq_offset = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
548 						 IS_CHAN_2GHZ(chan));
549 		freq_offset -= synth_freq;
550 		if (abs(freq_offset) < range) {
551 			ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
552 						 range, synth_freq);
553 
554 			if (AR_SREV_9565(ah) && (i < 4)) {
555 				freq_offset =
556 					ath9k_hw_fbin2freq(spur_fbin_ptr[i + 1],
557 							   IS_CHAN_2GHZ(chan));
558 				freq_offset -= synth_freq;
559 				if (abs(freq_offset) < range)
560 					ar9003_hw_spur_ofdm_9565(ah, freq_offset);
561 			}
562 
563 			break;
564 		}
565 	}
566 }
567 
568 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
569 				    struct ath9k_channel *chan)
570 {
571 	if (!AR_SREV_9565(ah))
572 		ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
573 	ar9003_hw_spur_mitigate_ofdm(ah, chan);
574 }
575 
576 static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah,
577 					     struct ath9k_channel *chan)
578 {
579 	u32 pll;
580 
581 	pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
582 
583 	if (chan && IS_CHAN_HALF_RATE(chan))
584 		pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
585 	else if (chan && IS_CHAN_QUARTER_RATE(chan))
586 		pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
587 
588 	pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
589 
590 	return pll;
591 }
592 
593 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
594 					 struct ath9k_channel *chan)
595 {
596 	u32 pll;
597 
598 	pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
599 
600 	if (chan && IS_CHAN_HALF_RATE(chan))
601 		pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
602 	else if (chan && IS_CHAN_QUARTER_RATE(chan))
603 		pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
604 
605 	pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
606 
607 	return pll;
608 }
609 
610 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
611 				       struct ath9k_channel *chan)
612 {
613 	u32 phymode;
614 	u32 enableDacFifo = 0;
615 
616 	enableDacFifo =
617 		(REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
618 
619 	/* Enable 11n HT, 20 MHz */
620 	phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
621 
622 	if (!AR_SREV_9561(ah))
623 		phymode |= AR_PHY_GC_SINGLE_HT_LTF1;
624 
625 	/* Configure baseband for dynamic 20/40 operation */
626 	if (IS_CHAN_HT40(chan)) {
627 		phymode |= AR_PHY_GC_DYN2040_EN;
628 		/* Configure control (primary) channel at +-10MHz */
629 		if (IS_CHAN_HT40PLUS(chan))
630 			phymode |= AR_PHY_GC_DYN2040_PRI_CH;
631 
632 	}
633 
634 	/* make sure we preserve INI settings */
635 	phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
636 	/* turn off Green Field detection for STA for now */
637 	phymode &= ~AR_PHY_GC_GF_DETECT_EN;
638 
639 	REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
640 
641 	/* Configure MAC for 20/40 operation */
642 	ath9k_hw_set11nmac2040(ah, chan);
643 
644 	/* global transmit timeout (25 TUs default)*/
645 	REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
646 	/* carrier sense timeout */
647 	REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
648 }
649 
650 static void ar9003_hw_init_bb(struct ath_hw *ah,
651 			      struct ath9k_channel *chan)
652 {
653 	u32 synthDelay;
654 
655 	/*
656 	 * Wait for the frequency synth to settle (synth goes on
657 	 * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
658 	 * Value is in 100ns increments.
659 	 */
660 	synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
661 
662 	/* Activate the PHY (includes baseband activate + synthesizer on) */
663 	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
664 	ath9k_hw_synth_delay(ah, chan, synthDelay);
665 }
666 
667 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
668 {
669 	if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
670 		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
671 			    AR_PHY_SWAP_ALT_CHAIN);
672 
673 	REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
674 	REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
675 
676 	if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
677 		tx = 3;
678 
679 	REG_WRITE(ah, AR_SELFGEN_MASK, tx);
680 }
681 
682 /*
683  * Override INI values with chip specific configuration.
684  */
685 static void ar9003_hw_override_ini(struct ath_hw *ah)
686 {
687 	u32 val;
688 
689 	/*
690 	 * Set the RX_ABORT and RX_DIS and clear it only after
691 	 * RXE is set for MAC. This prevents frames with
692 	 * corrupted descriptor status.
693 	 */
694 	REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
695 
696 	/*
697 	 * For AR9280 and above, there is a new feature that allows
698 	 * Multicast search based on both MAC Address and Key ID. By default,
699 	 * this feature is enabled. But since the driver is not using this
700 	 * feature, we switch it off; otherwise multicast search based on
701 	 * MAC addr only will fail.
702 	 */
703 	val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
704 	val |= AR_AGG_WEP_ENABLE_FIX |
705 	       AR_AGG_WEP_ENABLE |
706 	       AR_PCU_MISC_MODE2_CFP_IGNORE;
707 	REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
708 
709 	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
710 		REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
711 			  AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
712 
713 		if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah),
714 				   AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
715 			ah->enabled_cals |= TX_IQ_CAL;
716 		else
717 			ah->enabled_cals &= ~TX_IQ_CAL;
718 
719 	}
720 
721 	if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
722 		ah->enabled_cals |= TX_CL_CAL;
723 	else
724 		ah->enabled_cals &= ~TX_CL_CAL;
725 
726 	if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) ||
727 	    AR_SREV_9561(ah)) {
728 		if (ah->is_clk_25mhz) {
729 			REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x17c << 1);
730 			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
731 			REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
732 		} else {
733 			REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x261 << 1);
734 			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
735 			REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
736 		}
737 		udelay(100);
738 	}
739 }
740 
741 static void ar9003_hw_prog_ini(struct ath_hw *ah,
742 			       struct ar5416IniArray *iniArr,
743 			       int column)
744 {
745 	unsigned int i, regWrites = 0;
746 
747 	/* New INI format: Array may be undefined (pre, core, post arrays) */
748 	if (!iniArr->ia_array)
749 		return;
750 
751 	/*
752 	 * New INI format: Pre, core, and post arrays for a given subsystem
753 	 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
754 	 * the array is non-modal and force the column to 1.
755 	 */
756 	if (column >= iniArr->ia_columns)
757 		column = 1;
758 
759 	for (i = 0; i < iniArr->ia_rows; i++) {
760 		u32 reg = INI_RA(iniArr, i, 0);
761 		u32 val = INI_RA(iniArr, i, column);
762 
763 		REG_WRITE(ah, reg, val);
764 
765 		DO_DELAY(regWrites);
766 	}
767 }
768 
769 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
770 					    struct ath9k_channel *chan)
771 {
772 	int ret;
773 
774 	if (IS_CHAN_2GHZ(chan)) {
775 		if (IS_CHAN_HT40(chan))
776 			return 7;
777 		else
778 			return 8;
779 	}
780 
781 	if (chan->channel <= 5350)
782 		ret = 1;
783 	else if ((chan->channel > 5350) && (chan->channel <= 5600))
784 		ret = 3;
785 	else
786 		ret = 5;
787 
788 	if (IS_CHAN_HT40(chan))
789 		ret++;
790 
791 	return ret;
792 }
793 
794 static int ar9561_hw_get_modes_txgain_index(struct ath_hw *ah,
795 					    struct ath9k_channel *chan)
796 {
797 	if (IS_CHAN_2GHZ(chan)) {
798 		if (IS_CHAN_HT40(chan))
799 			return 1;
800 		else
801 			return 2;
802 	}
803 
804 	return 0;
805 }
806 
807 static void ar9003_doubler_fix(struct ath_hw *ah)
808 {
809 	if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
810 		REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
811 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
812 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
813 		REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
814 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
815 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
816 		REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
817 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
818 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
819 
820 		udelay(200);
821 
822 		REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
823 			    AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
824 		REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
825 			    AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
826 		REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
827 			    AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
828 
829 		udelay(1);
830 
831 		REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
832 			      AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
833 		REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
834 			      AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
835 		REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
836 			      AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
837 
838 		udelay(200);
839 
840 		REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
841 			      AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
842 
843 		REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
844 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
845 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
846 		REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
847 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
848 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
849 		REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
850 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
851 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
852 	}
853 }
854 
855 static int ar9003_hw_process_ini(struct ath_hw *ah,
856 				 struct ath9k_channel *chan)
857 {
858 	unsigned int regWrites = 0, i;
859 	u32 modesIndex;
860 
861 	if (IS_CHAN_5GHZ(chan))
862 		modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
863 	else
864 		modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
865 
866 	/*
867 	 * SOC, MAC, BB, RADIO initvals.
868 	 */
869 	for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
870 		ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
871 		ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
872 		ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
873 		ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
874 		if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
875 			ar9003_hw_prog_ini(ah,
876 					   &ah->ini_radio_post_sys2ant,
877 					   modesIndex);
878 	}
879 
880 	ar9003_doubler_fix(ah);
881 
882 	/*
883 	 * RXGAIN initvals.
884 	 */
885 	REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
886 
887 	if (AR_SREV_9462_20_OR_LATER(ah)) {
888 		/*
889 		 * CUS217 mix LNA mode.
890 		 */
891 		if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
892 			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
893 					1, regWrites);
894 			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
895 					modesIndex, regWrites);
896 		}
897 
898 		/*
899 		 * 5G-XLNA
900 		 */
901 		if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
902 		    (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
903 			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
904 					modesIndex, regWrites);
905 		}
906 	}
907 
908 	if (AR_SREV_9550(ah) || AR_SREV_9561(ah))
909 		REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
910 				regWrites);
911 
912 	if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0))
913 		REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
914 				modesIndex, regWrites);
915 	/*
916 	 * TXGAIN initvals.
917 	 */
918 	if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
919 		int modes_txgain_index = 1;
920 
921 		if (AR_SREV_9550(ah))
922 			modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
923 
924 		if (AR_SREV_9561(ah))
925 			modes_txgain_index =
926 				ar9561_hw_get_modes_txgain_index(ah, chan);
927 
928 		if (modes_txgain_index < 0)
929 			return -EINVAL;
930 
931 		REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
932 				regWrites);
933 	} else {
934 		REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
935 	}
936 
937 	/*
938 	 * For 5GHz channels requiring Fast Clock, apply
939 	 * different modal values.
940 	 */
941 	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
942 		REG_WRITE_ARRAY(&ah->iniModesFastClock,
943 				modesIndex, regWrites);
944 
945 	/*
946 	 * Clock frequency initvals.
947 	 */
948 	REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
949 
950 	/*
951 	 * JAPAN regulatory.
952 	 */
953 	if (chan->channel == 2484) {
954 		ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
955 
956 		if (AR_SREV_9531(ah))
957 			REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0,
958 				      AR_PHY_FLC_PWR_THRESH, 0);
959 	}
960 
961 	ah->modes_index = modesIndex;
962 	ar9003_hw_override_ini(ah);
963 	ar9003_hw_set_channel_regs(ah, chan);
964 	ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
965 	ath9k_hw_apply_txpower(ah, chan, false);
966 
967 	return 0;
968 }
969 
970 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
971 				 struct ath9k_channel *chan)
972 {
973 	u32 rfMode = 0;
974 
975 	if (chan == NULL)
976 		return;
977 
978 	if (IS_CHAN_2GHZ(chan))
979 		rfMode |= AR_PHY_MODE_DYNAMIC;
980 	else
981 		rfMode |= AR_PHY_MODE_OFDM;
982 
983 	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
984 		rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
985 
986 	if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
987 		REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
988 			      AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
989 
990 	REG_WRITE(ah, AR_PHY_MODE, rfMode);
991 }
992 
993 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
994 {
995 	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
996 }
997 
998 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
999 				      struct ath9k_channel *chan)
1000 {
1001 	u32 coef_scaled, ds_coef_exp, ds_coef_man;
1002 	u32 clockMhzScaled = 0x64000000;
1003 	struct chan_centers centers;
1004 
1005 	/*
1006 	 * half and quarter rate can divide the scaled clock by 2 or 4
1007 	 * scale for selected channel bandwidth
1008 	 */
1009 	if (IS_CHAN_HALF_RATE(chan))
1010 		clockMhzScaled = clockMhzScaled >> 1;
1011 	else if (IS_CHAN_QUARTER_RATE(chan))
1012 		clockMhzScaled = clockMhzScaled >> 2;
1013 
1014 	/*
1015 	 * ALGO -> coef = 1e8/fcarrier*fclock/40;
1016 	 * scaled coef to provide precision for this floating calculation
1017 	 */
1018 	ath9k_hw_get_channel_centers(ah, chan, &centers);
1019 	coef_scaled = clockMhzScaled / centers.synth_center;
1020 
1021 	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1022 				      &ds_coef_exp);
1023 
1024 	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1025 		      AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1026 	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1027 		      AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1028 
1029 	/*
1030 	 * For Short GI,
1031 	 * scaled coeff is 9/10 that of normal coeff
1032 	 */
1033 	coef_scaled = (9 * coef_scaled) / 10;
1034 
1035 	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1036 				      &ds_coef_exp);
1037 
1038 	/* for short gi */
1039 	REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1040 		      AR_PHY_SGI_DSC_MAN, ds_coef_man);
1041 	REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1042 		      AR_PHY_SGI_DSC_EXP, ds_coef_exp);
1043 }
1044 
1045 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
1046 {
1047 	REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1048 	return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1049 			     AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
1050 }
1051 
1052 /*
1053  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
1054  * Read the phy active delay register. Value is in 100ns increments.
1055  */
1056 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
1057 {
1058 	u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1059 
1060 	ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
1061 
1062 	REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1063 }
1064 
1065 static bool ar9003_hw_ani_control(struct ath_hw *ah,
1066 				  enum ath9k_ani_cmd cmd, int param)
1067 {
1068 	struct ath_common *common = ath9k_hw_common(ah);
1069 	struct ath9k_channel *chan = ah->curchan;
1070 	struct ar5416AniState *aniState = &ah->ani;
1071 	int m1ThreshLow, m2ThreshLow;
1072 	int m1Thresh, m2Thresh;
1073 	int m2CountThr, m2CountThrLow;
1074 	int m1ThreshLowExt, m2ThreshLowExt;
1075 	int m1ThreshExt, m2ThreshExt;
1076 	s32 value, value2;
1077 
1078 	switch (cmd & ah->ani_function) {
1079 	case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1080 		/*
1081 		 * on == 1 means ofdm weak signal detection is ON
1082 		 * on == 1 is the default, for less noise immunity
1083 		 *
1084 		 * on == 0 means ofdm weak signal detection is OFF
1085 		 * on == 0 means more noise imm
1086 		 */
1087 		u32 on = param ? 1 : 0;
1088 
1089 		if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
1090 			goto skip_ws_det;
1091 
1092 		m1ThreshLow = on ?
1093 			aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1094 		m2ThreshLow = on ?
1095 			aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1096 		m1Thresh = on ?
1097 			aniState->iniDef.m1Thresh : m1Thresh_off;
1098 		m2Thresh = on ?
1099 			aniState->iniDef.m2Thresh : m2Thresh_off;
1100 		m2CountThr = on ?
1101 			aniState->iniDef.m2CountThr : m2CountThr_off;
1102 		m2CountThrLow = on ?
1103 			aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1104 		m1ThreshLowExt = on ?
1105 			aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1106 		m2ThreshLowExt = on ?
1107 			aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1108 		m1ThreshExt = on ?
1109 			aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1110 		m2ThreshExt = on ?
1111 			aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1112 
1113 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1114 			      AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1115 			      m1ThreshLow);
1116 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1117 			      AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1118 			      m2ThreshLow);
1119 		REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1120 			      AR_PHY_SFCORR_M1_THRESH,
1121 			      m1Thresh);
1122 		REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1123 			      AR_PHY_SFCORR_M2_THRESH,
1124 			      m2Thresh);
1125 		REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1126 			      AR_PHY_SFCORR_M2COUNT_THR,
1127 			      m2CountThr);
1128 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1129 			      AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1130 			      m2CountThrLow);
1131 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1132 			      AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1133 			      m1ThreshLowExt);
1134 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1135 			      AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1136 			      m2ThreshLowExt);
1137 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1138 			      AR_PHY_SFCORR_EXT_M1_THRESH,
1139 			      m1ThreshExt);
1140 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1141 			      AR_PHY_SFCORR_EXT_M2_THRESH,
1142 			      m2ThreshExt);
1143 skip_ws_det:
1144 		if (on)
1145 			REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1146 				    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1147 		else
1148 			REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1149 				    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1150 
1151 		if (on != aniState->ofdmWeakSigDetect) {
1152 			ath_dbg(common, ANI,
1153 				"** ch %d: ofdm weak signal: %s=>%s\n",
1154 				chan->channel,
1155 				aniState->ofdmWeakSigDetect ?
1156 				"on" : "off",
1157 				on ? "on" : "off");
1158 			if (on)
1159 				ah->stats.ast_ani_ofdmon++;
1160 			else
1161 				ah->stats.ast_ani_ofdmoff++;
1162 			aniState->ofdmWeakSigDetect = on;
1163 		}
1164 		break;
1165 	}
1166 	case ATH9K_ANI_FIRSTEP_LEVEL:{
1167 		u32 level = param;
1168 
1169 		if (level >= ARRAY_SIZE(firstep_table)) {
1170 			ath_dbg(common, ANI,
1171 				"ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1172 				level, ARRAY_SIZE(firstep_table));
1173 			return false;
1174 		}
1175 
1176 		/*
1177 		 * make register setting relative to default
1178 		 * from INI file & cap value
1179 		 */
1180 		value = firstep_table[level] -
1181 			firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1182 			aniState->iniDef.firstep;
1183 		if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1184 			value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1185 		if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1186 			value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1187 		REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1188 			      AR_PHY_FIND_SIG_FIRSTEP,
1189 			      value);
1190 		/*
1191 		 * we need to set first step low register too
1192 		 * make register setting relative to default
1193 		 * from INI file & cap value
1194 		 */
1195 		value2 = firstep_table[level] -
1196 			 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1197 			 aniState->iniDef.firstepLow;
1198 		if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1199 			value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1200 		if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1201 			value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1202 
1203 		REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1204 			      AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1205 
1206 		if (level != aniState->firstepLevel) {
1207 			ath_dbg(common, ANI,
1208 				"** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1209 				chan->channel,
1210 				aniState->firstepLevel,
1211 				level,
1212 				ATH9K_ANI_FIRSTEP_LVL,
1213 				value,
1214 				aniState->iniDef.firstep);
1215 			ath_dbg(common, ANI,
1216 				"** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1217 				chan->channel,
1218 				aniState->firstepLevel,
1219 				level,
1220 				ATH9K_ANI_FIRSTEP_LVL,
1221 				value2,
1222 				aniState->iniDef.firstepLow);
1223 			if (level > aniState->firstepLevel)
1224 				ah->stats.ast_ani_stepup++;
1225 			else if (level < aniState->firstepLevel)
1226 				ah->stats.ast_ani_stepdown++;
1227 			aniState->firstepLevel = level;
1228 		}
1229 		break;
1230 	}
1231 	case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1232 		u32 level = param;
1233 
1234 		if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1235 			ath_dbg(common, ANI,
1236 				"ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1237 				level, ARRAY_SIZE(cycpwrThr1_table));
1238 			return false;
1239 		}
1240 		/*
1241 		 * make register setting relative to default
1242 		 * from INI file & cap value
1243 		 */
1244 		value = cycpwrThr1_table[level] -
1245 			cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1246 			aniState->iniDef.cycpwrThr1;
1247 		if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1248 			value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1249 		if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1250 			value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1251 		REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1252 			      AR_PHY_TIMING5_CYCPWR_THR1,
1253 			      value);
1254 
1255 		/*
1256 		 * set AR_PHY_EXT_CCA for extension channel
1257 		 * make register setting relative to default
1258 		 * from INI file & cap value
1259 		 */
1260 		value2 = cycpwrThr1_table[level] -
1261 			 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1262 			 aniState->iniDef.cycpwrThr1Ext;
1263 		if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1264 			value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1265 		if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1266 			value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1267 		REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1268 			      AR_PHY_EXT_CYCPWR_THR1, value2);
1269 
1270 		if (level != aniState->spurImmunityLevel) {
1271 			ath_dbg(common, ANI,
1272 				"** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1273 				chan->channel,
1274 				aniState->spurImmunityLevel,
1275 				level,
1276 				ATH9K_ANI_SPUR_IMMUNE_LVL,
1277 				value,
1278 				aniState->iniDef.cycpwrThr1);
1279 			ath_dbg(common, ANI,
1280 				"** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1281 				chan->channel,
1282 				aniState->spurImmunityLevel,
1283 				level,
1284 				ATH9K_ANI_SPUR_IMMUNE_LVL,
1285 				value2,
1286 				aniState->iniDef.cycpwrThr1Ext);
1287 			if (level > aniState->spurImmunityLevel)
1288 				ah->stats.ast_ani_spurup++;
1289 			else if (level < aniState->spurImmunityLevel)
1290 				ah->stats.ast_ani_spurdown++;
1291 			aniState->spurImmunityLevel = level;
1292 		}
1293 		break;
1294 	}
1295 	case ATH9K_ANI_MRC_CCK:{
1296 		/*
1297 		 * is_on == 1 means MRC CCK ON (default, less noise imm)
1298 		 * is_on == 0 means MRC CCK is OFF (more noise imm)
1299 		 */
1300 		bool is_on = param ? 1 : 0;
1301 
1302 		if (ah->caps.rx_chainmask == 1)
1303 			break;
1304 
1305 		REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1306 			      AR_PHY_MRC_CCK_ENABLE, is_on);
1307 		REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1308 			      AR_PHY_MRC_CCK_MUX_REG, is_on);
1309 		if (is_on != aniState->mrcCCK) {
1310 			ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1311 				chan->channel,
1312 				aniState->mrcCCK ? "on" : "off",
1313 				is_on ? "on" : "off");
1314 			if (is_on)
1315 				ah->stats.ast_ani_ccklow++;
1316 			else
1317 				ah->stats.ast_ani_cckhigh++;
1318 			aniState->mrcCCK = is_on;
1319 		}
1320 	break;
1321 	}
1322 	default:
1323 		ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1324 		return false;
1325 	}
1326 
1327 	ath_dbg(common, ANI,
1328 		"ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1329 		aniState->spurImmunityLevel,
1330 		aniState->ofdmWeakSigDetect ? "on" : "off",
1331 		aniState->firstepLevel,
1332 		aniState->mrcCCK ? "on" : "off",
1333 		aniState->listenTime,
1334 		aniState->ofdmPhyErrCount,
1335 		aniState->cckPhyErrCount);
1336 	return true;
1337 }
1338 
1339 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1340 			      int16_t nfarray[NUM_NF_READINGS])
1341 {
1342 #define AR_PHY_CH_MINCCA_PWR	0x1FF00000
1343 #define AR_PHY_CH_MINCCA_PWR_S	20
1344 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1345 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1346 
1347 	int16_t nf;
1348 	int i;
1349 
1350 	for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1351 		if (ah->rxchainmask & BIT(i)) {
1352 			nf = MS(REG_READ(ah, ah->nf_regs[i]),
1353 					 AR_PHY_CH_MINCCA_PWR);
1354 			nfarray[i] = sign_extend32(nf, 8);
1355 
1356 			if (IS_CHAN_HT40(ah->curchan)) {
1357 				u8 ext_idx = AR9300_MAX_CHAINS + i;
1358 
1359 				nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1360 						 AR_PHY_CH_EXT_MINCCA_PWR);
1361 				nfarray[ext_idx] = sign_extend32(nf, 8);
1362 			}
1363 		}
1364 	}
1365 }
1366 
1367 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1368 {
1369 	ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1370 	ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1371 	ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1372 	ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1373 	ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1374 	ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1375 
1376 	if (AR_SREV_9330(ah))
1377 		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1378 
1379 	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1380 		ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1381 		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1382 		ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1383 		ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1384 	}
1385 }
1386 
1387 /*
1388  * Initialize the ANI register values with default (ini) values.
1389  * This routine is called during a (full) hardware reset after
1390  * all the registers are initialised from the INI.
1391  */
1392 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1393 {
1394 	struct ar5416AniState *aniState;
1395 	struct ath_common *common = ath9k_hw_common(ah);
1396 	struct ath9k_channel *chan = ah->curchan;
1397 	struct ath9k_ani_default *iniDef;
1398 	u32 val;
1399 
1400 	aniState = &ah->ani;
1401 	iniDef = &aniState->iniDef;
1402 
1403 	ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
1404 		ah->hw_version.macVersion,
1405 		ah->hw_version.macRev,
1406 		ah->opmode,
1407 		chan->channel);
1408 
1409 	val = REG_READ(ah, AR_PHY_SFCORR);
1410 	iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1411 	iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1412 	iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1413 
1414 	val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1415 	iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1416 	iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1417 	iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1418 
1419 	val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1420 	iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1421 	iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1422 	iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1423 	iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1424 	iniDef->firstep = REG_READ_FIELD(ah,
1425 					 AR_PHY_FIND_SIG,
1426 					 AR_PHY_FIND_SIG_FIRSTEP);
1427 	iniDef->firstepLow = REG_READ_FIELD(ah,
1428 					    AR_PHY_FIND_SIG_LOW,
1429 					    AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1430 	iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1431 					    AR_PHY_TIMING5,
1432 					    AR_PHY_TIMING5_CYCPWR_THR1);
1433 	iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1434 					       AR_PHY_EXT_CCA,
1435 					       AR_PHY_EXT_CYCPWR_THR1);
1436 
1437 	/* these levels just got reset to defaults by the INI */
1438 	aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1439 	aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1440 	aniState->ofdmWeakSigDetect = true;
1441 	aniState->mrcCCK = true;
1442 }
1443 
1444 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1445 				       struct ath_hw_radar_conf *conf)
1446 {
1447 	unsigned int regWrites = 0;
1448 	u32 radar_0 = 0, radar_1;
1449 
1450 	if (!conf) {
1451 		REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1452 		return;
1453 	}
1454 
1455 	radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1456 	radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1457 	radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1458 	radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1459 	radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1460 	radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1461 
1462 	radar_1 = REG_READ(ah, AR_PHY_RADAR_1);
1463 	radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH |
1464 		     AR_PHY_RADAR_1_RELPWR_THRESH);
1465 	radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1466 	radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1467 	radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1468 	radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1469 	radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1470 
1471 	REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1472 	REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1473 	if (conf->ext_channel)
1474 		REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1475 	else
1476 		REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1477 
1478 	if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
1479 		REG_WRITE_ARRAY(&ah->ini_dfs,
1480 				IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
1481 	}
1482 }
1483 
1484 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1485 {
1486 	struct ath_hw_radar_conf *conf = &ah->radar_conf;
1487 
1488 	conf->fir_power = -28;
1489 	conf->radar_rssi = 0;
1490 	conf->pulse_height = 10;
1491 	conf->pulse_rssi = 15;
1492 	conf->pulse_inband = 8;
1493 	conf->pulse_maxlen = 255;
1494 	conf->pulse_inband_step = 12;
1495 	conf->radar_inband = 8;
1496 }
1497 
1498 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1499 					   struct ath_hw_antcomb_conf *antconf)
1500 {
1501 	u32 regval;
1502 
1503 	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1504 	antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1505 				  AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1506 	antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1507 				 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1508 	antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1509 				  AR_PHY_ANT_FAST_DIV_BIAS_S;
1510 
1511 	if (AR_SREV_9330_11(ah)) {
1512 		antconf->lna1_lna2_switch_delta = -1;
1513 		antconf->lna1_lna2_delta = -9;
1514 		antconf->div_group = 1;
1515 	} else if (AR_SREV_9485(ah)) {
1516 		antconf->lna1_lna2_switch_delta = -1;
1517 		antconf->lna1_lna2_delta = -9;
1518 		antconf->div_group = 2;
1519 	} else if (AR_SREV_9565(ah)) {
1520 		antconf->lna1_lna2_switch_delta = 3;
1521 		antconf->lna1_lna2_delta = -9;
1522 		antconf->div_group = 3;
1523 	} else {
1524 		antconf->lna1_lna2_switch_delta = -1;
1525 		antconf->lna1_lna2_delta = -3;
1526 		antconf->div_group = 0;
1527 	}
1528 }
1529 
1530 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1531 				   struct ath_hw_antcomb_conf *antconf)
1532 {
1533 	u32 regval;
1534 
1535 	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1536 	regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1537 		    AR_PHY_ANT_DIV_ALT_LNACONF |
1538 		    AR_PHY_ANT_FAST_DIV_BIAS |
1539 		    AR_PHY_ANT_DIV_MAIN_GAINTB |
1540 		    AR_PHY_ANT_DIV_ALT_GAINTB);
1541 	regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1542 		   & AR_PHY_ANT_DIV_MAIN_LNACONF);
1543 	regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1544 		   & AR_PHY_ANT_DIV_ALT_LNACONF);
1545 	regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1546 		   & AR_PHY_ANT_FAST_DIV_BIAS);
1547 	regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1548 		   & AR_PHY_ANT_DIV_MAIN_GAINTB);
1549 	regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1550 		   & AR_PHY_ANT_DIV_ALT_GAINTB);
1551 
1552 	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1553 }
1554 
1555 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1556 
1557 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
1558 {
1559 	struct ath9k_hw_capabilities *pCap = &ah->caps;
1560 	u8 ant_div_ctl1;
1561 	u32 regval;
1562 
1563 	if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
1564 		return;
1565 
1566 	if (AR_SREV_9485(ah)) {
1567 		regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1568 						 IS_CHAN_2GHZ(ah->curchan));
1569 		if (enable) {
1570 			regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1571 			regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1572 		}
1573 		REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1574 			      AR_SWITCH_TABLE_COM2_ALL, regval);
1575 	}
1576 
1577 	ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1578 
1579 	/*
1580 	 * Set MAIN/ALT LNA conf.
1581 	 * Set MAIN/ALT gain_tb.
1582 	 */
1583 	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1584 	regval &= (~AR_ANT_DIV_CTRL_ALL);
1585 	regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1586 	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1587 
1588 	if (AR_SREV_9485_11_OR_LATER(ah)) {
1589 		/*
1590 		 * Enable LNA diversity.
1591 		 */
1592 		regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1593 		regval &= ~AR_PHY_ANT_DIV_LNADIV;
1594 		regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1595 		if (enable)
1596 			regval |= AR_ANT_DIV_ENABLE;
1597 
1598 		REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1599 
1600 		/*
1601 		 * Enable fast antenna diversity.
1602 		 */
1603 		regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1604 		regval &= ~AR_FAST_DIV_ENABLE;
1605 		regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1606 		if (enable)
1607 			regval |= AR_FAST_DIV_ENABLE;
1608 
1609 		REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1610 
1611 		if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1612 			regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1613 			regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1614 				     AR_PHY_ANT_DIV_ALT_LNACONF |
1615 				     AR_PHY_ANT_DIV_ALT_GAINTB |
1616 				     AR_PHY_ANT_DIV_MAIN_GAINTB));
1617 			/*
1618 			 * Set MAIN to LNA1 and ALT to LNA2 at the
1619 			 * beginning.
1620 			 */
1621 			regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1622 				   AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1623 			regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1624 				   AR_PHY_ANT_DIV_ALT_LNACONF_S);
1625 			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1626 		}
1627 	} else if (AR_SREV_9565(ah)) {
1628 		if (enable) {
1629 			REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1630 				    AR_ANT_DIV_ENABLE);
1631 			REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1632 				    (1 << AR_PHY_ANT_SW_RX_PROT_S));
1633 			REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1634 				    AR_FAST_DIV_ENABLE);
1635 			REG_SET_BIT(ah, AR_PHY_RESTART,
1636 				    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1637 			REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1638 				    AR_BTCOEX_WL_LNADIV_FORCE_ON);
1639 		} else {
1640 			REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1641 				    AR_ANT_DIV_ENABLE);
1642 			REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1643 				    (1 << AR_PHY_ANT_SW_RX_PROT_S));
1644 			REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1645 				    AR_FAST_DIV_ENABLE);
1646 			REG_CLR_BIT(ah, AR_PHY_RESTART,
1647 				    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1648 			REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1649 				    AR_BTCOEX_WL_LNADIV_FORCE_ON);
1650 
1651 			regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1652 			regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1653 				    AR_PHY_ANT_DIV_ALT_LNACONF |
1654 				    AR_PHY_ANT_DIV_MAIN_GAINTB |
1655 				    AR_PHY_ANT_DIV_ALT_GAINTB);
1656 			regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1657 				   AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1658 			regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1659 				   AR_PHY_ANT_DIV_ALT_LNACONF_S);
1660 			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1661 		}
1662 	}
1663 }
1664 
1665 #endif
1666 
1667 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1668 				      struct ath9k_channel *chan,
1669 				      u8 *ini_reloaded)
1670 {
1671 	unsigned int regWrites = 0;
1672 	u32 modesIndex, txgain_index;
1673 
1674 	if (IS_CHAN_5GHZ(chan))
1675 		modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
1676 	else
1677 		modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
1678 
1679 	txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex;
1680 
1681 	if (modesIndex == ah->modes_index) {
1682 		*ini_reloaded = false;
1683 		goto set_rfmode;
1684 	}
1685 
1686 	ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1687 	ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1688 	ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1689 	ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1690 
1691 	if (AR_SREV_9462_20_OR_LATER(ah))
1692 		ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1693 				   modesIndex);
1694 
1695 	REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites);
1696 
1697 	if (AR_SREV_9462_20_OR_LATER(ah)) {
1698 		/*
1699 		 * CUS217 mix LNA mode.
1700 		 */
1701 		if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1702 			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1703 					1, regWrites);
1704 			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1705 					modesIndex, regWrites);
1706 		}
1707 	}
1708 
1709 	/*
1710 	 * For 5GHz channels requiring Fast Clock, apply
1711 	 * different modal values.
1712 	 */
1713 	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1714 		REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1715 
1716 	if (AR_SREV_9565(ah))
1717 		REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1718 
1719 	/*
1720 	 * JAPAN regulatory.
1721 	 */
1722 	if (chan->channel == 2484)
1723 		ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1724 
1725 	ah->modes_index = modesIndex;
1726 	*ini_reloaded = true;
1727 
1728 set_rfmode:
1729 	ar9003_hw_set_rfmode(ah, chan);
1730 	return 0;
1731 }
1732 
1733 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1734 					   struct ath_spec_scan *param)
1735 {
1736 	u8 count;
1737 
1738 	if (!param->enabled) {
1739 		REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1740 			    AR_PHY_SPECTRAL_SCAN_ENABLE);
1741 		return;
1742 	}
1743 
1744 	REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1745 	REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1746 
1747 	/* on AR93xx and newer, count = 0 will make the chip send
1748 	 * spectral samples endlessly. Check if this really was intended,
1749 	 * and fix otherwise.
1750 	 */
1751 	count = param->count;
1752 	if (param->endless)
1753 		count = 0;
1754 	else if (param->count == 0)
1755 		count = 1;
1756 
1757 	if (param->short_repeat)
1758 		REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1759 			    AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1760 	else
1761 		REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1762 			    AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1763 
1764 	REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1765 		      AR_PHY_SPECTRAL_SCAN_COUNT, count);
1766 	REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1767 		      AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1768 	REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1769 		      AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1770 
1771 	return;
1772 }
1773 
1774 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1775 {
1776 	REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1777 		    AR_PHY_SPECTRAL_SCAN_ENABLE);
1778 	/* Activate spectral scan */
1779 	REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1780 		    AR_PHY_SPECTRAL_SCAN_ACTIVE);
1781 }
1782 
1783 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1784 {
1785 	struct ath_common *common = ath9k_hw_common(ah);
1786 
1787 	/* Poll for spectral scan complete */
1788 	if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1789 			   AR_PHY_SPECTRAL_SCAN_ACTIVE,
1790 			   0, AH_WAIT_TIMEOUT)) {
1791 		ath_err(common, "spectral scan wait failed\n");
1792 		return;
1793 	}
1794 }
1795 
1796 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum)
1797 {
1798 	REG_SET_BIT(ah, AR_PHY_TEST(ah), PHY_AGC_CLR);
1799 	REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1800 	REG_WRITE(ah, AR_CR, AR_CR_RXD);
1801 	REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
1802 	REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
1803 	REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
1804 	REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
1805 	REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
1806 	REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
1807 }
1808 
1809 static void ar9003_hw_tx99_stop(struct ath_hw *ah)
1810 {
1811 	REG_CLR_BIT(ah, AR_PHY_TEST(ah), PHY_AGC_CLR);
1812 	REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1813 }
1814 
1815 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
1816 {
1817 	static u8 p_pwr_array[ar9300RateSize] = { 0 };
1818 	unsigned int i;
1819 
1820 	txpower = txpower <= MAX_RATE_POWER ? txpower : MAX_RATE_POWER;
1821 	for (i = 0; i < ar9300RateSize; i++)
1822 		p_pwr_array[i] = txpower;
1823 
1824 	ar9003_hw_tx_power_regwrite(ah, p_pwr_array);
1825 }
1826 
1827 static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array)
1828 {
1829 	ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1830 	ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1831 	ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L],
1832 			      rate_array[ALL_TARGET_LEGACY_5S]);
1833 	ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L],
1834 			      rate_array[ALL_TARGET_LEGACY_11S]);
1835 }
1836 
1837 static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array,
1838 					int offset)
1839 {
1840 	int i, j;
1841 
1842 	for (i = offset; i < offset + AR9300_OFDM_RATES; i++) {
1843 		/* OFDM rate to power table idx */
1844 		j = ofdm2pwr[i - offset];
1845 		ah->tx_power[i] = rate_array[j];
1846 	}
1847 }
1848 
1849 static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array,
1850 				      int ss_offset, int ds_offset,
1851 				      int ts_offset, bool is_40)
1852 {
1853 	int i, j, mcs_idx = 0;
1854 	const u8 *mcs2pwr = (is_40) ? mcs2pwr_ht40 : mcs2pwr_ht20;
1855 
1856 	for (i = ss_offset; i < ss_offset + AR9300_HT_SS_RATES; i++) {
1857 		j = mcs2pwr[mcs_idx];
1858 		ah->tx_power[i] = rate_array[j];
1859 		mcs_idx++;
1860 	}
1861 
1862 	for (i = ds_offset; i < ds_offset + AR9300_HT_DS_RATES; i++) {
1863 		j = mcs2pwr[mcs_idx];
1864 		ah->tx_power[i] = rate_array[j];
1865 		mcs_idx++;
1866 	}
1867 
1868 	for (i = ts_offset; i < ts_offset + AR9300_HT_TS_RATES; i++) {
1869 		j = mcs2pwr[mcs_idx];
1870 		ah->tx_power[i] = rate_array[j];
1871 		mcs_idx++;
1872 	}
1873 }
1874 
1875 static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset,
1876 					int ds_offset, int ts_offset)
1877 {
1878 	memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset],
1879 	       AR9300_HT_SS_RATES);
1880 	memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset],
1881 	       AR9300_HT_DS_RATES);
1882 	memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset],
1883 	       AR9300_HT_TS_RATES);
1884 }
1885 
1886 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
1887 				 struct ath9k_channel *chan)
1888 {
1889 	if (IS_CHAN_5GHZ(chan)) {
1890 		ar9003_hw_init_txpower_ofdm(ah, rate_array,
1891 					    AR9300_11NA_OFDM_SHIFT);
1892 		if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1893 			ar9003_hw_init_txpower_ht(ah, rate_array,
1894 						  AR9300_11NA_HT_SS_SHIFT,
1895 						  AR9300_11NA_HT_DS_SHIFT,
1896 						  AR9300_11NA_HT_TS_SHIFT,
1897 						  IS_CHAN_HT40(chan));
1898 			ar9003_hw_init_txpower_stbc(ah,
1899 						    AR9300_11NA_HT_SS_SHIFT,
1900 						    AR9300_11NA_HT_DS_SHIFT,
1901 						    AR9300_11NA_HT_TS_SHIFT);
1902 		}
1903 	} else {
1904 		ar9003_hw_init_txpower_cck(ah, rate_array);
1905 		ar9003_hw_init_txpower_ofdm(ah, rate_array,
1906 					    AR9300_11NG_OFDM_SHIFT);
1907 		if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1908 			ar9003_hw_init_txpower_ht(ah, rate_array,
1909 						  AR9300_11NG_HT_SS_SHIFT,
1910 						  AR9300_11NG_HT_DS_SHIFT,
1911 						  AR9300_11NG_HT_TS_SHIFT,
1912 						  IS_CHAN_HT40(chan));
1913 			ar9003_hw_init_txpower_stbc(ah,
1914 						    AR9300_11NG_HT_SS_SHIFT,
1915 						    AR9300_11NG_HT_DS_SHIFT,
1916 						    AR9300_11NG_HT_TS_SHIFT);
1917 		}
1918 	}
1919 }
1920 
1921 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1922 {
1923 	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1924 	struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1925 	static const u32 ar9300_cca_regs[6] = {
1926 		AR_PHY_CCA_0,
1927 		AR_PHY_CCA_1,
1928 		AR_PHY_CCA_2,
1929 		AR_PHY_EXT_CCA,
1930 		AR_PHY_EXT_CCA_1,
1931 		AR_PHY_EXT_CCA_2,
1932 	};
1933 
1934 	priv_ops->rf_set_freq = ar9003_hw_set_channel;
1935 	priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1936 
1937 	if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1938 	    AR_SREV_9561(ah))
1939 		priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc;
1940 	else
1941 		priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1942 
1943 	priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1944 	priv_ops->init_bb = ar9003_hw_init_bb;
1945 	priv_ops->process_ini = ar9003_hw_process_ini;
1946 	priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1947 	priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1948 	priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1949 	priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1950 	priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1951 	priv_ops->ani_control = ar9003_hw_ani_control;
1952 	priv_ops->do_getnf = ar9003_hw_do_getnf;
1953 	priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1954 	priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1955 	priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1956 
1957 	ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1958 	ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1959 	ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1960 	ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1961 	ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1962 
1963 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1964 	ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
1965 #endif
1966 	ops->tx99_start = ar9003_hw_tx99_start;
1967 	ops->tx99_stop = ar9003_hw_tx99_stop;
1968 	ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower;
1969 
1970 	ar9003_hw_set_nf_limits(ah);
1971 	ar9003_hw_set_radar_conf(ah);
1972 	memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1973 }
1974 
1975 /*
1976  * Baseband Watchdog signatures:
1977  *
1978  * 0x04000539: BB hang when operating in HT40 DFS Channel.
1979  *             Full chip reset is not required, but a recovery
1980  *             mechanism is needed.
1981  *
1982  * 0x1300000a: Related to CAC deafness.
1983  *             Chip reset is not required.
1984  *
1985  * 0x0400000a: Related to CAC deafness.
1986  *             Full chip reset is required.
1987  *
1988  * 0x04000b09: RX state machine gets into an illegal state
1989  *             when a packet with unsupported rate is received.
1990  *             Full chip reset is required and PHY_RESTART has
1991  *             to be disabled.
1992  *
1993  * 0x04000409: Packet stuck on receive.
1994  *             Full chip reset is required for all chips except
1995  *	       AR9340, AR9531 and AR9561.
1996  */
1997 
1998 /*
1999  * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required.
2000  */
2001 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah)
2002 {
2003 	u32 val;
2004 
2005 	switch(ah->bb_watchdog_last_status) {
2006 	case 0x04000539:
2007 		val = REG_READ(ah, AR_PHY_RADAR_0);
2008 		val &= (~AR_PHY_RADAR_0_FIRPWR);
2009 		val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR);
2010 		REG_WRITE(ah, AR_PHY_RADAR_0, val);
2011 		udelay(1);
2012 		val = REG_READ(ah, AR_PHY_RADAR_0);
2013 		val &= ~AR_PHY_RADAR_0_FIRPWR;
2014 		val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR);
2015 		REG_WRITE(ah, AR_PHY_RADAR_0, val);
2016 
2017 		return false;
2018 	case 0x1300000a:
2019 		return false;
2020 	case 0x0400000a:
2021 	case 0x04000b09:
2022 		return true;
2023 	case 0x04000409:
2024 		if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah))
2025 			return false;
2026 		else
2027 			return true;
2028 	default:
2029 		/*
2030 		 * For any other unknown signatures, do a
2031 		 * full chip reset.
2032 		 */
2033 		return true;
2034 	}
2035 }
2036 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check);
2037 
2038 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
2039 {
2040 	struct ath_common *common = ath9k_hw_common(ah);
2041 	u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
2042 	u32 val, idle_count;
2043 
2044 	if (!idle_tmo_ms) {
2045 		/* disable IRQ, disable chip-reset for BB panic */
2046 		REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2047 			  REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
2048 			  ~(AR_PHY_WATCHDOG_RST_ENABLE |
2049 			    AR_PHY_WATCHDOG_IRQ_ENABLE));
2050 
2051 		/* disable watchdog in non-IDLE mode, disable in IDLE mode */
2052 		REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2053 			  REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
2054 			  ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
2055 			    AR_PHY_WATCHDOG_IDLE_ENABLE));
2056 
2057 		ath_dbg(common, RESET, "Disabled BB Watchdog\n");
2058 		return;
2059 	}
2060 
2061 	/* enable IRQ, disable chip-reset for BB watchdog */
2062 	val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
2063 	REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2064 		  (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
2065 		  ~AR_PHY_WATCHDOG_RST_ENABLE);
2066 
2067 	/* bound limit to 10 secs */
2068 	if (idle_tmo_ms > 10000)
2069 		idle_tmo_ms = 10000;
2070 
2071 	/*
2072 	 * The time unit for watchdog event is 2^15 44/88MHz cycles.
2073 	 *
2074 	 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
2075 	 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
2076 	 *
2077 	 * Given we use fast clock now in 5 GHz, these time units should
2078 	 * be common for both 2 GHz and 5 GHz.
2079 	 */
2080 	idle_count = (100 * idle_tmo_ms) / 74;
2081 	if (ah->curchan && IS_CHAN_HT40(ah->curchan))
2082 		idle_count = (100 * idle_tmo_ms) / 37;
2083 
2084 	/*
2085 	 * enable watchdog in non-IDLE mode, disable in IDLE mode,
2086 	 * set idle time-out.
2087 	 */
2088 	REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2089 		  AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
2090 		  AR_PHY_WATCHDOG_IDLE_MASK |
2091 		  (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
2092 
2093 	ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
2094 		idle_tmo_ms);
2095 }
2096 
2097 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
2098 {
2099 	/*
2100 	 * we want to avoid printing in ISR context so we save the
2101 	 * watchdog status to be printed later in bottom half context.
2102 	 */
2103 	ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
2104 
2105 	/*
2106 	 * the watchdog timer should reset on status read but to be sure
2107 	 * sure we write 0 to the watchdog status bit.
2108 	 */
2109 	REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
2110 		  ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
2111 }
2112 
2113 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
2114 {
2115 	struct ath_common *common = ath9k_hw_common(ah);
2116 	u32 status;
2117 
2118 	if (likely(!(common->debug_mask & ATH_DBG_RESET)))
2119 		return;
2120 
2121 	status = ah->bb_watchdog_last_status;
2122 	ath_dbg(common, RESET,
2123 		"\n==== BB update: BB status=0x%08x ====\n", status);
2124 	ath_dbg(common, RESET,
2125 		"** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
2126 		MS(status, AR_PHY_WATCHDOG_INFO),
2127 		MS(status, AR_PHY_WATCHDOG_DET_HANG),
2128 		MS(status, AR_PHY_WATCHDOG_RADAR_SM),
2129 		MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
2130 		MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
2131 		MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
2132 		MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
2133 		MS(status, AR_PHY_WATCHDOG_AGC_SM),
2134 		MS(status, AR_PHY_WATCHDOG_SRCH_SM));
2135 
2136 	ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
2137 		REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
2138 		REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
2139 	ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
2140 		REG_READ(ah, AR_PHY_GEN_CTRL));
2141 
2142 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
2143 	if (common->cc_survey.cycles)
2144 		ath_dbg(common, RESET,
2145 			"** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
2146 			PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
2147 
2148 	ath_dbg(common, RESET, "==== BB update: done ====\n\n");
2149 }
2150 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
2151 
2152 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
2153 {
2154 	u8 result;
2155 	u32 val;
2156 
2157 	/* While receiving unsupported rate frame rx state machine
2158 	 * gets into a state 0xb and if phy_restart happens in that
2159 	 * state, BB would go hang. If RXSM is in 0xb state after
2160 	 * first bb panic, ensure to disable the phy_restart.
2161 	 */
2162 	result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM);
2163 
2164 	if ((result == 0xb) || ah->bb_hang_rx_ofdm) {
2165 		ah->bb_hang_rx_ofdm = true;
2166 		val = REG_READ(ah, AR_PHY_RESTART);
2167 		val &= ~AR_PHY_RESTART_ENA;
2168 		REG_WRITE(ah, AR_PHY_RESTART, val);
2169 	}
2170 }
2171 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
2172