1 /* 2 * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/etherdevice.h> 18 #include <linux/moduleparam.h> 19 #include <linux/prefetch.h> 20 #include <linux/types.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include "wil6210.h" 25 #include "txrx_edma.h" 26 #include "txrx.h" 27 #include "trace.h" 28 29 #define WIL_EDMA_MAX_DATA_OFFSET (2) 30 /* RX buffer size must be aligned to 4 bytes */ 31 #define WIL_EDMA_RX_BUF_LEN_DEFAULT (2048) 32 #define MAX_INVALID_BUFF_ID_RETRY (3) 33 34 static void wil_tx_desc_unmap_edma(struct device *dev, 35 union wil_tx_desc *desc, 36 struct wil_ctx *ctx) 37 { 38 struct wil_tx_enhanced_desc *d = (struct wil_tx_enhanced_desc *)desc; 39 dma_addr_t pa = wil_tx_desc_get_addr_edma(&d->dma); 40 u16 dmalen = le16_to_cpu(d->dma.length); 41 42 switch (ctx->mapped_as) { 43 case wil_mapped_as_single: 44 dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE); 45 break; 46 case wil_mapped_as_page: 47 dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE); 48 break; 49 default: 50 break; 51 } 52 } 53 54 static int wil_find_free_sring(struct wil6210_priv *wil) 55 { 56 int i; 57 58 for (i = 0; i < WIL6210_MAX_STATUS_RINGS; i++) { 59 if (!wil->srings[i].va) 60 return i; 61 } 62 63 return -EINVAL; 64 } 65 66 static void wil_sring_free(struct wil6210_priv *wil, 67 struct wil_status_ring *sring) 68 { 69 struct device *dev = wil_to_dev(wil); 70 size_t sz; 71 72 if (!sring || !sring->va) 73 return; 74 75 sz = sring->elem_size * sring->size; 76 77 wil_dbg_misc(wil, "status_ring_free, size(bytes)=%zu, 0x%p:%pad\n", 78 sz, sring->va, &sring->pa); 79 80 dma_free_coherent(dev, sz, (void *)sring->va, sring->pa); 81 sring->pa = 0; 82 sring->va = NULL; 83 } 84 85 static int wil_sring_alloc(struct wil6210_priv *wil, 86 struct wil_status_ring *sring) 87 { 88 struct device *dev = wil_to_dev(wil); 89 size_t sz = sring->elem_size * sring->size; 90 91 wil_dbg_misc(wil, "status_ring_alloc: size=%zu\n", sz); 92 93 if (sz == 0) { 94 wil_err(wil, "Cannot allocate a zero size status ring\n"); 95 return -EINVAL; 96 } 97 98 sring->swhead = 0; 99 100 /* Status messages are allocated and initialized to 0. This is necessary 101 * since DR bit should be initialized to 0. 102 */ 103 sring->va = dma_alloc_coherent(dev, sz, &sring->pa, GFP_KERNEL); 104 if (!sring->va) 105 return -ENOMEM; 106 107 wil_dbg_misc(wil, "status_ring[%d] 0x%p:%pad\n", sring->size, sring->va, 108 &sring->pa); 109 110 return 0; 111 } 112 113 static int wil_tx_init_edma(struct wil6210_priv *wil) 114 { 115 int ring_id = wil_find_free_sring(wil); 116 struct wil_status_ring *sring; 117 int rc; 118 u16 status_ring_size; 119 120 if (wil->tx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN || 121 wil->tx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX) 122 wil->tx_status_ring_order = WIL_TX_SRING_SIZE_ORDER_DEFAULT; 123 124 status_ring_size = 1 << wil->tx_status_ring_order; 125 126 wil_dbg_misc(wil, "init TX sring: size=%u, ring_id=%u\n", 127 status_ring_size, ring_id); 128 129 if (ring_id < 0) 130 return ring_id; 131 132 /* Allocate Tx status ring. Tx descriptor rings will be 133 * allocated on WMI connect event 134 */ 135 sring = &wil->srings[ring_id]; 136 137 sring->is_rx = false; 138 sring->size = status_ring_size; 139 sring->elem_size = sizeof(struct wil_ring_tx_status); 140 rc = wil_sring_alloc(wil, sring); 141 if (rc) 142 return rc; 143 144 rc = wil_wmi_tx_sring_cfg(wil, ring_id); 145 if (rc) 146 goto out_free; 147 148 sring->desc_rdy_pol = 1; 149 wil->tx_sring_idx = ring_id; 150 151 return 0; 152 out_free: 153 wil_sring_free(wil, sring); 154 return rc; 155 } 156 157 /** 158 * Allocate one skb for Rx descriptor RING 159 */ 160 static int wil_ring_alloc_skb_edma(struct wil6210_priv *wil, 161 struct wil_ring *ring, u32 i) 162 { 163 struct device *dev = wil_to_dev(wil); 164 unsigned int sz = wil->rx_buf_len; 165 dma_addr_t pa; 166 u16 buff_id; 167 struct list_head *active = &wil->rx_buff_mgmt.active; 168 struct list_head *free = &wil->rx_buff_mgmt.free; 169 struct wil_rx_buff *rx_buff; 170 struct wil_rx_buff *buff_arr = wil->rx_buff_mgmt.buff_arr; 171 struct sk_buff *skb; 172 struct wil_rx_enhanced_desc dd, *d = ⅆ 173 struct wil_rx_enhanced_desc *_d = (struct wil_rx_enhanced_desc *) 174 &ring->va[i].rx.enhanced; 175 176 if (unlikely(list_empty(free))) { 177 wil->rx_buff_mgmt.free_list_empty_cnt++; 178 return -EAGAIN; 179 } 180 181 skb = dev_alloc_skb(sz); 182 if (unlikely(!skb)) 183 return -ENOMEM; 184 185 skb_put(skb, sz); 186 187 /** 188 * Make sure that the network stack calculates checksum for packets 189 * which failed the HW checksum calculation 190 */ 191 skb->ip_summed = CHECKSUM_NONE; 192 193 pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE); 194 if (unlikely(dma_mapping_error(dev, pa))) { 195 kfree_skb(skb); 196 return -ENOMEM; 197 } 198 199 /* Get the buffer ID - the index of the rx buffer in the buff_arr */ 200 rx_buff = list_first_entry(free, struct wil_rx_buff, list); 201 buff_id = rx_buff->id; 202 203 /* Move a buffer from the free list to the active list */ 204 list_move(&rx_buff->list, active); 205 206 buff_arr[buff_id].skb = skb; 207 208 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa); 209 d->dma.length = cpu_to_le16(sz); 210 d->mac.buff_id = cpu_to_le16(buff_id); 211 *_d = *d; 212 213 /* Save the physical address in skb->cb for later use in dma_unmap */ 214 memcpy(skb->cb, &pa, sizeof(pa)); 215 216 return 0; 217 } 218 219 static inline 220 void wil_get_next_rx_status_msg(struct wil_status_ring *sring, void *msg) 221 { 222 memcpy(msg, (void *)(sring->va + (sring->elem_size * sring->swhead)), 223 sring->elem_size); 224 } 225 226 static inline void wil_sring_advance_swhead(struct wil_status_ring *sring) 227 { 228 sring->swhead = (sring->swhead + 1) % sring->size; 229 if (sring->swhead == 0) 230 sring->desc_rdy_pol = 1 - sring->desc_rdy_pol; 231 } 232 233 static int wil_rx_refill_edma(struct wil6210_priv *wil) 234 { 235 struct wil_ring *ring = &wil->ring_rx; 236 u32 next_head; 237 int rc = 0; 238 ring->swtail = *ring->edma_rx_swtail.va; 239 240 for (; next_head = wil_ring_next_head(ring), 241 (next_head != ring->swtail); 242 ring->swhead = next_head) { 243 rc = wil_ring_alloc_skb_edma(wil, ring, ring->swhead); 244 if (unlikely(rc)) { 245 if (rc == -EAGAIN) 246 wil_dbg_txrx(wil, "No free buffer ID found\n"); 247 else 248 wil_err_ratelimited(wil, 249 "Error %d in refill desc[%d]\n", 250 rc, ring->swhead); 251 break; 252 } 253 } 254 255 /* make sure all writes to descriptors (shared memory) are done before 256 * committing them to HW 257 */ 258 wmb(); 259 260 wil_w(wil, ring->hwtail, ring->swhead); 261 262 return rc; 263 } 264 265 static void wil_move_all_rx_buff_to_free_list(struct wil6210_priv *wil, 266 struct wil_ring *ring) 267 { 268 struct device *dev = wil_to_dev(wil); 269 struct list_head *active = &wil->rx_buff_mgmt.active; 270 dma_addr_t pa; 271 272 while (!list_empty(active)) { 273 struct wil_rx_buff *rx_buff = 274 list_first_entry(active, struct wil_rx_buff, list); 275 struct sk_buff *skb = rx_buff->skb; 276 277 if (unlikely(!skb)) { 278 wil_err(wil, "No Rx skb at buff_id %d\n", rx_buff->id); 279 } else { 280 rx_buff->skb = NULL; 281 memcpy(&pa, skb->cb, sizeof(pa)); 282 dma_unmap_single(dev, pa, wil->rx_buf_len, 283 DMA_FROM_DEVICE); 284 kfree_skb(skb); 285 } 286 287 /* Move the buffer from the active to the free list */ 288 list_move(&rx_buff->list, &wil->rx_buff_mgmt.free); 289 } 290 } 291 292 static void wil_free_rx_buff_arr(struct wil6210_priv *wil) 293 { 294 struct wil_ring *ring = &wil->ring_rx; 295 296 if (!wil->rx_buff_mgmt.buff_arr) 297 return; 298 299 /* Move all the buffers to the free list in case active list is 300 * not empty in order to release all SKBs before deleting the array 301 */ 302 wil_move_all_rx_buff_to_free_list(wil, ring); 303 304 kfree(wil->rx_buff_mgmt.buff_arr); 305 wil->rx_buff_mgmt.buff_arr = NULL; 306 } 307 308 static int wil_init_rx_buff_arr(struct wil6210_priv *wil, 309 size_t size) 310 { 311 struct wil_rx_buff *buff_arr; 312 struct list_head *active = &wil->rx_buff_mgmt.active; 313 struct list_head *free = &wil->rx_buff_mgmt.free; 314 int i; 315 316 wil->rx_buff_mgmt.buff_arr = kcalloc(size + 1, 317 sizeof(struct wil_rx_buff), 318 GFP_KERNEL); 319 if (!wil->rx_buff_mgmt.buff_arr) 320 return -ENOMEM; 321 322 /* Set list heads */ 323 INIT_LIST_HEAD(active); 324 INIT_LIST_HEAD(free); 325 326 /* Linkify the list. 327 * buffer id 0 should not be used (marks invalid id). 328 */ 329 buff_arr = wil->rx_buff_mgmt.buff_arr; 330 for (i = 1; i <= size; i++) { 331 list_add(&buff_arr[i].list, free); 332 buff_arr[i].id = i; 333 } 334 335 wil->rx_buff_mgmt.size = size + 1; 336 337 return 0; 338 } 339 340 static int wil_init_rx_sring(struct wil6210_priv *wil, 341 u16 status_ring_size, 342 size_t elem_size, 343 u16 ring_id) 344 { 345 struct wil_status_ring *sring = &wil->srings[ring_id]; 346 int rc; 347 348 wil_dbg_misc(wil, "init RX sring: size=%u, ring_id=%u\n", 349 status_ring_size, ring_id); 350 351 memset(&sring->rx_data, 0, sizeof(sring->rx_data)); 352 353 sring->is_rx = true; 354 sring->size = status_ring_size; 355 sring->elem_size = elem_size; 356 rc = wil_sring_alloc(wil, sring); 357 if (rc) 358 return rc; 359 360 rc = wil_wmi_rx_sring_add(wil, ring_id); 361 if (rc) 362 goto out_free; 363 364 sring->desc_rdy_pol = 1; 365 366 return 0; 367 out_free: 368 wil_sring_free(wil, sring); 369 return rc; 370 } 371 372 static int wil_ring_alloc_desc_ring(struct wil6210_priv *wil, 373 struct wil_ring *ring) 374 { 375 struct device *dev = wil_to_dev(wil); 376 size_t sz = ring->size * sizeof(ring->va[0]); 377 378 wil_dbg_misc(wil, "alloc_desc_ring:\n"); 379 380 BUILD_BUG_ON(sizeof(ring->va[0]) != 32); 381 382 ring->swhead = 0; 383 ring->swtail = 0; 384 ring->ctx = kcalloc(ring->size, sizeof(ring->ctx[0]), GFP_KERNEL); 385 if (!ring->ctx) 386 goto err; 387 388 ring->va = dma_alloc_coherent(dev, sz, &ring->pa, GFP_KERNEL); 389 if (!ring->va) 390 goto err_free_ctx; 391 392 if (ring->is_rx) { 393 sz = sizeof(*ring->edma_rx_swtail.va); 394 ring->edma_rx_swtail.va = 395 dma_alloc_coherent(dev, sz, &ring->edma_rx_swtail.pa, 396 GFP_KERNEL); 397 if (!ring->edma_rx_swtail.va) 398 goto err_free_va; 399 } 400 401 wil_dbg_misc(wil, "%s ring[%d] 0x%p:%pad 0x%p\n", 402 ring->is_rx ? "RX" : "TX", 403 ring->size, ring->va, &ring->pa, ring->ctx); 404 405 return 0; 406 err_free_va: 407 dma_free_coherent(dev, ring->size * sizeof(ring->va[0]), 408 (void *)ring->va, ring->pa); 409 ring->va = NULL; 410 err_free_ctx: 411 kfree(ring->ctx); 412 ring->ctx = NULL; 413 err: 414 return -ENOMEM; 415 } 416 417 static void wil_ring_free_edma(struct wil6210_priv *wil, struct wil_ring *ring) 418 { 419 struct device *dev = wil_to_dev(wil); 420 size_t sz; 421 int ring_index = 0; 422 423 if (!ring->va) 424 return; 425 426 sz = ring->size * sizeof(ring->va[0]); 427 428 lockdep_assert_held(&wil->mutex); 429 if (ring->is_rx) { 430 wil_dbg_misc(wil, "free Rx ring [%d] 0x%p:%pad 0x%p\n", 431 ring->size, ring->va, 432 &ring->pa, ring->ctx); 433 434 wil_move_all_rx_buff_to_free_list(wil, ring); 435 dma_free_coherent(dev, sizeof(*ring->edma_rx_swtail.va), 436 ring->edma_rx_swtail.va, 437 ring->edma_rx_swtail.pa); 438 goto out; 439 } 440 441 /* TX ring */ 442 ring_index = ring - wil->ring_tx; 443 444 wil_dbg_misc(wil, "free Tx ring %d [%d] 0x%p:%pad 0x%p\n", 445 ring_index, ring->size, ring->va, 446 &ring->pa, ring->ctx); 447 448 while (!wil_ring_is_empty(ring)) { 449 struct wil_ctx *ctx; 450 451 struct wil_tx_enhanced_desc dd, *d = ⅆ 452 struct wil_tx_enhanced_desc *_d = 453 (struct wil_tx_enhanced_desc *) 454 &ring->va[ring->swtail].tx.enhanced; 455 456 ctx = &ring->ctx[ring->swtail]; 457 if (!ctx) { 458 wil_dbg_txrx(wil, 459 "ctx(%d) was already completed\n", 460 ring->swtail); 461 ring->swtail = wil_ring_next_tail(ring); 462 continue; 463 } 464 *d = *_d; 465 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx); 466 if (ctx->skb) 467 dev_kfree_skb_any(ctx->skb); 468 ring->swtail = wil_ring_next_tail(ring); 469 } 470 471 out: 472 dma_free_coherent(dev, sz, (void *)ring->va, ring->pa); 473 kfree(ring->ctx); 474 ring->pa = 0; 475 ring->va = NULL; 476 ring->ctx = NULL; 477 } 478 479 static int wil_init_rx_desc_ring(struct wil6210_priv *wil, u16 desc_ring_size, 480 int status_ring_id) 481 { 482 struct wil_ring *ring = &wil->ring_rx; 483 int rc; 484 485 wil_dbg_misc(wil, "init RX desc ring\n"); 486 487 ring->size = desc_ring_size; 488 ring->is_rx = true; 489 rc = wil_ring_alloc_desc_ring(wil, ring); 490 if (rc) 491 return rc; 492 493 rc = wil_wmi_rx_desc_ring_add(wil, status_ring_id); 494 if (rc) 495 goto out_free; 496 497 return 0; 498 out_free: 499 wil_ring_free_edma(wil, ring); 500 return rc; 501 } 502 503 static void wil_get_reorder_params_edma(struct wil6210_priv *wil, 504 struct sk_buff *skb, int *tid, 505 int *cid, int *mid, u16 *seq, 506 int *mcast, int *retry) 507 { 508 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb); 509 510 *tid = wil_rx_status_get_tid(s); 511 *cid = wil_rx_status_get_cid(s); 512 *mid = wil_rx_status_get_mid(s); 513 *seq = le16_to_cpu(wil_rx_status_get_seq(wil, s)); 514 *mcast = wil_rx_status_get_mcast(s); 515 *retry = wil_rx_status_get_retry(s); 516 } 517 518 static void wil_get_netif_rx_params_edma(struct sk_buff *skb, int *cid, 519 int *security) 520 { 521 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb); 522 523 *cid = wil_rx_status_get_cid(s); 524 *security = wil_rx_status_get_security(s); 525 } 526 527 static int wil_rx_crypto_check_edma(struct wil6210_priv *wil, 528 struct sk_buff *skb) 529 { 530 struct wil_rx_status_extended *st; 531 int cid, tid, key_id, mc; 532 struct wil_sta_info *s; 533 struct wil_tid_crypto_rx *c; 534 struct wil_tid_crypto_rx_single *cc; 535 const u8 *pn; 536 537 /* In HW reorder, HW is responsible for crypto check */ 538 if (wil->use_rx_hw_reordering) 539 return 0; 540 541 st = wil_skb_rxstatus(skb); 542 543 cid = wil_rx_status_get_cid(st); 544 tid = wil_rx_status_get_tid(st); 545 key_id = wil_rx_status_get_key_id(st); 546 mc = wil_rx_status_get_mcast(st); 547 s = &wil->sta[cid]; 548 c = mc ? &s->group_crypto_rx : &s->tid_crypto_rx[tid]; 549 cc = &c->key_id[key_id]; 550 pn = (u8 *)&st->ext.pn_15_0; 551 552 if (!cc->key_set) { 553 wil_err_ratelimited(wil, 554 "Key missing. CID %d TID %d MCast %d KEY_ID %d\n", 555 cid, tid, mc, key_id); 556 return -EINVAL; 557 } 558 559 if (reverse_memcmp(pn, cc->pn, IEEE80211_GCMP_PN_LEN) <= 0) { 560 wil_err_ratelimited(wil, 561 "Replay attack. CID %d TID %d MCast %d KEY_ID %d PN %6phN last %6phN\n", 562 cid, tid, mc, key_id, pn, cc->pn); 563 return -EINVAL; 564 } 565 memcpy(cc->pn, pn, IEEE80211_GCMP_PN_LEN); 566 567 return 0; 568 } 569 570 static bool wil_is_rx_idle_edma(struct wil6210_priv *wil) 571 { 572 struct wil_status_ring *sring; 573 struct wil_rx_status_extended msg1; 574 void *msg = &msg1; 575 u8 dr_bit; 576 int i; 577 578 for (i = 0; i < wil->num_rx_status_rings; i++) { 579 sring = &wil->srings[i]; 580 if (!sring->va) 581 continue; 582 583 wil_get_next_rx_status_msg(sring, msg); 584 dr_bit = wil_rx_status_get_desc_rdy_bit(msg); 585 586 /* Check if there are unhandled RX status messages */ 587 if (dr_bit == sring->desc_rdy_pol) 588 return false; 589 } 590 591 return true; 592 } 593 594 static void wil_rx_buf_len_init_edma(struct wil6210_priv *wil) 595 { 596 /* RX buffer size must be aligned to 4 bytes */ 597 wil->rx_buf_len = rx_large_buf ? 598 WIL_MAX_ETH_MTU : WIL_EDMA_RX_BUF_LEN_DEFAULT; 599 } 600 601 static int wil_rx_init_edma(struct wil6210_priv *wil, uint desc_ring_order) 602 { 603 u16 status_ring_size, desc_ring_size = 1 << desc_ring_order; 604 struct wil_ring *ring = &wil->ring_rx; 605 int rc; 606 size_t elem_size = wil->use_compressed_rx_status ? 607 sizeof(struct wil_rx_status_compressed) : 608 sizeof(struct wil_rx_status_extended); 609 int i; 610 611 /* In SW reorder one must use extended status messages */ 612 if (wil->use_compressed_rx_status && !wil->use_rx_hw_reordering) { 613 wil_err(wil, 614 "compressed RX status cannot be used with SW reorder\n"); 615 return -EINVAL; 616 } 617 if (wil->rx_status_ring_order <= desc_ring_order) 618 /* make sure sring is larger than desc ring */ 619 wil->rx_status_ring_order = desc_ring_order + 1; 620 if (wil->rx_buff_id_count <= desc_ring_size) 621 /* make sure we will not run out of buff_ids */ 622 wil->rx_buff_id_count = desc_ring_size + 512; 623 if (wil->rx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN || 624 wil->rx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX) 625 wil->rx_status_ring_order = WIL_RX_SRING_SIZE_ORDER_DEFAULT; 626 627 status_ring_size = 1 << wil->rx_status_ring_order; 628 629 wil_dbg_misc(wil, 630 "rx_init, desc_ring_size=%u, status_ring_size=%u, elem_size=%zu\n", 631 desc_ring_size, status_ring_size, elem_size); 632 633 wil_rx_buf_len_init_edma(wil); 634 635 /* Use debugfs dbg_num_rx_srings if set, reserve one sring for TX */ 636 if (wil->num_rx_status_rings > WIL6210_MAX_STATUS_RINGS - 1) 637 wil->num_rx_status_rings = WIL6210_MAX_STATUS_RINGS - 1; 638 639 wil_dbg_misc(wil, "rx_init: allocate %d status rings\n", 640 wil->num_rx_status_rings); 641 642 rc = wil_wmi_cfg_def_rx_offload(wil, wil->rx_buf_len); 643 if (rc) 644 return rc; 645 646 /* Allocate status ring */ 647 for (i = 0; i < wil->num_rx_status_rings; i++) { 648 int sring_id = wil_find_free_sring(wil); 649 650 if (sring_id < 0) { 651 rc = -EFAULT; 652 goto err_free_status; 653 } 654 rc = wil_init_rx_sring(wil, status_ring_size, elem_size, 655 sring_id); 656 if (rc) 657 goto err_free_status; 658 } 659 660 /* Allocate descriptor ring */ 661 rc = wil_init_rx_desc_ring(wil, desc_ring_size, 662 WIL_DEFAULT_RX_STATUS_RING_ID); 663 if (rc) 664 goto err_free_status; 665 666 if (wil->rx_buff_id_count >= status_ring_size) { 667 wil_info(wil, 668 "rx_buff_id_count %d exceeds sring_size %d. set it to %d\n", 669 wil->rx_buff_id_count, status_ring_size, 670 status_ring_size - 1); 671 wil->rx_buff_id_count = status_ring_size - 1; 672 } 673 674 /* Allocate Rx buffer array */ 675 rc = wil_init_rx_buff_arr(wil, wil->rx_buff_id_count); 676 if (rc) 677 goto err_free_desc; 678 679 /* Fill descriptor ring with credits */ 680 rc = wil_rx_refill_edma(wil); 681 if (rc) 682 goto err_free_rx_buff_arr; 683 684 return 0; 685 err_free_rx_buff_arr: 686 wil_free_rx_buff_arr(wil); 687 err_free_desc: 688 wil_ring_free_edma(wil, ring); 689 err_free_status: 690 for (i = 0; i < wil->num_rx_status_rings; i++) 691 wil_sring_free(wil, &wil->srings[i]); 692 693 return rc; 694 } 695 696 static int wil_ring_init_tx_edma(struct wil6210_vif *vif, int ring_id, 697 int size, int cid, int tid) 698 { 699 struct wil6210_priv *wil = vif_to_wil(vif); 700 int rc; 701 struct wil_ring *ring = &wil->ring_tx[ring_id]; 702 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 703 704 lockdep_assert_held(&wil->mutex); 705 706 wil_dbg_misc(wil, 707 "init TX ring: ring_id=%u, cid=%u, tid=%u, sring_id=%u\n", 708 ring_id, cid, tid, wil->tx_sring_idx); 709 710 wil_tx_data_init(txdata); 711 ring->size = size; 712 rc = wil_ring_alloc_desc_ring(wil, ring); 713 if (rc) 714 goto out; 715 716 wil->ring2cid_tid[ring_id][0] = cid; 717 wil->ring2cid_tid[ring_id][1] = tid; 718 if (!vif->privacy) 719 txdata->dot1x_open = true; 720 721 rc = wil_wmi_tx_desc_ring_add(vif, ring_id, cid, tid); 722 if (rc) { 723 wil_err(wil, "WMI_TX_DESC_RING_ADD_CMD failed\n"); 724 goto out_free; 725 } 726 727 if (txdata->dot1x_open && agg_wsize >= 0) 728 wil_addba_tx_request(wil, ring_id, agg_wsize); 729 730 return 0; 731 out_free: 732 spin_lock_bh(&txdata->lock); 733 txdata->dot1x_open = false; 734 txdata->enabled = 0; 735 spin_unlock_bh(&txdata->lock); 736 wil_ring_free_edma(wil, ring); 737 wil->ring2cid_tid[ring_id][0] = max_assoc_sta; 738 wil->ring2cid_tid[ring_id][1] = 0; 739 740 out: 741 return rc; 742 } 743 744 static int wil_tx_ring_modify_edma(struct wil6210_vif *vif, int ring_id, 745 int cid, int tid) 746 { 747 struct wil6210_priv *wil = vif_to_wil(vif); 748 749 wil_err(wil, "ring modify is not supported for EDMA\n"); 750 751 return -EOPNOTSUPP; 752 } 753 754 /* This function is used only for RX SW reorder */ 755 static int wil_check_bar(struct wil6210_priv *wil, void *msg, int cid, 756 struct sk_buff *skb, struct wil_net_stats *stats) 757 { 758 u8 ftype; 759 u8 fc1; 760 int mid; 761 int tid; 762 u16 seq; 763 struct wil6210_vif *vif; 764 765 ftype = wil_rx_status_get_frame_type(wil, msg); 766 if (ftype == IEEE80211_FTYPE_DATA) 767 return 0; 768 769 fc1 = wil_rx_status_get_fc1(wil, msg); 770 mid = wil_rx_status_get_mid(msg); 771 tid = wil_rx_status_get_tid(msg); 772 seq = le16_to_cpu(wil_rx_status_get_seq(wil, msg)); 773 vif = wil->vifs[mid]; 774 775 if (unlikely(!vif)) { 776 wil_dbg_txrx(wil, "RX descriptor with invalid mid %d", mid); 777 return -EAGAIN; 778 } 779 780 wil_dbg_txrx(wil, 781 "Non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 782 fc1, mid, cid, tid, seq); 783 if (stats) 784 stats->rx_non_data_frame++; 785 if (wil_is_back_req(fc1)) { 786 wil_dbg_txrx(wil, 787 "BAR: MID %d CID %d TID %d Seq 0x%03x\n", 788 mid, cid, tid, seq); 789 wil_rx_bar(wil, vif, cid, tid, seq); 790 } else { 791 u32 sz = wil->use_compressed_rx_status ? 792 sizeof(struct wil_rx_status_compressed) : 793 sizeof(struct wil_rx_status_extended); 794 795 /* print again all info. One can enable only this 796 * without overhead for printing every Rx frame 797 */ 798 wil_dbg_txrx(wil, 799 "Unhandled non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 800 fc1, mid, cid, tid, seq); 801 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4, 802 (const void *)msg, sz, false); 803 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 804 skb->data, skb_headlen(skb), false); 805 } 806 807 return -EAGAIN; 808 } 809 810 static int wil_rx_error_check_edma(struct wil6210_priv *wil, 811 struct sk_buff *skb, 812 struct wil_net_stats *stats) 813 { 814 int l2_rx_status; 815 void *msg = wil_skb_rxstatus(skb); 816 817 l2_rx_status = wil_rx_status_get_l2_rx_status(msg); 818 if (l2_rx_status != 0) { 819 wil_dbg_txrx(wil, "L2 RX error, l2_rx_status=0x%x\n", 820 l2_rx_status); 821 /* Due to HW issue, KEY error will trigger a MIC error */ 822 if (l2_rx_status == WIL_RX_EDMA_ERROR_MIC) { 823 wil_err_ratelimited(wil, 824 "L2 MIC/KEY error, dropping packet\n"); 825 stats->rx_mic_error++; 826 } 827 if (l2_rx_status == WIL_RX_EDMA_ERROR_KEY) { 828 wil_err_ratelimited(wil, 829 "L2 KEY error, dropping packet\n"); 830 stats->rx_key_error++; 831 } 832 if (l2_rx_status == WIL_RX_EDMA_ERROR_REPLAY) { 833 wil_err_ratelimited(wil, 834 "L2 REPLAY error, dropping packet\n"); 835 stats->rx_replay++; 836 } 837 if (l2_rx_status == WIL_RX_EDMA_ERROR_AMSDU) { 838 wil_err_ratelimited(wil, 839 "L2 AMSDU error, dropping packet\n"); 840 stats->rx_amsdu_error++; 841 } 842 return -EFAULT; 843 } 844 845 skb->ip_summed = wil_rx_status_get_checksum(msg, stats); 846 847 return 0; 848 } 849 850 static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil, 851 struct wil_status_ring *sring) 852 { 853 struct device *dev = wil_to_dev(wil); 854 struct wil_rx_status_extended msg1; 855 void *msg = &msg1; 856 u16 buff_id; 857 struct sk_buff *skb; 858 dma_addr_t pa; 859 struct wil_ring_rx_data *rxdata = &sring->rx_data; 860 unsigned int sz = wil->rx_buf_len; 861 struct wil_net_stats *stats = NULL; 862 u16 dmalen; 863 int cid; 864 bool eop, headstolen; 865 int delta; 866 u8 dr_bit; 867 u8 data_offset; 868 struct wil_rx_status_extended *s; 869 u16 sring_idx = sring - wil->srings; 870 871 BUILD_BUG_ON(sizeof(struct wil_rx_status_extended) > sizeof(skb->cb)); 872 873 again: 874 wil_get_next_rx_status_msg(sring, msg); 875 dr_bit = wil_rx_status_get_desc_rdy_bit(msg); 876 877 /* Completed handling all the ready status messages */ 878 if (dr_bit != sring->desc_rdy_pol) 879 return NULL; 880 881 /* Extract the buffer ID from the status message */ 882 buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg)); 883 884 while (!buff_id) { 885 struct wil_rx_status_extended *s; 886 int invalid_buff_id_retry = 0; 887 888 wil_dbg_txrx(wil, 889 "buff_id is not updated yet by HW, (swhead 0x%x)\n", 890 sring->swhead); 891 if (++invalid_buff_id_retry > MAX_INVALID_BUFF_ID_RETRY) 892 break; 893 894 /* Read the status message again */ 895 s = (struct wil_rx_status_extended *) 896 (sring->va + (sring->elem_size * sring->swhead)); 897 *(struct wil_rx_status_extended *)msg = *s; 898 buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg)); 899 } 900 901 if (unlikely(!wil_val_in_range(buff_id, 1, wil->rx_buff_mgmt.size))) { 902 wil_err(wil, "Corrupt buff_id=%d, sring->swhead=%d\n", 903 buff_id, sring->swhead); 904 wil_rx_status_reset_buff_id(sring); 905 wil_sring_advance_swhead(sring); 906 sring->invalid_buff_id_cnt++; 907 goto again; 908 } 909 910 /* Extract the SKB from the rx_buff management array */ 911 skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb; 912 wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL; 913 if (!skb) { 914 wil_err(wil, "No Rx skb at buff_id %d\n", buff_id); 915 wil_rx_status_reset_buff_id(sring); 916 /* Move the buffer from the active list to the free list */ 917 list_move_tail(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 918 &wil->rx_buff_mgmt.free); 919 wil_sring_advance_swhead(sring); 920 sring->invalid_buff_id_cnt++; 921 goto again; 922 } 923 924 wil_rx_status_reset_buff_id(sring); 925 wil_sring_advance_swhead(sring); 926 927 memcpy(&pa, skb->cb, sizeof(pa)); 928 dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE); 929 dmalen = le16_to_cpu(wil_rx_status_get_length(msg)); 930 931 trace_wil6210_rx_status(wil, wil->use_compressed_rx_status, buff_id, 932 msg); 933 wil_dbg_txrx(wil, "Rx, buff_id=%u, sring_idx=%u, dmalen=%u bytes\n", 934 buff_id, sring_idx, dmalen); 935 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4, 936 (const void *)msg, wil->use_compressed_rx_status ? 937 sizeof(struct wil_rx_status_compressed) : 938 sizeof(struct wil_rx_status_extended), false); 939 940 /* Move the buffer from the active list to the free list */ 941 list_move_tail(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 942 &wil->rx_buff_mgmt.free); 943 944 eop = wil_rx_status_get_eop(msg); 945 946 cid = wil_rx_status_get_cid(msg); 947 if (unlikely(!wil_val_in_range(cid, 0, max_assoc_sta))) { 948 wil_err(wil, "Corrupt cid=%d, sring->swhead=%d\n", 949 cid, sring->swhead); 950 rxdata->skipping = true; 951 goto skipping; 952 } 953 stats = &wil->sta[cid].stats; 954 955 if (unlikely(skb->len < ETH_HLEN)) { 956 wil_dbg_txrx(wil, "Short frame, len = %d\n", skb->len); 957 stats->rx_short_frame++; 958 rxdata->skipping = true; 959 goto skipping; 960 } 961 962 if (unlikely(dmalen > sz)) { 963 wil_err(wil, "Rx size too large: %d bytes!\n", dmalen); 964 stats->rx_large_frame++; 965 rxdata->skipping = true; 966 } 967 968 skipping: 969 /* skipping indicates if a certain SKB should be dropped. 970 * It is set in case there is an error on the current SKB or in case 971 * of RX chaining: as long as we manage to merge the SKBs it will 972 * be false. once we have a bad SKB or we don't manage to merge SKBs 973 * it will be set to the !EOP value of the current SKB. 974 * This guarantees that all the following SKBs until EOP will also 975 * get dropped. 976 */ 977 if (unlikely(rxdata->skipping)) { 978 kfree_skb(skb); 979 if (rxdata->skb) { 980 kfree_skb(rxdata->skb); 981 rxdata->skb = NULL; 982 } 983 rxdata->skipping = !eop; 984 goto again; 985 } 986 987 skb_trim(skb, dmalen); 988 989 prefetch(skb->data); 990 991 if (!rxdata->skb) { 992 rxdata->skb = skb; 993 } else { 994 if (likely(skb_try_coalesce(rxdata->skb, skb, &headstolen, 995 &delta))) { 996 kfree_skb_partial(skb, headstolen); 997 } else { 998 wil_err(wil, "failed to merge skbs!\n"); 999 kfree_skb(skb); 1000 kfree_skb(rxdata->skb); 1001 rxdata->skb = NULL; 1002 rxdata->skipping = !eop; 1003 goto again; 1004 } 1005 } 1006 1007 if (!eop) 1008 goto again; 1009 1010 /* reaching here rxdata->skb always contains a full packet */ 1011 skb = rxdata->skb; 1012 rxdata->skb = NULL; 1013 rxdata->skipping = false; 1014 1015 if (stats) { 1016 stats->last_mcs_rx = wil_rx_status_get_mcs(msg); 1017 if (stats->last_mcs_rx < ARRAY_SIZE(stats->rx_per_mcs)) 1018 stats->rx_per_mcs[stats->last_mcs_rx]++; 1019 } 1020 1021 if (!wil->use_rx_hw_reordering && !wil->use_compressed_rx_status && 1022 wil_check_bar(wil, msg, cid, skb, stats) == -EAGAIN) { 1023 kfree_skb(skb); 1024 goto again; 1025 } 1026 1027 /* Compensate for the HW data alignment according to the status 1028 * message 1029 */ 1030 data_offset = wil_rx_status_get_data_offset(msg); 1031 if (data_offset == 0xFF || 1032 data_offset > WIL_EDMA_MAX_DATA_OFFSET) { 1033 wil_err(wil, "Unexpected data offset %d\n", data_offset); 1034 kfree_skb(skb); 1035 goto again; 1036 } 1037 1038 skb_pull(skb, data_offset); 1039 1040 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 1041 skb->data, skb_headlen(skb), false); 1042 1043 /* Has to be done after dma_unmap_single as skb->cb is also 1044 * used for holding the pa 1045 */ 1046 s = wil_skb_rxstatus(skb); 1047 memcpy(s, msg, sring->elem_size); 1048 1049 return skb; 1050 } 1051 1052 void wil_rx_handle_edma(struct wil6210_priv *wil, int *quota) 1053 { 1054 struct net_device *ndev; 1055 struct wil_ring *ring = &wil->ring_rx; 1056 struct wil_status_ring *sring; 1057 struct sk_buff *skb; 1058 int i; 1059 1060 if (unlikely(!ring->va)) { 1061 wil_err(wil, "Rx IRQ while Rx not yet initialized\n"); 1062 return; 1063 } 1064 wil_dbg_txrx(wil, "rx_handle\n"); 1065 1066 for (i = 0; i < wil->num_rx_status_rings; i++) { 1067 sring = &wil->srings[i]; 1068 if (unlikely(!sring->va)) { 1069 wil_err(wil, 1070 "Rx IRQ while Rx status ring %d not yet initialized\n", 1071 i); 1072 continue; 1073 } 1074 1075 while ((*quota > 0) && 1076 (NULL != (skb = 1077 wil_sring_reap_rx_edma(wil, sring)))) { 1078 (*quota)--; 1079 if (wil->use_rx_hw_reordering) { 1080 void *msg = wil_skb_rxstatus(skb); 1081 int mid = wil_rx_status_get_mid(msg); 1082 struct wil6210_vif *vif = wil->vifs[mid]; 1083 1084 if (unlikely(!vif)) { 1085 wil_dbg_txrx(wil, 1086 "RX desc invalid mid %d", 1087 mid); 1088 kfree_skb(skb); 1089 continue; 1090 } 1091 ndev = vif_to_ndev(vif); 1092 wil_netif_rx_any(skb, ndev); 1093 } else { 1094 wil_rx_reorder(wil, skb); 1095 } 1096 } 1097 1098 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size); 1099 } 1100 1101 wil_rx_refill_edma(wil); 1102 } 1103 1104 static int wil_tx_desc_map_edma(union wil_tx_desc *desc, 1105 dma_addr_t pa, 1106 u32 len, 1107 int ring_index) 1108 { 1109 struct wil_tx_enhanced_desc *d = 1110 (struct wil_tx_enhanced_desc *)&desc->enhanced; 1111 1112 memset(d, 0, sizeof(struct wil_tx_enhanced_desc)); 1113 1114 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa); 1115 1116 /* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/ 1117 d->dma.length = cpu_to_le16((u16)len); 1118 d->mac.d[0] = (ring_index << WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS); 1119 /* translation type: 0 - bypass; 1 - 802.3; 2 - native wifi; 1120 * 3 - eth mode 1121 */ 1122 d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) | 1123 (0x3 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS); 1124 1125 return 0; 1126 } 1127 1128 static inline void 1129 wil_get_next_tx_status_msg(struct wil_status_ring *sring, 1130 struct wil_ring_tx_status *msg) 1131 { 1132 struct wil_ring_tx_status *_msg = (struct wil_ring_tx_status *) 1133 (sring->va + (sring->elem_size * sring->swhead)); 1134 1135 *msg = *_msg; 1136 } 1137 1138 /** 1139 * Clean up transmitted skb's from the Tx descriptor RING. 1140 * Return number of descriptors cleared. 1141 */ 1142 int wil_tx_sring_handler(struct wil6210_priv *wil, 1143 struct wil_status_ring *sring) 1144 { 1145 struct net_device *ndev; 1146 struct device *dev = wil_to_dev(wil); 1147 struct wil_ring *ring = NULL; 1148 struct wil_ring_tx_data *txdata; 1149 /* Total number of completed descriptors in all descriptor rings */ 1150 int desc_cnt = 0; 1151 int cid; 1152 struct wil_net_stats *stats; 1153 struct wil_tx_enhanced_desc *_d; 1154 unsigned int ring_id; 1155 unsigned int num_descs; 1156 int i; 1157 u8 dr_bit; /* Descriptor Ready bit */ 1158 struct wil_ring_tx_status msg; 1159 struct wil6210_vif *vif; 1160 int used_before_complete; 1161 int used_new; 1162 1163 wil_get_next_tx_status_msg(sring, &msg); 1164 dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS; 1165 1166 /* Process completion messages while DR bit has the expected polarity */ 1167 while (dr_bit == sring->desc_rdy_pol) { 1168 num_descs = msg.num_descriptors; 1169 if (!num_descs) { 1170 wil_err(wil, "invalid num_descs 0\n"); 1171 goto again; 1172 } 1173 1174 /* Find the corresponding descriptor ring */ 1175 ring_id = msg.ring_id; 1176 1177 if (unlikely(ring_id >= WIL6210_MAX_TX_RINGS)) { 1178 wil_err(wil, "invalid ring id %d\n", ring_id); 1179 goto again; 1180 } 1181 ring = &wil->ring_tx[ring_id]; 1182 if (unlikely(!ring->va)) { 1183 wil_err(wil, "Tx irq[%d]: ring not initialized\n", 1184 ring_id); 1185 goto again; 1186 } 1187 txdata = &wil->ring_tx_data[ring_id]; 1188 if (unlikely(!txdata->enabled)) { 1189 wil_info(wil, "Tx irq[%d]: ring disabled\n", ring_id); 1190 goto again; 1191 } 1192 vif = wil->vifs[txdata->mid]; 1193 if (unlikely(!vif)) { 1194 wil_dbg_txrx(wil, "invalid MID %d for ring %d\n", 1195 txdata->mid, ring_id); 1196 goto again; 1197 } 1198 1199 ndev = vif_to_ndev(vif); 1200 1201 cid = wil->ring2cid_tid[ring_id][0]; 1202 stats = (cid < max_assoc_sta ? &wil->sta[cid].stats : NULL); 1203 1204 wil_dbg_txrx(wil, 1205 "tx_status: completed desc_ring (%d), num_descs (%d)\n", 1206 ring_id, num_descs); 1207 1208 used_before_complete = wil_ring_used_tx(ring); 1209 1210 for (i = 0 ; i < num_descs; ++i) { 1211 struct wil_ctx *ctx = &ring->ctx[ring->swtail]; 1212 struct wil_tx_enhanced_desc dd, *d = ⅆ 1213 u16 dmalen; 1214 struct sk_buff *skb = ctx->skb; 1215 1216 _d = (struct wil_tx_enhanced_desc *) 1217 &ring->va[ring->swtail].tx.enhanced; 1218 *d = *_d; 1219 1220 dmalen = le16_to_cpu(d->dma.length); 1221 trace_wil6210_tx_status(&msg, ring->swtail, dmalen); 1222 wil_dbg_txrx(wil, 1223 "TxC[%2d][%3d] : %d bytes, status 0x%02x\n", 1224 ring_id, ring->swtail, dmalen, 1225 msg.status); 1226 wil_hex_dump_txrx("TxS ", DUMP_PREFIX_NONE, 32, 4, 1227 (const void *)&msg, sizeof(msg), 1228 false); 1229 1230 wil_tx_desc_unmap_edma(dev, 1231 (union wil_tx_desc *)d, 1232 ctx); 1233 1234 if (skb) { 1235 if (likely(msg.status == 0)) { 1236 ndev->stats.tx_packets++; 1237 ndev->stats.tx_bytes += skb->len; 1238 if (stats) { 1239 stats->tx_packets++; 1240 stats->tx_bytes += skb->len; 1241 1242 wil_tx_latency_calc(wil, skb, 1243 &wil->sta[cid]); 1244 } 1245 } else { 1246 ndev->stats.tx_errors++; 1247 if (stats) 1248 stats->tx_errors++; 1249 } 1250 wil_consume_skb(skb, msg.status == 0); 1251 } 1252 memset(ctx, 0, sizeof(*ctx)); 1253 /* Make sure the ctx is zeroed before updating the tail 1254 * to prevent a case where wil_tx_ring will see 1255 * this descriptor as used and handle it before ctx zero 1256 * is completed. 1257 */ 1258 wmb(); 1259 1260 ring->swtail = wil_ring_next_tail(ring); 1261 1262 desc_cnt++; 1263 } 1264 1265 /* performance monitoring */ 1266 used_new = wil_ring_used_tx(ring); 1267 if (wil_val_in_range(wil->ring_idle_trsh, 1268 used_new, used_before_complete)) { 1269 wil_dbg_txrx(wil, "Ring[%2d] idle %d -> %d\n", 1270 ring_id, used_before_complete, used_new); 1271 txdata->last_idle = get_cycles(); 1272 } 1273 1274 again: 1275 wil_sring_advance_swhead(sring); 1276 1277 wil_get_next_tx_status_msg(sring, &msg); 1278 dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS; 1279 } 1280 1281 /* shall we wake net queues? */ 1282 if (desc_cnt) 1283 wil_update_net_queues(wil, vif, NULL, false); 1284 1285 /* Update the HW tail ptr (RD ptr) */ 1286 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size); 1287 1288 return desc_cnt; 1289 } 1290 1291 /** 1292 * Sets the descriptor @d up for csum and/or TSO offloading. The corresponding 1293 * @skb is used to obtain the protocol and headers length. 1294 * @tso_desc_type is a descriptor type for TSO: 0 - a header, 1 - first data, 1295 * 2 - middle, 3 - last descriptor. 1296 */ 1297 static void wil_tx_desc_offload_setup_tso_edma(struct wil_tx_enhanced_desc *d, 1298 int tso_desc_type, bool is_ipv4, 1299 int tcp_hdr_len, 1300 int skb_net_hdr_len, 1301 int mss) 1302 { 1303 /* Number of descriptors */ 1304 d->mac.d[2] |= 1; 1305 /* Maximum Segment Size */ 1306 d->mac.tso_mss |= cpu_to_le16(mss >> 2); 1307 /* L4 header len: TCP header length */ 1308 d->dma.l4_hdr_len |= tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK; 1309 /* EOP, TSO desc type, Segmentation enable, 1310 * Insert IPv4 and TCP / UDP Checksum 1311 */ 1312 d->dma.cmd |= BIT(WIL_EDMA_DESC_TX_CFG_EOP_POS) | 1313 tso_desc_type << WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_POS | 1314 BIT(WIL_EDMA_DESC_TX_CFG_SEG_EN_POS) | 1315 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS) | 1316 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS); 1317 /* Calculate pseudo-header */ 1318 d->dma.w1 |= BIT(WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS) | 1319 BIT(WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS); 1320 /* IP Header Length */ 1321 d->dma.ip_length |= skb_net_hdr_len; 1322 /* MAC header length and IP address family*/ 1323 d->dma.b11 |= ETH_HLEN | 1324 is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS; 1325 } 1326 1327 static int wil_tx_tso_gen_desc(struct wil6210_priv *wil, void *buff_addr, 1328 int len, uint i, int tso_desc_type, 1329 skb_frag_t *frag, struct wil_ring *ring, 1330 struct sk_buff *skb, bool is_ipv4, 1331 int tcp_hdr_len, int skb_net_hdr_len, 1332 int mss, int *descs_used) 1333 { 1334 struct device *dev = wil_to_dev(wil); 1335 struct wil_tx_enhanced_desc *_desc = (struct wil_tx_enhanced_desc *) 1336 &ring->va[i].tx.enhanced; 1337 struct wil_tx_enhanced_desc desc_mem, *d = &desc_mem; 1338 int ring_index = ring - wil->ring_tx; 1339 dma_addr_t pa; 1340 1341 if (len == 0) 1342 return 0; 1343 1344 if (!frag) { 1345 pa = dma_map_single(dev, buff_addr, len, DMA_TO_DEVICE); 1346 ring->ctx[i].mapped_as = wil_mapped_as_single; 1347 } else { 1348 pa = skb_frag_dma_map(dev, frag, 0, len, DMA_TO_DEVICE); 1349 ring->ctx[i].mapped_as = wil_mapped_as_page; 1350 } 1351 if (unlikely(dma_mapping_error(dev, pa))) { 1352 wil_err(wil, "TSO: Skb DMA map error\n"); 1353 return -EINVAL; 1354 } 1355 1356 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, pa, 1357 len, ring_index); 1358 wil_tx_desc_offload_setup_tso_edma(d, tso_desc_type, is_ipv4, 1359 tcp_hdr_len, 1360 skb_net_hdr_len, mss); 1361 1362 /* hold reference to skb 1363 * to prevent skb release before accounting 1364 * in case of immediate "tx done" 1365 */ 1366 if (tso_desc_type == wil_tso_type_lst) 1367 ring->ctx[i].skb = skb_get(skb); 1368 1369 wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4, 1370 (const void *)d, sizeof(*d), false); 1371 1372 *_desc = *d; 1373 (*descs_used)++; 1374 1375 return 0; 1376 } 1377 1378 static int __wil_tx_ring_tso_edma(struct wil6210_priv *wil, 1379 struct wil6210_vif *vif, 1380 struct wil_ring *ring, 1381 struct sk_buff *skb) 1382 { 1383 int ring_index = ring - wil->ring_tx; 1384 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index]; 1385 int nr_frags = skb_shinfo(skb)->nr_frags; 1386 int min_desc_required = nr_frags + 2; /* Headers, Head, Fragments */ 1387 int used, avail = wil_ring_avail_tx(ring); 1388 int f, hdrlen, headlen; 1389 int gso_type; 1390 bool is_ipv4; 1391 u32 swhead = ring->swhead; 1392 int descs_used = 0; /* total number of used descriptors */ 1393 int rc = -EINVAL; 1394 int tcp_hdr_len; 1395 int skb_net_hdr_len; 1396 int mss = skb_shinfo(skb)->gso_size; 1397 1398 wil_dbg_txrx(wil, "tx_ring_tso: %d bytes to ring %d\n", skb->len, 1399 ring_index); 1400 1401 if (unlikely(!txdata->enabled)) 1402 return -EINVAL; 1403 1404 if (unlikely(avail < min_desc_required)) { 1405 wil_err_ratelimited(wil, 1406 "TSO: Tx ring[%2d] full. No space for %d fragments\n", 1407 ring_index, min_desc_required); 1408 return -ENOMEM; 1409 } 1410 1411 gso_type = skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4); 1412 switch (gso_type) { 1413 case SKB_GSO_TCPV4: 1414 is_ipv4 = true; 1415 break; 1416 case SKB_GSO_TCPV6: 1417 is_ipv4 = false; 1418 break; 1419 default: 1420 return -EINVAL; 1421 } 1422 1423 if (skb->ip_summed != CHECKSUM_PARTIAL) 1424 return -EINVAL; 1425 1426 /* tcp header length and skb network header length are fixed for all 1427 * packet's descriptors - read them once here 1428 */ 1429 tcp_hdr_len = tcp_hdrlen(skb); 1430 skb_net_hdr_len = skb_network_header_len(skb); 1431 1432 /* First descriptor must contain the header only 1433 * Header Length = MAC header len + IP header len + TCP header len 1434 */ 1435 hdrlen = ETH_HLEN + tcp_hdr_len + skb_net_hdr_len; 1436 wil_dbg_txrx(wil, "TSO: process header descriptor, hdrlen %u\n", 1437 hdrlen); 1438 rc = wil_tx_tso_gen_desc(wil, skb->data, hdrlen, swhead, 1439 wil_tso_type_hdr, NULL, ring, skb, 1440 is_ipv4, tcp_hdr_len, skb_net_hdr_len, 1441 mss, &descs_used); 1442 if (rc) 1443 return -EINVAL; 1444 1445 /* Second descriptor contains the head */ 1446 headlen = skb_headlen(skb) - hdrlen; 1447 wil_dbg_txrx(wil, "TSO: process skb head, headlen %u\n", headlen); 1448 rc = wil_tx_tso_gen_desc(wil, skb->data + hdrlen, headlen, 1449 (swhead + descs_used) % ring->size, 1450 (nr_frags != 0) ? wil_tso_type_first : 1451 wil_tso_type_lst, NULL, ring, skb, 1452 is_ipv4, tcp_hdr_len, skb_net_hdr_len, 1453 mss, &descs_used); 1454 if (rc) 1455 goto mem_error; 1456 1457 /* Rest of the descriptors are from the SKB fragments */ 1458 for (f = 0; f < nr_frags; f++) { 1459 skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 1460 int len = frag->size; 1461 1462 wil_dbg_txrx(wil, "TSO: frag[%d]: len %u, descs_used %d\n", f, 1463 len, descs_used); 1464 1465 rc = wil_tx_tso_gen_desc(wil, NULL, len, 1466 (swhead + descs_used) % ring->size, 1467 (f != nr_frags - 1) ? 1468 wil_tso_type_mid : wil_tso_type_lst, 1469 frag, ring, skb, is_ipv4, 1470 tcp_hdr_len, skb_net_hdr_len, 1471 mss, &descs_used); 1472 if (rc) 1473 goto mem_error; 1474 } 1475 1476 /* performance monitoring */ 1477 used = wil_ring_used_tx(ring); 1478 if (wil_val_in_range(wil->ring_idle_trsh, 1479 used, used + descs_used)) { 1480 txdata->idle += get_cycles() - txdata->last_idle; 1481 wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n", 1482 ring_index, used, used + descs_used); 1483 } 1484 1485 /* advance swhead */ 1486 wil_ring_advance_head(ring, descs_used); 1487 wil_dbg_txrx(wil, "TSO: Tx swhead %d -> %d\n", swhead, ring->swhead); 1488 1489 /* make sure all writes to descriptors (shared memory) are done before 1490 * committing them to HW 1491 */ 1492 wmb(); 1493 1494 if (wil->tx_latency) 1495 *(ktime_t *)&skb->cb = ktime_get(); 1496 else 1497 memset(skb->cb, 0, sizeof(ktime_t)); 1498 1499 wil_w(wil, ring->hwtail, ring->swhead); 1500 1501 return 0; 1502 1503 mem_error: 1504 while (descs_used > 0) { 1505 struct device *dev = wil_to_dev(wil); 1506 struct wil_ctx *ctx; 1507 int i = (swhead + descs_used - 1) % ring->size; 1508 struct wil_tx_enhanced_desc dd, *d = ⅆ 1509 struct wil_tx_enhanced_desc *_desc = 1510 (struct wil_tx_enhanced_desc *) 1511 &ring->va[i].tx.enhanced; 1512 1513 *d = *_desc; 1514 ctx = &ring->ctx[i]; 1515 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx); 1516 memset(ctx, 0, sizeof(*ctx)); 1517 descs_used--; 1518 } 1519 return rc; 1520 } 1521 1522 static int wil_ring_init_bcast_edma(struct wil6210_vif *vif, int ring_id, 1523 int size) 1524 { 1525 struct wil6210_priv *wil = vif_to_wil(vif); 1526 struct wil_ring *ring = &wil->ring_tx[ring_id]; 1527 int rc; 1528 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 1529 1530 wil_dbg_misc(wil, "init bcast: ring_id=%d, sring_id=%d\n", 1531 ring_id, wil->tx_sring_idx); 1532 1533 lockdep_assert_held(&wil->mutex); 1534 1535 wil_tx_data_init(txdata); 1536 ring->size = size; 1537 ring->is_rx = false; 1538 rc = wil_ring_alloc_desc_ring(wil, ring); 1539 if (rc) 1540 goto out; 1541 1542 wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; /* CID */ 1543 wil->ring2cid_tid[ring_id][1] = 0; /* TID */ 1544 if (!vif->privacy) 1545 txdata->dot1x_open = true; 1546 1547 rc = wil_wmi_bcast_desc_ring_add(vif, ring_id); 1548 if (rc) 1549 goto out_free; 1550 1551 return 0; 1552 1553 out_free: 1554 spin_lock_bh(&txdata->lock); 1555 txdata->enabled = 0; 1556 txdata->dot1x_open = false; 1557 spin_unlock_bh(&txdata->lock); 1558 wil_ring_free_edma(wil, ring); 1559 1560 out: 1561 return rc; 1562 } 1563 1564 static void wil_tx_fini_edma(struct wil6210_priv *wil) 1565 { 1566 struct wil_status_ring *sring = &wil->srings[wil->tx_sring_idx]; 1567 1568 wil_dbg_misc(wil, "free TX sring\n"); 1569 1570 wil_sring_free(wil, sring); 1571 } 1572 1573 static void wil_rx_data_free(struct wil_status_ring *sring) 1574 { 1575 if (!sring) 1576 return; 1577 1578 kfree_skb(sring->rx_data.skb); 1579 sring->rx_data.skb = NULL; 1580 } 1581 1582 static void wil_rx_fini_edma(struct wil6210_priv *wil) 1583 { 1584 struct wil_ring *ring = &wil->ring_rx; 1585 int i; 1586 1587 wil_dbg_misc(wil, "rx_fini_edma\n"); 1588 1589 wil_ring_free_edma(wil, ring); 1590 1591 for (i = 0; i < wil->num_rx_status_rings; i++) { 1592 wil_rx_data_free(&wil->srings[i]); 1593 wil_sring_free(wil, &wil->srings[i]); 1594 } 1595 1596 wil_free_rx_buff_arr(wil); 1597 } 1598 1599 void wil_init_txrx_ops_edma(struct wil6210_priv *wil) 1600 { 1601 wil->txrx_ops.configure_interrupt_moderation = 1602 wil_configure_interrupt_moderation_edma; 1603 /* TX ops */ 1604 wil->txrx_ops.ring_init_tx = wil_ring_init_tx_edma; 1605 wil->txrx_ops.ring_fini_tx = wil_ring_free_edma; 1606 wil->txrx_ops.ring_init_bcast = wil_ring_init_bcast_edma; 1607 wil->txrx_ops.tx_init = wil_tx_init_edma; 1608 wil->txrx_ops.tx_fini = wil_tx_fini_edma; 1609 wil->txrx_ops.tx_desc_map = wil_tx_desc_map_edma; 1610 wil->txrx_ops.tx_desc_unmap = wil_tx_desc_unmap_edma; 1611 wil->txrx_ops.tx_ring_tso = __wil_tx_ring_tso_edma; 1612 wil->txrx_ops.tx_ring_modify = wil_tx_ring_modify_edma; 1613 /* RX ops */ 1614 wil->txrx_ops.rx_init = wil_rx_init_edma; 1615 wil->txrx_ops.wmi_addba_rx_resp = wmi_addba_rx_resp_edma; 1616 wil->txrx_ops.get_reorder_params = wil_get_reorder_params_edma; 1617 wil->txrx_ops.get_netif_rx_params = wil_get_netif_rx_params_edma; 1618 wil->txrx_ops.rx_crypto_check = wil_rx_crypto_check_edma; 1619 wil->txrx_ops.rx_error_check = wil_rx_error_check_edma; 1620 wil->txrx_ops.is_rx_idle = wil_is_rx_idle_edma; 1621 wil->txrx_ops.rx_fini = wil_rx_fini_edma; 1622 } 1623 1624