1 /* 2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __WIL6210_H__ 19 #define __WIL6210_H__ 20 21 #include <linux/etherdevice.h> 22 #include <linux/netdevice.h> 23 #include <linux/wireless.h> 24 #include <net/cfg80211.h> 25 #include <linux/timex.h> 26 #include <linux/types.h> 27 #include <linux/irqreturn.h> 28 #include "wmi.h" 29 #include "wil_platform.h" 30 #include "fw.h" 31 32 extern bool no_fw_recovery; 33 extern unsigned int mtu_max; 34 extern unsigned short rx_ring_overflow_thrsh; 35 extern int agg_wsize; 36 extern bool rx_align_2; 37 extern bool rx_large_buf; 38 extern bool debug_fw; 39 extern bool disable_ap_sme; 40 extern bool ftm_mode; 41 extern bool drop_if_ring_full; 42 extern uint max_assoc_sta; 43 44 struct wil6210_priv; 45 struct wil6210_vif; 46 union wil_tx_desc; 47 48 #define WIL_NAME "wil6210" 49 50 #define WIL_FW_NAME_DEFAULT "wil6210.fw" 51 #define WIL_FW_NAME_FTM_DEFAULT "wil6210_ftm.fw" 52 53 #define WIL_FW_NAME_SPARROW_PLUS "wil6210_sparrow_plus.fw" 54 #define WIL_FW_NAME_FTM_SPARROW_PLUS "wil6210_sparrow_plus_ftm.fw" 55 56 #define WIL_FW_NAME_TALYN "wil6436.fw" 57 #define WIL_FW_NAME_FTM_TALYN "wil6436_ftm.fw" 58 #define WIL_BRD_NAME_TALYN "wil6436.brd" 59 60 #define WIL_BOARD_FILE_NAME "wil6210.brd" /* board & radio parameters */ 61 62 #define WIL_DEFAULT_BUS_REQUEST_KBPS 128000 /* ~1Gbps */ 63 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */ 64 65 #define WIL_NUM_LATENCY_BINS 200 66 67 /* maximum number of virtual interfaces the driver supports 68 * (including the main interface) 69 */ 70 #define WIL_MAX_VIFS 4 71 72 /** 73 * extract bits [@b0:@b1] (inclusive) from the value @x 74 * it should be @b0 <= @b1, or result is incorrect 75 */ 76 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 77 { 78 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 79 } 80 81 #define WIL6210_MIN_MEM_SIZE (2 * 1024 * 1024UL) 82 #define WIL6210_MAX_MEM_SIZE (4 * 1024 * 1024UL) 83 84 #define WIL_TX_Q_LEN_DEFAULT (4000) 85 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (10) 86 #define WIL_RX_RING_SIZE_ORDER_TALYN_DEFAULT (11) 87 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (12) 88 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7) 89 #define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */ 90 /* limit ring size in range [32..32k] */ 91 #define WIL_RING_SIZE_ORDER_MIN (5) 92 #define WIL_RING_SIZE_ORDER_MAX (15) 93 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 94 #define WIL6210_MAX_CID (20) /* max number of stations */ 95 #define WIL6210_RX_DESC_MAX_CID (8) /* HW limit */ 96 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 97 #define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */ 98 #define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */ 99 #define WIL_MAX_AMPDU_SIZE_128 (128 * 1024) /* FW/HW limit */ 100 #define WIL_MAX_AGG_WSIZE_64 (64) /* FW/HW limit */ 101 #define WIL6210_MAX_STATUS_RINGS (8) 102 103 /* Hardware offload block adds the following: 104 * 26 bytes - 3-address QoS data header 105 * 8 bytes - IV + EIV (for GCMP) 106 * 8 bytes - SNAP 107 * 16 bytes - MIC (for GCMP) 108 * 4 bytes - CRC 109 */ 110 #define WIL_MAX_MPDU_OVERHEAD (62) 111 112 struct wil_suspend_count_stats { 113 unsigned long successful_suspends; 114 unsigned long successful_resumes; 115 unsigned long failed_suspends; 116 unsigned long failed_resumes; 117 }; 118 119 struct wil_suspend_stats { 120 struct wil_suspend_count_stats r_off; 121 struct wil_suspend_count_stats r_on; 122 unsigned long rejected_by_device; /* only radio on */ 123 unsigned long rejected_by_host; 124 }; 125 126 /* Calculate MAC buffer size for the firmware. It includes all overhead, 127 * as it will go over the air, and need to be 8 byte aligned 128 */ 129 static inline u32 wil_mtu2macbuf(u32 mtu) 130 { 131 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8); 132 } 133 134 /* MTU for Ethernet need to take into account 8-byte SNAP header 135 * to be added when encapsulating Ethernet frame into 802.11 136 */ 137 #define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8) 138 /* Max supported by wil6210 value for interrupt threshold is 5sec. */ 139 #define WIL6210_ITR_TRSH_MAX (5000000) 140 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 141 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 142 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 143 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 144 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */ 145 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000) 146 #define WIL6210_SCAN_TO msecs_to_jiffies(10000) 147 #define WIL6210_DISCONNECT_TO_MS (2000) 148 #define WIL6210_RX_HIGH_TRSH_INIT (0) 149 #define WIL6210_RX_HIGH_TRSH_DEFAULT \ 150 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3)) 151 #define WIL_MAX_DMG_AID 254 /* for DMG only 1-254 allowed (see 152 * 802.11REVmc/D5.0, section 9.4.1.8) 153 */ 154 /* Hardware definitions begin */ 155 156 /* 157 * Mapping 158 * RGF File | Host addr | FW addr 159 * | | 160 * user_rgf | 0x000000 | 0x880000 161 * dma_rgf | 0x001000 | 0x881000 162 * pcie_rgf | 0x002000 | 0x882000 163 * | | 164 */ 165 166 /* Where various structures placed in host address space */ 167 #define WIL6210_FW_HOST_OFF (0x880000UL) 168 169 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 170 171 /* 172 * Interrupt control registers block 173 * 174 * each interrupt controlled by the same bit in all registers 175 */ 176 struct RGF_ICR { 177 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 178 u32 ICR; /* Cause, W1C/COR depending on ICC */ 179 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 180 u32 ICS; /* Cause Set, WO */ 181 u32 IMV; /* Mask, RW+S/C */ 182 u32 IMS; /* Mask Set, write 1 to set */ 183 u32 IMC; /* Mask Clear, write 1 to clear */ 184 } __packed; 185 186 /* registers - FW addresses */ 187 #define RGF_USER_USAGE_1 (0x880004) 188 #define RGF_USER_USAGE_2 (0x880008) 189 #define RGF_USER_USAGE_6 (0x880018) 190 #define BIT_USER_OOB_MODE BIT(31) 191 #define BIT_USER_OOB_R2_MODE BIT(30) 192 #define RGF_USER_USAGE_8 (0x880020) 193 #define BIT_USER_PREVENT_DEEP_SLEEP BIT(0) 194 #define BIT_USER_SUPPORT_T_POWER_ON_0 BIT(1) 195 #define BIT_USER_EXT_CLK BIT(2) 196 #define RGF_USER_HW_MACHINE_STATE (0x8801dc) 197 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 198 #define RGF_USER_USER_CPU_0 (0x8801e0) 199 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ 200 #define RGF_USER_CPU_PC (0x8801e8) 201 #define RGF_USER_MAC_CPU_0 (0x8801fc) 202 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ 203 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 204 #define RGF_USER_BL (0x880A3C) /* Boot Loader */ 205 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 206 #define RGF_USER_FW_CALIB_RESULT (0x880a90) /* b0-7:result 207 * b8-15:signature 208 */ 209 #define CALIB_RESULT_SIGNATURE (0x11) 210 #define RGF_USER_CLKS_CTL_0 (0x880abc) 211 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ 212 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 213 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 214 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 215 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 216 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 217 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 218 #define BIT_HPAL_PERST_FROM_PAD BIT(6) 219 #define BIT_CAR_PERST_RST BIT(7) 220 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 221 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 222 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18) 223 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c) 224 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ 225 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) 226 #define RGF_USER_OTP_HW_RD_MACHINE_1 (0x880ce0) 227 #define BIT_OTP_SIGNATURE_ERR_TALYN_MB BIT(0) 228 #define BIT_OTP_HW_SECTION_DONE_TALYN_MB BIT(2) 229 #define BIT_NO_FLASH_INDICATION BIT(8) 230 #define RGF_USER_XPM_IFC_RD_TIME1 (0x880cec) 231 #define RGF_USER_XPM_IFC_RD_TIME2 (0x880cf0) 232 #define RGF_USER_XPM_IFC_RD_TIME3 (0x880cf4) 233 #define RGF_USER_XPM_IFC_RD_TIME4 (0x880cf8) 234 #define RGF_USER_XPM_IFC_RD_TIME5 (0x880cfc) 235 #define RGF_USER_XPM_IFC_RD_TIME6 (0x880d00) 236 #define RGF_USER_XPM_IFC_RD_TIME7 (0x880d04) 237 #define RGF_USER_XPM_IFC_RD_TIME8 (0x880d08) 238 #define RGF_USER_XPM_IFC_RD_TIME9 (0x880d0c) 239 #define RGF_USER_XPM_IFC_RD_TIME10 (0x880d10) 240 #define RGF_USER_XPM_RD_DOUT_SAMPLE_TIME (0x880d64) 241 242 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 243 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 244 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 245 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 246 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 247 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) 248 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 249 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 250 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 251 #define BIT_DMA_EP_MISC_ICR_HALP BIT(27) 252 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 253 254 /* Legacy interrupt moderation control (before Sparrow v2)*/ 255 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 256 #define RGF_DMA_ITR_CNT_DATA (0x881c60) 257 #define RGF_DMA_ITR_CNT_CRL (0x881c64) 258 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 259 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 260 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 261 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 262 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 263 264 /* Offload control (Sparrow B0+) */ 265 #define RGF_DMA_OFUL_NID_0 (0x881cd4) 266 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0) 267 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1) 268 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2) 269 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3) 270 271 /* New (sparrow v2+) interrupt moderation control */ 272 #define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40) 273 #define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34) 274 #define RGF_DMA_ITR_TX_CNT_DATA (0x881d38) 275 #define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c) 276 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0) 277 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1) 278 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2) 279 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3) 280 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4) 281 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5) 282 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6) 283 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60) 284 #define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64) 285 #define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68) 286 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0) 287 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 288 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2) 289 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3) 290 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 291 #define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50) 292 #define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44) 293 #define RGF_DMA_ITR_RX_CNT_DATA (0x881d48) 294 #define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c) 295 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0) 296 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1) 297 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2) 298 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3) 299 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4) 300 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5) 301 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6) 302 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54) 303 #define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58) 304 #define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c) 305 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0) 306 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 307 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) 308 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) 309 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 310 #define RGF_DMA_MISC_CTL (0x881d6c) 311 #define BIT_OFUL34_RDY_VALID_BUG_FIX_EN BIT(7) 312 313 #define RGF_DMA_PSEUDO_CAUSE (0x881c68) 314 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 315 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 316 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 317 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 318 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 319 320 #define RGF_HP_CTRL (0x88265c) 321 #define RGF_PAL_UNIT_ICR (0x88266c) /* struct RGF_ICR */ 322 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 323 324 /* MAC timer, usec, for packet lifetime */ 325 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8) 326 327 #define RGF_CAF_ICR_TALYN_MB (0x8893d4) /* struct RGF_ICR */ 328 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */ 329 #define RGF_CAF_OSC_CONTROL (0x88afa4) 330 #define BIT_CAF_OSC_XTAL_EN BIT(0) 331 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec) 332 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) 333 334 #define RGF_OTP_QC_SECURED (0x8a0038) 335 #define BIT_BOOT_FROM_ROM BIT(31) 336 337 /* eDMA */ 338 #define RGF_INT_COUNT_ON_SPECIAL_EVT (0x8b62d8) 339 340 #define RGF_INT_CTRL_INT_GEN_CFG_0 (0x8bc000) 341 #define RGF_INT_CTRL_INT_GEN_CFG_1 (0x8bc004) 342 #define RGF_INT_GEN_TIME_UNIT_LIMIT (0x8bc0c8) 343 344 #define RGF_INT_GEN_CTRL (0x8bc0ec) 345 #define BIT_CONTROL_0 BIT(0) 346 347 /* eDMA status interrupts */ 348 #define RGF_INT_GEN_RX_ICR (0x8bc0f4) 349 #define BIT_RX_STATUS_IRQ BIT(WIL_RX_STATUS_IRQ_IDX) 350 #define RGF_INT_GEN_TX_ICR (0x8bc110) 351 #define BIT_TX_STATUS_IRQ BIT(WIL_TX_STATUS_IRQ_IDX) 352 #define RGF_INT_CTRL_RX_INT_MASK (0x8bc12c) 353 #define RGF_INT_CTRL_TX_INT_MASK (0x8bc130) 354 355 #define RGF_INT_GEN_IDLE_TIME_LIMIT (0x8bc134) 356 357 #define USER_EXT_USER_PMU_3 (0x88d00c) 358 #define BIT_PMU_DEVICE_RDY BIT(0) 359 360 #define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */ 361 #define JTAG_DEV_ID_SPARROW (0x2632072f) 362 #define JTAG_DEV_ID_TALYN (0x7e0e1) 363 #define JTAG_DEV_ID_TALYN_MB (0x1007e0e1) 364 365 #define RGF_USER_REVISION_ID (0x88afe4) 366 #define RGF_USER_REVISION_ID_MASK (3) 367 #define REVISION_ID_SPARROW_B0 (0x0) 368 #define REVISION_ID_SPARROW_D0 (0x3) 369 370 #define RGF_OTP_MAC_TALYN_MB (0x8a0304) 371 #define RGF_OTP_OEM_MAC (0x8a0334) 372 #define RGF_OTP_MAC (0x8a0620) 373 374 /* Talyn-MB */ 375 #define RGF_USER_USER_CPU_0_TALYN_MB (0x8c0138) 376 #define RGF_USER_MAC_CPU_0_TALYN_MB (0x8c0154) 377 378 /* crash codes for FW/Ucode stored here */ 379 380 /* ASSERT RGFs */ 381 #define SPARROW_RGF_FW_ASSERT_CODE (0x91f020) 382 #define SPARROW_RGF_UCODE_ASSERT_CODE (0x91f028) 383 #define TALYN_RGF_FW_ASSERT_CODE (0xa37020) 384 #define TALYN_RGF_UCODE_ASSERT_CODE (0xa37028) 385 386 enum { 387 HW_VER_UNKNOWN, 388 HW_VER_SPARROW_B0, /* REVISION_ID_SPARROW_B0 */ 389 HW_VER_SPARROW_D0, /* REVISION_ID_SPARROW_D0 */ 390 HW_VER_TALYN, /* JTAG_DEV_ID_TALYN */ 391 HW_VER_TALYN_MB /* JTAG_DEV_ID_TALYN_MB */ 392 }; 393 394 /* popular locations */ 395 #define RGF_MBOX RGF_USER_USER_SCRATCH_PAD 396 #define HOST_MBOX HOSTADDR(RGF_MBOX) 397 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 398 399 /* ISR register bits */ 400 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 401 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 402 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 403 404 #define WIL_DATA_COMPLETION_TO_MS 200 405 406 /* Hardware definitions end */ 407 #define SPARROW_FW_MAPPING_TABLE_SIZE 10 408 #define TALYN_FW_MAPPING_TABLE_SIZE 13 409 #define TALYN_MB_FW_MAPPING_TABLE_SIZE 19 410 #define MAX_FW_MAPPING_TABLE_SIZE 19 411 412 /* Common representation of physical address in wil ring */ 413 struct wil_ring_dma_addr { 414 __le32 addr_low; 415 __le16 addr_high; 416 } __packed; 417 418 struct fw_map { 419 u32 from; /* linker address - from, inclusive */ 420 u32 to; /* linker address - to, exclusive */ 421 u32 host; /* PCI/Host address - BAR0 + 0x880000 */ 422 const char *name; /* for debugfs */ 423 bool fw; /* true if FW mapping, false if UCODE mapping */ 424 bool crash_dump; /* true if should be dumped during crash dump */ 425 }; 426 427 /* array size should be in sync with actual definition in the wmi.c */ 428 extern const struct fw_map sparrow_fw_mapping[SPARROW_FW_MAPPING_TABLE_SIZE]; 429 extern const struct fw_map sparrow_d0_mac_rgf_ext; 430 extern const struct fw_map talyn_fw_mapping[TALYN_FW_MAPPING_TABLE_SIZE]; 431 extern const struct fw_map talyn_mb_fw_mapping[TALYN_MB_FW_MAPPING_TABLE_SIZE]; 432 extern struct fw_map fw_mapping[MAX_FW_MAPPING_TABLE_SIZE]; 433 434 /** 435 * mk_cidxtid - construct @cidxtid field 436 * @cid: CID value 437 * @tid: TID value 438 * 439 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 440 */ 441 static inline u8 mk_cidxtid(u8 cid, u8 tid) 442 { 443 return ((tid & 0xf) << 4) | (cid & 0xf); 444 } 445 446 /** 447 * parse_cidxtid - parse @cidxtid field 448 * @cid: store CID value here 449 * @tid: store TID value here 450 * 451 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 452 */ 453 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 454 { 455 *cid = cidxtid & 0xf; 456 *tid = (cidxtid >> 4) & 0xf; 457 } 458 459 /** 460 * wil_cid_valid - check cid is valid 461 * @cid: CID value 462 */ 463 static inline bool wil_cid_valid(u8 cid) 464 { 465 return (cid >= 0 && cid < max_assoc_sta); 466 } 467 468 struct wil6210_mbox_ring { 469 u32 base; 470 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 471 u16 size; 472 u32 tail; 473 u32 head; 474 } __packed; 475 476 struct wil6210_mbox_ring_desc { 477 __le32 sync; 478 __le32 addr; 479 } __packed; 480 481 /* at HOST_OFF_WIL6210_MBOX_CTL */ 482 struct wil6210_mbox_ctl { 483 struct wil6210_mbox_ring tx; 484 struct wil6210_mbox_ring rx; 485 } __packed; 486 487 struct wil6210_mbox_hdr { 488 __le16 seq; 489 __le16 len; /* payload, bytes after this header */ 490 __le16 type; 491 u8 flags; 492 u8 reserved; 493 } __packed; 494 495 #define WIL_MBOX_HDR_TYPE_WMI (0) 496 497 /* max. value for wil6210_mbox_hdr.len */ 498 #define MAX_MBOXITEM_SIZE (240) 499 500 struct pending_wmi_event { 501 struct list_head list; 502 struct { 503 struct wil6210_mbox_hdr hdr; 504 struct wmi_cmd_hdr wmi; 505 u8 data[0]; 506 } __packed event; 507 }; 508 509 enum { /* for wil_ctx.mapped_as */ 510 wil_mapped_as_none = 0, 511 wil_mapped_as_single = 1, 512 wil_mapped_as_page = 2, 513 }; 514 515 /** 516 * struct wil_ctx - software context for ring descriptor 517 */ 518 struct wil_ctx { 519 struct sk_buff *skb; 520 u8 nr_frags; 521 u8 mapped_as; 522 }; 523 524 struct wil_desc_ring_rx_swtail { /* relevant for enhanced DMA only */ 525 u32 *va; 526 dma_addr_t pa; 527 }; 528 529 /** 530 * A general ring structure, used for RX and TX. 531 * In legacy DMA it represents the vring, 532 * In enahnced DMA it represents the descriptor ring (vrings are handled by FW) 533 */ 534 struct wil_ring { 535 dma_addr_t pa; 536 volatile union wil_ring_desc *va; 537 u16 size; /* number of wil_ring_desc elements */ 538 u32 swtail; 539 u32 swhead; 540 u32 hwtail; /* write here to inform hw */ 541 struct wil_ctx *ctx; /* ctx[size] - software context */ 542 struct wil_desc_ring_rx_swtail edma_rx_swtail; 543 bool is_rx; 544 }; 545 546 /** 547 * Additional data for Rx ring. 548 * Used for enhanced DMA RX chaining. 549 */ 550 struct wil_ring_rx_data { 551 /* the skb being assembled */ 552 struct sk_buff *skb; 553 /* true if we are skipping a bad fragmented packet */ 554 bool skipping; 555 u16 buff_size; 556 }; 557 558 /** 559 * Status ring structure, used for enhanced DMA completions for RX and TX. 560 */ 561 struct wil_status_ring { 562 dma_addr_t pa; 563 void *va; /* pointer to ring_[tr]x_status elements */ 564 u16 size; /* number of status elements */ 565 size_t elem_size; /* status element size in bytes */ 566 u32 swhead; 567 u32 hwtail; /* write here to inform hw */ 568 bool is_rx; 569 u8 desc_rdy_pol; /* Expected descriptor ready bit polarity */ 570 struct wil_ring_rx_data rx_data; 571 u32 invalid_buff_id_cnt; /* relevant only for RX */ 572 }; 573 574 #define WIL_STA_TID_NUM (16) 575 #define WIL_MCS_MAX (15) /* Maximum MCS supported */ 576 577 struct wil_net_stats { 578 unsigned long rx_packets; 579 unsigned long tx_packets; 580 unsigned long rx_bytes; 581 unsigned long tx_bytes; 582 unsigned long tx_errors; 583 u32 tx_latency_min_us; 584 u32 tx_latency_max_us; 585 u64 tx_latency_total_us; 586 unsigned long rx_dropped; 587 unsigned long rx_non_data_frame; 588 unsigned long rx_short_frame; 589 unsigned long rx_large_frame; 590 unsigned long rx_replay; 591 unsigned long rx_mic_error; 592 unsigned long rx_key_error; /* eDMA specific */ 593 unsigned long rx_amsdu_error; /* eDMA specific */ 594 unsigned long rx_csum_err; 595 u16 last_mcs_rx; 596 u64 rx_per_mcs[WIL_MCS_MAX + 1]; 597 u32 ft_roams; /* relevant in STA mode */ 598 }; 599 600 /** 601 * struct tx_rx_ops - different TX/RX ops for legacy and enhanced 602 * DMA flow 603 */ 604 struct wil_txrx_ops { 605 void (*configure_interrupt_moderation)(struct wil6210_priv *wil); 606 /* TX ops */ 607 int (*ring_init_tx)(struct wil6210_vif *vif, int ring_id, 608 int size, int cid, int tid); 609 void (*ring_fini_tx)(struct wil6210_priv *wil, struct wil_ring *ring); 610 int (*ring_init_bcast)(struct wil6210_vif *vif, int id, int size); 611 int (*tx_init)(struct wil6210_priv *wil); 612 void (*tx_fini)(struct wil6210_priv *wil); 613 int (*tx_desc_map)(union wil_tx_desc *desc, dma_addr_t pa, 614 u32 len, int ring_index); 615 void (*tx_desc_unmap)(struct device *dev, 616 union wil_tx_desc *desc, 617 struct wil_ctx *ctx); 618 int (*tx_ring_tso)(struct wil6210_priv *wil, struct wil6210_vif *vif, 619 struct wil_ring *ring, struct sk_buff *skb); 620 int (*tx_ring_modify)(struct wil6210_vif *vif, int ring_id, 621 int cid, int tid); 622 irqreturn_t (*irq_tx)(int irq, void *cookie); 623 /* RX ops */ 624 int (*rx_init)(struct wil6210_priv *wil, uint ring_order); 625 void (*rx_fini)(struct wil6210_priv *wil); 626 int (*wmi_addba_rx_resp)(struct wil6210_priv *wil, u8 mid, u8 cid, 627 u8 tid, u8 token, u16 status, bool amsdu, 628 u16 agg_wsize, u16 timeout); 629 void (*get_reorder_params)(struct wil6210_priv *wil, 630 struct sk_buff *skb, int *tid, int *cid, 631 int *mid, u16 *seq, int *mcast, int *retry); 632 void (*get_netif_rx_params)(struct sk_buff *skb, 633 int *cid, int *security); 634 int (*rx_crypto_check)(struct wil6210_priv *wil, struct sk_buff *skb); 635 int (*rx_error_check)(struct wil6210_priv *wil, struct sk_buff *skb, 636 struct wil_net_stats *stats); 637 bool (*is_rx_idle)(struct wil6210_priv *wil); 638 irqreturn_t (*irq_rx)(int irq, void *cookie); 639 }; 640 641 /** 642 * Additional data for Tx ring 643 */ 644 struct wil_ring_tx_data { 645 bool dot1x_open; 646 int enabled; 647 cycles_t idle, last_idle, begin; 648 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */ 649 u16 agg_timeout; 650 u8 agg_amsdu; 651 bool addba_in_progress; /* if set, agg_xxx is for request in progress */ 652 u8 mid; 653 spinlock_t lock; 654 }; 655 656 enum { /* for wil6210_priv.status */ 657 wil_status_fwready = 0, /* FW operational */ 658 wil_status_dontscan, 659 wil_status_mbox_ready, /* MBOX structures ready */ 660 wil_status_irqen, /* interrupts enabled - for debug */ 661 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 662 wil_status_resetting, /* reset in progress */ 663 wil_status_suspending, /* suspend in progress */ 664 wil_status_suspended, /* suspend completed, device is suspended */ 665 wil_status_resuming, /* resume in progress */ 666 wil_status_last /* keep last */ 667 }; 668 669 struct pci_dev; 670 671 /** 672 * struct tid_ampdu_rx - TID aggregation information (Rx). 673 * 674 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 675 * @last_rx: jiffies of last rx activity 676 * @head_seq_num: head sequence number in reordering buffer. 677 * @stored_mpdu_num: number of MPDUs in reordering buffer 678 * @ssn: Starting Sequence Number expected to be aggregated. 679 * @buf_size: buffer size for incoming A-MPDUs 680 * @ssn_last_drop: SSN of the last dropped frame 681 * @total: total number of processed incoming frames 682 * @drop_dup: duplicate frames dropped for this reorder buffer 683 * @drop_old: old frames dropped for this reorder buffer 684 * @first_time: true when this buffer used 1-st time 685 * @mcast_last_seq: sequence number (SN) of last received multicast packet 686 * @drop_dup_mcast: duplicate multicast frames dropped for this reorder buffer 687 */ 688 struct wil_tid_ampdu_rx { 689 struct sk_buff **reorder_buf; 690 unsigned long last_rx; 691 u16 head_seq_num; 692 u16 stored_mpdu_num; 693 u16 ssn; 694 u16 buf_size; 695 u16 ssn_last_drop; 696 unsigned long long total; /* frames processed */ 697 unsigned long long drop_dup; 698 unsigned long long drop_old; 699 bool first_time; /* is it 1-st time this buffer used? */ 700 u16 mcast_last_seq; /* multicast dup detection */ 701 unsigned long long drop_dup_mcast; 702 }; 703 704 /** 705 * struct wil_tid_crypto_rx_single - TID crypto information (Rx). 706 * 707 * @pn: GCMP PN for the session 708 * @key_set: valid key present 709 */ 710 struct wil_tid_crypto_rx_single { 711 u8 pn[IEEE80211_GCMP_PN_LEN]; 712 bool key_set; 713 }; 714 715 struct wil_tid_crypto_rx { 716 struct wil_tid_crypto_rx_single key_id[4]; 717 }; 718 719 struct wil_p2p_info { 720 struct ieee80211_channel listen_chan; 721 u8 discovery_started; 722 u64 cookie; 723 struct wireless_dev *pending_listen_wdev; 724 unsigned int listen_duration; 725 struct timer_list discovery_timer; /* listen/search duration */ 726 struct work_struct discovery_expired_work; /* listen/search expire */ 727 struct work_struct delayed_listen_work; /* listen after scan done */ 728 }; 729 730 enum wil_sta_status { 731 wil_sta_unused = 0, 732 wil_sta_conn_pending = 1, 733 wil_sta_connected = 2, 734 }; 735 736 /** 737 * struct wil_sta_info - data for peer 738 * 739 * Peer identified by its CID (connection ID) 740 * NIC performs beam forming for each peer; 741 * if no beam forming done, frame exchange is not 742 * possible. 743 */ 744 struct wil_sta_info { 745 u8 addr[ETH_ALEN]; 746 u8 mid; 747 enum wil_sta_status status; 748 struct wil_net_stats stats; 749 /** 750 * 20 latency bins. 1st bin counts packets with latency 751 * of 0..tx_latency_res, last bin counts packets with latency 752 * of 19*tx_latency_res and above. 753 * tx_latency_res is configured from "tx_latency" debug-fs. 754 */ 755 u64 *tx_latency_bins; 756 struct wmi_link_stats_basic fw_stats_basic; 757 /* Rx BACK */ 758 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 759 spinlock_t tid_rx_lock; /* guarding tid_rx array */ 760 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 761 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 762 struct wil_tid_crypto_rx tid_crypto_rx[WIL_STA_TID_NUM]; 763 struct wil_tid_crypto_rx group_crypto_rx; 764 u8 aid; /* 1-254; 0 if unknown/not reported */ 765 }; 766 767 enum { 768 fw_recovery_idle = 0, 769 fw_recovery_pending = 1, 770 fw_recovery_running = 2, 771 }; 772 773 enum { 774 hw_capa_no_flash, 775 hw_capa_last 776 }; 777 778 struct wil_probe_client_req { 779 struct list_head list; 780 u64 cookie; 781 u8 cid; 782 }; 783 784 struct pmc_ctx { 785 /* alloc, free, and read operations must own the lock */ 786 struct mutex lock; 787 struct vring_tx_desc *pring_va; 788 dma_addr_t pring_pa; 789 struct desc_alloc_info *descriptors; 790 int last_cmd_status; 791 int num_descriptors; 792 int descriptor_size; 793 }; 794 795 struct wil_halp { 796 struct mutex lock; /* protect halp ref_cnt */ 797 unsigned int ref_cnt; 798 struct completion comp; 799 u8 handle_icr; 800 }; 801 802 struct wil_blob_wrapper { 803 struct wil6210_priv *wil; 804 struct debugfs_blob_wrapper blob; 805 }; 806 807 #define WIL_LED_MAX_ID (2) 808 #define WIL_LED_INVALID_ID (0xF) 809 #define WIL_LED_BLINK_ON_SLOW_MS (300) 810 #define WIL_LED_BLINK_OFF_SLOW_MS (300) 811 #define WIL_LED_BLINK_ON_MED_MS (200) 812 #define WIL_LED_BLINK_OFF_MED_MS (200) 813 #define WIL_LED_BLINK_ON_FAST_MS (100) 814 #define WIL_LED_BLINK_OFF_FAST_MS (100) 815 enum { 816 WIL_LED_TIME_SLOW = 0, 817 WIL_LED_TIME_MED, 818 WIL_LED_TIME_FAST, 819 WIL_LED_TIME_LAST, 820 }; 821 822 struct blink_on_off_time { 823 u32 on_ms; 824 u32 off_ms; 825 }; 826 827 struct wil_debugfs_iomem_data { 828 void *offset; 829 struct wil6210_priv *wil; 830 }; 831 832 struct wil_debugfs_data { 833 struct wil_debugfs_iomem_data *data_arr; 834 int iomem_data_count; 835 }; 836 837 extern struct blink_on_off_time led_blink_time[WIL_LED_TIME_LAST]; 838 extern u8 led_id; 839 extern u8 led_polarity; 840 841 enum wil6210_vif_status { 842 wil_vif_fwconnecting, 843 wil_vif_fwconnected, 844 wil_vif_ft_roam, 845 wil_vif_status_last /* keep last */ 846 }; 847 848 struct wil6210_vif { 849 struct wireless_dev wdev; 850 struct net_device *ndev; 851 struct wil6210_priv *wil; 852 u8 mid; 853 DECLARE_BITMAP(status, wil_vif_status_last); 854 u32 privacy; /* secure connection? */ 855 u16 channel; /* relevant in AP mode */ 856 u8 hidden_ssid; /* relevant in AP mode */ 857 u32 ap_isolate; /* no intra-BSS communication */ 858 bool pbss; 859 int bi; 860 u8 *proberesp, *proberesp_ies, *assocresp_ies; 861 size_t proberesp_len, proberesp_ies_len, assocresp_ies_len; 862 u8 ssid[IEEE80211_MAX_SSID_LEN]; 863 size_t ssid_len; 864 u8 gtk_index; 865 u8 gtk[WMI_MAX_KEY_LEN]; 866 size_t gtk_len; 867 int bcast_ring; 868 struct cfg80211_bss *bss; /* connected bss, relevant in STA mode */ 869 int locally_generated_disc; /* relevant in STA mode */ 870 struct timer_list connect_timer; 871 struct work_struct disconnect_worker; 872 /* scan */ 873 struct cfg80211_scan_request *scan_request; 874 struct timer_list scan_timer; /* detect scan timeout */ 875 struct wil_p2p_info p2p; 876 /* keep alive */ 877 struct list_head probe_client_pending; 878 struct mutex probe_client_mutex; /* protect @probe_client_pending */ 879 struct work_struct probe_client_worker; 880 int net_queue_stopped; /* netif_tx_stop_all_queues invoked */ 881 bool fw_stats_ready; /* per-cid statistics are ready inside sta_info */ 882 u64 fw_stats_tsf; /* measurement timestamp */ 883 }; 884 885 /** 886 * RX buffer allocated for enhanced DMA RX descriptors 887 */ 888 struct wil_rx_buff { 889 struct sk_buff *skb; 890 struct list_head list; 891 int id; 892 }; 893 894 /** 895 * During Rx completion processing, the driver extracts a buffer ID which 896 * is used as an index to the rx_buff_mgmt.buff_arr array and then the SKB 897 * is given to the network stack and the buffer is moved from the 'active' 898 * list to the 'free' list. 899 * During Rx refill, SKBs are attached to free buffers and moved to the 900 * 'active' list. 901 */ 902 struct wil_rx_buff_mgmt { 903 struct wil_rx_buff *buff_arr; 904 size_t size; /* number of items in buff_arr */ 905 struct list_head active; 906 struct list_head free; 907 unsigned long free_list_empty_cnt; /* statistics */ 908 }; 909 910 struct wil_fw_stats_global { 911 bool ready; 912 u64 tsf; /* measurement timestamp */ 913 struct wmi_link_stats_global stats; 914 }; 915 916 struct wil6210_priv { 917 struct pci_dev *pdev; 918 u32 bar_size; 919 struct wiphy *wiphy; 920 struct net_device *main_ndev; 921 int n_msi; 922 void __iomem *csr; 923 DECLARE_BITMAP(status, wil_status_last); 924 u8 fw_version[ETHTOOL_FWVERS_LEN]; 925 u32 hw_version; 926 u8 chip_revision; 927 const char *hw_name; 928 const char *wil_fw_name; 929 char *board_file; 930 u32 brd_file_addr; 931 u32 brd_file_max_size; 932 DECLARE_BITMAP(hw_capa, hw_capa_last); 933 DECLARE_BITMAP(fw_capabilities, WMI_FW_CAPABILITY_MAX); 934 DECLARE_BITMAP(platform_capa, WIL_PLATFORM_CAPA_MAX); 935 u32 recovery_count; /* num of FW recovery attempts in a short time */ 936 u32 recovery_state; /* FW recovery state machine */ 937 unsigned long last_fw_recovery; /* jiffies of last fw recovery */ 938 wait_queue_head_t wq; /* for all wait_event() use */ 939 u8 max_vifs; /* maximum number of interfaces, including main */ 940 struct wil6210_vif *vifs[WIL_MAX_VIFS]; 941 struct mutex vif_mutex; /* protects access to VIF entries */ 942 atomic_t connected_vifs; 943 /* profile */ 944 struct cfg80211_chan_def monitor_chandef; 945 u32 monitor_flags; 946 int sinfo_gen; 947 /* interrupt moderation */ 948 u32 tx_max_burst_duration; 949 u32 tx_interframe_timeout; 950 u32 rx_max_burst_duration; 951 u32 rx_interframe_timeout; 952 /* cached ISR registers */ 953 u32 isr_misc; 954 /* mailbox related */ 955 struct mutex wmi_mutex; 956 struct wil6210_mbox_ctl mbox_ctl; 957 struct completion wmi_ready; 958 struct completion wmi_call; 959 u16 wmi_seq; 960 u16 reply_id; /**< wait for this WMI event */ 961 u8 reply_mid; 962 void *reply_buf; 963 u16 reply_size; 964 struct workqueue_struct *wmi_wq; /* for deferred calls */ 965 struct work_struct wmi_event_worker; 966 struct workqueue_struct *wq_service; 967 struct work_struct fw_error_worker; /* for FW error recovery */ 968 struct list_head pending_wmi_ev; 969 /* 970 * protect pending_wmi_ev 971 * - fill in IRQ from wil6210_irq_misc, 972 * - consumed in thread by wmi_event_worker 973 */ 974 spinlock_t wmi_ev_lock; 975 spinlock_t net_queue_lock; /* guarding stop/wake netif queue */ 976 struct napi_struct napi_rx; 977 struct napi_struct napi_tx; 978 struct net_device napi_ndev; /* dummy net_device serving all VIFs */ 979 980 /* DMA related */ 981 struct wil_ring ring_rx; 982 unsigned int rx_buf_len; 983 struct wil_ring ring_tx[WIL6210_MAX_TX_RINGS]; 984 struct wil_ring_tx_data ring_tx_data[WIL6210_MAX_TX_RINGS]; 985 struct wil_status_ring srings[WIL6210_MAX_STATUS_RINGS]; 986 u8 num_rx_status_rings; 987 int tx_sring_idx; 988 u8 ring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 989 struct wil_sta_info sta[WIL6210_MAX_CID]; 990 u32 ring_idle_trsh; /* HW fetches up to 16 descriptors at once */ 991 u32 dma_addr_size; /* indicates dma addr size */ 992 struct wil_rx_buff_mgmt rx_buff_mgmt; 993 bool use_enhanced_dma_hw; 994 struct wil_txrx_ops txrx_ops; 995 996 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 997 /* for synchronizing device memory access while reset or suspend */ 998 struct rw_semaphore mem_lock; 999 /* statistics */ 1000 atomic_t isr_count_rx, isr_count_tx; 1001 /* debugfs */ 1002 struct dentry *debug; 1003 struct wil_blob_wrapper blobs[MAX_FW_MAPPING_TABLE_SIZE]; 1004 u8 discovery_mode; 1005 u8 abft_len; 1006 u8 wakeup_trigger; 1007 struct wil_suspend_stats suspend_stats; 1008 struct wil_debugfs_data dbg_data; 1009 bool tx_latency; /* collect TX latency measurements */ 1010 size_t tx_latency_res; /* bin resolution in usec */ 1011 1012 void *platform_handle; 1013 struct wil_platform_ops platform_ops; 1014 bool keep_radio_on_during_sleep; 1015 1016 struct pmc_ctx pmc; 1017 1018 u8 p2p_dev_started; 1019 1020 /* P2P_DEVICE vif */ 1021 struct wireless_dev *p2p_wdev; 1022 struct wireless_dev *radio_wdev; 1023 1024 /* High Access Latency Policy voting */ 1025 struct wil_halp halp; 1026 1027 enum wmi_ps_profile_type ps_profile; 1028 1029 int fw_calib_result; 1030 1031 struct notifier_block pm_notify; 1032 1033 bool suspend_resp_rcvd; 1034 bool suspend_resp_comp; 1035 u32 bus_request_kbps; 1036 u32 bus_request_kbps_pre_suspend; 1037 1038 u32 rgf_fw_assert_code_addr; 1039 u32 rgf_ucode_assert_code_addr; 1040 u32 iccm_base; 1041 1042 /* relevant only for eDMA */ 1043 bool use_compressed_rx_status; 1044 u32 rx_status_ring_order; 1045 u32 tx_status_ring_order; 1046 u32 rx_buff_id_count; 1047 bool amsdu_en; 1048 bool use_rx_hw_reordering; 1049 bool secured_boot; 1050 u8 boot_config; 1051 1052 struct wil_fw_stats_global fw_stats_global; 1053 1054 u32 max_agg_wsize; 1055 u32 max_ampdu_size; 1056 }; 1057 1058 #define wil_to_wiphy(i) (i->wiphy) 1059 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 1060 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 1061 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 1062 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 1063 #define ndev_to_vif(n) (struct wil6210_vif *)(netdev_priv(n)) 1064 #define vif_to_wil(v) (v->wil) 1065 #define vif_to_ndev(v) (v->ndev) 1066 #define vif_to_wdev(v) (&v->wdev) 1067 #define GET_MAX_VIFS(wil) min_t(int, (wil)->max_vifs, WIL_MAX_VIFS) 1068 1069 static inline struct wil6210_vif *wdev_to_vif(struct wil6210_priv *wil, 1070 struct wireless_dev *wdev) 1071 { 1072 /* main interface is shared with P2P device */ 1073 if (wdev == wil->p2p_wdev) 1074 return ndev_to_vif(wil->main_ndev); 1075 else 1076 return container_of(wdev, struct wil6210_vif, wdev); 1077 } 1078 1079 static inline struct wireless_dev * 1080 vif_to_radio_wdev(struct wil6210_priv *wil, struct wil6210_vif *vif) 1081 { 1082 /* main interface is shared with P2P device */ 1083 if (vif->mid) 1084 return vif_to_wdev(vif); 1085 else 1086 return wil->radio_wdev; 1087 } 1088 1089 __printf(2, 3) 1090 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 1091 __printf(2, 3) 1092 void __wil_err(struct wil6210_priv *wil, const char *fmt, ...); 1093 __printf(2, 3) 1094 void __wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...); 1095 __printf(2, 3) 1096 void __wil_info(struct wil6210_priv *wil, const char *fmt, ...); 1097 __printf(2, 3) 1098 void wil_dbg_ratelimited(const struct wil6210_priv *wil, const char *fmt, ...); 1099 #define wil_dbg(wil, fmt, arg...) do { \ 1100 netdev_dbg(wil->main_ndev, fmt, ##arg); \ 1101 wil_dbg_trace(wil, fmt, ##arg); \ 1102 } while (0) 1103 1104 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 1105 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 1106 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 1107 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 1108 #define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg) 1109 #define wil_err(wil, fmt, arg...) __wil_err(wil, "%s: " fmt, __func__, ##arg) 1110 #define wil_info(wil, fmt, arg...) __wil_info(wil, "%s: " fmt, __func__, ##arg) 1111 #define wil_err_ratelimited(wil, fmt, arg...) \ 1112 __wil_err_ratelimited(wil, "%s: " fmt, __func__, ##arg) 1113 1114 /* target operations */ 1115 /* register read */ 1116 static inline u32 wil_r(struct wil6210_priv *wil, u32 reg) 1117 { 1118 return readl(wil->csr + HOSTADDR(reg)); 1119 } 1120 1121 /* register write. wmb() to make sure it is completed */ 1122 static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val) 1123 { 1124 writel(val, wil->csr + HOSTADDR(reg)); 1125 wmb(); /* wait for write to propagate to the HW */ 1126 } 1127 1128 /* register set = read, OR, write */ 1129 static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val) 1130 { 1131 wil_w(wil, reg, wil_r(wil, reg) | val); 1132 } 1133 1134 /* register clear = read, AND with inverted, write */ 1135 static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val) 1136 { 1137 wil_w(wil, reg, wil_r(wil, reg) & ~val); 1138 } 1139 1140 void wil_get_board_file(struct wil6210_priv *wil, char *buf, size_t len); 1141 1142 #if defined(CONFIG_DYNAMIC_DEBUG) 1143 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 1144 groupsize, buf, len, ascii) \ 1145 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 1146 prefix_type, rowsize, \ 1147 groupsize, buf, len, ascii) 1148 1149 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 1150 groupsize, buf, len, ascii) \ 1151 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 1152 prefix_type, rowsize, \ 1153 groupsize, buf, len, ascii) 1154 1155 #define wil_hex_dump_misc(prefix_str, prefix_type, rowsize, \ 1156 groupsize, buf, len, ascii) \ 1157 print_hex_dump_debug("DBG[MISC]" prefix_str,\ 1158 prefix_type, rowsize, \ 1159 groupsize, buf, len, ascii) 1160 #else /* defined(CONFIG_DYNAMIC_DEBUG) */ 1161 static inline 1162 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize, 1163 int groupsize, const void *buf, size_t len, bool ascii) 1164 { 1165 } 1166 1167 static inline 1168 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize, 1169 int groupsize, const void *buf, size_t len, bool ascii) 1170 { 1171 } 1172 1173 static inline 1174 void wil_hex_dump_misc(const char *prefix_str, int prefix_type, int rowsize, 1175 int groupsize, const void *buf, size_t len, bool ascii) 1176 { 1177 } 1178 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */ 1179 1180 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 1181 size_t count); 1182 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 1183 size_t count); 1184 int wil_mem_access_lock(struct wil6210_priv *wil); 1185 void wil_mem_access_unlock(struct wil6210_priv *wil); 1186 1187 struct wil6210_vif * 1188 wil_vif_alloc(struct wil6210_priv *wil, const char *name, 1189 unsigned char name_assign_type, enum nl80211_iftype iftype); 1190 void wil_vif_free(struct wil6210_vif *vif); 1191 void *wil_if_alloc(struct device *dev); 1192 bool wil_has_other_active_ifaces(struct wil6210_priv *wil, 1193 struct net_device *ndev, bool up, bool ok); 1194 bool wil_has_active_ifaces(struct wil6210_priv *wil, bool up, bool ok); 1195 void wil_if_free(struct wil6210_priv *wil); 1196 int wil_vif_add(struct wil6210_priv *wil, struct wil6210_vif *vif); 1197 int wil_if_add(struct wil6210_priv *wil); 1198 void wil_vif_remove(struct wil6210_priv *wil, u8 mid); 1199 void wil_if_remove(struct wil6210_priv *wil); 1200 int wil_priv_init(struct wil6210_priv *wil); 1201 void wil_priv_deinit(struct wil6210_priv *wil); 1202 int wil_ps_update(struct wil6210_priv *wil, 1203 enum wmi_ps_profile_type ps_profile); 1204 int wil_reset(struct wil6210_priv *wil, bool no_fw); 1205 void wil_fw_error_recovery(struct wil6210_priv *wil); 1206 void wil_set_recovery_state(struct wil6210_priv *wil, int state); 1207 bool wil_is_recovery_blocked(struct wil6210_priv *wil); 1208 int wil_up(struct wil6210_priv *wil); 1209 int __wil_up(struct wil6210_priv *wil); 1210 int wil_down(struct wil6210_priv *wil); 1211 int __wil_down(struct wil6210_priv *wil); 1212 void wil_refresh_fw_capabilities(struct wil6210_priv *wil); 1213 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 1214 int wil_find_cid(struct wil6210_priv *wil, u8 mid, const u8 *mac); 1215 void wil_set_ethtoolops(struct net_device *ndev); 1216 1217 struct fw_map *wil_find_fw_mapping(const char *section); 1218 void __iomem *wmi_buffer_block(struct wil6210_priv *wil, __le32 ptr, u32 size); 1219 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 1220 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 1221 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 1222 struct wil6210_mbox_hdr *hdr); 1223 int wmi_send(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len); 1224 void wmi_recv_cmd(struct wil6210_priv *wil); 1225 int wmi_call(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len, 1226 u16 reply_id, void *reply, u16 reply_size, int to_msec); 1227 void wmi_event_worker(struct work_struct *work); 1228 void wmi_event_flush(struct wil6210_priv *wil); 1229 int wmi_set_ssid(struct wil6210_vif *vif, u8 ssid_len, const void *ssid); 1230 int wmi_get_ssid(struct wil6210_vif *vif, u8 *ssid_len, void *ssid); 1231 int wmi_set_channel(struct wil6210_priv *wil, int channel); 1232 int wmi_get_channel(struct wil6210_priv *wil, int *channel); 1233 int wmi_del_cipher_key(struct wil6210_vif *vif, u8 key_index, 1234 const void *mac_addr, int key_usage); 1235 int wmi_add_cipher_key(struct wil6210_vif *vif, u8 key_index, 1236 const void *mac_addr, int key_len, const void *key, 1237 int key_usage); 1238 int wmi_echo(struct wil6210_priv *wil); 1239 int wmi_set_ie(struct wil6210_vif *vif, u8 type, u16 ie_len, const void *ie); 1240 int wmi_rx_chain_add(struct wil6210_priv *wil, struct wil_ring *vring); 1241 int wmi_update_ft_ies(struct wil6210_vif *vif, u16 ie_len, const void *ie); 1242 int wmi_rxon(struct wil6210_priv *wil, bool on); 1243 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 1244 int wmi_disconnect_sta(struct wil6210_vif *vif, const u8 *mac, u16 reason, 1245 bool del_sta); 1246 int wmi_addba(struct wil6210_priv *wil, u8 mid, 1247 u8 ringid, u8 size, u16 timeout); 1248 int wmi_delba_tx(struct wil6210_priv *wil, u8 mid, u8 ringid, u16 reason); 1249 int wmi_delba_rx(struct wil6210_priv *wil, u8 mid, u8 cid, u8 tid, u16 reason); 1250 int wmi_addba_rx_resp(struct wil6210_priv *wil, 1251 u8 mid, u8 cid, u8 tid, u8 token, 1252 u16 status, bool amsdu, u16 agg_wsize, u16 timeout); 1253 int wmi_ps_dev_profile_cfg(struct wil6210_priv *wil, 1254 enum wmi_ps_profile_type ps_profile); 1255 int wmi_set_mgmt_retry(struct wil6210_priv *wil, u8 retry_short); 1256 int wmi_get_mgmt_retry(struct wil6210_priv *wil, u8 *retry_short); 1257 int wmi_new_sta(struct wil6210_vif *vif, const u8 *mac, u8 aid); 1258 int wmi_port_allocate(struct wil6210_priv *wil, u8 mid, 1259 const u8 *mac, enum nl80211_iftype iftype); 1260 int wmi_port_delete(struct wil6210_priv *wil, u8 mid); 1261 int wmi_link_stats_cfg(struct wil6210_vif *vif, u32 type, u8 cid, u32 interval); 1262 int wil_addba_rx_request(struct wil6210_priv *wil, u8 mid, u8 cid, u8 tid, 1263 u8 dialog_token, __le16 ba_param_set, 1264 __le16 ba_timeout, __le16 ba_seq_ctrl); 1265 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize); 1266 1267 void wil6210_clear_irq(struct wil6210_priv *wil); 1268 int wil6210_init_irq(struct wil6210_priv *wil, int irq); 1269 void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 1270 void wil_mask_irq(struct wil6210_priv *wil); 1271 void wil_unmask_irq(struct wil6210_priv *wil); 1272 void wil_configure_interrupt_moderation(struct wil6210_priv *wil); 1273 void wil_disable_irq(struct wil6210_priv *wil); 1274 void wil_enable_irq(struct wil6210_priv *wil); 1275 void wil6210_mask_halp(struct wil6210_priv *wil); 1276 1277 /* P2P */ 1278 bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request); 1279 int wil_p2p_search(struct wil6210_vif *vif, 1280 struct cfg80211_scan_request *request); 1281 int wil_p2p_listen(struct wil6210_priv *wil, struct wireless_dev *wdev, 1282 unsigned int duration, struct ieee80211_channel *chan, 1283 u64 *cookie); 1284 u8 wil_p2p_stop_discovery(struct wil6210_vif *vif); 1285 int wil_p2p_cancel_listen(struct wil6210_vif *vif, u64 cookie); 1286 void wil_p2p_listen_expired(struct work_struct *work); 1287 void wil_p2p_search_expired(struct work_struct *work); 1288 void wil_p2p_stop_radio_operations(struct wil6210_priv *wil); 1289 void wil_p2p_delayed_listen_work(struct work_struct *work); 1290 1291 /* WMI for P2P */ 1292 int wmi_p2p_cfg(struct wil6210_vif *vif, int channel, int bi); 1293 int wmi_start_listen(struct wil6210_vif *vif); 1294 int wmi_start_search(struct wil6210_vif *vif); 1295 int wmi_stop_discovery(struct wil6210_vif *vif); 1296 1297 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, 1298 struct cfg80211_mgmt_tx_params *params, 1299 u64 *cookie); 1300 void wil_cfg80211_ap_recovery(struct wil6210_priv *wil); 1301 int wil_cfg80211_iface_combinations_from_fw( 1302 struct wil6210_priv *wil, 1303 const struct wil_fw_record_concurrency *conc); 1304 int wil_vif_prepare_stop(struct wil6210_vif *vif); 1305 1306 #if defined(CONFIG_WIL6210_DEBUGFS) 1307 int wil6210_debugfs_init(struct wil6210_priv *wil); 1308 void wil6210_debugfs_remove(struct wil6210_priv *wil); 1309 #else 1310 static inline int wil6210_debugfs_init(struct wil6210_priv *wil) { return 0; } 1311 static inline void wil6210_debugfs_remove(struct wil6210_priv *wil) {} 1312 #endif 1313 1314 int wil_cid_fill_sinfo(struct wil6210_vif *vif, int cid, 1315 struct station_info *sinfo); 1316 1317 struct wil6210_priv *wil_cfg80211_init(struct device *dev); 1318 void wil_cfg80211_deinit(struct wil6210_priv *wil); 1319 void wil_p2p_wdev_free(struct wil6210_priv *wil); 1320 1321 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 1322 int wmi_pcp_start(struct wil6210_vif *vif, int bi, u8 wmi_nettype, u8 chan, 1323 u8 hidden_ssid, u8 is_go); 1324 int wmi_pcp_stop(struct wil6210_vif *vif); 1325 int wmi_led_cfg(struct wil6210_priv *wil, bool enable); 1326 int wmi_abort_scan(struct wil6210_vif *vif); 1327 void wil_abort_scan(struct wil6210_vif *vif, bool sync); 1328 void wil_abort_scan_all_vifs(struct wil6210_priv *wil, bool sync); 1329 void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps); 1330 void wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid, 1331 u16 reason_code); 1332 void wil6210_disconnect_complete(struct wil6210_vif *vif, const u8 *bssid, 1333 u16 reason_code); 1334 void wil_probe_client_flush(struct wil6210_vif *vif); 1335 void wil_probe_client_worker(struct work_struct *work); 1336 void wil_disconnect_worker(struct work_struct *work); 1337 1338 void wil_init_txrx_ops(struct wil6210_priv *wil); 1339 1340 /* TX API */ 1341 int wil_ring_init_tx(struct wil6210_vif *vif, int cid); 1342 int wil_vring_init_bcast(struct wil6210_vif *vif, int id, int size); 1343 int wil_bcast_init(struct wil6210_vif *vif); 1344 void wil_bcast_fini(struct wil6210_vif *vif); 1345 void wil_bcast_fini_all(struct wil6210_priv *wil); 1346 1347 void wil_update_net_queues(struct wil6210_priv *wil, struct wil6210_vif *vif, 1348 struct wil_ring *ring, bool should_stop); 1349 void wil_update_net_queues_bh(struct wil6210_priv *wil, struct wil6210_vif *vif, 1350 struct wil_ring *ring, bool check_stop); 1351 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 1352 int wil_tx_complete(struct wil6210_vif *vif, int ringid); 1353 void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 1354 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil); 1355 1356 /* RX API */ 1357 void wil_rx_handle(struct wil6210_priv *wil, int *quota); 1358 void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 1359 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil); 1360 void wil_set_crypto_rx(u8 key_index, enum wmi_key_usage key_usage, 1361 struct wil_sta_info *cs, 1362 struct key_params *params); 1363 1364 int wil_iftype_nl2wmi(enum nl80211_iftype type); 1365 1366 int wil_request_firmware(struct wil6210_priv *wil, const char *name, 1367 bool load); 1368 int wil_request_board(struct wil6210_priv *wil, const char *name); 1369 bool wil_fw_verify_file_exists(struct wil6210_priv *wil, const char *name); 1370 1371 void wil_pm_runtime_allow(struct wil6210_priv *wil); 1372 void wil_pm_runtime_forbid(struct wil6210_priv *wil); 1373 int wil_pm_runtime_get(struct wil6210_priv *wil); 1374 void wil_pm_runtime_put(struct wil6210_priv *wil); 1375 1376 int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime); 1377 int wil_suspend(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1378 int wil_resume(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1379 bool wil_is_wmi_idle(struct wil6210_priv *wil); 1380 int wmi_resume(struct wil6210_priv *wil); 1381 int wmi_suspend(struct wil6210_priv *wil); 1382 bool wil_is_tx_idle(struct wil6210_priv *wil); 1383 1384 int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size); 1385 void wil_fw_core_dump(struct wil6210_priv *wil); 1386 1387 void wil_halp_vote(struct wil6210_priv *wil); 1388 void wil_halp_unvote(struct wil6210_priv *wil); 1389 void wil6210_set_halp(struct wil6210_priv *wil); 1390 void wil6210_clear_halp(struct wil6210_priv *wil); 1391 1392 int wmi_start_sched_scan(struct wil6210_priv *wil, 1393 struct cfg80211_sched_scan_request *request); 1394 int wmi_stop_sched_scan(struct wil6210_priv *wil); 1395 int wmi_mgmt_tx(struct wil6210_vif *vif, const u8 *buf, size_t len); 1396 int wmi_mgmt_tx_ext(struct wil6210_vif *vif, const u8 *buf, size_t len, 1397 u8 channel, u16 duration_ms); 1398 1399 int reverse_memcmp(const void *cs, const void *ct, size_t count); 1400 1401 /* WMI for enhanced DMA */ 1402 int wil_wmi_tx_sring_cfg(struct wil6210_priv *wil, int ring_id); 1403 int wil_wmi_cfg_def_rx_offload(struct wil6210_priv *wil, 1404 u16 max_rx_pl_per_desc); 1405 int wil_wmi_rx_sring_add(struct wil6210_priv *wil, u16 ring_id); 1406 int wil_wmi_rx_desc_ring_add(struct wil6210_priv *wil, int status_ring_id); 1407 int wil_wmi_tx_desc_ring_add(struct wil6210_vif *vif, int ring_id, int cid, 1408 int tid); 1409 int wil_wmi_bcast_desc_ring_add(struct wil6210_vif *vif, int ring_id); 1410 int wmi_addba_rx_resp_edma(struct wil6210_priv *wil, u8 mid, u8 cid, 1411 u8 tid, u8 token, u16 status, bool amsdu, 1412 u16 agg_wsize, u16 timeout); 1413 1414 void update_supported_bands(struct wil6210_priv *wil); 1415 1416 #endif /* __WIL6210_H__ */ 1417