1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #include <linux/devcoredump.h> 65 #include "iwl-drv.h" 66 #include "runtime.h" 67 #include "dbg.h" 68 #include "debugfs.h" 69 #include "iwl-io.h" 70 #include "iwl-prph.h" 71 #include "iwl-csr.h" 72 73 /** 74 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 75 * 76 * @fwrt_ptr: pointer to the buffer coming from fwrt 77 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 78 * transport's data. 79 * @trans_len: length of the valid data in trans_ptr 80 * @fwrt_len: length of the valid data in fwrt_ptr 81 */ 82 struct iwl_fw_dump_ptrs { 83 struct iwl_trans_dump_data *trans_ptr; 84 void *fwrt_ptr; 85 u32 fwrt_len; 86 }; 87 88 #define RADIO_REG_MAX_READ 0x2ad 89 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 90 struct iwl_fw_error_dump_data **dump_data) 91 { 92 u8 *pos = (void *)(*dump_data)->data; 93 unsigned long flags; 94 int i; 95 96 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 97 98 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 99 return; 100 101 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 102 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 103 104 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 105 u32 rd_cmd = RADIO_RSP_RD_CMD; 106 107 rd_cmd |= i << RADIO_RSP_ADDR_POS; 108 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 109 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 110 111 pos++; 112 } 113 114 *dump_data = iwl_fw_error_next_data(*dump_data); 115 116 iwl_trans_release_nic_access(fwrt->trans, &flags); 117 } 118 119 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 120 struct iwl_fw_error_dump_data **dump_data, 121 int size, u32 offset, int fifo_num) 122 { 123 struct iwl_fw_error_dump_fifo *fifo_hdr; 124 u32 *fifo_data; 125 u32 fifo_len; 126 int i; 127 128 fifo_hdr = (void *)(*dump_data)->data; 129 fifo_data = (void *)fifo_hdr->data; 130 fifo_len = size; 131 132 /* No need to try to read the data if the length is 0 */ 133 if (fifo_len == 0) 134 return; 135 136 /* Add a TLV for the RXF */ 137 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 138 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 139 140 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 141 fifo_hdr->available_bytes = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 RXF_RD_D_SPACE + offset)); 144 fifo_hdr->wr_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 RXF_RD_WR_PTR + offset)); 147 fifo_hdr->rd_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 RXF_RD_RD_PTR + offset)); 150 fifo_hdr->fence_ptr = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 RXF_RD_FENCE_PTR + offset)); 153 fifo_hdr->fence_mode = 154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 155 RXF_SET_FENCE_MODE + offset)); 156 157 /* Lock fence */ 158 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 159 /* Set fence pointer to the same place like WR pointer */ 160 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 161 /* Set fence offset */ 162 iwl_trans_write_prph(fwrt->trans, 163 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 164 165 /* Read FIFO */ 166 fifo_len /= sizeof(u32); /* Size in DWORDS */ 167 for (i = 0; i < fifo_len; i++) 168 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 169 RXF_FIFO_RD_FENCE_INC + 170 offset); 171 *dump_data = iwl_fw_error_next_data(*dump_data); 172 } 173 174 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 175 struct iwl_fw_error_dump_data **dump_data, 176 int size, u32 offset, int fifo_num) 177 { 178 struct iwl_fw_error_dump_fifo *fifo_hdr; 179 u32 *fifo_data; 180 u32 fifo_len; 181 int i; 182 183 fifo_hdr = (void *)(*dump_data)->data; 184 fifo_data = (void *)fifo_hdr->data; 185 fifo_len = size; 186 187 /* No need to try to read the data if the length is 0 */ 188 if (fifo_len == 0) 189 return; 190 191 /* Add a TLV for the FIFO */ 192 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 193 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 194 195 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 196 fifo_hdr->available_bytes = 197 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 198 TXF_FIFO_ITEM_CNT + offset)); 199 fifo_hdr->wr_ptr = 200 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 201 TXF_WR_PTR + offset)); 202 fifo_hdr->rd_ptr = 203 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 204 TXF_RD_PTR + offset)); 205 fifo_hdr->fence_ptr = 206 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 207 TXF_FENCE_PTR + offset)); 208 fifo_hdr->fence_mode = 209 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 210 TXF_LOCK_FENCE + offset)); 211 212 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 213 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 214 TXF_WR_PTR + offset); 215 216 /* Dummy-read to advance the read pointer to the head */ 217 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 218 219 /* Read FIFO */ 220 fifo_len /= sizeof(u32); /* Size in DWORDS */ 221 for (i = 0; i < fifo_len; i++) 222 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 223 TXF_READ_MODIFY_DATA + 224 offset); 225 *dump_data = iwl_fw_error_next_data(*dump_data); 226 } 227 228 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 229 struct iwl_fw_error_dump_data **dump_data) 230 { 231 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 232 unsigned long flags; 233 234 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 235 236 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 237 return; 238 239 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 240 /* Pull RXF1 */ 241 iwl_fwrt_dump_rxf(fwrt, dump_data, 242 cfg->lmac[0].rxfifo1_size, 0, 0); 243 /* Pull RXF2 */ 244 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 245 RXF_DIFF_FROM_PREV + 246 fwrt->trans->trans_cfg->umac_prph_offset, 1); 247 /* Pull LMAC2 RXF1 */ 248 if (fwrt->smem_cfg.num_lmacs > 1) 249 iwl_fwrt_dump_rxf(fwrt, dump_data, 250 cfg->lmac[1].rxfifo1_size, 251 LMAC2_PRPH_OFFSET, 2); 252 } 253 254 iwl_trans_release_nic_access(fwrt->trans, &flags); 255 } 256 257 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 258 struct iwl_fw_error_dump_data **dump_data) 259 { 260 struct iwl_fw_error_dump_fifo *fifo_hdr; 261 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 262 u32 *fifo_data; 263 u32 fifo_len; 264 unsigned long flags; 265 int i, j; 266 267 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 268 269 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 270 return; 271 272 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 273 /* Pull TXF data from LMAC1 */ 274 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 275 /* Mark the number of TXF we're pulling now */ 276 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 277 iwl_fwrt_dump_txf(fwrt, dump_data, 278 cfg->lmac[0].txfifo_size[i], 0, i); 279 } 280 281 /* Pull TXF data from LMAC2 */ 282 if (fwrt->smem_cfg.num_lmacs > 1) { 283 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 284 i++) { 285 /* Mark the number of TXF we're pulling now */ 286 iwl_trans_write_prph(fwrt->trans, 287 TXF_LARC_NUM + 288 LMAC2_PRPH_OFFSET, i); 289 iwl_fwrt_dump_txf(fwrt, dump_data, 290 cfg->lmac[1].txfifo_size[i], 291 LMAC2_PRPH_OFFSET, 292 i + cfg->num_txfifo_entries); 293 } 294 } 295 } 296 297 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 298 fw_has_capa(&fwrt->fw->ucode_capa, 299 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 300 /* Pull UMAC internal TXF data from all TXFs */ 301 for (i = 0; 302 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 303 i++) { 304 fifo_hdr = (void *)(*dump_data)->data; 305 fifo_data = (void *)fifo_hdr->data; 306 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 307 308 /* No need to try to read the data if the length is 0 */ 309 if (fifo_len == 0) 310 continue; 311 312 /* Add a TLV for the internal FIFOs */ 313 (*dump_data)->type = 314 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 315 (*dump_data)->len = 316 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 317 318 fifo_hdr->fifo_num = cpu_to_le32(i); 319 320 /* Mark the number of TXF we're pulling now */ 321 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 322 fwrt->smem_cfg.num_txfifo_entries); 323 324 fifo_hdr->available_bytes = 325 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 326 TXF_CPU2_FIFO_ITEM_CNT)); 327 fifo_hdr->wr_ptr = 328 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 329 TXF_CPU2_WR_PTR)); 330 fifo_hdr->rd_ptr = 331 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 332 TXF_CPU2_RD_PTR)); 333 fifo_hdr->fence_ptr = 334 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 335 TXF_CPU2_FENCE_PTR)); 336 fifo_hdr->fence_mode = 337 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 338 TXF_CPU2_LOCK_FENCE)); 339 340 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 341 iwl_trans_write_prph(fwrt->trans, 342 TXF_CPU2_READ_MODIFY_ADDR, 343 TXF_CPU2_WR_PTR); 344 345 /* Dummy-read to advance the read pointer to head */ 346 iwl_trans_read_prph(fwrt->trans, 347 TXF_CPU2_READ_MODIFY_DATA); 348 349 /* Read FIFO */ 350 fifo_len /= sizeof(u32); /* Size in DWORDS */ 351 for (j = 0; j < fifo_len; j++) 352 fifo_data[j] = 353 iwl_trans_read_prph(fwrt->trans, 354 TXF_CPU2_READ_MODIFY_DATA); 355 *dump_data = iwl_fw_error_next_data(*dump_data); 356 } 357 } 358 359 iwl_trans_release_nic_access(fwrt->trans, &flags); 360 } 361 362 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 363 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 364 365 struct iwl_prph_range { 366 u32 start, end; 367 }; 368 369 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 370 { .start = 0x00a00000, .end = 0x00a00000 }, 371 { .start = 0x00a0000c, .end = 0x00a00024 }, 372 { .start = 0x00a0002c, .end = 0x00a0003c }, 373 { .start = 0x00a00410, .end = 0x00a00418 }, 374 { .start = 0x00a00420, .end = 0x00a00420 }, 375 { .start = 0x00a00428, .end = 0x00a00428 }, 376 { .start = 0x00a00430, .end = 0x00a0043c }, 377 { .start = 0x00a00444, .end = 0x00a00444 }, 378 { .start = 0x00a004c0, .end = 0x00a004cc }, 379 { .start = 0x00a004d8, .end = 0x00a004d8 }, 380 { .start = 0x00a004e0, .end = 0x00a004f0 }, 381 { .start = 0x00a00840, .end = 0x00a00840 }, 382 { .start = 0x00a00850, .end = 0x00a00858 }, 383 { .start = 0x00a01004, .end = 0x00a01008 }, 384 { .start = 0x00a01010, .end = 0x00a01010 }, 385 { .start = 0x00a01018, .end = 0x00a01018 }, 386 { .start = 0x00a01024, .end = 0x00a01024 }, 387 { .start = 0x00a0102c, .end = 0x00a01034 }, 388 { .start = 0x00a0103c, .end = 0x00a01040 }, 389 { .start = 0x00a01048, .end = 0x00a01094 }, 390 { .start = 0x00a01c00, .end = 0x00a01c20 }, 391 { .start = 0x00a01c58, .end = 0x00a01c58 }, 392 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 393 { .start = 0x00a01c28, .end = 0x00a01c54 }, 394 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 395 { .start = 0x00a01c60, .end = 0x00a01cdc }, 396 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 397 { .start = 0x00a01d18, .end = 0x00a01d20 }, 398 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 399 { .start = 0x00a01d40, .end = 0x00a01d5c }, 400 { .start = 0x00a01d80, .end = 0x00a01d80 }, 401 { .start = 0x00a01d98, .end = 0x00a01d9c }, 402 { .start = 0x00a01da8, .end = 0x00a01da8 }, 403 { .start = 0x00a01db8, .end = 0x00a01df4 }, 404 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 405 { .start = 0x00a01e00, .end = 0x00a01e2c }, 406 { .start = 0x00a01e40, .end = 0x00a01e60 }, 407 { .start = 0x00a01e68, .end = 0x00a01e6c }, 408 { .start = 0x00a01e74, .end = 0x00a01e74 }, 409 { .start = 0x00a01e84, .end = 0x00a01e90 }, 410 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 411 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 412 { .start = 0x00a01f00, .end = 0x00a01f1c }, 413 { .start = 0x00a01f44, .end = 0x00a01ffc }, 414 { .start = 0x00a02000, .end = 0x00a02048 }, 415 { .start = 0x00a02068, .end = 0x00a020f0 }, 416 { .start = 0x00a02100, .end = 0x00a02118 }, 417 { .start = 0x00a02140, .end = 0x00a0214c }, 418 { .start = 0x00a02168, .end = 0x00a0218c }, 419 { .start = 0x00a021c0, .end = 0x00a021c0 }, 420 { .start = 0x00a02400, .end = 0x00a02410 }, 421 { .start = 0x00a02418, .end = 0x00a02420 }, 422 { .start = 0x00a02428, .end = 0x00a0242c }, 423 { .start = 0x00a02434, .end = 0x00a02434 }, 424 { .start = 0x00a02440, .end = 0x00a02460 }, 425 { .start = 0x00a02468, .end = 0x00a024b0 }, 426 { .start = 0x00a024c8, .end = 0x00a024cc }, 427 { .start = 0x00a02500, .end = 0x00a02504 }, 428 { .start = 0x00a0250c, .end = 0x00a02510 }, 429 { .start = 0x00a02540, .end = 0x00a02554 }, 430 { .start = 0x00a02580, .end = 0x00a025f4 }, 431 { .start = 0x00a02600, .end = 0x00a0260c }, 432 { .start = 0x00a02648, .end = 0x00a02650 }, 433 { .start = 0x00a02680, .end = 0x00a02680 }, 434 { .start = 0x00a026c0, .end = 0x00a026d0 }, 435 { .start = 0x00a02700, .end = 0x00a0270c }, 436 { .start = 0x00a02804, .end = 0x00a02804 }, 437 { .start = 0x00a02818, .end = 0x00a0281c }, 438 { .start = 0x00a02c00, .end = 0x00a02db4 }, 439 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 440 { .start = 0x00a03000, .end = 0x00a03014 }, 441 { .start = 0x00a0301c, .end = 0x00a0302c }, 442 { .start = 0x00a03034, .end = 0x00a03038 }, 443 { .start = 0x00a03040, .end = 0x00a03048 }, 444 { .start = 0x00a03060, .end = 0x00a03068 }, 445 { .start = 0x00a03070, .end = 0x00a03074 }, 446 { .start = 0x00a0307c, .end = 0x00a0307c }, 447 { .start = 0x00a03080, .end = 0x00a03084 }, 448 { .start = 0x00a0308c, .end = 0x00a03090 }, 449 { .start = 0x00a03098, .end = 0x00a03098 }, 450 { .start = 0x00a030a0, .end = 0x00a030a0 }, 451 { .start = 0x00a030a8, .end = 0x00a030b4 }, 452 { .start = 0x00a030bc, .end = 0x00a030bc }, 453 { .start = 0x00a030c0, .end = 0x00a0312c }, 454 { .start = 0x00a03c00, .end = 0x00a03c5c }, 455 { .start = 0x00a04400, .end = 0x00a04454 }, 456 { .start = 0x00a04460, .end = 0x00a04474 }, 457 { .start = 0x00a044c0, .end = 0x00a044ec }, 458 { .start = 0x00a04500, .end = 0x00a04504 }, 459 { .start = 0x00a04510, .end = 0x00a04538 }, 460 { .start = 0x00a04540, .end = 0x00a04548 }, 461 { .start = 0x00a04560, .end = 0x00a0457c }, 462 { .start = 0x00a04590, .end = 0x00a04598 }, 463 { .start = 0x00a045c0, .end = 0x00a045f4 }, 464 }; 465 466 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 467 { .start = 0x00a05c00, .end = 0x00a05c18 }, 468 { .start = 0x00a05400, .end = 0x00a056e8 }, 469 { .start = 0x00a08000, .end = 0x00a098bc }, 470 { .start = 0x00a02400, .end = 0x00a02758 }, 471 { .start = 0x00a04764, .end = 0x00a0476c }, 472 { .start = 0x00a04770, .end = 0x00a04774 }, 473 { .start = 0x00a04620, .end = 0x00a04624 }, 474 }; 475 476 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 477 { .start = 0x00a00000, .end = 0x00a00000 }, 478 { .start = 0x00a0000c, .end = 0x00a00024 }, 479 { .start = 0x00a0002c, .end = 0x00a00034 }, 480 { .start = 0x00a0003c, .end = 0x00a0003c }, 481 { .start = 0x00a00410, .end = 0x00a00418 }, 482 { .start = 0x00a00420, .end = 0x00a00420 }, 483 { .start = 0x00a00428, .end = 0x00a00428 }, 484 { .start = 0x00a00430, .end = 0x00a0043c }, 485 { .start = 0x00a00444, .end = 0x00a00444 }, 486 { .start = 0x00a00840, .end = 0x00a00840 }, 487 { .start = 0x00a00850, .end = 0x00a00858 }, 488 { .start = 0x00a01004, .end = 0x00a01008 }, 489 { .start = 0x00a01010, .end = 0x00a01010 }, 490 { .start = 0x00a01018, .end = 0x00a01018 }, 491 { .start = 0x00a01024, .end = 0x00a01024 }, 492 { .start = 0x00a0102c, .end = 0x00a01034 }, 493 { .start = 0x00a0103c, .end = 0x00a01040 }, 494 { .start = 0x00a01048, .end = 0x00a01050 }, 495 { .start = 0x00a01058, .end = 0x00a01058 }, 496 { .start = 0x00a01060, .end = 0x00a01070 }, 497 { .start = 0x00a0108c, .end = 0x00a0108c }, 498 { .start = 0x00a01c20, .end = 0x00a01c28 }, 499 { .start = 0x00a01d10, .end = 0x00a01d10 }, 500 { .start = 0x00a01e28, .end = 0x00a01e2c }, 501 { .start = 0x00a01e60, .end = 0x00a01e60 }, 502 { .start = 0x00a01e80, .end = 0x00a01e80 }, 503 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 504 { .start = 0x00a02000, .end = 0x00a0201c }, 505 { .start = 0x00a02024, .end = 0x00a02024 }, 506 { .start = 0x00a02040, .end = 0x00a02048 }, 507 { .start = 0x00a020c0, .end = 0x00a020e0 }, 508 { .start = 0x00a02400, .end = 0x00a02404 }, 509 { .start = 0x00a0240c, .end = 0x00a02414 }, 510 { .start = 0x00a0241c, .end = 0x00a0243c }, 511 { .start = 0x00a02448, .end = 0x00a024bc }, 512 { .start = 0x00a024c4, .end = 0x00a024cc }, 513 { .start = 0x00a02508, .end = 0x00a02508 }, 514 { .start = 0x00a02510, .end = 0x00a02514 }, 515 { .start = 0x00a0251c, .end = 0x00a0251c }, 516 { .start = 0x00a0252c, .end = 0x00a0255c }, 517 { .start = 0x00a02564, .end = 0x00a025a0 }, 518 { .start = 0x00a025a8, .end = 0x00a025b4 }, 519 { .start = 0x00a025c0, .end = 0x00a025c0 }, 520 { .start = 0x00a025e8, .end = 0x00a025f4 }, 521 { .start = 0x00a02c08, .end = 0x00a02c18 }, 522 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 523 { .start = 0x00a02c68, .end = 0x00a02c78 }, 524 { .start = 0x00a03000, .end = 0x00a03000 }, 525 { .start = 0x00a03010, .end = 0x00a03014 }, 526 { .start = 0x00a0301c, .end = 0x00a0302c }, 527 { .start = 0x00a03034, .end = 0x00a03038 }, 528 { .start = 0x00a03040, .end = 0x00a03044 }, 529 { .start = 0x00a03060, .end = 0x00a03068 }, 530 { .start = 0x00a03070, .end = 0x00a03070 }, 531 { .start = 0x00a0307c, .end = 0x00a03084 }, 532 { .start = 0x00a0308c, .end = 0x00a03090 }, 533 { .start = 0x00a03098, .end = 0x00a03098 }, 534 { .start = 0x00a030a0, .end = 0x00a030a0 }, 535 { .start = 0x00a030a8, .end = 0x00a030b4 }, 536 { .start = 0x00a030bc, .end = 0x00a030c0 }, 537 { .start = 0x00a030c8, .end = 0x00a030f4 }, 538 { .start = 0x00a03100, .end = 0x00a0312c }, 539 { .start = 0x00a03c00, .end = 0x00a03c5c }, 540 { .start = 0x00a04400, .end = 0x00a04454 }, 541 { .start = 0x00a04460, .end = 0x00a04474 }, 542 { .start = 0x00a044c0, .end = 0x00a044ec }, 543 { .start = 0x00a04500, .end = 0x00a04504 }, 544 { .start = 0x00a04510, .end = 0x00a04538 }, 545 { .start = 0x00a04540, .end = 0x00a04548 }, 546 { .start = 0x00a04560, .end = 0x00a04560 }, 547 { .start = 0x00a04570, .end = 0x00a0457c }, 548 { .start = 0x00a04590, .end = 0x00a04590 }, 549 { .start = 0x00a04598, .end = 0x00a04598 }, 550 { .start = 0x00a045c0, .end = 0x00a045f4 }, 551 { .start = 0x00a05c18, .end = 0x00a05c1c }, 552 { .start = 0x00a0c000, .end = 0x00a0c018 }, 553 { .start = 0x00a0c020, .end = 0x00a0c028 }, 554 { .start = 0x00a0c038, .end = 0x00a0c094 }, 555 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 556 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 557 { .start = 0x00a0c150, .end = 0x00a0c174 }, 558 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 559 { .start = 0x00a0c190, .end = 0x00a0c198 }, 560 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 561 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 562 }; 563 564 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 565 { .start = 0x00d03c00, .end = 0x00d03c64 }, 566 { .start = 0x00d05c18, .end = 0x00d05c1c }, 567 { .start = 0x00d0c000, .end = 0x00d0c174 }, 568 }; 569 570 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 571 u32 len_bytes, __le32 *data) 572 { 573 u32 i; 574 575 for (i = 0; i < len_bytes; i += 4) 576 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 577 } 578 579 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 580 const struct iwl_prph_range *iwl_prph_dump_addr, 581 u32 range_len, void *ptr) 582 { 583 struct iwl_fw_error_dump_prph *prph; 584 struct iwl_trans *trans = fwrt->trans; 585 struct iwl_fw_error_dump_data **data = 586 (struct iwl_fw_error_dump_data **)ptr; 587 unsigned long flags; 588 u32 i; 589 590 if (!data) 591 return; 592 593 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 594 595 if (!iwl_trans_grab_nic_access(trans, &flags)) 596 return; 597 598 for (i = 0; i < range_len; i++) { 599 /* The range includes both boundaries */ 600 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 601 iwl_prph_dump_addr[i].start + 4; 602 603 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 604 (*data)->len = cpu_to_le32(sizeof(*prph) + 605 num_bytes_in_chunk); 606 prph = (void *)(*data)->data; 607 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 608 609 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 610 /* our range is inclusive, hence + 4 */ 611 iwl_prph_dump_addr[i].end - 612 iwl_prph_dump_addr[i].start + 4, 613 (void *)prph->data); 614 615 *data = iwl_fw_error_next_data(*data); 616 } 617 618 iwl_trans_release_nic_access(trans, &flags); 619 } 620 621 /* 622 * alloc_sgtable - allocates scallerlist table in the given size, 623 * fills it with pages and returns it 624 * @size: the size (in bytes) of the table 625 */ 626 static struct scatterlist *alloc_sgtable(int size) 627 { 628 int alloc_size, nents, i; 629 struct page *new_page; 630 struct scatterlist *iter; 631 struct scatterlist *table; 632 633 nents = DIV_ROUND_UP(size, PAGE_SIZE); 634 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 635 if (!table) 636 return NULL; 637 sg_init_table(table, nents); 638 iter = table; 639 for_each_sg(table, iter, sg_nents(table), i) { 640 new_page = alloc_page(GFP_KERNEL); 641 if (!new_page) { 642 /* release all previous allocated pages in the table */ 643 iter = table; 644 for_each_sg(table, iter, sg_nents(table), i) { 645 new_page = sg_page(iter); 646 if (new_page) 647 __free_page(new_page); 648 } 649 kfree(table); 650 return NULL; 651 } 652 alloc_size = min_t(int, size, PAGE_SIZE); 653 size -= PAGE_SIZE; 654 sg_set_page(iter, new_page, alloc_size, 0); 655 } 656 return table; 657 } 658 659 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 660 const struct iwl_prph_range *iwl_prph_dump_addr, 661 u32 range_len, void *ptr) 662 { 663 u32 *prph_len = (u32 *)ptr; 664 int i, num_bytes_in_chunk; 665 666 if (!prph_len) 667 return; 668 669 for (i = 0; i < range_len; i++) { 670 /* The range includes both boundaries */ 671 num_bytes_in_chunk = 672 iwl_prph_dump_addr[i].end - 673 iwl_prph_dump_addr[i].start + 4; 674 675 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 676 sizeof(struct iwl_fw_error_dump_prph) + 677 num_bytes_in_chunk; 678 } 679 } 680 681 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 682 void (*handler)(struct iwl_fw_runtime *, 683 const struct iwl_prph_range *, 684 u32, void *)) 685 { 686 u32 range_len; 687 688 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 689 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 690 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 691 } else if (fwrt->trans->trans_cfg->device_family >= 692 IWL_DEVICE_FAMILY_22000) { 693 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 694 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 695 } else { 696 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 697 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 698 699 if (fwrt->trans->trans_cfg->mq_rx_supported) { 700 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 701 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 702 } 703 } 704 } 705 706 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 707 struct iwl_fw_error_dump_data **dump_data, 708 u32 len, u32 ofs, u32 type) 709 { 710 struct iwl_fw_error_dump_mem *dump_mem; 711 712 if (!len) 713 return; 714 715 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 716 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 717 dump_mem = (void *)(*dump_data)->data; 718 dump_mem->type = cpu_to_le32(type); 719 dump_mem->offset = cpu_to_le32(ofs); 720 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 721 *dump_data = iwl_fw_error_next_data(*dump_data); 722 723 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 724 } 725 726 #define ADD_LEN(len, item_len, const_len) \ 727 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 728 while (0) 729 730 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 731 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 732 { 733 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 734 sizeof(struct iwl_fw_error_dump_fifo); 735 u32 fifo_len = 0; 736 int i; 737 738 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 739 return 0; 740 741 /* Count RXF2 size */ 742 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 743 744 /* Count RXF1 sizes */ 745 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 746 mem_cfg->num_lmacs = MAX_NUM_LMAC; 747 748 for (i = 0; i < mem_cfg->num_lmacs; i++) 749 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 750 751 return fifo_len; 752 } 753 754 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 755 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 756 { 757 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 758 sizeof(struct iwl_fw_error_dump_fifo); 759 u32 fifo_len = 0; 760 int i; 761 762 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 763 goto dump_internal_txf; 764 765 /* Count TXF sizes */ 766 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 767 mem_cfg->num_lmacs = MAX_NUM_LMAC; 768 769 for (i = 0; i < mem_cfg->num_lmacs; i++) { 770 int j; 771 772 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 773 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 774 hdr_len); 775 } 776 777 dump_internal_txf: 778 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 779 fw_has_capa(&fwrt->fw->ucode_capa, 780 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 781 goto out; 782 783 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 784 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 785 786 out: 787 return fifo_len; 788 } 789 790 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 791 struct iwl_fw_error_dump_data **data) 792 { 793 int i; 794 795 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 796 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 797 struct iwl_fw_error_dump_paging *paging; 798 struct page *pages = 799 fwrt->fw_paging_db[i].fw_paging_block; 800 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 801 802 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 803 (*data)->len = cpu_to_le32(sizeof(*paging) + 804 PAGING_BLOCK_SIZE); 805 paging = (void *)(*data)->data; 806 paging->index = cpu_to_le32(i); 807 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 808 PAGING_BLOCK_SIZE, 809 DMA_BIDIRECTIONAL); 810 memcpy(paging->data, page_address(pages), 811 PAGING_BLOCK_SIZE); 812 dma_sync_single_for_device(fwrt->trans->dev, addr, 813 PAGING_BLOCK_SIZE, 814 DMA_BIDIRECTIONAL); 815 (*data) = iwl_fw_error_next_data(*data); 816 } 817 } 818 819 static struct iwl_fw_error_dump_file * 820 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 821 struct iwl_fw_dump_ptrs *fw_error_dump) 822 { 823 struct iwl_fw_error_dump_file *dump_file; 824 struct iwl_fw_error_dump_data *dump_data; 825 struct iwl_fw_error_dump_info *dump_info; 826 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 827 struct iwl_fw_error_dump_trigger_desc *dump_trig; 828 u32 sram_len, sram_ofs; 829 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 830 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 831 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 832 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 833 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 834 0 : fwrt->trans->cfg->dccm2_len; 835 int i; 836 837 /* SRAM - include stack CCM if driver knows the values for it */ 838 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 839 const struct fw_img *img; 840 841 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 842 return NULL; 843 img = &fwrt->fw->img[fwrt->cur_fw_img]; 844 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 845 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 846 } else { 847 sram_ofs = fwrt->trans->cfg->dccm_offset; 848 sram_len = fwrt->trans->cfg->dccm_len; 849 } 850 851 /* reading RXF/TXF sizes */ 852 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 853 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 854 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 855 856 /* Make room for PRPH registers */ 857 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 858 iwl_fw_prph_handler(fwrt, &prph_len, 859 iwl_fw_get_prph_len); 860 861 if (fwrt->trans->trans_cfg->device_family == 862 IWL_DEVICE_FAMILY_7000 && 863 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 864 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 865 } 866 867 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 868 869 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 870 file_len += sizeof(*dump_data) + sizeof(*dump_info); 871 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 872 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 873 874 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 875 size_t hdr_len = sizeof(*dump_data) + 876 sizeof(struct iwl_fw_error_dump_mem); 877 878 /* Dump SRAM only if no mem_tlvs */ 879 if (!fwrt->fw->dbg.n_mem_tlv) 880 ADD_LEN(file_len, sram_len, hdr_len); 881 882 /* Make room for all mem types that exist */ 883 ADD_LEN(file_len, smem_len, hdr_len); 884 ADD_LEN(file_len, sram2_len, hdr_len); 885 886 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 887 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 888 } 889 890 /* Make room for fw's virtual image pages, if it exists */ 891 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 892 file_len += fwrt->num_of_paging_blk * 893 (sizeof(*dump_data) + 894 sizeof(struct iwl_fw_error_dump_paging) + 895 PAGING_BLOCK_SIZE); 896 897 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 898 file_len += sizeof(*dump_data) + 899 fwrt->trans->cfg->d3_debug_data_length * 2; 900 } 901 902 /* If we only want a monitor dump, reset the file length */ 903 if (fwrt->dump.monitor_only) { 904 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 905 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 906 } 907 908 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 909 fwrt->dump.desc) 910 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 911 fwrt->dump.desc->len; 912 913 dump_file = vzalloc(file_len); 914 if (!dump_file) 915 return NULL; 916 917 fw_error_dump->fwrt_ptr = dump_file; 918 919 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 920 dump_data = (void *)dump_file->data; 921 922 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 923 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 924 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 925 dump_info = (void *)dump_data->data; 926 dump_info->hw_type = 927 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 928 dump_info->hw_step = 929 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 930 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 931 sizeof(dump_info->fw_human_readable)); 932 strncpy(dump_info->dev_human_readable, fwrt->trans->name, 933 sizeof(dump_info->dev_human_readable) - 1); 934 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 935 sizeof(dump_info->bus_human_readable) - 1); 936 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 937 dump_info->lmac_err_id[0] = 938 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 939 if (fwrt->smem_cfg.num_lmacs > 1) 940 dump_info->lmac_err_id[1] = 941 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 942 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 943 944 dump_data = iwl_fw_error_next_data(dump_data); 945 } 946 947 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 948 /* Dump shared memory configuration */ 949 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 950 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 951 dump_smem_cfg = (void *)dump_data->data; 952 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 953 dump_smem_cfg->num_txfifo_entries = 954 cpu_to_le32(mem_cfg->num_txfifo_entries); 955 for (i = 0; i < MAX_NUM_LMAC; i++) { 956 int j; 957 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 958 959 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 960 dump_smem_cfg->lmac[i].txfifo_size[j] = 961 cpu_to_le32(txf_size[j]); 962 dump_smem_cfg->lmac[i].rxfifo1_size = 963 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 964 } 965 dump_smem_cfg->rxfifo2_size = 966 cpu_to_le32(mem_cfg->rxfifo2_size); 967 dump_smem_cfg->internal_txfifo_addr = 968 cpu_to_le32(mem_cfg->internal_txfifo_addr); 969 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 970 dump_smem_cfg->internal_txfifo_size[i] = 971 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 972 } 973 974 dump_data = iwl_fw_error_next_data(dump_data); 975 } 976 977 /* We only dump the FIFOs if the FW is in error state */ 978 if (fifo_len) { 979 iwl_fw_dump_rxf(fwrt, &dump_data); 980 iwl_fw_dump_txf(fwrt, &dump_data); 981 } 982 983 if (radio_len) 984 iwl_read_radio_regs(fwrt, &dump_data); 985 986 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 987 fwrt->dump.desc) { 988 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 989 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 990 fwrt->dump.desc->len); 991 dump_trig = (void *)dump_data->data; 992 memcpy(dump_trig, &fwrt->dump.desc->trig_desc, 993 sizeof(*dump_trig) + fwrt->dump.desc->len); 994 995 dump_data = iwl_fw_error_next_data(dump_data); 996 } 997 998 /* In case we only want monitor dump, skip to dump trasport data */ 999 if (fwrt->dump.monitor_only) 1000 goto out; 1001 1002 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 1003 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 1004 fwrt->fw->dbg.mem_tlv; 1005 1006 if (!fwrt->fw->dbg.n_mem_tlv) 1007 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 1008 IWL_FW_ERROR_DUMP_MEM_SRAM); 1009 1010 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 1011 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 1012 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 1013 1014 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 1015 le32_to_cpu(fw_dbg_mem[i].data_type)); 1016 } 1017 1018 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 1019 fwrt->trans->cfg->smem_offset, 1020 IWL_FW_ERROR_DUMP_MEM_SMEM); 1021 1022 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 1023 fwrt->trans->cfg->dccm2_offset, 1024 IWL_FW_ERROR_DUMP_MEM_SRAM); 1025 } 1026 1027 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 1028 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 1029 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 1030 1031 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 1032 dump_data->len = cpu_to_le32(data_size * 2); 1033 1034 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 1035 1036 kfree(fwrt->dump.d3_debug_data); 1037 fwrt->dump.d3_debug_data = NULL; 1038 1039 iwl_trans_read_mem_bytes(fwrt->trans, addr, 1040 dump_data->data + data_size, 1041 data_size); 1042 1043 dump_data = iwl_fw_error_next_data(dump_data); 1044 } 1045 1046 /* Dump fw's virtual image */ 1047 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1048 iwl_dump_paging(fwrt, &dump_data); 1049 1050 if (prph_len) 1051 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1052 1053 out: 1054 dump_file->file_len = cpu_to_le32(file_len); 1055 return dump_file; 1056 } 1057 1058 /** 1059 * struct iwl_dump_ini_region_data - region data 1060 * @reg_tlv: region TLV 1061 * @dump_data: dump data 1062 */ 1063 struct iwl_dump_ini_region_data { 1064 struct iwl_ucode_tlv *reg_tlv; 1065 struct iwl_fwrt_dump_data *dump_data; 1066 }; 1067 1068 static int iwl_dump_ini_prph_iter(struct iwl_fw_runtime *fwrt, 1069 struct iwl_dump_ini_region_data *reg_data, 1070 void *range_ptr, int idx) 1071 { 1072 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1073 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1074 __le32 *val = range->data; 1075 u32 prph_val; 1076 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1077 le32_to_cpu(reg->dev_addr.offset); 1078 int i; 1079 1080 range->internal_base_addr = cpu_to_le32(addr); 1081 range->range_data_size = reg->dev_addr.size; 1082 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1083 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1084 if (prph_val == 0x5a5a5a5a) 1085 return -EBUSY; 1086 *val++ = cpu_to_le32(prph_val); 1087 } 1088 1089 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1090 } 1091 1092 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1093 struct iwl_dump_ini_region_data *reg_data, 1094 void *range_ptr, int idx) 1095 { 1096 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1097 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1098 __le32 *val = range->data; 1099 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1100 le32_to_cpu(reg->dev_addr.offset); 1101 int i; 1102 1103 range->internal_base_addr = cpu_to_le32(addr); 1104 range->range_data_size = reg->dev_addr.size; 1105 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) 1106 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1107 1108 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1109 } 1110 1111 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1112 struct iwl_dump_ini_region_data *reg_data, 1113 void *range_ptr, int idx) 1114 { 1115 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1116 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1117 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1118 le32_to_cpu(reg->dev_addr.offset); 1119 1120 range->internal_base_addr = cpu_to_le32(addr); 1121 range->range_data_size = reg->dev_addr.size; 1122 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1123 le32_to_cpu(reg->dev_addr.size)); 1124 1125 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1126 } 1127 1128 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1129 void *range_ptr, int idx) 1130 { 1131 /* increase idx by 1 since the pages are from 1 to 1132 * fwrt->num_of_paging_blk + 1 1133 */ 1134 struct page *page = fwrt->fw_paging_db[++idx].fw_paging_block; 1135 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1136 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1137 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1138 1139 range->page_num = cpu_to_le32(idx); 1140 range->range_data_size = cpu_to_le32(page_size); 1141 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1142 DMA_BIDIRECTIONAL); 1143 memcpy(range->data, page_address(page), page_size); 1144 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1145 DMA_BIDIRECTIONAL); 1146 1147 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1148 } 1149 1150 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1151 struct iwl_dump_ini_region_data *reg_data, 1152 void *range_ptr, int idx) 1153 { 1154 struct iwl_fw_ini_error_dump_range *range; 1155 u32 page_size; 1156 1157 if (!fwrt->trans->trans_cfg->gen2) 1158 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, idx); 1159 1160 range = range_ptr; 1161 page_size = fwrt->trans->init_dram.paging[idx].size; 1162 1163 range->page_num = cpu_to_le32(idx); 1164 range->range_data_size = cpu_to_le32(page_size); 1165 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1166 page_size); 1167 1168 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1169 } 1170 1171 static int 1172 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1173 struct iwl_dump_ini_region_data *reg_data, 1174 void *range_ptr, int idx) 1175 { 1176 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1177 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1178 struct iwl_dram_data *frag; 1179 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1180 1181 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx]; 1182 1183 range->dram_base_addr = cpu_to_le64(frag->physical); 1184 range->range_data_size = cpu_to_le32(frag->size); 1185 1186 memcpy(range->data, frag->block, frag->size); 1187 1188 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1189 } 1190 1191 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt, 1192 struct iwl_dump_ini_region_data *reg_data, 1193 void *range_ptr, int idx) 1194 { 1195 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1196 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1197 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr); 1198 1199 range->internal_base_addr = cpu_to_le32(addr); 1200 range->range_data_size = reg->internal_buffer.size; 1201 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1202 le32_to_cpu(reg->internal_buffer.size)); 1203 1204 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1205 } 1206 1207 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1208 struct iwl_dump_ini_region_data *reg_data, int idx) 1209 { 1210 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1211 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1212 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1213 int txf_num = cfg->num_txfifo_entries; 1214 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1215 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]); 1216 1217 if (!idx) { 1218 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) { 1219 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n", 1220 le32_to_cpu(reg->fifos.offset)); 1221 return false; 1222 } 1223 1224 iter->internal_txf = 0; 1225 iter->fifo_size = 0; 1226 iter->fifo = -1; 1227 if (le32_to_cpu(reg->fifos.offset)) 1228 iter->lmac = 1; 1229 else 1230 iter->lmac = 0; 1231 } 1232 1233 if (!iter->internal_txf) { 1234 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1235 iter->fifo_size = 1236 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1237 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1238 return true; 1239 } 1240 iter->fifo--; 1241 } 1242 1243 iter->internal_txf = 1; 1244 1245 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1246 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1247 return false; 1248 1249 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1250 iter->fifo_size = 1251 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1252 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1253 return true; 1254 } 1255 1256 return false; 1257 } 1258 1259 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1260 struct iwl_dump_ini_region_data *reg_data, 1261 void *range_ptr, int idx) 1262 { 1263 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1264 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1265 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1266 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1267 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1268 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1269 u32 registers_size = registers_num * sizeof(*reg_dump); 1270 __le32 *data; 1271 unsigned long flags; 1272 int i; 1273 1274 if (!iwl_ini_txf_iter(fwrt, reg_data, idx)) 1275 return -EIO; 1276 1277 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1278 return -EBUSY; 1279 1280 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1281 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1282 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1283 1284 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1285 1286 /* 1287 * read txf registers. for each register, write to the dump the 1288 * register address and its value 1289 */ 1290 for (i = 0; i < registers_num; i++) { 1291 addr = le32_to_cpu(reg->addrs[i]) + offs; 1292 1293 reg_dump->addr = cpu_to_le32(addr); 1294 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1295 addr)); 1296 1297 reg_dump++; 1298 } 1299 1300 if (reg->fifos.hdr_only) { 1301 range->range_data_size = cpu_to_le32(registers_size); 1302 goto out; 1303 } 1304 1305 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1306 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1307 TXF_WR_PTR + offs); 1308 1309 /* Dummy-read to advance the read pointer to the head */ 1310 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1311 1312 /* Read FIFO */ 1313 addr = TXF_READ_MODIFY_DATA + offs; 1314 data = (void *)reg_dump; 1315 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1316 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1317 1318 out: 1319 iwl_trans_release_nic_access(fwrt->trans, &flags); 1320 1321 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1322 } 1323 1324 struct iwl_ini_rxf_data { 1325 u32 fifo_num; 1326 u32 size; 1327 u32 offset; 1328 }; 1329 1330 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1331 struct iwl_dump_ini_region_data *reg_data, 1332 struct iwl_ini_rxf_data *data) 1333 { 1334 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1335 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]); 1336 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]); 1337 u32 fifo_idx; 1338 1339 if (!data) 1340 return; 1341 1342 memset(data, 0, sizeof(*data)); 1343 1344 if (WARN_ON_ONCE((fid1 && fid2) || (!fid1 && !fid2))) 1345 return; 1346 1347 fifo_idx = ffs(fid1) - 1; 1348 if (fid1 && !WARN_ON_ONCE((~BIT(fifo_idx) & fid1) || 1349 fifo_idx >= MAX_NUM_LMAC)) { 1350 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1351 data->fifo_num = fifo_idx; 1352 return; 1353 } 1354 1355 fifo_idx = ffs(fid2) - 1; 1356 if (fid2 && !WARN_ON_ONCE(fifo_idx != 0)) { 1357 data->size = fwrt->smem_cfg.rxfifo2_size; 1358 data->offset = RXF_DIFF_FROM_PREV; 1359 /* use bit 31 to distinguish between umac and lmac rxf while 1360 * parsing the dump 1361 */ 1362 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1363 return; 1364 } 1365 } 1366 1367 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1368 struct iwl_dump_ini_region_data *reg_data, 1369 void *range_ptr, int idx) 1370 { 1371 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1372 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1373 struct iwl_ini_rxf_data rxf_data; 1374 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1375 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1376 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1377 u32 registers_size = registers_num * sizeof(*reg_dump); 1378 __le32 *data; 1379 unsigned long flags; 1380 int i; 1381 1382 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data); 1383 if (!rxf_data.size) 1384 return -EIO; 1385 1386 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1387 return -EBUSY; 1388 1389 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1390 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1391 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1392 1393 /* 1394 * read rxf registers. for each register, write to the dump the 1395 * register address and its value 1396 */ 1397 for (i = 0; i < registers_num; i++) { 1398 addr = le32_to_cpu(reg->addrs[i]) + offs; 1399 1400 reg_dump->addr = cpu_to_le32(addr); 1401 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1402 addr)); 1403 1404 reg_dump++; 1405 } 1406 1407 if (reg->fifos.hdr_only) { 1408 range->range_data_size = cpu_to_le32(registers_size); 1409 goto out; 1410 } 1411 1412 /* 1413 * region register have absolute value so apply rxf offset after 1414 * reading the registers 1415 */ 1416 offs += rxf_data.offset; 1417 1418 /* Lock fence */ 1419 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1420 /* Set fence pointer to the same place like WR pointer */ 1421 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1422 /* Set fence offset */ 1423 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1424 0x0); 1425 1426 /* Read FIFO */ 1427 addr = RXF_FIFO_RD_FENCE_INC + offs; 1428 data = (void *)reg_dump; 1429 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1430 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1431 1432 out: 1433 iwl_trans_release_nic_access(fwrt->trans, &flags); 1434 1435 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1436 } 1437 1438 static int 1439 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt, 1440 struct iwl_dump_ini_region_data *reg_data, 1441 void *range_ptr, int idx) 1442 { 1443 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1444 struct iwl_fw_ini_region_err_table *err_table = ®->err_table; 1445 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1446 u32 addr = le32_to_cpu(err_table->base_addr) + 1447 le32_to_cpu(err_table->offset); 1448 1449 range->internal_base_addr = cpu_to_le32(addr); 1450 range->range_data_size = err_table->size; 1451 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1452 le32_to_cpu(err_table->size)); 1453 1454 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1455 } 1456 1457 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, 1458 struct iwl_dump_ini_region_data *reg_data, 1459 void *range_ptr, int idx) 1460 { 1461 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1462 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt; 1463 u32 pkt_len; 1464 1465 if (!pkt) 1466 return -EIO; 1467 1468 pkt_len = iwl_rx_packet_payload_len(pkt); 1469 1470 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr)); 1471 range->range_data_size = cpu_to_le32(pkt_len); 1472 1473 memcpy(range->data, pkt->data, pkt_len); 1474 1475 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1476 } 1477 1478 static void * 1479 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1480 struct iwl_dump_ini_region_data *reg_data, 1481 void *data) 1482 { 1483 struct iwl_fw_ini_error_dump *dump = data; 1484 1485 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1486 1487 return dump->ranges; 1488 } 1489 1490 /** 1491 * mask_apply_and_normalize - applies mask on val and normalize the result 1492 * 1493 * The normalization is based on the first set bit in the mask 1494 * 1495 * @val: value 1496 * @mask: mask to apply and to normalize with 1497 */ 1498 static u32 mask_apply_and_normalize(u32 val, u32 mask) 1499 { 1500 return (val & mask) >> (ffs(mask) - 1); 1501 } 1502 1503 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1504 const struct iwl_fw_mon_reg *reg_info) 1505 { 1506 u32 val, offs; 1507 1508 /* The header addresses of DBGCi is calculate as follows: 1509 * DBGC1 address + (0x100 * i) 1510 */ 1511 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100; 1512 1513 if (!reg_info || !reg_info->addr || !reg_info->mask) 1514 return 0; 1515 1516 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); 1517 1518 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); 1519 } 1520 1521 static void * 1522 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, 1523 struct iwl_dump_ini_region_data *reg_data, 1524 struct iwl_fw_ini_monitor_dump *data, 1525 const struct iwl_fw_mon_regs *addrs) 1526 { 1527 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1528 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1529 unsigned long flags; 1530 1531 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) { 1532 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1533 return NULL; 1534 } 1535 1536 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id, 1537 &addrs->write_ptr); 1538 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id, 1539 &addrs->cycle_cnt); 1540 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id, 1541 &addrs->cur_frag); 1542 1543 iwl_trans_release_nic_access(fwrt->trans, &flags); 1544 1545 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1546 1547 return data->ranges; 1548 } 1549 1550 static void * 1551 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1552 struct iwl_dump_ini_region_data *reg_data, 1553 void *data) 1554 { 1555 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1556 1557 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1558 &fwrt->trans->cfg->mon_dram_regs); 1559 } 1560 1561 static void * 1562 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1563 struct iwl_dump_ini_region_data *reg_data, 1564 void *data) 1565 { 1566 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1567 1568 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1569 &fwrt->trans->cfg->mon_smem_regs); 1570 } 1571 1572 static void * 1573 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt, 1574 struct iwl_dump_ini_region_data *reg_data, 1575 void *data) 1576 { 1577 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1578 struct iwl_fw_ini_err_table_dump *dump = data; 1579 1580 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1581 dump->version = reg->err_table.version; 1582 1583 return dump->ranges; 1584 } 1585 1586 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1587 struct iwl_dump_ini_region_data *reg_data) 1588 { 1589 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1590 1591 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1592 } 1593 1594 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1595 struct iwl_dump_ini_region_data *reg_data) 1596 { 1597 if (fwrt->trans->trans_cfg->gen2) 1598 return fwrt->trans->init_dram.paging_cnt; 1599 1600 return fwrt->num_of_paging_blk; 1601 } 1602 1603 static u32 1604 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1605 struct iwl_dump_ini_region_data *reg_data) 1606 { 1607 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1608 struct iwl_fw_mon *fw_mon; 1609 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1610 int i; 1611 1612 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1613 1614 for (i = 0; i < fw_mon->num_frags; i++) { 1615 if (!fw_mon->frags[i].size) 1616 break; 1617 1618 ranges++; 1619 } 1620 1621 return ranges; 1622 } 1623 1624 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1625 struct iwl_dump_ini_region_data *reg_data) 1626 { 1627 u32 num_of_fifos = 0; 1628 1629 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos)) 1630 num_of_fifos++; 1631 1632 return num_of_fifos; 1633 } 1634 1635 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt, 1636 struct iwl_dump_ini_region_data *reg_data) 1637 { 1638 return 1; 1639 } 1640 1641 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1642 struct iwl_dump_ini_region_data *reg_data) 1643 { 1644 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1645 u32 size = le32_to_cpu(reg->dev_addr.size); 1646 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1647 1648 if (!size || !ranges) 1649 return 0; 1650 1651 return sizeof(struct iwl_fw_ini_error_dump) + ranges * 1652 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1653 } 1654 1655 static u32 1656 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1657 struct iwl_dump_ini_region_data *reg_data) 1658 { 1659 int i; 1660 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1661 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1662 1663 if (fwrt->trans->trans_cfg->gen2) { 1664 for (i = 0; i < iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) 1665 size += range_header_len + 1666 fwrt->trans->init_dram.paging[i].size; 1667 } else { 1668 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); 1669 i++) 1670 size += range_header_len + 1671 fwrt->fw_paging_db[i].fw_paging_size; 1672 } 1673 1674 return size; 1675 } 1676 1677 static u32 1678 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1679 struct iwl_dump_ini_region_data *reg_data) 1680 { 1681 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1682 struct iwl_fw_mon *fw_mon; 1683 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1684 int i; 1685 1686 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1687 1688 for (i = 0; i < fw_mon->num_frags; i++) { 1689 struct iwl_dram_data *frag = &fw_mon->frags[i]; 1690 1691 if (!frag->size) 1692 break; 1693 1694 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size; 1695 } 1696 1697 if (size) 1698 size += sizeof(struct iwl_fw_ini_monitor_dump); 1699 1700 return size; 1701 } 1702 1703 static u32 1704 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 1705 struct iwl_dump_ini_region_data *reg_data) 1706 { 1707 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1708 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 1709 u32 alloc_id = le32_to_cpu(reg->internal_buffer.alloc_id), size; 1710 1711 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id]; 1712 if (le32_to_cpu(fw_mon_cfg->buf_location) != 1713 IWL_FW_INI_LOCATION_SRAM_PATH) 1714 return 0; 1715 1716 size = le32_to_cpu(reg->internal_buffer.size); 1717 if (!size) 1718 return 0; 1719 1720 size += sizeof(struct iwl_fw_ini_monitor_dump) + 1721 sizeof(struct iwl_fw_ini_error_dump_range); 1722 1723 return size; 1724 } 1725 1726 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1727 struct iwl_dump_ini_region_data *reg_data) 1728 { 1729 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1730 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1731 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1732 u32 size = 0; 1733 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 1734 registers_num * 1735 sizeof(struct iwl_fw_ini_error_dump_register); 1736 1737 while (iwl_ini_txf_iter(fwrt, reg_data, size)) { 1738 size += fifo_hdr; 1739 if (!reg->fifos.hdr_only) 1740 size += iter->fifo_size; 1741 } 1742 1743 if (!size) 1744 return 0; 1745 1746 return size + sizeof(struct iwl_fw_ini_error_dump); 1747 } 1748 1749 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1750 struct iwl_dump_ini_region_data *reg_data) 1751 { 1752 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1753 struct iwl_ini_rxf_data rx_data; 1754 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1755 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 1756 sizeof(struct iwl_fw_ini_error_dump_range) + 1757 registers_num * sizeof(struct iwl_fw_ini_error_dump_register); 1758 1759 if (reg->fifos.hdr_only) 1760 return size; 1761 1762 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data); 1763 size += rx_data.size; 1764 1765 return size; 1766 } 1767 1768 static u32 1769 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt, 1770 struct iwl_dump_ini_region_data *reg_data) 1771 { 1772 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1773 u32 size = le32_to_cpu(reg->err_table.size); 1774 1775 if (size) 1776 size += sizeof(struct iwl_fw_ini_err_table_dump) + 1777 sizeof(struct iwl_fw_ini_error_dump_range); 1778 1779 return size; 1780 } 1781 1782 static u32 1783 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt, 1784 struct iwl_dump_ini_region_data *reg_data) 1785 { 1786 u32 size = 0; 1787 1788 if (!reg_data->dump_data->fw_pkt) 1789 return 0; 1790 1791 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt); 1792 if (size) 1793 size += sizeof(struct iwl_fw_ini_error_dump) + 1794 sizeof(struct iwl_fw_ini_error_dump_range); 1795 1796 return size; 1797 } 1798 1799 /** 1800 * struct iwl_dump_ini_mem_ops - ini memory dump operations 1801 * @get_num_of_ranges: returns the number of memory ranges in the region. 1802 * @get_size: returns the total size of the region. 1803 * @fill_mem_hdr: fills region type specific headers and returns pointer to 1804 * the first range or NULL if failed to fill headers. 1805 * @fill_range: copies a given memory range into the dump. 1806 * Returns the size of the range or negative error value otherwise. 1807 */ 1808 struct iwl_dump_ini_mem_ops { 1809 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 1810 struct iwl_dump_ini_region_data *reg_data); 1811 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 1812 struct iwl_dump_ini_region_data *reg_data); 1813 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 1814 struct iwl_dump_ini_region_data *reg_data, 1815 void *data); 1816 int (*fill_range)(struct iwl_fw_runtime *fwrt, 1817 struct iwl_dump_ini_region_data *reg_data, 1818 void *range, int idx); 1819 }; 1820 1821 /** 1822 * iwl_dump_ini_mem 1823 * 1824 * Creates a dump tlv and copy a memory region into it. 1825 * Returns the size of the current dump tlv or 0 if failed 1826 * 1827 * @fwrt: fw runtime struct 1828 * @list: list to add the dump tlv to 1829 * @reg: memory region 1830 * @ops: memory dump operations 1831 */ 1832 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 1833 struct iwl_dump_ini_region_data *reg_data, 1834 const struct iwl_dump_ini_mem_ops *ops) 1835 { 1836 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1837 struct iwl_fw_ini_dump_entry *entry; 1838 struct iwl_fw_error_dump_data *tlv; 1839 struct iwl_fw_ini_error_dump_header *header; 1840 u32 type = le32_to_cpu(reg->type), id = le32_to_cpu(reg->id); 1841 u32 num_of_ranges, i, size; 1842 void *range; 1843 1844 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 1845 !ops->fill_range) 1846 return 0; 1847 1848 size = ops->get_size(fwrt, reg_data); 1849 if (!size) 1850 return 0; 1851 1852 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size); 1853 if (!entry) 1854 return 0; 1855 1856 entry->size = sizeof(*tlv) + size; 1857 1858 tlv = (void *)entry->data; 1859 tlv->type = reg->type; 1860 tlv->len = cpu_to_le32(size); 1861 1862 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: id=%d, type=%d\n", id, 1863 type); 1864 1865 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data); 1866 1867 header = (void *)tlv->data; 1868 header->region_id = reg->id; 1869 header->num_of_ranges = cpu_to_le32(num_of_ranges); 1870 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME); 1871 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME); 1872 1873 range = ops->fill_mem_hdr(fwrt, reg_data, header); 1874 if (!range) { 1875 IWL_ERR(fwrt, 1876 "WRT: Failed to fill region header: id=%d, type=%d\n", 1877 id, type); 1878 goto out_err; 1879 } 1880 1881 for (i = 0; i < num_of_ranges; i++) { 1882 int range_size = ops->fill_range(fwrt, reg_data, range, i); 1883 1884 if (range_size < 0) { 1885 IWL_ERR(fwrt, 1886 "WRT: Failed to dump region: id=%d, type=%d\n", 1887 id, type); 1888 goto out_err; 1889 } 1890 range = range + range_size; 1891 } 1892 1893 list_add_tail(&entry->list, list); 1894 1895 return entry->size; 1896 1897 out_err: 1898 vfree(entry); 1899 1900 return 0; 1901 } 1902 1903 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 1904 struct iwl_fw_ini_trigger_tlv *trigger, 1905 struct list_head *list) 1906 { 1907 struct iwl_fw_ini_dump_entry *entry; 1908 struct iwl_fw_error_dump_data *tlv; 1909 struct iwl_fw_ini_dump_info *dump; 1910 struct iwl_dbg_tlv_node *node; 1911 struct iwl_fw_ini_dump_cfg_name *cfg_name; 1912 u32 size = sizeof(*tlv) + sizeof(*dump); 1913 u32 num_of_cfg_names = 0; 1914 1915 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 1916 size += sizeof(*cfg_name); 1917 num_of_cfg_names++; 1918 } 1919 1920 entry = vzalloc(sizeof(*entry) + size); 1921 if (!entry) 1922 return 0; 1923 1924 entry->size = size; 1925 1926 tlv = (void *)entry->data; 1927 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 1928 tlv->len = cpu_to_le32(size - sizeof(*tlv)); 1929 1930 dump = (void *)tlv->data; 1931 1932 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 1933 dump->time_point = trigger->time_point; 1934 dump->trigger_reason = trigger->trigger_reason; 1935 dump->external_cfg_state = 1936 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 1937 1938 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 1939 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 1940 1941 dump->hw_step = cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 1942 dump->hw_type = cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 1943 1944 dump->rf_id_flavor = 1945 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 1946 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 1947 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 1948 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 1949 1950 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 1951 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 1952 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 1953 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 1954 1955 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest); 1956 dump->regions_mask = trigger->regions_mask; 1957 1958 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 1959 memcpy(dump->build_tag, fwrt->fw->human_readable, 1960 sizeof(dump->build_tag)); 1961 1962 cfg_name = dump->cfg_names; 1963 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names); 1964 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 1965 struct iwl_fw_ini_debug_info_tlv *debug_info = 1966 (void *)node->tlv.data; 1967 1968 cfg_name->image_type = debug_info->image_type; 1969 cfg_name->cfg_name_len = 1970 cpu_to_le32(IWL_FW_INI_MAX_CFG_NAME); 1971 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name, 1972 sizeof(cfg_name->cfg_name)); 1973 cfg_name++; 1974 } 1975 1976 /* add dump info TLV to the beginning of the list since it needs to be 1977 * the first TLV in the dump 1978 */ 1979 list_add(&entry->list, list); 1980 1981 return entry->size; 1982 } 1983 1984 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 1985 [IWL_FW_INI_REGION_INVALID] = {}, 1986 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 1987 .get_num_of_ranges = iwl_dump_ini_single_range, 1988 .get_size = iwl_dump_ini_mon_smem_get_size, 1989 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 1990 .fill_range = iwl_dump_ini_mon_smem_iter, 1991 }, 1992 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 1993 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 1994 .get_size = iwl_dump_ini_mon_dram_get_size, 1995 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 1996 .fill_range = iwl_dump_ini_mon_dram_iter, 1997 }, 1998 [IWL_FW_INI_REGION_TXF] = { 1999 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 2000 .get_size = iwl_dump_ini_txf_get_size, 2001 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2002 .fill_range = iwl_dump_ini_txf_iter, 2003 }, 2004 [IWL_FW_INI_REGION_RXF] = { 2005 .get_num_of_ranges = iwl_dump_ini_single_range, 2006 .get_size = iwl_dump_ini_rxf_get_size, 2007 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2008 .fill_range = iwl_dump_ini_rxf_iter, 2009 }, 2010 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 2011 .get_num_of_ranges = iwl_dump_ini_single_range, 2012 .get_size = iwl_dump_ini_err_table_get_size, 2013 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2014 .fill_range = iwl_dump_ini_err_table_iter, 2015 }, 2016 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 2017 .get_num_of_ranges = iwl_dump_ini_single_range, 2018 .get_size = iwl_dump_ini_err_table_get_size, 2019 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2020 .fill_range = iwl_dump_ini_err_table_iter, 2021 }, 2022 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = { 2023 .get_num_of_ranges = iwl_dump_ini_single_range, 2024 .get_size = iwl_dump_ini_fw_pkt_get_size, 2025 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2026 .fill_range = iwl_dump_ini_fw_pkt_iter, 2027 }, 2028 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 2029 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2030 .get_size = iwl_dump_ini_mem_get_size, 2031 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2032 .fill_range = iwl_dump_ini_dev_mem_iter, 2033 }, 2034 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 2035 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2036 .get_size = iwl_dump_ini_mem_get_size, 2037 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2038 .fill_range = iwl_dump_ini_prph_iter, 2039 }, 2040 [IWL_FW_INI_REGION_PERIPHERY_PHY] = {}, 2041 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 2042 [IWL_FW_INI_REGION_PAGING] = { 2043 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2044 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 2045 .get_size = iwl_dump_ini_paging_get_size, 2046 .fill_range = iwl_dump_ini_paging_iter, 2047 }, 2048 [IWL_FW_INI_REGION_CSR] = { 2049 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2050 .get_size = iwl_dump_ini_mem_get_size, 2051 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2052 .fill_range = iwl_dump_ini_csr_iter, 2053 }, 2054 [IWL_FW_INI_REGION_DRAM_IMR] = {}, 2055 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = {}, 2056 }; 2057 2058 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 2059 struct iwl_fwrt_dump_data *dump_data, 2060 struct list_head *list) 2061 { 2062 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2063 struct iwl_dump_ini_region_data reg_data = { 2064 .dump_data = dump_data, 2065 }; 2066 int i; 2067 u32 size = 0; 2068 u64 regions_mask = le64_to_cpu(trigger->regions_mask); 2069 2070 for (i = 0; i < 64; i++) { 2071 u32 reg_type; 2072 struct iwl_fw_ini_region_tlv *reg; 2073 2074 if (!(BIT_ULL(i) & regions_mask)) 2075 continue; 2076 2077 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2078 if (!reg_data.reg_tlv) { 2079 IWL_WARN(fwrt, 2080 "WRT: Unassigned region id %d, skipping\n", i); 2081 continue; 2082 } 2083 2084 reg = (void *)reg_data.reg_tlv->data; 2085 reg_type = le32_to_cpu(reg->type); 2086 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 2087 continue; 2088 2089 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2090 &iwl_dump_ini_region_ops[reg_type]); 2091 } 2092 2093 if (size) 2094 size += iwl_dump_ini_info(fwrt, trigger, list); 2095 2096 return size; 2097 } 2098 2099 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt, 2100 struct iwl_fw_ini_trigger_tlv *trig) 2101 { 2102 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2103 u32 usec = le32_to_cpu(trig->ignore_consec); 2104 2105 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 2106 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 2107 tp_id >= IWL_FW_INI_TIME_POINT_NUM || 2108 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec)) 2109 return false; 2110 2111 return true; 2112 } 2113 2114 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 2115 struct iwl_fwrt_dump_data *dump_data, 2116 struct list_head *list) 2117 { 2118 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2119 struct iwl_fw_ini_dump_entry *entry; 2120 struct iwl_fw_ini_dump_file_hdr *hdr; 2121 u32 size; 2122 2123 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) || 2124 !le64_to_cpu(trigger->regions_mask)) 2125 return 0; 2126 2127 entry = vzalloc(sizeof(*entry) + sizeof(*hdr)); 2128 if (!entry) 2129 return 0; 2130 2131 entry->size = sizeof(*hdr); 2132 2133 size = iwl_dump_ini_trigger(fwrt, dump_data, list); 2134 if (!size) { 2135 vfree(entry); 2136 return 0; 2137 } 2138 2139 hdr = (void *)entry->data; 2140 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2141 hdr->file_len = cpu_to_le32(size + entry->size); 2142 2143 list_add(&entry->list, list); 2144 2145 return le32_to_cpu(hdr->file_len); 2146 } 2147 2148 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt) 2149 { 2150 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2151 struct iwl_fw_error_dump_file *dump_file; 2152 struct scatterlist *sg_dump_data; 2153 u32 file_len; 2154 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2155 2156 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump); 2157 if (!dump_file) 2158 goto out; 2159 2160 if (fwrt->dump.monitor_only) 2161 dump_mask &= IWL_FW_ERROR_DUMP_FW_MONITOR; 2162 2163 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask); 2164 file_len = le32_to_cpu(dump_file->file_len); 2165 fw_error_dump.fwrt_len = file_len; 2166 2167 if (fw_error_dump.trans_ptr) { 2168 file_len += fw_error_dump.trans_ptr->len; 2169 dump_file->file_len = cpu_to_le32(file_len); 2170 } 2171 2172 sg_dump_data = alloc_sgtable(file_len); 2173 if (sg_dump_data) { 2174 sg_pcopy_from_buffer(sg_dump_data, 2175 sg_nents(sg_dump_data), 2176 fw_error_dump.fwrt_ptr, 2177 fw_error_dump.fwrt_len, 0); 2178 if (fw_error_dump.trans_ptr) 2179 sg_pcopy_from_buffer(sg_dump_data, 2180 sg_nents(sg_dump_data), 2181 fw_error_dump.trans_ptr->data, 2182 fw_error_dump.trans_ptr->len, 2183 fw_error_dump.fwrt_len); 2184 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2185 GFP_KERNEL); 2186 } 2187 vfree(fw_error_dump.fwrt_ptr); 2188 vfree(fw_error_dump.trans_ptr); 2189 2190 out: 2191 iwl_fw_free_dump_desc(fwrt); 2192 } 2193 2194 static void iwl_dump_ini_list_free(struct list_head *list) 2195 { 2196 while (!list_empty(list)) { 2197 struct iwl_fw_ini_dump_entry *entry = 2198 list_entry(list->next, typeof(*entry), list); 2199 2200 list_del(&entry->list); 2201 vfree(entry); 2202 } 2203 } 2204 2205 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data) 2206 { 2207 dump_data->trig = NULL; 2208 kfree(dump_data->fw_pkt); 2209 dump_data->fw_pkt = NULL; 2210 } 2211 2212 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 2213 struct iwl_fwrt_dump_data *dump_data) 2214 { 2215 struct list_head dump_list = LIST_HEAD_INIT(dump_list); 2216 struct scatterlist *sg_dump_data; 2217 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list); 2218 2219 if (!file_len) 2220 goto out; 2221 2222 sg_dump_data = alloc_sgtable(file_len); 2223 if (sg_dump_data) { 2224 struct iwl_fw_ini_dump_entry *entry; 2225 int sg_entries = sg_nents(sg_dump_data); 2226 u32 offs = 0; 2227 2228 list_for_each_entry(entry, &dump_list, list) { 2229 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2230 entry->data, entry->size, offs); 2231 offs += entry->size; 2232 } 2233 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2234 GFP_KERNEL); 2235 } 2236 iwl_dump_ini_list_free(&dump_list); 2237 2238 out: 2239 iwl_fw_error_dump_data_free(dump_data); 2240 } 2241 2242 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2243 .trig_desc = { 2244 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2245 }, 2246 }; 2247 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2248 2249 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2250 const struct iwl_fw_dump_desc *desc, 2251 bool monitor_only, 2252 unsigned int delay) 2253 { 2254 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2255 iwl_fw_free_dump_desc(fwrt); 2256 return 0; 2257 } 2258 2259 /* use wks[0] since dump flow prior to ini does not need to support 2260 * consecutive triggers collection 2261 */ 2262 if (test_and_set_bit(fwrt->dump.wks[0].idx, &fwrt->dump.active_wks)) 2263 return -EBUSY; 2264 2265 if (WARN_ON(fwrt->dump.desc)) 2266 iwl_fw_free_dump_desc(fwrt); 2267 2268 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2269 le32_to_cpu(desc->trig_desc.type)); 2270 2271 fwrt->dump.desc = desc; 2272 fwrt->dump.monitor_only = monitor_only; 2273 2274 schedule_delayed_work(&fwrt->dump.wks[0].wk, usecs_to_jiffies(delay)); 2275 2276 return 0; 2277 } 2278 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2279 2280 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2281 enum iwl_fw_dbg_trigger trig_type) 2282 { 2283 int ret; 2284 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2285 2286 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2287 return -EIO; 2288 2289 iwl_dump_error_desc = kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2290 if (!iwl_dump_error_desc) 2291 return -ENOMEM; 2292 2293 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2294 iwl_dump_error_desc->len = 0; 2295 2296 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, false, 0); 2297 if (ret) 2298 kfree(iwl_dump_error_desc); 2299 else 2300 iwl_trans_sync_nmi(fwrt->trans); 2301 2302 return ret; 2303 } 2304 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2305 2306 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2307 enum iwl_fw_dbg_trigger trig, 2308 const char *str, size_t len, 2309 struct iwl_fw_dbg_trigger_tlv *trigger) 2310 { 2311 struct iwl_fw_dump_desc *desc; 2312 unsigned int delay = 0; 2313 bool monitor_only = false; 2314 2315 if (trigger) { 2316 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2317 2318 if (!le16_to_cpu(trigger->occurrences)) 2319 return 0; 2320 2321 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2322 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2323 trig); 2324 iwl_force_nmi(fwrt->trans); 2325 return 0; 2326 } 2327 2328 trigger->occurrences = cpu_to_le16(occurrences); 2329 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2330 2331 /* convert msec to usec */ 2332 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2333 } 2334 2335 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 2336 if (!desc) 2337 return -ENOMEM; 2338 2339 2340 desc->len = len; 2341 desc->trig_desc.type = cpu_to_le32(trig); 2342 memcpy(desc->trig_desc.data, str, len); 2343 2344 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2345 } 2346 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2347 2348 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 2349 struct iwl_fwrt_dump_data *dump_data) 2350 { 2351 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig; 2352 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2353 u32 occur, delay; 2354 unsigned long idx; 2355 2356 if (!iwl_fw_ini_trigger_on(fwrt, trig)) { 2357 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 2358 tp_id); 2359 return -EINVAL; 2360 } 2361 2362 delay = le32_to_cpu(trig->dump_delay); 2363 occur = le32_to_cpu(trig->occurrences); 2364 if (!occur) 2365 return 0; 2366 2367 trig->occurrences = cpu_to_le32(--occur); 2368 2369 /* Check there is an available worker. 2370 * ffz return value is undefined if no zero exists, 2371 * so check against ~0UL first. 2372 */ 2373 if (fwrt->dump.active_wks == ~0UL) 2374 return -EBUSY; 2375 2376 idx = ffz(fwrt->dump.active_wks); 2377 2378 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2379 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2380 return -EBUSY; 2381 2382 fwrt->dump.wks[idx].dump_data = *dump_data; 2383 2384 IWL_WARN(fwrt, "WRT: Collecting data: ini trigger %d fired.\n", tp_id); 2385 2386 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay)); 2387 2388 return 0; 2389 } 2390 2391 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2392 struct iwl_fw_dbg_trigger_tlv *trigger, 2393 const char *fmt, ...) 2394 { 2395 int ret, len = 0; 2396 char buf[64]; 2397 2398 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2399 return 0; 2400 2401 if (fmt) { 2402 va_list ap; 2403 2404 buf[sizeof(buf) - 1] = '\0'; 2405 2406 va_start(ap, fmt); 2407 vsnprintf(buf, sizeof(buf), fmt, ap); 2408 va_end(ap); 2409 2410 /* check for truncation */ 2411 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2412 buf[sizeof(buf) - 1] = '\0'; 2413 2414 len = strlen(buf) + 1; 2415 } 2416 2417 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2418 trigger); 2419 2420 if (ret) 2421 return ret; 2422 2423 return 0; 2424 } 2425 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2426 2427 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2428 { 2429 u8 *ptr; 2430 int ret; 2431 int i; 2432 2433 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2434 "Invalid configuration %d\n", conf_id)) 2435 return -EINVAL; 2436 2437 /* EARLY START - firmware's configuration is hard coded */ 2438 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2439 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2440 conf_id == FW_DBG_START_FROM_ALIVE) 2441 return 0; 2442 2443 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2444 return -EINVAL; 2445 2446 if (fwrt->dump.conf != FW_DBG_INVALID) 2447 IWL_WARN(fwrt, "FW already configured (%d) - re-configuring\n", 2448 fwrt->dump.conf); 2449 2450 /* Send all HCMDs for configuring the FW debug */ 2451 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2452 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2453 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2454 struct iwl_host_cmd hcmd = { 2455 .id = cmd->id, 2456 .len = { le16_to_cpu(cmd->len), }, 2457 .data = { cmd->data, }, 2458 }; 2459 2460 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2461 if (ret) 2462 return ret; 2463 2464 ptr += sizeof(*cmd); 2465 ptr += le16_to_cpu(cmd->len); 2466 } 2467 2468 fwrt->dump.conf = conf_id; 2469 2470 return 0; 2471 } 2472 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2473 2474 /* this function assumes dump_start was called beforehand and dump_end will be 2475 * called afterwards 2476 */ 2477 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 2478 { 2479 struct iwl_fw_dbg_params params = {0}; 2480 2481 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 2482 return; 2483 2484 if (fwrt->ops && fwrt->ops->fw_running && 2485 !fwrt->ops->fw_running(fwrt->ops_ctx)) { 2486 IWL_ERR(fwrt, "Firmware not running - cannot dump error\n"); 2487 iwl_fw_free_dump_desc(fwrt); 2488 goto out; 2489 } 2490 2491 /* there's no point in fw dump if the bus is dead */ 2492 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 2493 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 2494 goto out; 2495 } 2496 2497 if (iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true)) { 2498 IWL_ERR(fwrt, "Failed to stop DBGC recording, aborting dump\n"); 2499 goto out; 2500 } 2501 2502 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 2503 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2504 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 2505 else 2506 iwl_fw_error_dump(fwrt); 2507 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 2508 2509 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 2510 2511 out: 2512 clear_bit(wk_idx, &fwrt->dump.active_wks); 2513 } 2514 2515 void iwl_fw_error_dump_wk(struct work_struct *work) 2516 { 2517 struct iwl_fwrt_wk_data *wks = 2518 container_of(work, typeof(*wks), wk.work); 2519 struct iwl_fw_runtime *fwrt = 2520 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]); 2521 2522 /* assumes the op mode mutex is locked in dump_start since 2523 * iwl_fw_dbg_collect_sync can't run in parallel 2524 */ 2525 if (fwrt->ops && fwrt->ops->dump_start && 2526 fwrt->ops->dump_start(fwrt->ops_ctx)) 2527 return; 2528 2529 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 2530 2531 if (fwrt->ops && fwrt->ops->dump_end) 2532 fwrt->ops->dump_end(fwrt->ops_ctx); 2533 } 2534 2535 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 2536 { 2537 const struct iwl_cfg *cfg = fwrt->trans->cfg; 2538 2539 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 2540 return; 2541 2542 if (!fwrt->dump.d3_debug_data) { 2543 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 2544 GFP_KERNEL); 2545 if (!fwrt->dump.d3_debug_data) { 2546 IWL_ERR(fwrt, 2547 "failed to allocate memory for D3 debug data\n"); 2548 return; 2549 } 2550 } 2551 2552 /* if the buffer holds previous debug data it is overwritten */ 2553 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 2554 fwrt->dump.d3_debug_data, 2555 cfg->d3_debug_data_length); 2556 } 2557 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 2558 2559 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 2560 { 2561 int i; 2562 2563 iwl_dbg_tlv_del_timers(fwrt->trans); 2564 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 2565 iwl_fw_dbg_collect_sync(fwrt, i); 2566 2567 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 2568 } 2569 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 2570 2571 #define FSEQ_REG(x) { .addr = (x), .str = #x, } 2572 2573 void iwl_fw_error_print_fseq_regs(struct iwl_fw_runtime *fwrt) 2574 { 2575 struct iwl_trans *trans = fwrt->trans; 2576 unsigned long flags; 2577 int i; 2578 struct { 2579 u32 addr; 2580 const char *str; 2581 } fseq_regs[] = { 2582 FSEQ_REG(FSEQ_ERROR_CODE), 2583 FSEQ_REG(FSEQ_TOP_INIT_VERSION), 2584 FSEQ_REG(FSEQ_CNVIO_INIT_VERSION), 2585 FSEQ_REG(FSEQ_OTP_VERSION), 2586 FSEQ_REG(FSEQ_TOP_CONTENT_VERSION), 2587 FSEQ_REG(FSEQ_ALIVE_TOKEN), 2588 FSEQ_REG(FSEQ_CNVI_ID), 2589 FSEQ_REG(FSEQ_CNVR_ID), 2590 FSEQ_REG(CNVI_AUX_MISC_CHIP), 2591 FSEQ_REG(CNVR_AUX_MISC_CHIP), 2592 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM), 2593 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR), 2594 }; 2595 2596 if (!iwl_trans_grab_nic_access(trans, &flags)) 2597 return; 2598 2599 IWL_ERR(fwrt, "Fseq Registers:\n"); 2600 2601 for (i = 0; i < ARRAY_SIZE(fseq_regs); i++) 2602 IWL_ERR(fwrt, "0x%08X | %s\n", 2603 iwl_read_prph_no_grab(trans, fseq_regs[i].addr), 2604 fseq_regs[i].str); 2605 2606 iwl_trans_release_nic_access(trans, &flags); 2607 } 2608 IWL_EXPORT_SYMBOL(iwl_fw_error_print_fseq_regs); 2609 2610 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 2611 { 2612 struct iwl_dbg_suspend_resume_cmd cmd = { 2613 .operation = suspend ? 2614 cpu_to_le32(DBGC_SUSPEND_CMD) : 2615 cpu_to_le32(DBGC_RESUME_CMD), 2616 }; 2617 struct iwl_host_cmd hcmd = { 2618 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 2619 .data[0] = &cmd, 2620 .len[0] = sizeof(cmd), 2621 }; 2622 2623 return iwl_trans_send_cmd(trans, &hcmd); 2624 } 2625 2626 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 2627 struct iwl_fw_dbg_params *params) 2628 { 2629 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2630 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2631 return; 2632 } 2633 2634 if (params) { 2635 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 2636 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 2637 } 2638 2639 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 2640 /* wait for the DBGC to finish writing the internal buffer to DRAM to 2641 * avoid halting the HW while writing 2642 */ 2643 usleep_range(700, 1000); 2644 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 2645 } 2646 2647 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 2648 struct iwl_fw_dbg_params *params) 2649 { 2650 if (!params) 2651 return -EIO; 2652 2653 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2654 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2655 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2656 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2657 } else { 2658 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 2659 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 2660 } 2661 2662 return 0; 2663 } 2664 2665 int iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 2666 struct iwl_fw_dbg_params *params, 2667 bool stop) 2668 { 2669 int ret = 0; 2670 2671 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 2672 return 0; 2673 2674 if (fw_has_capa(&fwrt->fw->ucode_capa, 2675 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) 2676 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 2677 else if (stop) 2678 iwl_fw_dbg_stop_recording(fwrt->trans, params); 2679 else 2680 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 2681 #ifdef CONFIG_IWLWIFI_DEBUGFS 2682 if (!ret) { 2683 if (stop) 2684 fwrt->trans->dbg.rec_on = false; 2685 else 2686 iwl_fw_set_dbg_rec_on(fwrt); 2687 } 2688 #endif 2689 2690 return ret; 2691 } 2692 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 2693