1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 Intel Deutschland GmbH 11 * Copyright (C) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 Intel Deutschland GmbH 34 * Copyright (C) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 *****************************************************************************/ 63 64 #ifndef __iwl_prph_h__ 65 #define __iwl_prph_h__ 66 #include <linux/bitfield.h> 67 68 /* 69 * Registers in this file are internal, not PCI bus memory mapped. 70 * Driver accesses these via HBUS_TARG_PRPH_* registers. 71 */ 72 #define PRPH_BASE (0x00000) 73 #define PRPH_END (0xFFFFF) 74 75 /* APMG (power management) constants */ 76 #define APMG_BASE (PRPH_BASE + 0x3000) 77 #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000) 78 #define APMG_CLK_EN_REG (APMG_BASE + 0x0004) 79 #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008) 80 #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c) 81 #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010) 82 #define APMG_RFKILL_REG (APMG_BASE + 0x0014) 83 #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c) 84 #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020) 85 #define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058) 86 #define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C) 87 88 #define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 89 #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 90 #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 91 92 #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 93 #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 94 #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 95 #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 96 #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 97 #define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 98 #define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 99 100 #define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200) 101 #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 102 #define APMG_PCIDEV_STT_VAL_WAKE_ME (0x00004000) 103 104 #define APMG_RTC_INT_STT_RFKILL (0x10000000) 105 106 /* Device system time */ 107 #define DEVICE_SYSTEM_TIME_REG 0xA0206C 108 109 /* Device NMI register and value for 8000 family and lower hw's */ 110 #define DEVICE_SET_NMI_REG 0x00a01c30 111 #define DEVICE_SET_NMI_VAL_DRV BIT(7) 112 /* Device NMI register and value for 9000 family and above hw's */ 113 #define UREG_NIC_SET_NMI_DRIVER 0x00a05c10 114 #define UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER_MSK 0xff000000 115 116 /* Shared registers (0x0..0x3ff, via target indirect or periphery */ 117 #define SHR_BASE 0x00a10000 118 119 /* Shared GP1 register */ 120 #define SHR_APMG_GP1_REG 0x01dc 121 #define SHR_APMG_GP1_REG_PRPH (SHR_BASE + SHR_APMG_GP1_REG) 122 #define SHR_APMG_GP1_WF_XTAL_LP_EN 0x00000004 123 #define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x80000000 124 125 /* Shared DL_CFG register */ 126 #define SHR_APMG_DL_CFG_REG 0x01c4 127 #define SHR_APMG_DL_CFG_REG_PRPH (SHR_BASE + SHR_APMG_DL_CFG_REG) 128 #define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c0 129 #define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x00000080 130 #define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x00000100 131 132 /* Shared APMG_XTAL_CFG register */ 133 #define SHR_APMG_XTAL_CFG_REG 0x1c0 134 #define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x80000000 135 136 /* 137 * Device reset for family 8000 138 * write to bit 24 in order to reset the CPU 139 */ 140 #define RELEASE_CPU_RESET (0x300C) 141 #define RELEASE_CPU_RESET_BIT BIT(24) 142 143 /***************************************************************************** 144 * 7000/3000 series SHR DTS addresses * 145 *****************************************************************************/ 146 147 #define SHR_MISC_WFM_DTS_EN (0x00a10024) 148 #define DTSC_CFG_MODE (0x00a10604) 149 #define DTSC_VREF_AVG (0x00a10648) 150 #define DTSC_VREF5_AVG (0x00a1064c) 151 #define DTSC_CFG_MODE_PERIODIC (0x2) 152 #define DTSC_PTAT_AVG (0x00a10650) 153 154 155 /** 156 * Tx Scheduler 157 * 158 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 159 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 160 * host DRAM. It steers each frame's Tx command (which contains the frame 161 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 162 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 163 * but one DMA channel may take input from several queues. 164 * 165 * Tx DMA FIFOs have dedicated purposes. 166 * 167 * For 5000 series and up, they are used differently 168 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 169 * 170 * 0 -- EDCA BK (background) frames, lowest priority 171 * 1 -- EDCA BE (best effort) frames, normal priority 172 * 2 -- EDCA VI (video) frames, higher priority 173 * 3 -- EDCA VO (voice) and management frames, highest priority 174 * 4 -- unused 175 * 5 -- unused 176 * 6 -- unused 177 * 7 -- Commands 178 * 179 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 180 * In addition, driver can map the remaining queues to Tx DMA/FIFO 181 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 182 * 183 * The driver sets up each queue to work in one of two modes: 184 * 185 * 1) Scheduler-Ack, in which the scheduler automatically supports a 186 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 187 * contains TFDs for a unique combination of Recipient Address (RA) 188 * and Traffic Identifier (TID), that is, traffic of a given 189 * Quality-Of-Service (QOS) priority, destined for a single station. 190 * 191 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 192 * each frame within the BA window, including whether it's been transmitted, 193 * and whether it's been acknowledged by the receiving station. The device 194 * automatically processes block-acks received from the receiving STA, 195 * and reschedules un-acked frames to be retransmitted (successful 196 * Tx completion may end up being out-of-order). 197 * 198 * The driver must maintain the queue's Byte Count table in host DRAM 199 * for this mode. 200 * This mode does not support fragmentation. 201 * 202 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 203 * The device may automatically retry Tx, but will retry only one frame 204 * at a time, until receiving ACK from receiving station, or reaching 205 * retry limit and giving up. 206 * 207 * The command queue (#4/#9) must use this mode! 208 * This mode does not require use of the Byte Count table in host DRAM. 209 * 210 * Driver controls scheduler operation via 3 means: 211 * 1) Scheduler registers 212 * 2) Shared scheduler data base in internal SRAM 213 * 3) Shared data in host DRAM 214 * 215 * Initialization: 216 * 217 * When loading, driver should allocate memory for: 218 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 219 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 220 * (1024 bytes for each queue). 221 * 222 * After receiving "Alive" response from uCode, driver must initialize 223 * the scheduler (especially for queue #4/#9, the command queue, otherwise 224 * the driver can't issue commands!): 225 */ 226 #define SCD_MEM_LOWER_BOUND (0x0000) 227 228 /** 229 * Max Tx window size is the max number of contiguous TFDs that the scheduler 230 * can keep track of at one time when creating block-ack chains of frames. 231 * Note that "64" matches the number of ack bits in a block-ack packet. 232 */ 233 #define SCD_WIN_SIZE 64 234 #define SCD_FRAME_LIMIT 64 235 236 #define SCD_TXFIFO_POS_TID (0) 237 #define SCD_TXFIFO_POS_RA (4) 238 #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 239 240 /* agn SCD */ 241 #define SCD_QUEUE_STTS_REG_POS_TXF (0) 242 #define SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 243 #define SCD_QUEUE_STTS_REG_POS_WSL (4) 244 #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 245 #define SCD_QUEUE_STTS_REG_MSK (0x017F0000) 246 247 #define SCD_QUEUE_CTX_REG1_CREDIT (0x00FFFF00) 248 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT (0xFF000000) 249 #define SCD_QUEUE_CTX_REG1_VAL(_n, _v) FIELD_PREP(SCD_QUEUE_CTX_REG1_ ## _n, _v) 250 251 #define SCD_QUEUE_CTX_REG2_WIN_SIZE (0x0000007F) 252 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT (0x007F0000) 253 #define SCD_QUEUE_CTX_REG2_VAL(_n, _v) FIELD_PREP(SCD_QUEUE_CTX_REG2_ ## _n, _v) 254 255 #define SCD_GP_CTRL_ENABLE_31_QUEUES BIT(0) 256 #define SCD_GP_CTRL_AUTO_ACTIVE_MODE BIT(18) 257 258 /* Context Data */ 259 #define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600) 260 #define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0) 261 262 /* Tx status */ 263 #define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0) 264 #define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0) 265 266 /* Translation Data */ 267 #define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0) 268 #define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808) 269 270 #define SCD_CONTEXT_QUEUE_OFFSET(x)\ 271 (SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 272 273 #define SCD_TX_STTS_QUEUE_OFFSET(x)\ 274 (SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 275 276 #define SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 277 ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 278 279 #define SCD_BASE (PRPH_BASE + 0xa02c00) 280 281 #define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0) 282 #define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8) 283 #define SCD_AIT (SCD_BASE + 0x0c) 284 #define SCD_TXFACT (SCD_BASE + 0x10) 285 #define SCD_ACTIVE (SCD_BASE + 0x14) 286 #define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8) 287 #define SCD_CHAINEXT_EN (SCD_BASE + 0x244) 288 #define SCD_AGGR_SEL (SCD_BASE + 0x248) 289 #define SCD_INTERRUPT_MASK (SCD_BASE + 0x108) 290 #define SCD_GP_CTRL (SCD_BASE + 0x1a8) 291 #define SCD_EN_CTRL (SCD_BASE + 0x254) 292 293 /*********************** END TX SCHEDULER *************************************/ 294 295 /* Oscillator clock */ 296 #define OSC_CLK (0xa04068) 297 #define OSC_CLK_FORCE_CONTROL (0x8) 298 299 #define FH_UCODE_LOAD_STATUS (0x1AF0) 300 301 /* 302 * Replacing FH_UCODE_LOAD_STATUS 303 * This register is writen by driver and is read by uCode during boot flow. 304 * Note this address is cleared after MAC reset. 305 */ 306 #define UREG_UCODE_LOAD_STATUS (0xa05c40) 307 #define UREG_CPU_INIT_RUN (0xa05c44) 308 309 #define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78) 310 #define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C) 311 312 #define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000) 313 #define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400) 314 315 #define LMAC2_PRPH_OFFSET (0x100000) 316 317 /* Rx FIFO */ 318 #define RXF_SIZE_ADDR (0xa00c88) 319 #define RXF_RD_D_SPACE (0xa00c40) 320 #define RXF_RD_WR_PTR (0xa00c50) 321 #define RXF_RD_RD_PTR (0xa00c54) 322 #define RXF_RD_FENCE_PTR (0xa00c4c) 323 #define RXF_SET_FENCE_MODE (0xa00c14) 324 #define RXF_LD_WR2FENCE (0xa00c1c) 325 #define RXF_FIFO_RD_FENCE_INC (0xa00c68) 326 #define RXF_SIZE_BYTE_CND_POS (7) 327 #define RXF_SIZE_BYTE_CNT_MSK (0x3ff << RXF_SIZE_BYTE_CND_POS) 328 #define RXF_DIFF_FROM_PREV (0x200) 329 330 #define RXF_LD_FENCE_OFFSET_ADDR (0xa00c10) 331 #define RXF_FIFO_RD_FENCE_ADDR (0xa00c0c) 332 333 /* Tx FIFO */ 334 #define TXF_FIFO_ITEM_CNT (0xa00438) 335 #define TXF_WR_PTR (0xa00414) 336 #define TXF_RD_PTR (0xa00410) 337 #define TXF_FENCE_PTR (0xa00418) 338 #define TXF_LOCK_FENCE (0xa00424) 339 #define TXF_LARC_NUM (0xa0043c) 340 #define TXF_READ_MODIFY_DATA (0xa00448) 341 #define TXF_READ_MODIFY_ADDR (0xa0044c) 342 343 /* UMAC Internal Tx Fifo */ 344 #define TXF_CPU2_FIFO_ITEM_CNT (0xA00538) 345 #define TXF_CPU2_WR_PTR (0xA00514) 346 #define TXF_CPU2_RD_PTR (0xA00510) 347 #define TXF_CPU2_FENCE_PTR (0xA00518) 348 #define TXF_CPU2_LOCK_FENCE (0xA00524) 349 #define TXF_CPU2_NUM (0xA0053C) 350 #define TXF_CPU2_READ_MODIFY_DATA (0xA00548) 351 #define TXF_CPU2_READ_MODIFY_ADDR (0xA0054C) 352 353 /* Radio registers access */ 354 #define RSP_RADIO_CMD (0xa02804) 355 #define RSP_RADIO_RDDAT (0xa02814) 356 #define RADIO_RSP_ADDR_POS (6) 357 #define RADIO_RSP_RD_CMD (3) 358 359 /* FW monitor */ 360 #define MON_BUFF_SAMPLE_CTL (0xa03c00) 361 #define MON_BUFF_BASE_ADDR (0xa03c1c) 362 #define MON_BUFF_END_ADDR (0xa03c40) 363 #define MON_BUFF_WRPTR (0xa03c44) 364 #define MON_BUFF_CYCLE_CNT (0xa03c48) 365 /* FW monitor family 8000 and on */ 366 #define MON_BUFF_BASE_ADDR_VER2 (0xa03c1c) 367 #define MON_BUFF_END_ADDR_VER2 (0xa03c20) 368 #define MON_BUFF_WRPTR_VER2 (0xa03c24) 369 #define MON_BUFF_CYCLE_CNT_VER2 (0xa03c28) 370 #define MON_BUFF_SHIFT_VER2 (0x8) 371 /* FW monitor familiy AX210 and on */ 372 #define DBGC_CUR_DBGBUF_BASE_ADDR_LSB (0xd03c20) 373 #define DBGC_CUR_DBGBUF_BASE_ADDR_MSB (0xd03c24) 374 #define DBGC_CUR_DBGBUF_STATUS (0xd03c1c) 375 #define DBGC_DBGBUF_WRAP_AROUND (0xd03c2c) 376 #define DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK (0x00ffffff) 377 378 #define MON_DMARB_RD_CTL_ADDR (0xa03c60) 379 #define MON_DMARB_RD_DATA_ADDR (0xa03c5c) 380 381 #define DBGC_IN_SAMPLE (0xa03c00) 382 #define DBGC_OUT_CTRL (0xa03c0c) 383 384 /* enable the ID buf for read */ 385 #define WFPM_PS_CTL_CLR 0xA0300C 386 #define WFMP_MAC_ADDR_0 0xA03080 387 #define WFMP_MAC_ADDR_1 0xA03084 388 #define LMPM_PMG_EN 0xA01CEC 389 #define RADIO_REG_SYS_MANUAL_DFT_0 0xAD4078 390 #define RFIC_REG_RD 0xAD0470 391 #define WFPM_CTRL_REG 0xA03030 392 #define WFPM_GP2 0xA030B4 393 enum { 394 ENABLE_WFPM = BIT(31), 395 WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK = 0x80000000, 396 }; 397 398 #define CNVI_AUX_MISC_CHIP 0xA200B0 399 #define CNVR_AUX_MISC_CHIP 0xA2B800 400 #define CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM 0xA29890 401 #define CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR 0xA29938 402 403 enum { 404 HW_STEP_LOCATION_BITS = 24, 405 }; 406 407 #define AUX_MISC_MASTER1_EN 0xA20818 408 enum aux_misc_master1_en { 409 AUX_MISC_MASTER1_EN_SBE_MSK = 0x1, 410 }; 411 412 #define AUX_MISC_MASTER1_SMPHR_STATUS 0xA20800 413 #define RSA_ENABLE 0xA24B08 414 #define PREG_AUX_BUS_WPROT_0 0xA04CC0 415 416 /* device family 9000 WPROT register */ 417 #define PREG_PRPH_WPROT_9000 0xA04CE0 418 /* device family 22000 WPROT register */ 419 #define PREG_PRPH_WPROT_22000 0xA04D00 420 421 #define SB_CPU_1_STATUS 0xA01E30 422 #define SB_CPU_2_STATUS 0xA01E34 423 #define UMAG_SB_CPU_1_STATUS 0xA038C0 424 #define UMAG_SB_CPU_2_STATUS 0xA038C4 425 #define UMAG_GEN_HW_STATUS 0xA038C8 426 427 /* For UMAG_GEN_HW_STATUS reg check */ 428 enum { 429 UMAG_GEN_HW_IS_FPGA = BIT(1), 430 }; 431 432 /* FW chicken bits */ 433 #define LMPM_CHICK 0xA01FF8 434 enum { 435 LMPM_CHICK_EXTENDED_ADDR_SPACE = BIT(0), 436 }; 437 438 /* FW chicken bits */ 439 #define LMPM_PAGE_PASS_NOTIF 0xA03824 440 enum { 441 LMPM_PAGE_PASS_NOTIF_POS = BIT(20), 442 }; 443 444 #define UREG_CHICK (0xA05C00) 445 #define UREG_CHICK_MSI_ENABLE BIT(24) 446 #define UREG_CHICK_MSIX_ENABLE BIT(25) 447 448 #define HPM_DEBUG 0xA03440 449 #define PERSISTENCE_BIT BIT(12) 450 #define PREG_WFPM_ACCESS BIT(12) 451 452 #define HPM_HIPM_GEN_CFG 0xA03458 453 #define HPM_HIPM_GEN_CFG_CR_PG_EN BIT(0) 454 #define HPM_HIPM_GEN_CFG_CR_SLP_EN BIT(1) 455 #define HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE BIT(10) 456 457 #define UREG_DOORBELL_TO_ISR6 0xA05C04 458 #define UREG_DOORBELL_TO_ISR6_NMI_BIT BIT(0) 459 #define UREG_DOORBELL_TO_ISR6_SUSPEND BIT(18) 460 #define UREG_DOORBELL_TO_ISR6_RESUME BIT(19) 461 462 #define FSEQ_ERROR_CODE 0xA340C8 463 #define FSEQ_TOP_INIT_VERSION 0xA34038 464 #define FSEQ_CNVIO_INIT_VERSION 0xA3403C 465 #define FSEQ_OTP_VERSION 0xA340FC 466 #define FSEQ_TOP_CONTENT_VERSION 0xA340F4 467 #define FSEQ_ALIVE_TOKEN 0xA340F0 468 #define FSEQ_CNVI_ID 0xA3408C 469 #define FSEQ_CNVR_ID 0xA34090 470 471 #define IWL_D3_SLEEP_STATUS_SUSPEND 0xD3 472 #define IWL_D3_SLEEP_STATUS_RESUME 0xD0 473 #endif /* __iwl_prph_h__ */ 474