1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 * more details. 21 * 22 * The full GNU General Public License is included in this distribution in the 23 * file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #ifndef __iwl_trans_int_pcie_h__ 65 #define __iwl_trans_int_pcie_h__ 66 67 #include <linux/spinlock.h> 68 #include <linux/interrupt.h> 69 #include <linux/skbuff.h> 70 #include <linux/wait.h> 71 #include <linux/pci.h> 72 #include <linux/timer.h> 73 #include <linux/cpu.h> 74 75 #include "iwl-fh.h" 76 #include "iwl-csr.h" 77 #include "iwl-trans.h" 78 #include "iwl-debug.h" 79 #include "iwl-io.h" 80 #include "iwl-op-mode.h" 81 #include "iwl-drv.h" 82 83 /* We need 2 entries for the TX command and header, and another one might 84 * be needed for potential data in the SKB's head. The remaining ones can 85 * be used for frags. 86 */ 87 #define IWL_PCIE_MAX_FRAGS(x) (x->max_tbs - 3) 88 89 /* 90 * RX related structures and functions 91 */ 92 #define RX_NUM_QUEUES 1 93 #define RX_POST_REQ_ALLOC 2 94 #define RX_CLAIM_REQ_ALLOC 8 95 #define RX_PENDING_WATERMARK 16 96 #define FIRST_RX_QUEUE 512 97 98 struct iwl_host_cmd; 99 100 /*This file includes the declaration that are internal to the 101 * trans_pcie layer */ 102 103 /** 104 * struct iwl_rx_mem_buffer 105 * @page_dma: bus address of rxb page 106 * @page: driver's pointer to the rxb page 107 * @invalid: rxb is in driver ownership - not owned by HW 108 * @vid: index of this rxb in the global table 109 */ 110 struct iwl_rx_mem_buffer { 111 dma_addr_t page_dma; 112 struct page *page; 113 u16 vid; 114 bool invalid; 115 struct list_head list; 116 }; 117 118 /** 119 * struct isr_statistics - interrupt statistics 120 * 121 */ 122 struct isr_statistics { 123 u32 hw; 124 u32 sw; 125 u32 err_code; 126 u32 sch; 127 u32 alive; 128 u32 rfkill; 129 u32 ctkill; 130 u32 wakeup; 131 u32 rx; 132 u32 tx; 133 u32 unhandled; 134 }; 135 136 /** 137 * struct iwl_rx_transfer_desc - transfer descriptor 138 * @addr: ptr to free buffer start address 139 * @rbid: unique tag of the buffer 140 * @reserved: reserved 141 */ 142 struct iwl_rx_transfer_desc { 143 __le16 rbid; 144 __le16 reserved[3]; 145 __le64 addr; 146 } __packed; 147 148 #define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0) 149 150 /** 151 * struct iwl_rx_completion_desc - completion descriptor 152 * @reserved1: reserved 153 * @rbid: unique tag of the received buffer 154 * @flags: flags (0: fragmented, all others: reserved) 155 * @reserved2: reserved 156 */ 157 struct iwl_rx_completion_desc { 158 __le32 reserved1; 159 __le16 rbid; 160 u8 flags; 161 u8 reserved2[25]; 162 } __packed; 163 164 /** 165 * struct iwl_rxq - Rx queue 166 * @id: queue index 167 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 168 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 169 * In AX210 devices it is a pointer to a list of iwl_rx_transfer_desc's 170 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 171 * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd) 172 * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd) 173 * @tr_tail: driver's pointer to the transmission ring tail buffer 174 * @tr_tail_dma: physical address of the buffer for the transmission ring tail 175 * @cr_tail: driver's pointer to the completion ring tail buffer 176 * @cr_tail_dma: physical address of the buffer for the completion ring tail 177 * @read: Shared index to newest available Rx buffer 178 * @write: Shared index to oldest written Rx packet 179 * @free_count: Number of pre-allocated buffers in rx_free 180 * @used_count: Number of RBDs handled to allocator to use for allocation 181 * @write_actual: 182 * @rx_free: list of RBDs with allocated RB ready for use 183 * @rx_used: list of RBDs with no RB attached 184 * @need_update: flag to indicate we need to update read/write index 185 * @rb_stts: driver's pointer to receive buffer status 186 * @rb_stts_dma: bus address of receive buffer status 187 * @lock: 188 * @queue: actual rx queue. Not used for multi-rx queue. 189 * 190 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 191 */ 192 struct iwl_rxq { 193 int id; 194 void *bd; 195 dma_addr_t bd_dma; 196 union { 197 void *used_bd; 198 __le32 *bd_32; 199 struct iwl_rx_completion_desc *cd; 200 }; 201 dma_addr_t used_bd_dma; 202 __le16 *tr_tail; 203 dma_addr_t tr_tail_dma; 204 __le16 *cr_tail; 205 dma_addr_t cr_tail_dma; 206 u32 read; 207 u32 write; 208 u32 free_count; 209 u32 used_count; 210 u32 write_actual; 211 u32 queue_size; 212 struct list_head rx_free; 213 struct list_head rx_used; 214 bool need_update; 215 void *rb_stts; 216 dma_addr_t rb_stts_dma; 217 spinlock_t lock; 218 struct napi_struct napi; 219 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 220 }; 221 222 /** 223 * struct iwl_rb_allocator - Rx allocator 224 * @req_pending: number of requests the allcator had not processed yet 225 * @req_ready: number of requests honored and ready for claiming 226 * @rbd_allocated: RBDs with pages allocated and ready to be handled to 227 * the queue. This is a list of &struct iwl_rx_mem_buffer 228 * @rbd_empty: RBDs with no page attached for allocator use. This is a list 229 * of &struct iwl_rx_mem_buffer 230 * @lock: protects the rbd_allocated and rbd_empty lists 231 * @alloc_wq: work queue for background calls 232 * @rx_alloc: work struct for background calls 233 */ 234 struct iwl_rb_allocator { 235 atomic_t req_pending; 236 atomic_t req_ready; 237 struct list_head rbd_allocated; 238 struct list_head rbd_empty; 239 spinlock_t lock; 240 struct workqueue_struct *alloc_wq; 241 struct work_struct rx_alloc; 242 }; 243 244 struct iwl_dma_ptr { 245 dma_addr_t dma; 246 void *addr; 247 size_t size; 248 }; 249 250 /** 251 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 252 * @index -- current index 253 */ 254 static inline int iwl_queue_inc_wrap(struct iwl_trans *trans, int index) 255 { 256 return ++index & 257 (trans->trans_cfg->base_params->max_tfd_queue_size - 1); 258 } 259 260 /** 261 * iwl_get_closed_rb_stts - get closed rb stts from different structs 262 * @rxq - the rxq to get the rb stts from 263 */ 264 static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans, 265 struct iwl_rxq *rxq) 266 { 267 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 268 __le16 *rb_stts = rxq->rb_stts; 269 270 return READ_ONCE(*rb_stts); 271 } else { 272 struct iwl_rb_status *rb_stts = rxq->rb_stts; 273 274 return READ_ONCE(rb_stts->closed_rb_num); 275 } 276 } 277 278 /** 279 * iwl_queue_dec_wrap - decrement queue index, wrap back to end 280 * @index -- current index 281 */ 282 static inline int iwl_queue_dec_wrap(struct iwl_trans *trans, int index) 283 { 284 return --index & 285 (trans->trans_cfg->base_params->max_tfd_queue_size - 1); 286 } 287 288 struct iwl_cmd_meta { 289 /* only for SYNC commands, iff the reply skb is wanted */ 290 struct iwl_host_cmd *source; 291 u32 flags; 292 u32 tbs; 293 }; 294 295 /* 296 * The FH will write back to the first TB only, so we need to copy some data 297 * into the buffer regardless of whether it should be mapped or not. 298 * This indicates how big the first TB must be to include the scratch buffer 299 * and the assigned PN. 300 * Since PN location is 8 bytes at offset 12, it's 20 now. 301 * If we make it bigger then allocations will be bigger and copy slower, so 302 * that's probably not useful. 303 */ 304 #define IWL_FIRST_TB_SIZE 20 305 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 306 307 struct iwl_pcie_txq_entry { 308 struct iwl_device_cmd *cmd; 309 struct sk_buff *skb; 310 /* buffer to free after command completes */ 311 const void *free_buf; 312 struct iwl_cmd_meta meta; 313 }; 314 315 struct iwl_pcie_first_tb_buf { 316 u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 317 }; 318 319 /** 320 * struct iwl_txq - Tx Queue for DMA 321 * @q: generic Rx/Tx queue descriptor 322 * @tfds: transmit frame descriptors (DMA memory) 323 * @first_tb_bufs: start of command headers, including scratch buffers, for 324 * the writeback -- this is DMA memory and an array holding one buffer 325 * for each command on the queue 326 * @first_tb_dma: DMA address for the first_tb_bufs start 327 * @entries: transmit entries (driver state) 328 * @lock: queue lock 329 * @stuck_timer: timer that fires if queue gets stuck 330 * @trans_pcie: pointer back to transport (for timer) 331 * @need_update: indicates need to update read/write index 332 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 333 * @wd_timeout: queue watchdog timeout (jiffies) - per queue 334 * @frozen: tx stuck queue timer is frozen 335 * @frozen_expiry_remainder: remember how long until the timer fires 336 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 337 * @write_ptr: 1-st empty entry (index) host_w 338 * @read_ptr: last used entry (index) host_r 339 * @dma_addr: physical addr for BD's 340 * @n_window: safe queue window 341 * @id: queue id 342 * @low_mark: low watermark, resume queue if free space more than this 343 * @high_mark: high watermark, stop queue if free space less than this 344 * 345 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 346 * descriptors) and required locking structures. 347 * 348 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 349 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 350 * there might be HW changes in the future). For the normal TX 351 * queues, n_window, which is the size of the software queue data 352 * is also 256; however, for the command queue, n_window is only 353 * 32 since we don't need so many commands pending. Since the HW 354 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 355 * This means that we end up with the following: 356 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 357 * SW entries: | 0 | ... | 31 | 358 * where N is a number between 0 and 7. This means that the SW 359 * data is a window overlayed over the HW queue. 360 */ 361 struct iwl_txq { 362 void *tfds; 363 struct iwl_pcie_first_tb_buf *first_tb_bufs; 364 dma_addr_t first_tb_dma; 365 struct iwl_pcie_txq_entry *entries; 366 spinlock_t lock; 367 unsigned long frozen_expiry_remainder; 368 struct timer_list stuck_timer; 369 struct iwl_trans_pcie *trans_pcie; 370 bool need_update; 371 bool frozen; 372 bool ampdu; 373 int block; 374 unsigned long wd_timeout; 375 struct sk_buff_head overflow_q; 376 struct iwl_dma_ptr bc_tbl; 377 378 int write_ptr; 379 int read_ptr; 380 dma_addr_t dma_addr; 381 int n_window; 382 u32 id; 383 int low_mark; 384 int high_mark; 385 386 bool overflow_tx; 387 }; 388 389 static inline dma_addr_t 390 iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx) 391 { 392 return txq->first_tb_dma + 393 sizeof(struct iwl_pcie_first_tb_buf) * idx; 394 } 395 396 struct iwl_tso_hdr_page { 397 struct page *page; 398 u8 *pos; 399 }; 400 401 #ifdef CONFIG_IWLWIFI_DEBUGFS 402 /** 403 * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data 404 * debugfs file 405 * 406 * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed. 407 * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open. 408 * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is 409 * set the file can no longer be used. 410 */ 411 enum iwl_fw_mon_dbgfs_state { 412 IWL_FW_MON_DBGFS_STATE_CLOSED, 413 IWL_FW_MON_DBGFS_STATE_OPEN, 414 IWL_FW_MON_DBGFS_STATE_DISABLED, 415 }; 416 #endif 417 418 /** 419 * enum iwl_shared_irq_flags - level of sharing for irq 420 * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes. 421 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue. 422 */ 423 enum iwl_shared_irq_flags { 424 IWL_SHARED_IRQ_NON_RX = BIT(0), 425 IWL_SHARED_IRQ_FIRST_RSS = BIT(1), 426 }; 427 428 /** 429 * enum iwl_image_response_code - image response values 430 * @IWL_IMAGE_RESP_DEF: the default value of the register 431 * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully 432 * @IWL_IMAGE_RESP_FAIL: iml reading failed 433 */ 434 enum iwl_image_response_code { 435 IWL_IMAGE_RESP_DEF = 0, 436 IWL_IMAGE_RESP_SUCCESS = 1, 437 IWL_IMAGE_RESP_FAIL = 2, 438 }; 439 440 /** 441 * struct cont_rec: continuous recording data structure 442 * @prev_wr_ptr: the last address that was read in monitor_data 443 * debugfs file 444 * @prev_wrap_cnt: the wrap count that was used during the last read in 445 * monitor_data debugfs file 446 * @state: the state of monitor_data debugfs file as described 447 * in &iwl_fw_mon_dbgfs_state enum 448 * @mutex: locked while reading from monitor_data debugfs file 449 */ 450 #ifdef CONFIG_IWLWIFI_DEBUGFS 451 struct cont_rec { 452 u32 prev_wr_ptr; 453 u32 prev_wrap_cnt; 454 u8 state; 455 /* Used to sync monitor_data debugfs file with driver unload flow */ 456 struct mutex mutex; 457 }; 458 #endif 459 460 /** 461 * struct iwl_trans_pcie - PCIe transport specific data 462 * @rxq: all the RX queue data 463 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 464 * @global_table: table mapping received VID from hw to rxb 465 * @rba: allocator for RX replenishing 466 * @ctxt_info: context information for FW self init 467 * @ctxt_info_gen3: context information for gen3 devices 468 * @prph_info: prph info for self init 469 * @prph_scratch: prph scratch for self init 470 * @ctxt_info_dma_addr: dma addr of context information 471 * @prph_info_dma_addr: dma addr of prph info 472 * @prph_scratch_dma_addr: dma addr of prph scratch 473 * @ctxt_info_dma_addr: dma addr of context information 474 * @init_dram: DRAM data of firmware image (including paging). 475 * Context information addresses will be taken from here. 476 * This is driver's local copy for keeping track of size and 477 * count for allocating and freeing the memory. 478 * @trans: pointer to the generic transport area 479 * @scd_base_addr: scheduler sram base address in SRAM 480 * @scd_bc_tbls: pointer to the byte count table of the scheduler 481 * @kw: keep warm address 482 * @pci_dev: basic pci-network driver stuff 483 * @hw_base: pci hardware address support 484 * @ucode_write_complete: indicates that the ucode has been copied. 485 * @ucode_write_waitq: wait queue for uCode load 486 * @cmd_queue - command queue number 487 * @def_rx_queue - default rx queue number 488 * @rx_buf_size: Rx buffer size 489 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 490 * @scd_set_active: should the transport configure the SCD for HCMD queue 491 * @sw_csum_tx: if true, then the transport will compute the csum of the TXed 492 * frame. 493 * @rx_page_order: page order for receive buffer size 494 * @reg_lock: protect hw register access 495 * @mutex: to protect stop_device / start_fw / start_hw 496 * @cmd_in_flight: true when we have a host command in flight 497 #ifdef CONFIG_IWLWIFI_DEBUGFS 498 * @fw_mon_data: fw continuous recording data 499 #endif 500 * @msix_entries: array of MSI-X entries 501 * @msix_enabled: true if managed to enable MSI-X 502 * @shared_vec_mask: the type of causes the shared vector handles 503 * (see iwl_shared_irq_flags). 504 * @alloc_vecs: the number of interrupt vectors allocated by the OS 505 * @def_irq: default irq for non rx causes 506 * @fh_init_mask: initial unmasked fh causes 507 * @hw_init_mask: initial unmasked hw causes 508 * @fh_mask: current unmasked fh causes 509 * @hw_mask: current unmasked hw causes 510 * @in_rescan: true if we have triggered a device rescan 511 * @base_rb_stts: base virtual address of receive buffer status for all queues 512 * @base_rb_stts_dma: base physical address of receive buffer status 513 */ 514 struct iwl_trans_pcie { 515 struct iwl_rxq *rxq; 516 struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE]; 517 struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE]; 518 struct iwl_rb_allocator rba; 519 union { 520 struct iwl_context_info *ctxt_info; 521 struct iwl_context_info_gen3 *ctxt_info_gen3; 522 }; 523 struct iwl_prph_info *prph_info; 524 struct iwl_prph_scratch *prph_scratch; 525 dma_addr_t ctxt_info_dma_addr; 526 dma_addr_t prph_info_dma_addr; 527 dma_addr_t prph_scratch_dma_addr; 528 dma_addr_t iml_dma_addr; 529 struct iwl_trans *trans; 530 531 struct net_device napi_dev; 532 533 struct __percpu iwl_tso_hdr_page *tso_hdr_page; 534 535 /* INT ICT Table */ 536 __le32 *ict_tbl; 537 dma_addr_t ict_tbl_dma; 538 int ict_index; 539 bool use_ict; 540 bool is_down, opmode_down; 541 s8 debug_rfkill; 542 struct isr_statistics isr_stats; 543 544 spinlock_t irq_lock; 545 struct mutex mutex; 546 u32 inta_mask; 547 u32 scd_base_addr; 548 struct iwl_dma_ptr scd_bc_tbls; 549 struct iwl_dma_ptr kw; 550 551 struct iwl_txq *txq_memory; 552 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 553 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 554 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 555 556 /* PCI bus related data */ 557 struct pci_dev *pci_dev; 558 void __iomem *hw_base; 559 560 bool ucode_write_complete; 561 bool sx_complete; 562 wait_queue_head_t ucode_write_waitq; 563 wait_queue_head_t wait_command_queue; 564 wait_queue_head_t sx_waitq; 565 566 u8 page_offs, dev_cmd_offs; 567 568 u8 cmd_queue; 569 u8 def_rx_queue; 570 u8 cmd_fifo; 571 unsigned int cmd_q_wdg_timeout; 572 u8 n_no_reclaim_cmds; 573 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 574 u8 max_tbs; 575 u16 tfd_size; 576 577 enum iwl_amsdu_size rx_buf_size; 578 bool bc_table_dword; 579 bool scd_set_active; 580 bool sw_csum_tx; 581 bool pcie_dbg_dumped_once; 582 u32 rx_page_order; 583 584 /*protect hw register */ 585 spinlock_t reg_lock; 586 bool cmd_hold_nic_awake; 587 588 #ifdef CONFIG_IWLWIFI_DEBUGFS 589 struct cont_rec fw_mon_data; 590 #endif 591 592 struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 593 bool msix_enabled; 594 u8 shared_vec_mask; 595 u32 alloc_vecs; 596 u32 def_irq; 597 u32 fh_init_mask; 598 u32 hw_init_mask; 599 u32 fh_mask; 600 u32 hw_mask; 601 cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES]; 602 u16 tx_cmd_queue_size; 603 bool in_rescan; 604 605 void *base_rb_stts; 606 dma_addr_t base_rb_stts_dma; 607 }; 608 609 static inline struct iwl_trans_pcie * 610 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 611 { 612 return (void *)trans->trans_specific; 613 } 614 615 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, 616 struct msix_entry *entry) 617 { 618 /* 619 * Before sending the interrupt the HW disables it to prevent 620 * a nested interrupt. This is done by writing 1 to the corresponding 621 * bit in the mask register. After handling the interrupt, it should be 622 * re-enabled by clearing this bit. This register is defined as 623 * write 1 clear (W1C) register, meaning that it's being clear 624 * by writing 1 to the bit. 625 */ 626 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); 627 } 628 629 static inline struct iwl_trans * 630 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 631 { 632 return container_of((void *)trans_pcie, struct iwl_trans, 633 trans_specific); 634 } 635 636 /* 637 * Convention: trans API functions: iwl_trans_pcie_XXX 638 * Other functions: iwl_pcie_XXX 639 */ 640 struct iwl_trans 641 *iwl_trans_pcie_alloc(struct pci_dev *pdev, 642 const struct pci_device_id *ent, 643 const struct iwl_cfg_trans_params *cfg_trans); 644 void iwl_trans_pcie_free(struct iwl_trans *trans); 645 646 /***************************************************** 647 * RX 648 ******************************************************/ 649 int iwl_pcie_rx_init(struct iwl_trans *trans); 650 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans); 651 irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 652 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 653 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 654 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 655 int iwl_pcie_rx_stop(struct iwl_trans *trans); 656 void iwl_pcie_rx_free(struct iwl_trans *trans); 657 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans); 658 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq); 659 int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget); 660 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 661 struct iwl_rxq *rxq); 662 663 /***************************************************** 664 * ICT - interrupt handling 665 ******************************************************/ 666 irqreturn_t iwl_pcie_isr(int irq, void *data); 667 int iwl_pcie_alloc_ict(struct iwl_trans *trans); 668 void iwl_pcie_free_ict(struct iwl_trans *trans); 669 void iwl_pcie_reset_ict(struct iwl_trans *trans); 670 void iwl_pcie_disable_ict(struct iwl_trans *trans); 671 672 /***************************************************** 673 * TX / HCMD 674 ******************************************************/ 675 int iwl_pcie_tx_init(struct iwl_trans *trans); 676 int iwl_pcie_gen2_tx_init(struct iwl_trans *trans, int txq_id, 677 int queue_size); 678 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 679 int iwl_pcie_tx_stop(struct iwl_trans *trans); 680 void iwl_pcie_tx_free(struct iwl_trans *trans); 681 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 682 const struct iwl_trans_txq_scd_cfg *cfg, 683 unsigned int wdg_timeout); 684 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 685 bool configure_scd); 686 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 687 bool shared_mode); 688 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, 689 struct iwl_txq *txq); 690 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 691 struct iwl_device_cmd *dev_cmd, int txq_id); 692 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 693 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 694 void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx); 695 void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans, 696 struct iwl_txq *txq); 697 void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 698 struct iwl_rx_cmd_buffer *rxb); 699 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 700 struct sk_buff_head *skbs); 701 void iwl_trans_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr); 702 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 703 704 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd, 705 u8 idx) 706 { 707 if (trans->trans_cfg->use_tfh) { 708 struct iwl_tfh_tfd *tfd = _tfd; 709 struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 710 711 return le16_to_cpu(tb->tb_len); 712 } else { 713 struct iwl_tfd *tfd = _tfd; 714 struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 715 716 return le16_to_cpu(tb->hi_n_len) >> 4; 717 } 718 } 719 720 /***************************************************** 721 * Error handling 722 ******************************************************/ 723 void iwl_pcie_dump_csr(struct iwl_trans *trans); 724 725 /***************************************************** 726 * Helpers 727 ******************************************************/ 728 static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 729 { 730 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 731 732 clear_bit(STATUS_INT_ENABLED, &trans->status); 733 if (!trans_pcie->msix_enabled) { 734 /* disable interrupts from uCode/NIC to host */ 735 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 736 737 /* acknowledge/clear/reset any interrupts still pending 738 * from uCode or flow handler (Rx/Tx DMA) */ 739 iwl_write32(trans, CSR_INT, 0xffffffff); 740 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 741 } else { 742 /* disable all the interrupt we might use */ 743 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 744 trans_pcie->fh_init_mask); 745 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 746 trans_pcie->hw_init_mask); 747 } 748 IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 749 } 750 751 #define IWL_NUM_OF_COMPLETION_RINGS 31 752 #define IWL_NUM_OF_TRANSFER_RINGS 527 753 754 static inline int iwl_pcie_get_num_sections(const struct fw_img *fw, 755 int start) 756 { 757 int i = 0; 758 759 while (start < fw->num_sec && 760 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION && 761 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) { 762 start++; 763 i++; 764 } 765 766 return i; 767 } 768 769 static inline int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans, 770 const struct fw_desc *sec, 771 struct iwl_dram_data *dram) 772 { 773 dram->block = dma_alloc_coherent(trans->dev, sec->len, 774 &dram->physical, 775 GFP_KERNEL); 776 if (!dram->block) 777 return -ENOMEM; 778 779 dram->size = sec->len; 780 memcpy(dram->block, sec->data, sec->len); 781 782 return 0; 783 } 784 785 static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans) 786 { 787 struct iwl_self_init_dram *dram = &trans->init_dram; 788 int i; 789 790 if (!dram->fw) { 791 WARN_ON(dram->fw_cnt); 792 return; 793 } 794 795 for (i = 0; i < dram->fw_cnt; i++) 796 dma_free_coherent(trans->dev, dram->fw[i].size, 797 dram->fw[i].block, dram->fw[i].physical); 798 799 kfree(dram->fw); 800 dram->fw_cnt = 0; 801 dram->fw = NULL; 802 } 803 804 static inline void iwl_disable_interrupts(struct iwl_trans *trans) 805 { 806 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 807 808 spin_lock(&trans_pcie->irq_lock); 809 _iwl_disable_interrupts(trans); 810 spin_unlock(&trans_pcie->irq_lock); 811 } 812 813 static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 814 { 815 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 816 817 IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 818 set_bit(STATUS_INT_ENABLED, &trans->status); 819 if (!trans_pcie->msix_enabled) { 820 trans_pcie->inta_mask = CSR_INI_SET_MASK; 821 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 822 } else { 823 /* 824 * fh/hw_mask keeps all the unmasked causes. 825 * Unlike msi, in msix cause is enabled when it is unset. 826 */ 827 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 828 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 829 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 830 ~trans_pcie->fh_mask); 831 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 832 ~trans_pcie->hw_mask); 833 } 834 } 835 836 static inline void iwl_enable_interrupts(struct iwl_trans *trans) 837 { 838 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 839 840 spin_lock(&trans_pcie->irq_lock); 841 _iwl_enable_interrupts(trans); 842 spin_unlock(&trans_pcie->irq_lock); 843 } 844 static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 845 { 846 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 847 848 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 849 trans_pcie->hw_mask = msk; 850 } 851 852 static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 853 { 854 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 855 856 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 857 trans_pcie->fh_mask = msk; 858 } 859 860 static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 861 { 862 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 863 864 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 865 if (!trans_pcie->msix_enabled) { 866 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 867 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 868 } else { 869 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 870 trans_pcie->hw_init_mask); 871 iwl_enable_fh_int_msk_msix(trans, 872 MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 873 } 874 } 875 876 static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans) 877 { 878 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 879 880 IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n"); 881 882 if (!trans_pcie->msix_enabled) { 883 /* 884 * When we'll receive the ALIVE interrupt, the ISR will call 885 * iwl_enable_fw_load_int_ctx_info again to set the ALIVE 886 * interrupt (which is not really needed anymore) but also the 887 * RX interrupt which will allow us to receive the ALIVE 888 * notification (which is Rx) and continue the flow. 889 */ 890 trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX; 891 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 892 } else { 893 iwl_enable_hw_int_msk_msix(trans, 894 MSIX_HW_INT_CAUSES_REG_ALIVE); 895 /* 896 * Leave all the FH causes enabled to get the ALIVE 897 * notification. 898 */ 899 iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask); 900 } 901 } 902 903 static inline u16 iwl_pcie_get_cmd_index(const struct iwl_txq *q, u32 index) 904 { 905 return index & (q->n_window - 1); 906 } 907 908 static inline void *iwl_pcie_get_tfd(struct iwl_trans *trans, 909 struct iwl_txq *txq, int idx) 910 { 911 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 912 913 if (trans->trans_cfg->use_tfh) 914 idx = iwl_pcie_get_cmd_index(txq, idx); 915 916 return txq->tfds + trans_pcie->tfd_size * idx; 917 } 918 919 static inline const char *queue_name(struct device *dev, 920 struct iwl_trans_pcie *trans_p, int i) 921 { 922 if (trans_p->shared_vec_mask) { 923 int vec = trans_p->shared_vec_mask & 924 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 925 926 if (i == 0) 927 return DRV_NAME ": shared IRQ"; 928 929 return devm_kasprintf(dev, GFP_KERNEL, 930 DRV_NAME ": queue %d", i + vec); 931 } 932 if (i == 0) 933 return DRV_NAME ": default queue"; 934 935 if (i == trans_p->alloc_vecs - 1) 936 return DRV_NAME ": exception"; 937 938 return devm_kasprintf(dev, GFP_KERNEL, 939 DRV_NAME ": queue %d", i); 940 } 941 942 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 943 { 944 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 945 946 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 947 if (!trans_pcie->msix_enabled) { 948 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 949 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 950 } else { 951 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 952 trans_pcie->fh_init_mask); 953 iwl_enable_hw_int_msk_msix(trans, 954 MSIX_HW_INT_CAUSES_REG_RF_KILL); 955 } 956 957 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) { 958 /* 959 * On 9000-series devices this bit isn't enabled by default, so 960 * when we power down the device we need set the bit to allow it 961 * to wake up the PCI-E bus for RF-kill interrupts. 962 */ 963 iwl_set_bit(trans, CSR_GP_CNTRL, 964 CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); 965 } 966 } 967 968 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans); 969 970 static inline void iwl_wake_queue(struct iwl_trans *trans, 971 struct iwl_txq *txq) 972 { 973 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 974 975 if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) { 976 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id); 977 iwl_op_mode_queue_not_full(trans->op_mode, txq->id); 978 } 979 } 980 981 static inline void iwl_stop_queue(struct iwl_trans *trans, 982 struct iwl_txq *txq) 983 { 984 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 985 986 if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) { 987 iwl_op_mode_queue_full(trans->op_mode, txq->id); 988 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id); 989 } else 990 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 991 txq->id); 992 } 993 994 static inline bool iwl_queue_used(const struct iwl_txq *q, int i) 995 { 996 int index = iwl_pcie_get_cmd_index(q, i); 997 int r = iwl_pcie_get_cmd_index(q, q->read_ptr); 998 int w = iwl_pcie_get_cmd_index(q, q->write_ptr); 999 1000 return w >= r ? 1001 (index >= r && index < w) : 1002 !(index < r && index >= w); 1003 } 1004 1005 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 1006 { 1007 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1008 1009 lockdep_assert_held(&trans_pcie->mutex); 1010 1011 if (trans_pcie->debug_rfkill == 1) 1012 return true; 1013 1014 return !(iwl_read32(trans, CSR_GP_CNTRL) & 1015 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 1016 } 1017 1018 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 1019 u32 reg, u32 mask, u32 value) 1020 { 1021 u32 v; 1022 1023 #ifdef CONFIG_IWLWIFI_DEBUG 1024 WARN_ON_ONCE(value & ~mask); 1025 #endif 1026 1027 v = iwl_read32(trans, reg); 1028 v &= ~mask; 1029 v |= value; 1030 iwl_write32(trans, reg, v); 1031 } 1032 1033 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 1034 u32 reg, u32 mask) 1035 { 1036 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 1037 } 1038 1039 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 1040 u32 reg, u32 mask) 1041 { 1042 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 1043 } 1044 1045 static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans) 1046 { 1047 return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans)); 1048 } 1049 1050 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 1051 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans); 1052 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans); 1053 1054 #ifdef CONFIG_IWLWIFI_DEBUGFS 1055 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 1056 #else 1057 static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { } 1058 #endif 1059 1060 void iwl_pcie_rx_allocator_work(struct work_struct *data); 1061 1062 /* common functions that are used by gen2 transport */ 1063 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans); 1064 void iwl_pcie_apm_config(struct iwl_trans *trans); 1065 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans); 1066 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans); 1067 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans); 1068 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1069 bool was_in_rfkill); 1070 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq); 1071 int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q); 1072 void iwl_pcie_apm_stop_master(struct iwl_trans *trans); 1073 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie); 1074 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 1075 int slots_num, bool cmd_queue); 1076 int iwl_pcie_txq_alloc(struct iwl_trans *trans, 1077 struct iwl_txq *txq, int slots_num, bool cmd_queue); 1078 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 1079 struct iwl_dma_ptr *ptr, size_t size); 1080 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr); 1081 void iwl_pcie_apply_destination(struct iwl_trans *trans); 1082 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 1083 struct sk_buff *skb); 1084 #ifdef CONFIG_INET 1085 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len); 1086 #endif 1087 1088 /* common functions that are used by gen3 transport */ 1089 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power); 1090 1091 /* transport gen 2 exported functions */ 1092 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 1093 const struct fw_img *fw, bool run_in_rfkill); 1094 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr); 1095 void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans, 1096 struct iwl_txq *txq); 1097 int iwl_trans_pcie_dyn_txq_alloc_dma(struct iwl_trans *trans, 1098 struct iwl_txq **intxq, int size, 1099 unsigned int timeout); 1100 int iwl_trans_pcie_txq_alloc_response(struct iwl_trans *trans, 1101 struct iwl_txq *txq, 1102 struct iwl_host_cmd *hcmd); 1103 int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans, 1104 __le16 flags, u8 sta_id, u8 tid, 1105 int cmd_id, int size, 1106 unsigned int timeout); 1107 void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue); 1108 int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb, 1109 struct iwl_device_cmd *dev_cmd, int txq_id); 1110 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 1111 struct iwl_host_cmd *cmd); 1112 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans); 1113 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans); 1114 void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id); 1115 void iwl_pcie_gen2_tx_free(struct iwl_trans *trans); 1116 void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans); 1117 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1118 bool test, bool reset); 1119 #endif /* __iwl_trans_int_pcie_h__ */ 1120