1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2017 Intel Deutschland GmbH
4  * Copyright (C) 2018-2023 Intel Corporation
5  */
6 #include "iwl-trans.h"
7 #include "iwl-prph.h"
8 #include "iwl-context-info.h"
9 #include "iwl-context-info-gen3.h"
10 #include "internal.h"
11 #include "fw/dbg.h"
12 
13 #define FW_RESET_TIMEOUT (HZ / 5)
14 
15 /*
16  * Start up NIC's basic functionality after it has been reset
17  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
18  * NOTE:  This does not load uCode nor start the embedded processor
19  */
20 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
21 {
22 	int ret = 0;
23 
24 	IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
25 
26 	/*
27 	 * Use "set_bit" below rather than "write", to preserve any hardware
28 	 * bits already set by default after reset.
29 	 */
30 
31 	/*
32 	 * Disable L0s without affecting L1;
33 	 * don't wait for ICH L0s (ICH bug W/A)
34 	 */
35 	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
36 		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
37 
38 	/* Set FH wait threshold to maximum (HW error during stress W/A) */
39 	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
40 
41 	/*
42 	 * Enable HAP INTA (interrupt from management bus) to
43 	 * wake device's PCI Express link L1a -> L0s
44 	 */
45 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
46 		    CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
47 
48 	iwl_pcie_apm_config(trans);
49 
50 	ret = iwl_finish_nic_init(trans);
51 	if (ret)
52 		return ret;
53 
54 	set_bit(STATUS_DEVICE_ENABLED, &trans->status);
55 
56 	return 0;
57 }
58 
59 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
60 {
61 	IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
62 
63 	if (op_mode_leave) {
64 		if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
65 			iwl_pcie_gen2_apm_init(trans);
66 
67 		/* inform ME that we are leaving */
68 		iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
69 			    CSR_RESET_LINK_PWR_MGMT_DISABLED);
70 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
71 			    CSR_HW_IF_CONFIG_REG_PREPARE |
72 			    CSR_HW_IF_CONFIG_REG_ENABLE_PME);
73 		mdelay(1);
74 		iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
75 			      CSR_RESET_LINK_PWR_MGMT_DISABLED);
76 		mdelay(5);
77 	}
78 
79 	clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
80 
81 	/* Stop device's DMA activity */
82 	iwl_pcie_apm_stop_master(trans);
83 
84 	iwl_trans_sw_reset(trans, false);
85 
86 	/*
87 	 * Clear "initialization complete" bit to move adapter from
88 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
89 	 */
90 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
91 		iwl_clear_bit(trans, CSR_GP_CNTRL,
92 			      CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
93 	else
94 		iwl_clear_bit(trans, CSR_GP_CNTRL,
95 			      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
96 }
97 
98 static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)
99 {
100 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
101 	int ret;
102 
103 	trans_pcie->fw_reset_state = FW_RESET_REQUESTED;
104 
105 	if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
106 		iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
107 				    UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);
108 	else if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
109 		iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
110 				    UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
111 	else
112 		iwl_write32(trans, CSR_DOORBELL_VECTOR,
113 			    UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
114 
115 	/* wait 200ms */
116 	ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
117 				 trans_pcie->fw_reset_state != FW_RESET_REQUESTED,
118 				 FW_RESET_TIMEOUT);
119 	if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) {
120 		u32 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
121 
122 		IWL_ERR(trans,
123 			"timeout waiting for FW reset ACK (inta_hw=0x%x)\n",
124 			inta_hw);
125 
126 		if (!(inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE))
127 			iwl_trans_fw_error(trans, true);
128 	}
129 
130 	trans_pcie->fw_reset_state = FW_RESET_IDLE;
131 }
132 
133 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
134 {
135 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
136 
137 	lockdep_assert_held(&trans_pcie->mutex);
138 
139 	if (trans_pcie->is_down)
140 		return;
141 
142 	if (trans->state >= IWL_TRANS_FW_STARTED)
143 		if (trans_pcie->fw_reset_handshake)
144 			iwl_trans_pcie_fw_reset_handshake(trans);
145 
146 	trans_pcie->is_down = true;
147 
148 	/* tell the device to stop sending interrupts */
149 	iwl_disable_interrupts(trans);
150 
151 	/* device going down, Stop using ICT table */
152 	iwl_pcie_disable_ict(trans);
153 
154 	/*
155 	 * If a HW restart happens during firmware loading,
156 	 * then the firmware loading might call this function
157 	 * and later it might be called again due to the
158 	 * restart. So don't process again if the device is
159 	 * already dead.
160 	 */
161 	if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
162 		IWL_DEBUG_INFO(trans,
163 			       "DEVICE_ENABLED bit was set and is now cleared\n");
164 		iwl_pcie_rx_napi_sync(trans);
165 		iwl_txq_gen2_tx_free(trans);
166 		iwl_pcie_rx_stop(trans);
167 	}
168 
169 	iwl_pcie_ctxt_info_free_paging(trans);
170 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
171 		iwl_pcie_ctxt_info_gen3_free(trans, false);
172 	else
173 		iwl_pcie_ctxt_info_free(trans);
174 
175 	/* Stop the device, and put it in low power state */
176 	iwl_pcie_gen2_apm_stop(trans, false);
177 
178 	/* re-take ownership to prevent other users from stealing the device */
179 	iwl_trans_sw_reset(trans, true);
180 
181 	/*
182 	 * Upon stop, the IVAR table gets erased, so msi-x won't
183 	 * work. This causes a bug in RF-KILL flows, since the interrupt
184 	 * that enables radio won't fire on the correct irq, and the
185 	 * driver won't be able to handle the interrupt.
186 	 * Configure the IVAR table again after reset.
187 	 */
188 	iwl_pcie_conf_msix_hw(trans_pcie);
189 
190 	/*
191 	 * Upon stop, the APM issues an interrupt if HW RF kill is set.
192 	 * This is a bug in certain verions of the hardware.
193 	 * Certain devices also keep sending HW RF kill interrupt all
194 	 * the time, unless the interrupt is ACKed even if the interrupt
195 	 * should be masked. Re-ACK all the interrupts here.
196 	 */
197 	iwl_disable_interrupts(trans);
198 
199 	/* clear all status bits */
200 	clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
201 	clear_bit(STATUS_INT_ENABLED, &trans->status);
202 	clear_bit(STATUS_TPOWER_PMI, &trans->status);
203 
204 	/*
205 	 * Even if we stop the HW, we still want the RF kill
206 	 * interrupt
207 	 */
208 	iwl_enable_rfkill_int(trans);
209 }
210 
211 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
212 {
213 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
214 	bool was_in_rfkill;
215 
216 	iwl_op_mode_time_point(trans->op_mode,
217 			       IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
218 			       NULL);
219 
220 	mutex_lock(&trans_pcie->mutex);
221 	trans_pcie->opmode_down = true;
222 	was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
223 	_iwl_trans_pcie_gen2_stop_device(trans);
224 	iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
225 	mutex_unlock(&trans_pcie->mutex);
226 }
227 
228 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
229 {
230 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
231 	int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
232 			       trans->cfg->min_txq_size);
233 
234 	/* TODO: most of the logic can be removed in A0 - but not in Z0 */
235 	spin_lock_bh(&trans_pcie->irq_lock);
236 	iwl_pcie_gen2_apm_init(trans);
237 	spin_unlock_bh(&trans_pcie->irq_lock);
238 
239 	iwl_op_mode_nic_config(trans->op_mode);
240 
241 	/* Allocate the RX queue, or reset if it is already allocated */
242 	if (iwl_pcie_gen2_rx_init(trans))
243 		return -ENOMEM;
244 
245 	/* Allocate or reset and init all Tx and Command queues */
246 	if (iwl_txq_gen2_init(trans, trans->txqs.cmd.q_id, queue_size))
247 		return -ENOMEM;
248 
249 	/* enable shadow regs in HW */
250 	iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
251 	IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
252 
253 	return 0;
254 }
255 
256 static void iwl_pcie_get_rf_name(struct iwl_trans *trans)
257 {
258 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
259 	char *buf = trans_pcie->rf_name;
260 	size_t buflen = sizeof(trans_pcie->rf_name);
261 	size_t pos;
262 	u32 version;
263 
264 	if (buf[0])
265 		return;
266 
267 	switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
268 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF):
269 		pos = scnprintf(buf, buflen, "JF");
270 		break;
271 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF):
272 		pos = scnprintf(buf, buflen, "GF");
273 		break;
274 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4):
275 		pos = scnprintf(buf, buflen, "GF4");
276 		break;
277 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
278 		pos = scnprintf(buf, buflen, "HR");
279 		break;
280 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
281 		pos = scnprintf(buf, buflen, "HR1");
282 		break;
283 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
284 		pos = scnprintf(buf, buflen, "HRCDB");
285 		break;
286 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_MS):
287 		pos = scnprintf(buf, buflen, "MS");
288 		break;
289 	default:
290 		return;
291 	}
292 
293 	switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
294 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
295 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
296 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
297 		version = iwl_read_prph(trans, CNVI_MBOX_C);
298 		switch (version) {
299 		case 0x20000:
300 			pos += scnprintf(buf + pos, buflen - pos, " B3");
301 			break;
302 		case 0x120000:
303 			pos += scnprintf(buf + pos, buflen - pos, " B5");
304 			break;
305 		default:
306 			pos += scnprintf(buf + pos, buflen - pos,
307 					 " (0x%x)", version);
308 			break;
309 		}
310 		break;
311 	default:
312 		break;
313 	}
314 
315 	pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x",
316 			 trans->hw_rf_id);
317 
318 	IWL_INFO(trans, "Detected RF %s\n", buf);
319 
320 	/*
321 	 * also add a \n for debugfs - need to do it after printing
322 	 * since our IWL_INFO machinery wants to see a static \n at
323 	 * the end of the string
324 	 */
325 	pos += scnprintf(buf + pos, buflen - pos, "\n");
326 }
327 
328 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
329 {
330 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
331 
332 	iwl_pcie_reset_ict(trans);
333 
334 	/* make sure all queue are not stopped/used */
335 	memset(trans->txqs.queue_stopped, 0,
336 	       sizeof(trans->txqs.queue_stopped));
337 	memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
338 
339 	/* now that we got alive we can free the fw image & the context info.
340 	 * paging memory cannot be freed included since FW will still use it
341 	 */
342 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
343 		iwl_pcie_ctxt_info_gen3_free(trans, true);
344 	else
345 		iwl_pcie_ctxt_info_free(trans);
346 
347 	/*
348 	 * Re-enable all the interrupts, including the RF-Kill one, now that
349 	 * the firmware is alive.
350 	 */
351 	iwl_enable_interrupts(trans);
352 	mutex_lock(&trans_pcie->mutex);
353 	iwl_pcie_check_hw_rf_kill(trans);
354 
355 	iwl_pcie_get_rf_name(trans);
356 	mutex_unlock(&trans_pcie->mutex);
357 }
358 
359 static bool iwl_pcie_set_ltr(struct iwl_trans *trans)
360 {
361 	u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
362 		      u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
363 				      CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
364 		      u32_encode_bits(250,
365 				      CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
366 		      CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
367 		      u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
368 				      CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
369 		      u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
370 
371 	/*
372 	 * To workaround hardware latency issues during the boot process,
373 	 * initialize the LTR to ~250 usec (see ltr_val above).
374 	 * The firmware initializes this again later (to a smaller value).
375 	 */
376 	if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
377 	     trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
378 	    !trans->trans_cfg->integrated) {
379 		iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
380 		return true;
381 	}
382 
383 	if (trans->trans_cfg->integrated &&
384 	    trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
385 		iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
386 		iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
387 		return true;
388 	}
389 
390 	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
391 		/* First clear the interrupt, just in case */
392 		iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
393 			    MSIX_HW_INT_CAUSES_REG_IML);
394 		/* In this case, unfortunately the same ROM bug exists in the
395 		 * device (not setting LTR correctly), but we don't have control
396 		 * over the settings from the host due to some hardware security
397 		 * features. The only workaround we've been able to come up with
398 		 * so far is to try to keep the CPU and device busy by polling
399 		 * it and the IML (image loader) completed interrupt.
400 		 */
401 		return false;
402 	}
403 
404 	/* nothing needs to be done on other devices */
405 	return true;
406 }
407 
408 static void iwl_pcie_spin_for_iml(struct iwl_trans *trans)
409 {
410 /* in practice, this seems to complete in around 20-30ms at most, wait 100 */
411 #define IML_WAIT_TIMEOUT	(HZ / 10)
412 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
413 	unsigned long end_time = jiffies + IML_WAIT_TIMEOUT;
414 	u32 value, loops = 0;
415 	bool irq = false;
416 
417 	if (WARN_ON(!trans_pcie->iml))
418 		return;
419 
420 	value = iwl_read32(trans, CSR_LTR_LAST_MSG);
421 	IWL_DEBUG_INFO(trans, "Polling for IML load - CSR_LTR_LAST_MSG=0x%x\n",
422 		       value);
423 
424 	while (time_before(jiffies, end_time)) {
425 		if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) &
426 				MSIX_HW_INT_CAUSES_REG_IML) {
427 			irq = true;
428 			break;
429 		}
430 		/* Keep the CPU and device busy. */
431 		value = iwl_read32(trans, CSR_LTR_LAST_MSG);
432 		loops++;
433 	}
434 
435 	IWL_DEBUG_INFO(trans,
436 		       "Polled for IML load: irq=%d, loops=%d, CSR_LTR_LAST_MSG=0x%x\n",
437 		       irq, loops, value);
438 
439 	/* We don't fail here even if we timed out - maybe we get lucky and the
440 	 * interrupt comes in later (and we get alive from firmware) and then
441 	 * we're all happy - but if not we'll fail on alive timeout or get some
442 	 * other error out.
443 	 */
444 }
445 
446 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
447 				 const struct fw_img *fw, bool run_in_rfkill)
448 {
449 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
450 	bool hw_rfkill, keep_ram_busy;
451 	int ret;
452 
453 	/* This may fail if AMT took ownership of the device */
454 	if (iwl_pcie_prepare_card_hw(trans)) {
455 		IWL_WARN(trans, "Exit HW not ready\n");
456 		return -EIO;
457 	}
458 
459 	iwl_enable_rfkill_int(trans);
460 
461 	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
462 
463 	/*
464 	 * We enabled the RF-Kill interrupt and the handler may very
465 	 * well be running. Disable the interrupts to make sure no other
466 	 * interrupt can be fired.
467 	 */
468 	iwl_disable_interrupts(trans);
469 
470 	/* Make sure it finished running */
471 	iwl_pcie_synchronize_irqs(trans);
472 
473 	mutex_lock(&trans_pcie->mutex);
474 
475 	/* If platform's RF_KILL switch is NOT set to KILL */
476 	hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
477 	if (hw_rfkill && !run_in_rfkill) {
478 		ret = -ERFKILL;
479 		goto out;
480 	}
481 
482 	/* Someone called stop_device, don't try to start_fw */
483 	if (trans_pcie->is_down) {
484 		IWL_WARN(trans,
485 			 "Can't start_fw since the HW hasn't been started\n");
486 		ret = -EIO;
487 		goto out;
488 	}
489 
490 	/* make sure rfkill handshake bits are cleared */
491 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
492 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
493 		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
494 
495 	/* clear (again), then enable host interrupts */
496 	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
497 
498 	ret = iwl_pcie_gen2_nic_init(trans);
499 	if (ret) {
500 		IWL_ERR(trans, "Unable to init nic\n");
501 		goto out;
502 	}
503 
504 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
505 		ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
506 	else
507 		ret = iwl_pcie_ctxt_info_init(trans, fw);
508 	if (ret)
509 		goto out;
510 
511 	keep_ram_busy = !iwl_pcie_set_ltr(trans);
512 
513 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
514 		iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
515 		iwl_set_bit(trans, CSR_GP_CNTRL,
516 			    CSR_GP_CNTRL_REG_FLAG_ROM_START);
517 	} else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
518 		iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
519 	} else {
520 		iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
521 	}
522 
523 	if (keep_ram_busy)
524 		iwl_pcie_spin_for_iml(trans);
525 
526 	/* re-check RF-Kill state since we may have missed the interrupt */
527 	hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
528 	if (hw_rfkill && !run_in_rfkill)
529 		ret = -ERFKILL;
530 
531 out:
532 	mutex_unlock(&trans_pcie->mutex);
533 	return ret;
534 }
535