1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #include <net/mac80211.h> 18 #include <net/page_pool/helpers.h> 19 #include "util.h" 20 #include "testmode.h" 21 22 #define MT_MCU_RING_SIZE 32 23 #define MT_RX_BUF_SIZE 2048 24 #define MT_SKB_HEAD_LEN 256 25 26 #define MT_MAX_NON_AQL_PKT 16 27 #define MT_TXQ_FREE_THR 32 28 29 #define MT76_TOKEN_FREE_THR 64 30 31 #define MT_QFLAG_WED_RING GENMASK(1, 0) 32 #define MT_QFLAG_WED_TYPE GENMASK(4, 2) 33 #define MT_QFLAG_WED BIT(5) 34 #define MT_QFLAG_WED_RRO BIT(6) 35 #define MT_QFLAG_WED_RRO_EN BIT(7) 36 37 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 38 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 39 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 40 #define __MT_WED_RRO_Q(_type, _n) (MT_QFLAG_WED_RRO | __MT_WED_Q(_type, _n)) 41 42 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 43 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 44 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 45 #define MT_WED_RRO_Q_DATA(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_DATA, _n) 46 #define MT_WED_RRO_Q_MSDU_PG(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_MSDU_PG, _n) 47 #define MT_WED_RRO_Q_IND __MT_WED_RRO_Q(MT76_WED_RRO_Q_IND, 0) 48 49 struct mt76_dev; 50 struct mt76_phy; 51 struct mt76_wcid; 52 struct mt76s_intr; 53 54 struct mt76_reg_pair { 55 u32 reg; 56 u32 value; 57 }; 58 59 enum mt76_bus_type { 60 MT76_BUS_MMIO, 61 MT76_BUS_USB, 62 MT76_BUS_SDIO, 63 }; 64 65 enum mt76_wed_type { 66 MT76_WED_Q_TX, 67 MT76_WED_Q_TXFREE, 68 MT76_WED_Q_RX, 69 MT76_WED_RRO_Q_DATA, 70 MT76_WED_RRO_Q_MSDU_PG, 71 MT76_WED_RRO_Q_IND, 72 }; 73 74 struct mt76_bus_ops { 75 u32 (*rr)(struct mt76_dev *dev, u32 offset); 76 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 77 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 78 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 79 int len); 80 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 81 int len); 82 int (*wr_rp)(struct mt76_dev *dev, u32 base, 83 const struct mt76_reg_pair *rp, int len); 84 int (*rd_rp)(struct mt76_dev *dev, u32 base, 85 struct mt76_reg_pair *rp, int len); 86 enum mt76_bus_type type; 87 }; 88 89 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 90 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 91 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 92 93 enum mt76_txq_id { 94 MT_TXQ_VO = IEEE80211_AC_VO, 95 MT_TXQ_VI = IEEE80211_AC_VI, 96 MT_TXQ_BE = IEEE80211_AC_BE, 97 MT_TXQ_BK = IEEE80211_AC_BK, 98 MT_TXQ_PSD, 99 MT_TXQ_BEACON, 100 MT_TXQ_CAB, 101 __MT_TXQ_MAX 102 }; 103 104 enum mt76_mcuq_id { 105 MT_MCUQ_WM, 106 MT_MCUQ_WA, 107 MT_MCUQ_FWDL, 108 __MT_MCUQ_MAX 109 }; 110 111 enum mt76_rxq_id { 112 MT_RXQ_MAIN, 113 MT_RXQ_MCU, 114 MT_RXQ_MCU_WA, 115 MT_RXQ_BAND1, 116 MT_RXQ_BAND1_WA, 117 MT_RXQ_MAIN_WA, 118 MT_RXQ_BAND2, 119 MT_RXQ_BAND2_WA, 120 MT_RXQ_RRO_BAND0, 121 MT_RXQ_RRO_BAND1, 122 MT_RXQ_RRO_BAND2, 123 MT_RXQ_MSDU_PAGE_BAND0, 124 MT_RXQ_MSDU_PAGE_BAND1, 125 MT_RXQ_MSDU_PAGE_BAND2, 126 MT_RXQ_TXFREE_BAND0, 127 MT_RXQ_TXFREE_BAND1, 128 MT_RXQ_TXFREE_BAND2, 129 MT_RXQ_RRO_IND, 130 __MT_RXQ_MAX 131 }; 132 133 enum mt76_band_id { 134 MT_BAND0, 135 MT_BAND1, 136 MT_BAND2, 137 __MT_MAX_BAND 138 }; 139 140 enum mt76_cipher_type { 141 MT_CIPHER_NONE, 142 MT_CIPHER_WEP40, 143 MT_CIPHER_TKIP, 144 MT_CIPHER_TKIP_NO_MIC, 145 MT_CIPHER_AES_CCMP, 146 MT_CIPHER_WEP104, 147 MT_CIPHER_BIP_CMAC_128, 148 MT_CIPHER_WEP128, 149 MT_CIPHER_WAPI, 150 MT_CIPHER_CCMP_CCX, 151 MT_CIPHER_CCMP_256, 152 MT_CIPHER_GCMP, 153 MT_CIPHER_GCMP_256, 154 }; 155 156 enum mt76_dfs_state { 157 MT_DFS_STATE_UNKNOWN, 158 MT_DFS_STATE_DISABLED, 159 MT_DFS_STATE_CAC, 160 MT_DFS_STATE_ACTIVE, 161 }; 162 163 struct mt76_queue_buf { 164 dma_addr_t addr; 165 u16 len; 166 bool skip_unmap; 167 }; 168 169 struct mt76_tx_info { 170 struct mt76_queue_buf buf[32]; 171 struct sk_buff *skb; 172 int nbuf; 173 u32 info; 174 }; 175 176 struct mt76_queue_entry { 177 union { 178 void *buf; 179 struct sk_buff *skb; 180 }; 181 union { 182 struct mt76_txwi_cache *txwi; 183 struct urb *urb; 184 int buf_sz; 185 }; 186 dma_addr_t dma_addr[2]; 187 u16 dma_len[2]; 188 u16 wcid; 189 bool skip_buf0:1; 190 bool skip_buf1:1; 191 bool done:1; 192 }; 193 194 struct mt76_queue_regs { 195 u32 desc_base; 196 u32 ring_size; 197 u32 cpu_idx; 198 u32 dma_idx; 199 } __packed __aligned(4); 200 201 struct mt76_queue { 202 struct mt76_queue_regs __iomem *regs; 203 204 spinlock_t lock; 205 spinlock_t cleanup_lock; 206 struct mt76_queue_entry *entry; 207 struct mt76_rro_desc *rro_desc; 208 struct mt76_desc *desc; 209 210 u16 first; 211 u16 head; 212 u16 tail; 213 u8 hw_idx; 214 u8 ep; 215 int ndesc; 216 int queued; 217 int buf_size; 218 bool stopped; 219 bool blocked; 220 221 u8 buf_offset; 222 u16 flags; 223 224 struct mtk_wed_device *wed; 225 u32 wed_regs; 226 227 dma_addr_t desc_dma; 228 struct sk_buff *rx_head; 229 struct page_pool *page_pool; 230 }; 231 232 struct mt76_mcu_ops { 233 u32 headroom; 234 u32 tailroom; 235 236 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 237 int len, bool wait_resp); 238 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 239 int cmd, int *seq); 240 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 241 struct sk_buff *skb, int seq); 242 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 243 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 244 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 245 const struct mt76_reg_pair *rp, int len); 246 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 247 struct mt76_reg_pair *rp, int len); 248 int (*mcu_restart)(struct mt76_dev *dev); 249 }; 250 251 struct mt76_queue_ops { 252 int (*init)(struct mt76_dev *dev, 253 int (*poll)(struct napi_struct *napi, int budget)); 254 255 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 256 int idx, int n_desc, int bufsize, 257 u32 ring_base); 258 259 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 260 enum mt76_txq_id qid, struct sk_buff *skb, 261 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 262 263 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 264 struct sk_buff *skb, u32 tx_info); 265 266 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 267 int *len, u32 *info, bool *more); 268 269 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 270 271 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 272 bool flush); 273 274 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 275 276 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 277 278 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 279 }; 280 281 enum mt76_phy_type { 282 MT_PHY_TYPE_CCK, 283 MT_PHY_TYPE_OFDM, 284 MT_PHY_TYPE_HT, 285 MT_PHY_TYPE_HT_GF, 286 MT_PHY_TYPE_VHT, 287 MT_PHY_TYPE_HE_SU = 8, 288 MT_PHY_TYPE_HE_EXT_SU, 289 MT_PHY_TYPE_HE_TB, 290 MT_PHY_TYPE_HE_MU, 291 MT_PHY_TYPE_EHT_SU = 13, 292 MT_PHY_TYPE_EHT_TRIG, 293 MT_PHY_TYPE_EHT_MU, 294 __MT_PHY_TYPE_MAX, 295 }; 296 297 struct mt76_sta_stats { 298 u64 tx_mode[__MT_PHY_TYPE_MAX]; 299 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */ 300 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 301 u64 tx_mcs[16]; /* mcs idx */ 302 u64 tx_bytes; 303 /* WED TX */ 304 u32 tx_packets; /* unit: MSDU */ 305 u32 tx_retries; 306 u32 tx_failed; 307 /* WED RX */ 308 u64 rx_bytes; 309 u32 rx_packets; 310 u32 rx_errors; 311 u32 rx_drops; 312 }; 313 314 enum mt76_wcid_flags { 315 MT_WCID_FLAG_CHECK_PS, 316 MT_WCID_FLAG_PS, 317 MT_WCID_FLAG_4ADDR, 318 MT_WCID_FLAG_HDR_TRANS, 319 }; 320 321 #define MT76_N_WCIDS 1088 322 323 /* stored in ieee80211_tx_info::hw_queue */ 324 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 325 326 DECLARE_EWMA(signal, 10, 8); 327 328 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 329 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 330 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 331 #define MT_WCID_TX_INFO_SET BIT(31) 332 333 struct mt76_wcid { 334 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 335 336 atomic_t non_aql_packets; 337 unsigned long flags; 338 339 struct ewma_signal rssi; 340 int inactive_count; 341 342 struct rate_info rate; 343 unsigned long ampdu_state; 344 345 u16 idx; 346 u8 hw_key_idx; 347 u8 hw_key_idx2; 348 349 u8 sta:1; 350 u8 amsdu:1; 351 u8 phy_idx:2; 352 353 u8 rx_check_pn; 354 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 355 u16 cipher; 356 357 u32 tx_info; 358 bool sw_iv; 359 360 struct list_head tx_list; 361 struct sk_buff_head tx_pending; 362 363 struct list_head list; 364 struct idr pktid; 365 366 struct mt76_sta_stats stats; 367 368 struct list_head poll_list; 369 }; 370 371 struct mt76_txq { 372 u16 wcid; 373 374 u16 agg_ssn; 375 bool send_bar; 376 bool aggr; 377 }; 378 379 struct mt76_wed_rro_ind { 380 u32 se_id : 12; 381 u32 rsv : 4; 382 u32 start_sn : 12; 383 u32 ind_reason : 4; 384 u32 ind_cnt : 13; 385 u32 win_sz : 3; 386 u32 rsv2 : 13; 387 u32 magic_cnt : 3; 388 }; 389 390 struct mt76_txwi_cache { 391 struct list_head list; 392 dma_addr_t dma_addr; 393 394 union { 395 struct sk_buff *skb; 396 void *ptr; 397 }; 398 }; 399 400 struct mt76_rx_tid { 401 struct rcu_head rcu_head; 402 403 struct mt76_dev *dev; 404 405 spinlock_t lock; 406 struct delayed_work reorder_work; 407 408 u16 id; 409 u16 head; 410 u16 size; 411 u16 nframes; 412 413 u8 num; 414 415 u8 started:1, stopped:1, timer_pending:1; 416 417 struct sk_buff *reorder_buf[] __counted_by(size); 418 }; 419 420 #define MT_TX_CB_DMA_DONE BIT(0) 421 #define MT_TX_CB_TXS_DONE BIT(1) 422 #define MT_TX_CB_TXS_FAILED BIT(2) 423 424 #define MT_PACKET_ID_MASK GENMASK(6, 0) 425 #define MT_PACKET_ID_NO_ACK 0 426 #define MT_PACKET_ID_NO_SKB 1 427 #define MT_PACKET_ID_WED 2 428 #define MT_PACKET_ID_FIRST 3 429 #define MT_PACKET_ID_HAS_RATE BIT(7) 430 /* This is timer for when to give up when waiting for TXS callback, 431 * with starting time being the time at which the DMA_DONE callback 432 * was seen (so, we know packet was processed then, it should not take 433 * long after that for firmware to send the TXS callback if it is going 434 * to do so.) 435 */ 436 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 437 438 struct mt76_tx_cb { 439 unsigned long jiffies; 440 u16 wcid; 441 u8 pktid; 442 u8 flags; 443 }; 444 445 enum { 446 MT76_STATE_INITIALIZED, 447 MT76_STATE_REGISTERED, 448 MT76_STATE_RUNNING, 449 MT76_STATE_MCU_RUNNING, 450 MT76_SCANNING, 451 MT76_HW_SCANNING, 452 MT76_HW_SCHED_SCANNING, 453 MT76_RESTART, 454 MT76_RESET, 455 MT76_MCU_RESET, 456 MT76_REMOVED, 457 MT76_READING_STATS, 458 MT76_STATE_POWER_OFF, 459 MT76_STATE_SUSPEND, 460 MT76_STATE_ROC, 461 MT76_STATE_PM, 462 MT76_STATE_WED_RESET, 463 }; 464 465 struct mt76_hw_cap { 466 bool has_2ghz; 467 bool has_5ghz; 468 bool has_6ghz; 469 }; 470 471 #define MT_DRV_TXWI_NO_FREE BIT(0) 472 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 473 #define MT_DRV_SW_RX_AIRTIME BIT(2) 474 #define MT_DRV_RX_DMA_HDR BIT(3) 475 #define MT_DRV_HW_MGMT_TXQ BIT(4) 476 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 477 478 struct mt76_driver_ops { 479 u32 drv_flags; 480 u32 survey_flags; 481 u16 txwi_size; 482 u16 token_size; 483 u8 mcs_rates; 484 485 void (*update_survey)(struct mt76_phy *phy); 486 487 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 488 enum mt76_txq_id qid, struct mt76_wcid *wcid, 489 struct ieee80211_sta *sta, 490 struct mt76_tx_info *tx_info); 491 492 void (*tx_complete_skb)(struct mt76_dev *dev, 493 struct mt76_queue_entry *e); 494 495 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 496 497 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 498 499 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 500 struct sk_buff *skb, u32 *info); 501 502 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 503 504 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 505 bool ps); 506 507 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 508 struct ieee80211_sta *sta); 509 510 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 511 struct ieee80211_sta *sta); 512 513 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 514 struct ieee80211_sta *sta); 515 }; 516 517 struct mt76_channel_state { 518 u64 cc_active; 519 u64 cc_busy; 520 u64 cc_rx; 521 u64 cc_bss_rx; 522 u64 cc_tx; 523 524 s8 noise; 525 }; 526 527 struct mt76_sband { 528 struct ieee80211_supported_band sband; 529 struct mt76_channel_state *chan; 530 }; 531 532 /* addr req mask */ 533 #define MT_VEND_TYPE_EEPROM BIT(31) 534 #define MT_VEND_TYPE_CFG BIT(30) 535 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 536 537 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 538 enum mt_vendor_req { 539 MT_VEND_DEV_MODE = 0x1, 540 MT_VEND_WRITE = 0x2, 541 MT_VEND_POWER_ON = 0x4, 542 MT_VEND_MULTI_WRITE = 0x6, 543 MT_VEND_MULTI_READ = 0x7, 544 MT_VEND_READ_EEPROM = 0x9, 545 MT_VEND_WRITE_FCE = 0x42, 546 MT_VEND_WRITE_CFG = 0x46, 547 MT_VEND_READ_CFG = 0x47, 548 MT_VEND_READ_EXT = 0x63, 549 MT_VEND_WRITE_EXT = 0x66, 550 MT_VEND_FEATURE_SET = 0x91, 551 }; 552 553 enum mt76u_in_ep { 554 MT_EP_IN_PKT_RX, 555 MT_EP_IN_CMD_RESP, 556 __MT_EP_IN_MAX, 557 }; 558 559 enum mt76u_out_ep { 560 MT_EP_OUT_INBAND_CMD, 561 MT_EP_OUT_AC_BE, 562 MT_EP_OUT_AC_BK, 563 MT_EP_OUT_AC_VI, 564 MT_EP_OUT_AC_VO, 565 MT_EP_OUT_HCCA, 566 __MT_EP_OUT_MAX, 567 }; 568 569 struct mt76_mcu { 570 struct mutex mutex; 571 u32 msg_seq; 572 int timeout; 573 574 struct sk_buff_head res_q; 575 wait_queue_head_t wait; 576 }; 577 578 #define MT_TX_SG_MAX_SIZE 8 579 #define MT_RX_SG_MAX_SIZE 4 580 #define MT_NUM_TX_ENTRIES 256 581 #define MT_NUM_RX_ENTRIES 128 582 #define MCU_RESP_URB_SIZE 1024 583 struct mt76_usb { 584 struct mutex usb_ctrl_mtx; 585 u8 *data; 586 u16 data_len; 587 588 struct mt76_worker status_worker; 589 struct mt76_worker rx_worker; 590 591 struct work_struct stat_work; 592 593 u8 out_ep[__MT_EP_OUT_MAX]; 594 u8 in_ep[__MT_EP_IN_MAX]; 595 bool sg_en; 596 597 struct mt76u_mcu { 598 u8 *data; 599 /* multiple reads */ 600 struct mt76_reg_pair *rp; 601 int rp_len; 602 u32 base; 603 } mcu; 604 }; 605 606 #define MT76S_XMIT_BUF_SZ 0x3fe00 607 #define MT76S_NUM_TX_ENTRIES 256 608 #define MT76S_NUM_RX_ENTRIES 512 609 struct mt76_sdio { 610 struct mt76_worker txrx_worker; 611 struct mt76_worker status_worker; 612 struct mt76_worker net_worker; 613 struct mt76_worker stat_worker; 614 615 u8 *xmit_buf; 616 u32 xmit_buf_sz; 617 618 struct sdio_func *func; 619 void *intr_data; 620 u8 hw_ver; 621 wait_queue_head_t wait; 622 623 struct { 624 int pse_data_quota; 625 int ple_data_quota; 626 int pse_mcu_quota; 627 int pse_page_size; 628 int deficit; 629 } sched; 630 631 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 632 }; 633 634 struct mt76_mmio { 635 void __iomem *regs; 636 spinlock_t irq_lock; 637 u32 irqmask; 638 639 struct mtk_wed_device wed; 640 struct mtk_wed_device wed_hif2; 641 struct completion wed_reset; 642 struct completion wed_reset_complete; 643 }; 644 645 struct mt76_rx_status { 646 union { 647 struct mt76_wcid *wcid; 648 u16 wcid_idx; 649 }; 650 651 u32 reorder_time; 652 653 u32 ampdu_ref; 654 u32 timestamp; 655 656 u8 iv[6]; 657 658 u8 phy_idx:2; 659 u8 aggr:1; 660 u8 qos_ctl; 661 u16 seqno; 662 663 u16 freq; 664 u32 flag; 665 u8 enc_flags; 666 u8 encoding:3, bw:4; 667 union { 668 struct { 669 u8 he_ru:3; 670 u8 he_gi:2; 671 u8 he_dcm:1; 672 }; 673 struct { 674 u8 ru:4; 675 u8 gi:2; 676 } eht; 677 }; 678 679 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 680 u8 rate_idx; 681 u8 nss:5, band:3; 682 s8 signal; 683 u8 chains; 684 s8 chain_signal[IEEE80211_MAX_CHAINS]; 685 }; 686 687 struct mt76_freq_range_power { 688 const struct cfg80211_sar_freq_ranges *range; 689 s8 power; 690 }; 691 692 struct mt76_testmode_ops { 693 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 694 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 695 enum mt76_testmode_state new_state); 696 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 697 }; 698 699 struct mt76_testmode_data { 700 enum mt76_testmode_state state; 701 702 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 703 struct sk_buff *tx_skb; 704 705 u32 tx_count; 706 u16 tx_mpdu_len; 707 708 u8 tx_rate_mode; 709 u8 tx_rate_idx; 710 u8 tx_rate_nss; 711 u8 tx_rate_sgi; 712 u8 tx_rate_ldpc; 713 u8 tx_rate_stbc; 714 u8 tx_ltf; 715 716 u8 tx_antenna_mask; 717 u8 tx_spe_idx; 718 719 u8 tx_duty_cycle; 720 u32 tx_time; 721 u32 tx_ipg; 722 723 u32 freq_offset; 724 725 u8 tx_power[4]; 726 u8 tx_power_control; 727 728 u8 addr[3][ETH_ALEN]; 729 730 u32 tx_pending; 731 u32 tx_queued; 732 u16 tx_queued_limit; 733 u32 tx_done; 734 struct { 735 u64 packets[__MT_RXQ_MAX]; 736 u64 fcs_error[__MT_RXQ_MAX]; 737 } rx_stats; 738 }; 739 740 struct mt76_vif { 741 u8 idx; 742 u8 omac_idx; 743 u8 band_idx; 744 u8 wmm_idx; 745 u8 scan_seq_num; 746 u8 cipher; 747 u8 basic_rates_idx; 748 u8 mcast_rates_idx; 749 u8 beacon_rates_idx; 750 struct ieee80211_chanctx_conf *ctx; 751 }; 752 753 struct mt76_phy { 754 struct ieee80211_hw *hw; 755 struct mt76_dev *dev; 756 void *priv; 757 758 unsigned long state; 759 u8 band_idx; 760 761 spinlock_t tx_lock; 762 struct list_head tx_list; 763 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 764 765 struct cfg80211_chan_def chandef; 766 struct ieee80211_channel *main_chan; 767 768 struct mt76_channel_state *chan_state; 769 enum mt76_dfs_state dfs_state; 770 ktime_t survey_time; 771 772 u32 aggr_stats[32]; 773 774 struct mt76_hw_cap cap; 775 struct mt76_sband sband_2g; 776 struct mt76_sband sband_5g; 777 struct mt76_sband sband_6g; 778 779 u8 macaddr[ETH_ALEN]; 780 781 int txpower_cur; 782 u8 antenna_mask; 783 u16 chainmask; 784 785 #ifdef CONFIG_NL80211_TESTMODE 786 struct mt76_testmode_data test; 787 #endif 788 789 struct delayed_work mac_work; 790 u8 mac_work_count; 791 792 struct { 793 struct sk_buff *head; 794 struct sk_buff **tail; 795 u16 seqno; 796 } rx_amsdu[__MT_RXQ_MAX]; 797 798 struct mt76_freq_range_power *frp; 799 800 struct { 801 struct led_classdev cdev; 802 char name[32]; 803 bool al; 804 u8 pin; 805 } leds; 806 }; 807 808 struct mt76_dev { 809 struct mt76_phy phy; /* must be first */ 810 struct mt76_phy *phys[__MT_MAX_BAND]; 811 812 struct ieee80211_hw *hw; 813 814 spinlock_t wed_lock; 815 spinlock_t lock; 816 spinlock_t cc_lock; 817 818 u32 cur_cc_bss_rx; 819 820 struct mt76_rx_status rx_ampdu_status; 821 u32 rx_ampdu_len; 822 u32 rx_ampdu_ref; 823 824 struct mutex mutex; 825 826 const struct mt76_bus_ops *bus; 827 const struct mt76_driver_ops *drv; 828 const struct mt76_mcu_ops *mcu_ops; 829 struct device *dev; 830 struct device *dma_dev; 831 832 struct mt76_mcu mcu; 833 834 struct net_device napi_dev; 835 struct net_device tx_napi_dev; 836 spinlock_t rx_lock; 837 struct napi_struct napi[__MT_RXQ_MAX]; 838 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 839 struct tasklet_struct irq_tasklet; 840 841 struct list_head txwi_cache; 842 struct list_head rxwi_cache; 843 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 844 struct mt76_queue q_rx[__MT_RXQ_MAX]; 845 const struct mt76_queue_ops *queue_ops; 846 int tx_dma_idx[4]; 847 848 struct mt76_worker tx_worker; 849 struct napi_struct tx_napi; 850 851 spinlock_t token_lock; 852 struct idr token; 853 u16 wed_token_count; 854 u16 token_count; 855 u16 token_size; 856 857 spinlock_t rx_token_lock; 858 struct idr rx_token; 859 u16 rx_token_size; 860 861 wait_queue_head_t tx_wait; 862 /* spinclock used to protect wcid pktid linked list */ 863 spinlock_t status_lock; 864 865 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 866 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 867 868 u64 vif_mask; 869 870 struct mt76_wcid global_wcid; 871 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 872 struct list_head wcid_list; 873 874 struct list_head sta_poll_list; 875 spinlock_t sta_poll_lock; 876 877 u32 rev; 878 879 struct tasklet_struct pre_tbtt_tasklet; 880 int beacon_int; 881 u8 beacon_mask; 882 883 struct debugfs_blob_wrapper eeprom; 884 struct debugfs_blob_wrapper otp; 885 886 char alpha2[3]; 887 enum nl80211_dfs_regions region; 888 889 u32 debugfs_reg; 890 891 u8 csa_complete; 892 893 u32 rxfilter; 894 895 #ifdef CONFIG_NL80211_TESTMODE 896 const struct mt76_testmode_ops *test_ops; 897 struct { 898 const char *name; 899 u32 offset; 900 } test_mtd; 901 #endif 902 struct workqueue_struct *wq; 903 904 union { 905 struct mt76_mmio mmio; 906 struct mt76_usb usb; 907 struct mt76_sdio sdio; 908 }; 909 }; 910 911 /* per-phy stats. */ 912 struct mt76_mib_stats { 913 u32 ack_fail_cnt; 914 u32 fcs_err_cnt; 915 u32 rts_cnt; 916 u32 rts_retries_cnt; 917 u32 ba_miss_cnt; 918 u32 tx_bf_cnt; 919 u32 tx_mu_bf_cnt; 920 u32 tx_mu_mpdu_cnt; 921 u32 tx_mu_acked_mpdu_cnt; 922 u32 tx_su_acked_mpdu_cnt; 923 u32 tx_bf_ibf_ppdu_cnt; 924 u32 tx_bf_ebf_ppdu_cnt; 925 926 u32 tx_bf_rx_fb_all_cnt; 927 u32 tx_bf_rx_fb_eht_cnt; 928 u32 tx_bf_rx_fb_he_cnt; 929 u32 tx_bf_rx_fb_vht_cnt; 930 u32 tx_bf_rx_fb_ht_cnt; 931 932 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ 933 u32 tx_bf_rx_fb_nc_cnt; 934 u32 tx_bf_rx_fb_nr_cnt; 935 u32 tx_bf_fb_cpl_cnt; 936 u32 tx_bf_fb_trig_cnt; 937 938 u32 tx_ampdu_cnt; 939 u32 tx_stop_q_empty_cnt; 940 u32 tx_mpdu_attempts_cnt; 941 u32 tx_mpdu_success_cnt; 942 u32 tx_pkt_ebf_cnt; 943 u32 tx_pkt_ibf_cnt; 944 945 u32 tx_rwp_fail_cnt; 946 u32 tx_rwp_need_cnt; 947 948 /* rx stats */ 949 u32 rx_fifo_full_cnt; 950 u32 channel_idle_cnt; 951 u32 primary_cca_busy_time; 952 u32 secondary_cca_busy_time; 953 u32 primary_energy_detect_time; 954 u32 cck_mdrdy_time; 955 u32 ofdm_mdrdy_time; 956 u32 green_mdrdy_time; 957 u32 rx_vector_mismatch_cnt; 958 u32 rx_delimiter_fail_cnt; 959 u32 rx_mrdy_cnt; 960 u32 rx_len_mismatch_cnt; 961 u32 rx_mpdu_cnt; 962 u32 rx_ampdu_cnt; 963 u32 rx_ampdu_bytes_cnt; 964 u32 rx_ampdu_valid_subframe_cnt; 965 u32 rx_ampdu_valid_subframe_bytes_cnt; 966 u32 rx_pfdrop_cnt; 967 u32 rx_vec_queue_overflow_drop_cnt; 968 u32 rx_ba_cnt; 969 970 u32 tx_amsdu[8]; 971 u32 tx_amsdu_cnt; 972 973 /* mcu_muru_stats */ 974 u32 dl_cck_cnt; 975 u32 dl_ofdm_cnt; 976 u32 dl_htmix_cnt; 977 u32 dl_htgf_cnt; 978 u32 dl_vht_su_cnt; 979 u32 dl_vht_2mu_cnt; 980 u32 dl_vht_3mu_cnt; 981 u32 dl_vht_4mu_cnt; 982 u32 dl_he_su_cnt; 983 u32 dl_he_ext_su_cnt; 984 u32 dl_he_2ru_cnt; 985 u32 dl_he_2mu_cnt; 986 u32 dl_he_3ru_cnt; 987 u32 dl_he_3mu_cnt; 988 u32 dl_he_4ru_cnt; 989 u32 dl_he_4mu_cnt; 990 u32 dl_he_5to8ru_cnt; 991 u32 dl_he_9to16ru_cnt; 992 u32 dl_he_gtr16ru_cnt; 993 994 u32 ul_hetrig_su_cnt; 995 u32 ul_hetrig_2ru_cnt; 996 u32 ul_hetrig_3ru_cnt; 997 u32 ul_hetrig_4ru_cnt; 998 u32 ul_hetrig_5to8ru_cnt; 999 u32 ul_hetrig_9to16ru_cnt; 1000 u32 ul_hetrig_gtr16ru_cnt; 1001 u32 ul_hetrig_2mu_cnt; 1002 u32 ul_hetrig_3mu_cnt; 1003 u32 ul_hetrig_4mu_cnt; 1004 }; 1005 1006 struct mt76_power_limits { 1007 s8 cck[4]; 1008 s8 ofdm[8]; 1009 s8 mcs[4][10]; 1010 s8 ru[7][12]; 1011 s8 eht[16][16]; 1012 }; 1013 1014 struct mt76_ethtool_worker_info { 1015 u64 *data; 1016 int idx; 1017 int initial_stat_idx; 1018 int worker_stat_count; 1019 int sta_count; 1020 }; 1021 1022 #define CCK_RATE(_idx, _rate) { \ 1023 .bitrate = _rate, \ 1024 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 1025 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 1026 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 1027 } 1028 1029 #define OFDM_RATE(_idx, _rate) { \ 1030 .bitrate = _rate, \ 1031 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 1032 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 1033 } 1034 1035 extern struct ieee80211_rate mt76_rates[12]; 1036 1037 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 1038 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 1039 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 1040 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 1041 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 1042 1043 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 1044 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 1045 1046 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 1047 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 1048 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 1049 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 1050 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 1051 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 1052 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 1053 1054 1055 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 1056 1057 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 1058 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 1059 1060 #define mt76_get_field(_dev, _reg, _field) \ 1061 FIELD_GET(_field, mt76_rr(dev, _reg)) 1062 1063 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 1064 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1065 1066 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 1067 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1068 1069 #define mt76_hw(dev) (dev)->mphy.hw 1070 1071 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1072 int timeout); 1073 1074 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 1075 1076 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1077 int timeout, int kick); 1078 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 1079 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 1080 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 1081 1082 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 1083 void mt76_pci_disable_aspm(struct pci_dev *pdev); 1084 1085 static inline u16 mt76_chip(struct mt76_dev *dev) 1086 { 1087 return dev->rev >> 16; 1088 } 1089 1090 static inline u16 mt76_rev(struct mt76_dev *dev) 1091 { 1092 return dev->rev & 0xffff; 1093 } 1094 1095 void mt76_wed_release_rx_buf(struct mtk_wed_device *wed); 1096 void mt76_wed_offload_disable(struct mtk_wed_device *wed); 1097 void mt76_wed_reset_complete(struct mtk_wed_device *wed); 1098 void mt76_wed_dma_reset(struct mt76_dev *dev); 1099 int mt76_wed_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1100 struct net_device *netdev, enum tc_setup_type type, 1101 void *type_data); 1102 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 1103 u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size); 1104 int mt76_wed_offload_enable(struct mtk_wed_device *wed); 1105 int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset); 1106 #else 1107 static inline u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size) 1108 { 1109 return 0; 1110 } 1111 1112 static inline int mt76_wed_offload_enable(struct mtk_wed_device *wed) 1113 { 1114 return 0; 1115 } 1116 1117 static inline int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, 1118 bool reset) 1119 { 1120 return 0; 1121 } 1122 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 1123 1124 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 1125 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 1126 1127 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 1128 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 1129 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 1130 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 1131 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 1132 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 1133 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 1134 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 1135 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 1136 1137 #define mt76_for_each_q_rx(dev, i) \ 1138 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 1139 if ((dev)->q_rx[i].ndesc) 1140 1141 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 1142 const struct ieee80211_ops *ops, 1143 const struct mt76_driver_ops *drv_ops); 1144 int mt76_register_device(struct mt76_dev *dev, bool vht, 1145 struct ieee80211_rate *rates, int n_rates); 1146 void mt76_unregister_device(struct mt76_dev *dev); 1147 void mt76_free_device(struct mt76_dev *dev); 1148 void mt76_unregister_phy(struct mt76_phy *phy); 1149 1150 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 1151 const struct ieee80211_ops *ops, 1152 u8 band_idx); 1153 int mt76_register_phy(struct mt76_phy *phy, bool vht, 1154 struct ieee80211_rate *rates, int n_rates); 1155 1156 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 1157 const struct file_operations *ops); 1158 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 1159 { 1160 return mt76_register_debugfs_fops(&dev->phy, NULL); 1161 } 1162 1163 int mt76_queues_read(struct seq_file *s, void *data); 1164 void mt76_seq_puts_array(struct seq_file *file, const char *str, 1165 s8 *val, int len); 1166 1167 int mt76_eeprom_init(struct mt76_dev *dev, int len); 1168 void mt76_eeprom_override(struct mt76_phy *phy); 1169 int mt76_get_of_data_from_mtd(struct mt76_dev *dev, void *eep, int offset, int len); 1170 int mt76_get_of_data_from_nvmem(struct mt76_dev *dev, void *eep, 1171 const char *cell_name, int len); 1172 1173 struct mt76_queue * 1174 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 1175 int ring_base, void *wed, u32 flags); 1176 u16 mt76_calculate_default_rate(struct mt76_phy *phy, 1177 struct ieee80211_vif *vif, int rateidx); 1178 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 1179 int n_desc, int ring_base, void *wed, 1180 u32 flags) 1181 { 1182 struct mt76_queue *q; 1183 1184 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, wed, flags); 1185 if (IS_ERR(q)) 1186 return PTR_ERR(q); 1187 1188 phy->q_tx[qid] = q; 1189 1190 return 0; 1191 } 1192 1193 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 1194 int n_desc, int ring_base) 1195 { 1196 struct mt76_queue *q; 1197 1198 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, NULL, 0); 1199 if (IS_ERR(q)) 1200 return PTR_ERR(q); 1201 1202 dev->q_mcu[qid] = q; 1203 1204 return 0; 1205 } 1206 1207 static inline struct mt76_phy * 1208 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1209 { 1210 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1211 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1212 return dev->phys[phy_idx]; 1213 1214 return &dev->phy; 1215 } 1216 1217 static inline struct ieee80211_hw * 1218 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1219 { 1220 return mt76_dev_phy(dev, phy_idx)->hw; 1221 } 1222 1223 static inline u8 * 1224 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1225 { 1226 return (u8 *)t - dev->drv->txwi_size; 1227 } 1228 1229 /* increment with wrap-around */ 1230 static inline int mt76_incr(int val, int size) 1231 { 1232 return (val + 1) & (size - 1); 1233 } 1234 1235 /* decrement with wrap-around */ 1236 static inline int mt76_decr(int val, int size) 1237 { 1238 return (val - 1) & (size - 1); 1239 } 1240 1241 u8 mt76_ac_to_hwq(u8 ac); 1242 1243 static inline struct ieee80211_txq * 1244 mtxq_to_txq(struct mt76_txq *mtxq) 1245 { 1246 void *ptr = mtxq; 1247 1248 return container_of(ptr, struct ieee80211_txq, drv_priv); 1249 } 1250 1251 static inline struct ieee80211_sta * 1252 wcid_to_sta(struct mt76_wcid *wcid) 1253 { 1254 void *ptr = wcid; 1255 1256 if (!wcid || !wcid->sta) 1257 return NULL; 1258 1259 return container_of(ptr, struct ieee80211_sta, drv_priv); 1260 } 1261 1262 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1263 { 1264 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1265 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1266 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1267 } 1268 1269 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1270 { 1271 struct mt76_rx_status mstat; 1272 u8 *data = skb->data; 1273 1274 /* Alignment concerns */ 1275 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1276 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1277 1278 mstat = *((struct mt76_rx_status *)skb->cb); 1279 1280 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1281 data += sizeof(struct ieee80211_radiotap_he); 1282 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1283 data += sizeof(struct ieee80211_radiotap_he_mu); 1284 1285 return data; 1286 } 1287 1288 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1289 { 1290 int len = ieee80211_get_hdrlen_from_skb(skb); 1291 1292 if (len % 4 == 0) 1293 return; 1294 1295 skb_push(skb, 2); 1296 memmove(skb->data, skb->data + 2, len); 1297 1298 skb->data[len] = 0; 1299 skb->data[len + 1] = 0; 1300 } 1301 1302 static inline bool mt76_is_skb_pktid(u8 pktid) 1303 { 1304 if (pktid & MT_PACKET_ID_HAS_RATE) 1305 return false; 1306 1307 return pktid >= MT_PACKET_ID_FIRST; 1308 } 1309 1310 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1311 { 1312 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1313 u8 idx = nss - 1; 1314 1315 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0; 1316 } 1317 1318 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1319 { 1320 #ifdef CONFIG_NL80211_TESTMODE 1321 return phy->test.state != MT76_TM_STATE_OFF; 1322 #else 1323 return false; 1324 #endif 1325 } 1326 1327 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1328 struct sk_buff *skb, 1329 struct ieee80211_hw **hw) 1330 { 1331 #ifdef CONFIG_NL80211_TESTMODE 1332 int i; 1333 1334 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1335 struct mt76_phy *phy = dev->phys[i]; 1336 1337 if (phy && skb == phy->test.tx_skb) { 1338 *hw = dev->phys[i]->hw; 1339 return true; 1340 } 1341 } 1342 return false; 1343 #else 1344 return false; 1345 #endif 1346 } 1347 1348 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1349 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1350 struct mt76_wcid *wcid, struct sk_buff *skb); 1351 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1352 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1353 bool send_bar); 1354 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1355 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1356 void mt76_txq_schedule_all(struct mt76_phy *phy); 1357 void mt76_tx_worker_run(struct mt76_dev *dev); 1358 void mt76_tx_worker(struct mt76_worker *w); 1359 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1360 struct ieee80211_sta *sta, 1361 u16 tids, int nframes, 1362 enum ieee80211_frame_release_type reason, 1363 bool more_data); 1364 bool mt76_has_tx_pending(struct mt76_phy *phy); 1365 void mt76_set_channel(struct mt76_phy *phy); 1366 void mt76_update_survey(struct mt76_phy *phy); 1367 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1368 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1369 struct survey_info *survey); 1370 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1371 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1372 1373 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1374 u16 ssn, u16 size); 1375 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1376 1377 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1378 struct ieee80211_key_conf *key); 1379 1380 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1381 __acquires(&dev->status_lock); 1382 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1383 __releases(&dev->status_lock); 1384 1385 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1386 struct sk_buff *skb); 1387 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1388 struct mt76_wcid *wcid, int pktid, 1389 struct sk_buff_head *list); 1390 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1391 struct sk_buff_head *list); 1392 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1393 struct list_head *free_list); 1394 static inline void 1395 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1396 { 1397 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1398 } 1399 1400 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1401 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1402 struct ieee80211_sta *sta, 1403 enum ieee80211_sta_state old_state, 1404 enum ieee80211_sta_state new_state); 1405 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1406 struct ieee80211_sta *sta); 1407 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1408 struct ieee80211_sta *sta); 1409 1410 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1411 1412 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1413 int *dbm); 1414 int mt76_init_sar_power(struct ieee80211_hw *hw, 1415 const struct cfg80211_sar_specs *sar); 1416 int mt76_get_sar_power(struct mt76_phy *phy, 1417 struct ieee80211_channel *chan, 1418 int power); 1419 1420 void mt76_csa_check(struct mt76_dev *dev); 1421 void mt76_csa_finish(struct mt76_dev *dev); 1422 1423 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1424 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1425 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1426 int mt76_get_rate(struct mt76_dev *dev, 1427 struct ieee80211_supported_band *sband, 1428 int idx, bool cck); 1429 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1430 const u8 *mac); 1431 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1432 struct ieee80211_vif *vif); 1433 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1434 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1435 void *data, int len); 1436 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1437 struct netlink_callback *cb, void *data, int len); 1438 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1439 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1440 1441 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1442 { 1443 #ifdef CONFIG_NL80211_TESTMODE 1444 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1445 1446 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1447 state = MT76_TM_STATE_OFF; 1448 1449 mt76_testmode_set_state(phy, state); 1450 #endif 1451 } 1452 1453 1454 /* internal */ 1455 static inline struct ieee80211_hw * 1456 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1457 { 1458 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1459 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1460 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1461 1462 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1463 1464 return hw; 1465 } 1466 1467 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1468 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1469 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1470 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1471 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1472 struct napi_struct *napi); 1473 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1474 struct napi_struct *napi); 1475 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1476 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1477 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1478 struct mt76_queue_entry *e); 1479 1480 /* usb */ 1481 static inline bool mt76u_urb_error(struct urb *urb) 1482 { 1483 return urb->status && 1484 urb->status != -ECONNRESET && 1485 urb->status != -ESHUTDOWN && 1486 urb->status != -ENOENT; 1487 } 1488 1489 static inline int 1490 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1491 int timeout, int ep) 1492 { 1493 struct usb_interface *uintf = to_usb_interface(dev->dev); 1494 struct usb_device *udev = interface_to_usbdev(uintf); 1495 struct mt76_usb *usb = &dev->usb; 1496 unsigned int pipe; 1497 1498 if (actual_len) 1499 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1500 else 1501 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1502 1503 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1504 } 1505 1506 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1507 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1508 struct mt76_sta_stats *stats, bool eht); 1509 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1510 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1511 u16 val, u16 offset, void *buf, size_t len); 1512 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1513 u8 req_type, u16 val, u16 offset, 1514 void *buf, size_t len); 1515 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1516 const u16 offset, const u32 val); 1517 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1518 void *data, int len); 1519 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1520 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1521 u32 addr, u32 val); 1522 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1523 struct mt76_bus_ops *ops); 1524 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1525 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1526 int mt76u_alloc_queues(struct mt76_dev *dev); 1527 void mt76u_stop_tx(struct mt76_dev *dev); 1528 void mt76u_stop_rx(struct mt76_dev *dev); 1529 int mt76u_resume_rx(struct mt76_dev *dev); 1530 void mt76u_queues_deinit(struct mt76_dev *dev); 1531 1532 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1533 const struct mt76_bus_ops *bus_ops); 1534 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1535 int mt76s_alloc_tx(struct mt76_dev *dev); 1536 void mt76s_deinit(struct mt76_dev *dev); 1537 void mt76s_sdio_irq(struct sdio_func *func); 1538 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1539 bool mt76s_txqs_empty(struct mt76_dev *dev); 1540 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1541 int hw_ver); 1542 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1543 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1544 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1545 u32 mt76s_read_pcr(struct mt76_dev *dev); 1546 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1547 const void *data, int len); 1548 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1549 void *data, int len); 1550 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1551 const struct mt76_reg_pair *data, 1552 int len); 1553 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1554 struct mt76_reg_pair *data, int len); 1555 1556 struct sk_buff * 1557 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1558 int len, int data_len, gfp_t gfp); 1559 static inline struct sk_buff * 1560 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1561 int data_len) 1562 { 1563 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1564 } 1565 1566 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1567 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1568 unsigned long expires); 1569 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1570 int len, bool wait_resp, struct sk_buff **ret); 1571 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1572 int cmd, bool wait_resp, struct sk_buff **ret); 1573 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1574 int len, int max_len); 1575 static inline int 1576 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1577 int len) 1578 { 1579 int max_len = 4096 - dev->mcu_ops->headroom; 1580 1581 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1582 } 1583 1584 static inline int 1585 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1586 bool wait_resp) 1587 { 1588 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1589 } 1590 1591 static inline int 1592 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1593 bool wait_resp) 1594 { 1595 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1596 } 1597 1598 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1599 1600 struct device_node * 1601 mt76_find_power_limits_node(struct mt76_dev *dev); 1602 struct device_node * 1603 mt76_find_channel_node(struct device_node *np, struct ieee80211_channel *chan); 1604 1605 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1606 struct ieee80211_channel *chan, 1607 struct mt76_power_limits *dest, 1608 s8 target_power); 1609 1610 static inline bool mt76_queue_is_rx(struct mt76_dev *dev, struct mt76_queue *q) 1611 { 1612 int i; 1613 1614 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) { 1615 if (q == &dev->q_rx[i]) 1616 return true; 1617 } 1618 1619 return false; 1620 } 1621 1622 static inline bool mt76_queue_is_wed_tx_free(struct mt76_queue *q) 1623 { 1624 return (q->flags & MT_QFLAG_WED) && 1625 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TXFREE; 1626 } 1627 1628 static inline bool mt76_queue_is_wed_rro(struct mt76_queue *q) 1629 { 1630 return q->flags & MT_QFLAG_WED_RRO; 1631 } 1632 1633 static inline bool mt76_queue_is_wed_rro_ind(struct mt76_queue *q) 1634 { 1635 return mt76_queue_is_wed_rro(q) && 1636 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_IND; 1637 } 1638 1639 static inline bool mt76_queue_is_wed_rro_data(struct mt76_queue *q) 1640 { 1641 return mt76_queue_is_wed_rro(q) && 1642 (FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA || 1643 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_MSDU_PG); 1644 } 1645 1646 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1647 { 1648 if (!(q->flags & MT_QFLAG_WED)) 1649 return false; 1650 1651 return FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX || 1652 mt76_queue_is_wed_rro_ind(q) || mt76_queue_is_wed_rro_data(q); 1653 1654 } 1655 1656 struct mt76_txwi_cache * 1657 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1658 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1659 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1660 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 1661 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 1662 struct mt76_txwi_cache *r, dma_addr_t phys); 1663 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 1664 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 1665 { 1666 struct page *page = virt_to_head_page(buf); 1667 1668 page_pool_put_full_page(page->pp, page, allow_direct); 1669 } 1670 1671 static inline void * 1672 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 1673 { 1674 struct page *page; 1675 1676 page = page_pool_dev_alloc_frag(q->page_pool, offset, size); 1677 if (!page) 1678 return NULL; 1679 1680 return page_address(page) + *offset; 1681 } 1682 1683 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1684 { 1685 spin_lock_bh(&dev->token_lock); 1686 __mt76_set_tx_blocked(dev, blocked); 1687 spin_unlock_bh(&dev->token_lock); 1688 } 1689 1690 static inline int 1691 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1692 { 1693 int token; 1694 1695 spin_lock_bh(&dev->token_lock); 1696 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1697 spin_unlock_bh(&dev->token_lock); 1698 1699 return token; 1700 } 1701 1702 static inline struct mt76_txwi_cache * 1703 mt76_token_put(struct mt76_dev *dev, int token) 1704 { 1705 struct mt76_txwi_cache *txwi; 1706 1707 spin_lock_bh(&dev->token_lock); 1708 txwi = idr_remove(&dev->token, token); 1709 spin_unlock_bh(&dev->token_lock); 1710 1711 return txwi; 1712 } 1713 1714 void mt76_wcid_init(struct mt76_wcid *wcid); 1715 void mt76_wcid_cleanup(struct mt76_dev *dev, struct mt76_wcid *wcid); 1716 1717 #endif 1718