1 /* 2 * (c) Copyright 2002-2010, Ralink Technology, Inc. 3 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 5 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 9 * as published by the Free Software Foundation 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include "mt76x0.h" 18 #include "eeprom.h" 19 #include "mcu.h" 20 #include "initvals.h" 21 22 static void mt76x0_vht_cap_mask(struct ieee80211_supported_band *sband) 23 { 24 struct ieee80211_sta_vht_cap *vht_cap = &sband->vht_cap; 25 u16 mcs_map = 0; 26 int i; 27 28 vht_cap->cap &= ~IEEE80211_VHT_CAP_RXLDPC; 29 for (i = 0; i < 8; i++) { 30 if (!i) 31 mcs_map |= (IEEE80211_VHT_MCS_SUPPORT_0_7 << (i * 2)); 32 else 33 mcs_map |= 34 (IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2)); 35 } 36 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 37 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 38 } 39 40 static void 41 mt76x0_set_wlan_state(struct mt76x02_dev *dev, u32 val, bool enable) 42 { 43 u32 mask = MT_CMB_CTRL_XTAL_RDY | MT_CMB_CTRL_PLL_LD; 44 45 /* Note: we don't turn off WLAN_CLK because that makes the device 46 * not respond properly on the probe path. 47 * In case anyone (PSM?) wants to use this function we can 48 * bring the clock stuff back and fixup the probe path. 49 */ 50 51 if (enable) 52 val |= (MT_WLAN_FUN_CTRL_WLAN_EN | 53 MT_WLAN_FUN_CTRL_WLAN_CLK_EN); 54 else 55 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN); 56 57 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 58 udelay(20); 59 60 /* Note: vendor driver tries to disable/enable wlan here and retry 61 * but the code which does it is so buggy it must have never 62 * triggered, so don't bother. 63 */ 64 if (enable && !mt76_poll(dev, MT_CMB_CTRL, mask, mask, 2000)) 65 dev_err(dev->mt76.dev, "PLL and XTAL check failed\n"); 66 } 67 68 void mt76x0_chip_onoff(struct mt76x02_dev *dev, bool enable, bool reset) 69 { 70 u32 val; 71 72 val = mt76_rr(dev, MT_WLAN_FUN_CTRL); 73 74 if (reset) { 75 val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN; 76 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL; 77 78 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) { 79 val |= (MT_WLAN_FUN_CTRL_WLAN_RESET | 80 MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 81 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 82 udelay(20); 83 84 val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET | 85 MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 86 } 87 } 88 89 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 90 udelay(20); 91 92 mt76x0_set_wlan_state(dev, val, enable); 93 } 94 EXPORT_SYMBOL_GPL(mt76x0_chip_onoff); 95 96 static void mt76x0_reset_csr_bbp(struct mt76x02_dev *dev) 97 { 98 mt76_wr(dev, MT_MAC_SYS_CTRL, 99 MT_MAC_SYS_CTRL_RESET_CSR | 100 MT_MAC_SYS_CTRL_RESET_BBP); 101 msleep(200); 102 mt76_clear(dev, MT_MAC_SYS_CTRL, 103 MT_MAC_SYS_CTRL_RESET_CSR | 104 MT_MAC_SYS_CTRL_RESET_BBP); 105 } 106 107 #define RANDOM_WRITE(dev, tab) \ 108 mt76_wr_rp(dev, MT_MCU_MEMMAP_WLAN, \ 109 tab, ARRAY_SIZE(tab)) 110 111 static int mt76x0_init_bbp(struct mt76x02_dev *dev) 112 { 113 int ret, i; 114 115 ret = mt76x0_phy_wait_bbp_ready(dev); 116 if (ret) 117 return ret; 118 119 RANDOM_WRITE(dev, mt76x0_bbp_init_tab); 120 121 for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) { 122 const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i]; 123 const struct mt76_reg_pair *pair = &item->reg_pair; 124 125 if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20)) 126 mt76_wr(dev, pair->reg, pair->value); 127 } 128 129 RANDOM_WRITE(dev, mt76x0_dcoc_tab); 130 131 return 0; 132 } 133 134 static void mt76x0_init_mac_registers(struct mt76x02_dev *dev) 135 { 136 RANDOM_WRITE(dev, common_mac_reg_table); 137 138 /* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */ 139 RANDOM_WRITE(dev, mt76x0_mac_reg_table); 140 141 /* Release BBP and MAC reset MAC_SYS_CTRL[1:0] = 0x0 */ 142 mt76_clear(dev, MT_MAC_SYS_CTRL, 0x3); 143 144 /* Set 0x141C[15:12]=0xF */ 145 mt76_set(dev, MT_EXT_CCA_CFG, 0xf000); 146 147 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); 148 149 /* 150 * tx_ring 9 is for mgmt frame 151 * tx_ring 8 is for in-band command frame. 152 * WMM_RG0_TXQMA: this register setting is for FCE to 153 * define the rule of tx_ring 9 154 * WMM_RG1_TXQMA: this register setting is for FCE to 155 * define the rule of tx_ring 8 156 */ 157 mt76_rmw(dev, MT_WMM_CTRL, 0x3ff, 0x201); 158 } 159 160 static void mt76x0_reset_counters(struct mt76x02_dev *dev) 161 { 162 mt76_rr(dev, MT_RX_STAT_0); 163 mt76_rr(dev, MT_RX_STAT_1); 164 mt76_rr(dev, MT_RX_STAT_2); 165 mt76_rr(dev, MT_TX_STA_0); 166 mt76_rr(dev, MT_TX_STA_1); 167 mt76_rr(dev, MT_TX_STA_2); 168 } 169 170 int mt76x0_mac_start(struct mt76x02_dev *dev) 171 { 172 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 173 174 if (!mt76x02_wait_for_wpdma(&dev->mt76, 200000)) 175 return -ETIMEDOUT; 176 177 mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter); 178 mt76_wr(dev, MT_MAC_SYS_CTRL, 179 MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); 180 181 return !mt76x02_wait_for_wpdma(&dev->mt76, 50) ? -ETIMEDOUT : 0; 182 } 183 EXPORT_SYMBOL_GPL(mt76x0_mac_start); 184 185 void mt76x0_mac_stop(struct mt76x02_dev *dev) 186 { 187 int i = 200, ok = 0; 188 189 /* Page count on TxQ */ 190 while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) || 191 (mt76_rr(dev, 0x0a30) & 0x000000ff) || 192 (mt76_rr(dev, 0x0a34) & 0x00ff00ff))) 193 msleep(10); 194 195 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000)) 196 dev_warn(dev->mt76.dev, "Warning: MAC TX did not stop!\n"); 197 198 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX | 199 MT_MAC_SYS_CTRL_ENABLE_TX); 200 201 /* Page count on RxQ */ 202 for (i = 0; i < 200; i++) { 203 if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) && 204 !mt76_rr(dev, 0x0a30) && 205 !mt76_rr(dev, 0x0a34)) { 206 if (ok++ > 5) 207 break; 208 continue; 209 } 210 msleep(1); 211 } 212 213 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000)) 214 dev_warn(dev->mt76.dev, "Warning: MAC RX did not stop!\n"); 215 } 216 EXPORT_SYMBOL_GPL(mt76x0_mac_stop); 217 218 int mt76x0_init_hardware(struct mt76x02_dev *dev) 219 { 220 int ret, i, k; 221 222 if (!mt76x02_wait_for_wpdma(&dev->mt76, 1000)) 223 return -EIO; 224 225 /* Wait for ASIC ready after FW load. */ 226 if (!mt76x02_wait_for_mac(&dev->mt76)) 227 return -ETIMEDOUT; 228 229 mt76x0_reset_csr_bbp(dev); 230 ret = mt76x02_mcu_function_select(dev, Q_SELECT, 1); 231 if (ret) 232 return ret; 233 234 mt76x0_init_mac_registers(dev); 235 236 if (!mt76x02_wait_for_txrx_idle(&dev->mt76)) 237 return -EIO; 238 239 ret = mt76x0_init_bbp(dev); 240 if (ret) 241 return ret; 242 243 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); 244 245 for (i = 0; i < 16; i++) 246 for (k = 0; k < 4; k++) 247 mt76x02_mac_shared_key_setup(dev, i, k, NULL); 248 249 for (i = 0; i < 256; i++) 250 mt76x02_mac_wcid_setup(dev, i, 0, NULL); 251 252 mt76x0_reset_counters(dev); 253 254 ret = mt76x0_eeprom_init(dev); 255 if (ret) 256 return ret; 257 258 mt76x0_phy_init(dev); 259 mt76x02_init_beacon_config(dev); 260 261 return 0; 262 } 263 EXPORT_SYMBOL_GPL(mt76x0_init_hardware); 264 265 struct mt76x02_dev * 266 mt76x0_alloc_device(struct device *pdev, 267 const struct mt76_driver_ops *drv_ops, 268 const struct ieee80211_ops *ops) 269 { 270 struct mt76x02_dev *dev; 271 struct mt76_dev *mdev; 272 273 mdev = mt76_alloc_device(sizeof(*dev), ops); 274 if (!mdev) 275 return NULL; 276 277 mdev->dev = pdev; 278 mdev->drv = drv_ops; 279 280 dev = container_of(mdev, struct mt76x02_dev, mt76); 281 mutex_init(&dev->phy_mutex); 282 283 return dev; 284 } 285 EXPORT_SYMBOL_GPL(mt76x0_alloc_device); 286 287 int mt76x0_register_device(struct mt76x02_dev *dev) 288 { 289 int ret; 290 291 mt76x02_init_device(dev); 292 ret = mt76_register_device(&dev->mt76, true, mt76x02_rates, 293 ARRAY_SIZE(mt76x02_rates)); 294 if (ret) 295 return ret; 296 297 /* overwrite unsupported features */ 298 if (dev->mt76.cap.has_5ghz) 299 mt76x0_vht_cap_mask(&dev->mt76.sband_5g.sband); 300 301 mt76x02_init_debugfs(dev); 302 303 return 0; 304 } 305 EXPORT_SYMBOL_GPL(mt76x0_register_device); 306