1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __MT76X02_MAC_H 19 #define __MT76X02_MAC_H 20 21 struct mt76x02_dev; 22 23 struct mt76x02_tx_status { 24 u8 valid:1; 25 u8 success:1; 26 u8 aggr:1; 27 u8 ack_req:1; 28 u8 wcid; 29 u8 pktid; 30 u8 retry; 31 u16 rate; 32 } __packed __aligned(2); 33 34 #define MT_VIF_WCID(_n) (254 - ((_n) & 7)) 35 #define MT_MAX_VIFS 8 36 37 struct mt76x02_vif { 38 struct mt76_wcid group_wcid; /* must be first */ 39 u8 idx; 40 }; 41 42 struct mt76x02_sta { 43 struct mt76_wcid wcid; /* must be first */ 44 45 struct mt76x02_vif *vif; 46 struct mt76x02_tx_status status; 47 int n_frames; 48 49 }; 50 51 #define MT_RXINFO_BA BIT(0) 52 #define MT_RXINFO_DATA BIT(1) 53 #define MT_RXINFO_NULL BIT(2) 54 #define MT_RXINFO_FRAG BIT(3) 55 #define MT_RXINFO_UNICAST BIT(4) 56 #define MT_RXINFO_MULTICAST BIT(5) 57 #define MT_RXINFO_BROADCAST BIT(6) 58 #define MT_RXINFO_MYBSS BIT(7) 59 #define MT_RXINFO_CRCERR BIT(8) 60 #define MT_RXINFO_ICVERR BIT(9) 61 #define MT_RXINFO_MICERR BIT(10) 62 #define MT_RXINFO_AMSDU BIT(11) 63 #define MT_RXINFO_HTC BIT(12) 64 #define MT_RXINFO_RSSI BIT(13) 65 #define MT_RXINFO_L2PAD BIT(14) 66 #define MT_RXINFO_AMPDU BIT(15) 67 #define MT_RXINFO_DECRYPT BIT(16) 68 #define MT_RXINFO_BSSIDX3 BIT(17) 69 #define MT_RXINFO_WAPI_KEY BIT(18) 70 #define MT_RXINFO_PN_LEN GENMASK(21, 19) 71 #define MT_RXINFO_SW_FTYPE0 BIT(22) 72 #define MT_RXINFO_SW_FTYPE1 BIT(23) 73 #define MT_RXINFO_PROBE_RESP BIT(24) 74 #define MT_RXINFO_BEACON BIT(25) 75 #define MT_RXINFO_DISASSOC BIT(26) 76 #define MT_RXINFO_DEAUTH BIT(27) 77 #define MT_RXINFO_ACTION BIT(28) 78 #define MT_RXINFO_TCP_SUM_ERR BIT(30) 79 #define MT_RXINFO_IP_SUM_ERR BIT(31) 80 81 #define MT_RXWI_CTL_WCID GENMASK(7, 0) 82 #define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8) 83 #define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10) 84 #define MT_RXWI_CTL_UDF GENMASK(15, 13) 85 #define MT_RXWI_CTL_MPDU_LEN GENMASK(29, 16) 86 #define MT_RXWI_CTL_EOF BIT(31) 87 88 #define MT_RXWI_TID GENMASK(3, 0) 89 #define MT_RXWI_SN GENMASK(15, 4) 90 91 #define MT_RXWI_RATE_INDEX GENMASK(5, 0) 92 #define MT_RXWI_RATE_LDPC BIT(6) 93 #define MT_RXWI_RATE_BW GENMASK(8, 7) 94 #define MT_RXWI_RATE_SGI BIT(9) 95 #define MT_RXWI_RATE_STBC BIT(10) 96 #define MT_RXWI_RATE_LDPC_EXSYM BIT(11) 97 #define MT_RXWI_RATE_PHY GENMASK(15, 13) 98 99 #define MT_RATE_INDEX_VHT_IDX GENMASK(3, 0) 100 #define MT_RATE_INDEX_VHT_NSS GENMASK(5, 4) 101 102 struct mt76x02_rxwi { 103 __le32 rxinfo; 104 105 __le32 ctl; 106 107 __le16 tid_sn; 108 __le16 rate; 109 110 u8 rssi[4]; 111 112 __le32 bbp_rxinfo[4]; 113 }; 114 115 #define MT_TX_PWR_ADJ GENMASK(3, 0) 116 117 enum mt76x2_phy_bandwidth { 118 MT_PHY_BW_20, 119 MT_PHY_BW_40, 120 MT_PHY_BW_80, 121 }; 122 123 #define MT_TXWI_FLAGS_FRAG BIT(0) 124 #define MT_TXWI_FLAGS_MMPS BIT(1) 125 #define MT_TXWI_FLAGS_CFACK BIT(2) 126 #define MT_TXWI_FLAGS_TS BIT(3) 127 #define MT_TXWI_FLAGS_AMPDU BIT(4) 128 #define MT_TXWI_FLAGS_MPDU_DENSITY GENMASK(7, 5) 129 #define MT_TXWI_FLAGS_TXOP GENMASK(9, 8) 130 #define MT_TXWI_FLAGS_NDPS BIT(10) 131 #define MT_TXWI_FLAGS_RTSBWSIG BIT(11) 132 #define MT_TXWI_FLAGS_NDP_BW GENMASK(13, 12) 133 #define MT_TXWI_FLAGS_SOUND BIT(14) 134 #define MT_TXWI_FLAGS_TX_RATE_LUT BIT(15) 135 136 #define MT_TXWI_ACK_CTL_REQ BIT(0) 137 #define MT_TXWI_ACK_CTL_NSEQ BIT(1) 138 #define MT_TXWI_ACK_CTL_BA_WINDOW GENMASK(7, 2) 139 140 struct mt76x02_txwi { 141 __le16 flags; 142 __le16 rate; 143 u8 ack_ctl; 144 u8 wcid; 145 __le16 len_ctl; 146 __le32 iv; 147 __le32 eiv; 148 u8 aid; 149 u8 txstream; 150 u8 ctl2; 151 u8 pktid; 152 } __packed __aligned(4); 153 154 static inline bool mt76x02_wait_for_mac(struct mt76_dev *dev) 155 { 156 const u32 MAC_CSR0 = 0x1000; 157 int i; 158 159 for (i = 0; i < 500; i++) { 160 if (test_bit(MT76_REMOVED, &dev->state)) 161 return false; 162 163 switch (dev->bus->rr(dev, MAC_CSR0)) { 164 case 0: 165 case ~0: 166 break; 167 default: 168 return true; 169 } 170 usleep_range(5000, 10000); 171 } 172 return false; 173 } 174 175 void mt76x02_mac_set_short_preamble(struct mt76x02_dev *dev, bool enable); 176 int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx, 177 u8 key_idx, struct ieee80211_key_conf *key); 178 int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx, 179 struct ieee80211_key_conf *key); 180 void mt76x02_mac_wcid_sync_pn(struct mt76x02_dev *dev, u8 idx, 181 struct ieee80211_key_conf *key); 182 void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, u8 vif_idx, 183 u8 *mac); 184 void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop); 185 void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid, 186 const struct ieee80211_tx_rate *rate); 187 bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev, 188 struct mt76x02_tx_status *stat); 189 void mt76x02_send_tx_status(struct mt76x02_dev *dev, 190 struct mt76x02_tx_status *stat, u8 *update); 191 int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb, 192 void *rxi); 193 void mt76x02_mac_set_tx_protection(struct mt76x02_dev *dev, bool legacy_prot, 194 int ht_mode); 195 void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val); 196 void mt76x02_mac_setaddr(struct mt76x02_dev *dev, const u8 *addr); 197 void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi, 198 struct sk_buff *skb, struct mt76_wcid *wcid, 199 struct ieee80211_sta *sta, int len); 200 void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq); 201 void mt76x02_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid, 202 struct mt76_queue_entry *e); 203 void mt76x02_update_channel(struct mt76_dev *mdev); 204 void mt76x02_mac_work(struct work_struct *work); 205 206 void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr); 207 int mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 vif_idx, 208 struct sk_buff *skb); 209 void mt76x02_mac_set_beacon_enable(struct mt76x02_dev *dev, 210 struct ieee80211_vif *vif, bool val); 211 212 void mt76x02_edcca_init(struct mt76x02_dev *dev, bool enable); 213 #endif 214