1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_MAC_H 5 #define __MT7915_MAC_H 6 7 #include "../mt76_connac2_mac.h" 8 9 #define MT_TX_FREE_VER GENMASK(18, 16) 10 #define MT_TX_FREE_MSDU_CNT_V0 GENMASK(6, 0) 11 /* 0: success, others: dropped */ 12 #define MT_TX_FREE_MPDU_HEADER BIT(30) 13 #define MT_TX_FREE_MSDU_ID_V3 GENMASK(14, 0) 14 15 #define MT_TXS5_F0_FINAL_MPDU BIT(31) 16 #define MT_TXS5_F0_QOS BIT(30) 17 #define MT_TXS5_F0_TX_COUNT GENMASK(29, 25) 18 #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0) 19 #define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24) 20 #define MT_TXS5_F1_MPDU_TX_BYTES GENMASK(23, 0) 21 22 #define MT_TXS6_F0_NOISE_3 GENMASK(31, 24) 23 #define MT_TXS6_F0_NOISE_2 GENMASK(23, 16) 24 #define MT_TXS6_F0_NOISE_1 GENMASK(15, 8) 25 #define MT_TXS6_F0_NOISE_0 GENMASK(7, 0) 26 #define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24) 27 #define MT_TXS6_F1_MPDU_FAIL_BYTES GENMASK(23, 0) 28 29 #define MT_TXS7_F0_RCPI_3 GENMASK(31, 24) 30 #define MT_TXS7_F0_RCPI_2 GENMASK(23, 16) 31 #define MT_TXS7_F0_RCPI_1 GENMASK(15, 8) 32 #define MT_TXS7_F0_RCPI_0 GENMASK(7, 0) 33 #define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24) 34 #define MT_TXS7_F1_MPDU_RETRY_BYTES GENMASK(23, 0) 35 36 struct mt7915_dfs_pulse { 37 u32 max_width; /* us */ 38 int max_pwr; /* dbm */ 39 int min_pwr; /* dbm */ 40 u32 min_stgr_pri; /* us */ 41 u32 max_stgr_pri; /* us */ 42 u32 min_cr_pri; /* us */ 43 u32 max_cr_pri; /* us */ 44 }; 45 46 struct mt7915_dfs_pattern { 47 u8 enb; 48 u8 stgr; 49 u8 min_crpn; 50 u8 max_crpn; 51 u8 min_crpr; 52 u8 min_pw; 53 u32 min_pri; 54 u32 max_pri; 55 u8 max_pw; 56 u8 min_crbn; 57 u8 max_crbn; 58 u8 min_stgpn; 59 u8 max_stgpn; 60 u8 min_stgpr; 61 u8 rsv[2]; 62 u32 min_stgpr_diff; 63 } __packed; 64 65 struct mt7915_dfs_radar_spec { 66 struct mt7915_dfs_pulse pulse_th; 67 struct mt7915_dfs_pattern radar_pattern[16]; 68 }; 69 70 #endif 71