1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_H 5 #define __MT7915_H 6 7 #include <linux/interrupt.h> 8 #include <linux/ktime.h> 9 #include "../mt76_connac.h" 10 #include "regs.h" 11 12 #define MT7915_MAX_INTERFACES 19 13 #define MT7915_WTBL_SIZE 288 14 #define MT7916_WTBL_SIZE 544 15 #define MT7915_WTBL_RESERVED (mt7915_wtbl_size(dev) - 1) 16 #define MT7915_WTBL_STA (MT7915_WTBL_RESERVED - \ 17 MT7915_MAX_INTERFACES) 18 19 #define MT7915_WATCHDOG_TIME (HZ / 10) 20 #define MT7915_RESET_TIMEOUT (30 * HZ) 21 22 #define MT7915_TX_RING_SIZE 2048 23 #define MT7915_TX_MCU_RING_SIZE 256 24 #define MT7915_TX_FWDL_RING_SIZE 128 25 26 #define MT7915_RX_RING_SIZE 1536 27 #define MT7915_RX_MCU_RING_SIZE 512 28 29 #define MT7915_FIRMWARE_WA "mediatek/mt7915_wa.bin" 30 #define MT7915_FIRMWARE_WM "mediatek/mt7915_wm.bin" 31 #define MT7915_ROM_PATCH "mediatek/mt7915_rom_patch.bin" 32 33 #define MT7916_FIRMWARE_WA "mediatek/mt7916_wa.bin" 34 #define MT7916_FIRMWARE_WM "mediatek/mt7916_wm.bin" 35 #define MT7916_ROM_PATCH "mediatek/mt7916_rom_patch.bin" 36 37 #define MT7981_FIRMWARE_WA "mediatek/mt7981_wa.bin" 38 #define MT7981_FIRMWARE_WM "mediatek/mt7981_wm.bin" 39 #define MT7981_ROM_PATCH "mediatek/mt7981_rom_patch.bin" 40 41 #define MT7986_FIRMWARE_WA "mediatek/mt7986_wa.bin" 42 #define MT7986_FIRMWARE_WM "mediatek/mt7986_wm.bin" 43 #define MT7986_FIRMWARE_WM_MT7975 "mediatek/mt7986_wm_mt7975.bin" 44 #define MT7986_ROM_PATCH "mediatek/mt7986_rom_patch.bin" 45 #define MT7986_ROM_PATCH_MT7975 "mediatek/mt7986_rom_patch_mt7975.bin" 46 47 #define MT7915_EEPROM_DEFAULT "mediatek/mt7915_eeprom.bin" 48 #define MT7915_EEPROM_DEFAULT_DBDC "mediatek/mt7915_eeprom_dbdc.bin" 49 #define MT7916_EEPROM_DEFAULT "mediatek/mt7916_eeprom.bin" 50 51 #define MT7981_EEPROM_MT7976_DEFAULT_DBDC "mediatek/mt7981_eeprom_mt7976_dbdc.bin" 52 53 #define MT7986_EEPROM_MT7975_DEFAULT "mediatek/mt7986_eeprom_mt7975.bin" 54 #define MT7986_EEPROM_MT7975_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7975_dual.bin" 55 #define MT7986_EEPROM_MT7976_DEFAULT "mediatek/mt7986_eeprom_mt7976.bin" 56 #define MT7986_EEPROM_MT7976_DEFAULT_DBDC "mediatek/mt7986_eeprom_mt7976_dbdc.bin" 57 #define MT7986_EEPROM_MT7976_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7976_dual.bin" 58 59 #define MT7915_EEPROM_SIZE 3584 60 #define MT7916_EEPROM_SIZE 4096 61 62 #define MT7915_EEPROM_BLOCK_SIZE 16 63 #define MT7915_HW_TOKEN_SIZE 4096 64 #define MT7915_TOKEN_SIZE 8192 65 66 #define MT7915_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ 67 #define MT7915_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 68 69 #define MT7915_THERMAL_THROTTLE_MAX 100 70 #define MT7915_CDEV_THROTTLE_MAX 99 71 72 #define MT7915_SKU_RATE_NUM 161 73 74 #define MT7915_MAX_TWT_AGRT 16 75 #define MT7915_MAX_STA_TWT_AGRT 8 76 #define MT7915_MIN_TWT_DUR 64 77 #define MT7915_MAX_QUEUE (MT_RXQ_BAND2 + __MT_MCUQ_MAX + 2) 78 79 #define MT7915_WED_RX_TOKEN_SIZE 12288 80 81 #define MT7915_CRIT_TEMP_IDX 0 82 #define MT7915_MAX_TEMP_IDX 1 83 #define MT7915_CRIT_TEMP 110 84 #define MT7915_MAX_TEMP 120 85 86 struct mt7915_vif; 87 struct mt7915_sta; 88 struct mt7915_dfs_pulse; 89 struct mt7915_dfs_pattern; 90 91 enum mt7915_txq_id { 92 MT7915_TXQ_FWDL = 16, 93 MT7915_TXQ_MCU_WM, 94 MT7915_TXQ_BAND0, 95 MT7915_TXQ_BAND1, 96 MT7915_TXQ_MCU_WA, 97 }; 98 99 enum mt7915_rxq_id { 100 MT7915_RXQ_BAND0 = 0, 101 MT7915_RXQ_BAND1, 102 MT7915_RXQ_MCU_WM = 0, 103 MT7915_RXQ_MCU_WA, 104 MT7915_RXQ_MCU_WA_EXT, 105 }; 106 107 enum mt7916_rxq_id { 108 MT7916_RXQ_MCU_WM = 0, 109 MT7916_RXQ_MCU_WA, 110 MT7916_RXQ_MCU_WA_MAIN, 111 MT7916_RXQ_MCU_WA_EXT, 112 MT7916_RXQ_BAND0, 113 MT7916_RXQ_BAND1, 114 }; 115 116 struct mt7915_twt_flow { 117 struct list_head list; 118 u64 start_tsf; 119 u64 tsf; 120 u32 duration; 121 u16 wcid; 122 __le16 mantissa; 123 u8 exp; 124 u8 table_id; 125 u8 id; 126 u8 protection:1; 127 u8 flowtype:1; 128 u8 trigger:1; 129 u8 sched:1; 130 }; 131 132 DECLARE_EWMA(avg_signal, 10, 8) 133 134 struct mt7915_sta { 135 struct mt76_wcid wcid; /* must be first */ 136 137 struct mt7915_vif *vif; 138 139 struct list_head rc_list; 140 u32 airtime_ac[8]; 141 142 int ack_signal; 143 struct ewma_avg_signal avg_ack_signal; 144 145 unsigned long changed; 146 unsigned long jiffies; 147 struct mt76_connac_sta_key_conf bip; 148 149 struct { 150 u8 flowid_mask; 151 struct mt7915_twt_flow flow[MT7915_MAX_STA_TWT_AGRT]; 152 } twt; 153 }; 154 155 struct mt7915_vif_cap { 156 bool ht_ldpc:1; 157 bool vht_ldpc:1; 158 bool he_ldpc:1; 159 bool vht_su_ebfer:1; 160 bool vht_su_ebfee:1; 161 bool vht_mu_ebfer:1; 162 bool vht_mu_ebfee:1; 163 bool he_su_ebfer:1; 164 bool he_su_ebfee:1; 165 bool he_mu_ebfer:1; 166 }; 167 168 struct mt7915_vif { 169 struct mt76_vif mt76; /* must be first */ 170 171 struct mt7915_vif_cap cap; 172 struct mt7915_sta sta; 173 struct mt7915_phy *phy; 174 175 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 176 struct cfg80211_bitrate_mask bitrate_mask; 177 }; 178 179 /* crash-dump */ 180 struct mt7915_crash_data { 181 guid_t guid; 182 struct timespec64 timestamp; 183 184 u8 *memdump_buf; 185 size_t memdump_buf_len; 186 }; 187 188 struct mt7915_hif { 189 struct list_head list; 190 191 struct device *dev; 192 void __iomem *regs; 193 int irq; 194 }; 195 196 struct mt7915_phy { 197 struct mt76_phy *mt76; 198 struct mt7915_dev *dev; 199 200 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 201 202 struct ieee80211_vif *monitor_vif; 203 204 struct thermal_cooling_device *cdev; 205 u8 cdev_state; 206 u8 throttle_state; 207 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */ 208 209 u32 rxfilter; 210 u64 omac_mask; 211 212 u16 noise; 213 214 s16 coverage_class; 215 u8 slottime; 216 217 u8 rdd_state; 218 219 u32 trb_ts; 220 221 u32 rx_ampdu_ts; 222 u32 ampdu_ref; 223 224 struct mt76_mib_stats mib; 225 struct mt76_channel_state state_ts; 226 227 #ifdef CONFIG_NL80211_TESTMODE 228 struct { 229 u32 *reg_backup; 230 231 s32 last_freq_offset; 232 u8 last_rcpi[4]; 233 s8 last_ib_rssi[4]; 234 s8 last_wb_rssi[4]; 235 u8 last_snr; 236 237 u8 spe_idx; 238 } test; 239 #endif 240 }; 241 242 struct mt7915_dev { 243 union { /* must be first */ 244 struct mt76_dev mt76; 245 struct mt76_phy mphy; 246 }; 247 248 struct mt7915_hif *hif2; 249 struct mt7915_reg_desc reg; 250 u8 q_id[MT7915_MAX_QUEUE]; 251 u32 q_int_mask[MT7915_MAX_QUEUE]; 252 u32 wfdma_mask; 253 254 const struct mt76_bus_ops *bus_ops; 255 struct mt7915_phy phy; 256 257 /* monitor rx chain configured channel */ 258 struct cfg80211_chan_def rdd2_chandef; 259 struct mt7915_phy *rdd2_phy; 260 261 u16 chainmask; 262 u16 chainshift; 263 u32 hif_idx; 264 265 struct work_struct init_work; 266 struct work_struct rc_work; 267 struct work_struct dump_work; 268 struct work_struct reset_work; 269 wait_queue_head_t reset_wait; 270 271 struct { 272 u32 state; 273 u32 wa_reset_count; 274 u32 wm_reset_count; 275 bool hw_full_reset:1; 276 bool hw_init_done:1; 277 bool restart:1; 278 } recovery; 279 280 /* protects coredump data */ 281 struct mutex dump_mutex; 282 #ifdef CONFIG_DEV_COREDUMP 283 struct { 284 struct mt7915_crash_data *crash_data; 285 } coredump; 286 #endif 287 288 struct list_head sta_rc_list; 289 struct list_head twt_list; 290 291 u32 hw_pattern; 292 293 bool dbdc_support; 294 bool flash_mode; 295 bool muru_debug; 296 bool ibf; 297 298 u8 monitor_mask; 299 300 struct dentry *debugfs_dir; 301 struct rchan *relay_fwlog; 302 303 void *cal; 304 305 struct { 306 u8 debug_wm; 307 u8 debug_wa; 308 u8 debug_bin; 309 } fw; 310 311 struct { 312 u16 table_mask; 313 u8 n_agrt; 314 } twt; 315 316 struct reset_control *rstc; 317 void __iomem *dcm; 318 void __iomem *sku; 319 }; 320 321 enum { 322 WFDMA0 = 0x0, 323 WFDMA1, 324 WFDMA_EXT, 325 __MT_WFDMA_MAX, 326 }; 327 328 enum { 329 MT_RX_SEL0, 330 MT_RX_SEL1, 331 MT_RX_SEL2, /* monitor chain */ 332 }; 333 334 enum mt7915_rdd_cmd { 335 RDD_STOP, 336 RDD_START, 337 RDD_DET_MODE, 338 RDD_RADAR_EMULATE, 339 RDD_START_TXQ = 20, 340 RDD_SET_WF_ANT = 30, 341 RDD_CAC_START = 50, 342 RDD_CAC_END, 343 RDD_NORMAL_START, 344 RDD_DISABLE_DFS_CAL, 345 RDD_PULSE_DBG, 346 RDD_READ_PULSE, 347 RDD_RESUME_BF, 348 RDD_IRQ_OFF, 349 }; 350 351 static inline struct mt7915_phy * 352 mt7915_hw_phy(struct ieee80211_hw *hw) 353 { 354 struct mt76_phy *phy = hw->priv; 355 356 return phy->priv; 357 } 358 359 static inline struct mt7915_dev * 360 mt7915_hw_dev(struct ieee80211_hw *hw) 361 { 362 struct mt76_phy *phy = hw->priv; 363 364 return container_of(phy->dev, struct mt7915_dev, mt76); 365 } 366 367 static inline struct mt7915_phy * 368 mt7915_ext_phy(struct mt7915_dev *dev) 369 { 370 struct mt76_phy *phy = dev->mt76.phys[MT_BAND1]; 371 372 if (!phy) 373 return NULL; 374 375 return phy->priv; 376 } 377 378 static inline u32 mt7915_check_adie(struct mt7915_dev *dev, bool sku) 379 { 380 u32 mask = sku ? MT_CONNINFRA_SKU_MASK : MT_ADIE_TYPE_MASK; 381 if (!is_mt798x(&dev->mt76)) 382 return 0; 383 384 return mt76_rr(dev, MT_CONNINFRA_SKU_DEC_ADDR) & mask; 385 } 386 387 extern const struct ieee80211_ops mt7915_ops; 388 extern const struct mt76_testmode_ops mt7915_testmode_ops; 389 extern struct pci_driver mt7915_pci_driver; 390 extern struct pci_driver mt7915_hif_driver; 391 extern struct platform_driver mt798x_wmac_driver; 392 393 #ifdef CONFIG_MT798X_WMAC 394 int mt7986_wmac_enable(struct mt7915_dev *dev); 395 void mt7986_wmac_disable(struct mt7915_dev *dev); 396 #else 397 static inline int mt7986_wmac_enable(struct mt7915_dev *dev) 398 { 399 return 0; 400 } 401 402 static inline void mt7986_wmac_disable(struct mt7915_dev *dev) 403 { 404 } 405 #endif 406 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, 407 void __iomem *mem_base, u32 device_id); 408 void mt7915_wfsys_reset(struct mt7915_dev *dev); 409 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance); 410 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif); 411 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id); 412 413 int mt7915_register_device(struct mt7915_dev *dev); 414 void mt7915_unregister_device(struct mt7915_dev *dev); 415 int mt7915_eeprom_init(struct mt7915_dev *dev); 416 void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev, 417 struct mt7915_phy *phy); 418 int mt7915_eeprom_get_target_power(struct mt7915_dev *dev, 419 struct ieee80211_channel *chan, 420 u8 chain_idx); 421 s8 mt7915_eeprom_get_power_delta(struct mt7915_dev *dev, int band); 422 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2); 423 void mt7915_dma_prefetch(struct mt7915_dev *dev); 424 void mt7915_dma_cleanup(struct mt7915_dev *dev); 425 int mt7915_dma_reset(struct mt7915_dev *dev, bool force); 426 int mt7915_dma_start(struct mt7915_dev *dev, bool reset, bool wed_reset); 427 int mt7915_txbf_init(struct mt7915_dev *dev); 428 void mt7915_init_txpower(struct mt7915_dev *dev, 429 struct ieee80211_supported_band *sband); 430 void mt7915_reset(struct mt7915_dev *dev); 431 int mt7915_run(struct ieee80211_hw *hw); 432 int mt7915_mcu_init(struct mt7915_dev *dev); 433 int mt7915_mcu_init_firmware(struct mt7915_dev *dev); 434 int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev, 435 struct mt7915_vif *mvif, 436 struct mt7915_twt_flow *flow, 437 int cmd); 438 int mt7915_mcu_add_dev_info(struct mt7915_phy *phy, 439 struct ieee80211_vif *vif, bool enable); 440 int mt7915_mcu_add_bss_info(struct mt7915_phy *phy, 441 struct ieee80211_vif *vif, int enable); 442 int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif, 443 struct ieee80211_sta *sta, bool enable); 444 int mt7915_mcu_add_tx_ba(struct mt7915_dev *dev, 445 struct ieee80211_ampdu_params *params, 446 bool add); 447 int mt7915_mcu_add_rx_ba(struct mt7915_dev *dev, 448 struct ieee80211_ampdu_params *params, 449 bool add); 450 int mt7915_mcu_update_bss_color(struct mt7915_dev *dev, struct ieee80211_vif *vif, 451 struct cfg80211_he_bss_color *he_bss_color); 452 int mt7915_mcu_add_inband_discov(struct mt7915_dev *dev, struct ieee80211_vif *vif, 453 u32 changed); 454 int mt7915_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 455 int enable, u32 changed); 456 int mt7915_mcu_add_obss_spr(struct mt7915_phy *phy, struct ieee80211_vif *vif, 457 struct ieee80211_he_obss_pd *he_obss_pd); 458 int mt7915_mcu_add_rate_ctrl(struct mt7915_dev *dev, struct ieee80211_vif *vif, 459 struct ieee80211_sta *sta, bool changed); 460 int mt7915_mcu_add_smps(struct mt7915_dev *dev, struct ieee80211_vif *vif, 461 struct ieee80211_sta *sta); 462 int mt7915_set_channel(struct mt7915_phy *phy); 463 int mt7915_mcu_set_chan_info(struct mt7915_phy *phy, int cmd); 464 int mt7915_mcu_set_tx(struct mt7915_dev *dev, struct ieee80211_vif *vif); 465 int mt7915_mcu_update_edca(struct mt7915_dev *dev, void *req); 466 int mt7915_mcu_set_fixed_rate_ctrl(struct mt7915_dev *dev, 467 struct ieee80211_vif *vif, 468 struct ieee80211_sta *sta, 469 void *data, u32 field); 470 int mt7915_mcu_set_eeprom(struct mt7915_dev *dev); 471 int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset); 472 int mt7915_mcu_get_eeprom_free_block(struct mt7915_dev *dev, u8 *block_num); 473 int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable, 474 bool hdr_trans); 475 int mt7915_mcu_set_test_param(struct mt7915_dev *dev, u8 param, bool test_mode, 476 u8 en); 477 int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band); 478 int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable); 479 int mt7915_mcu_set_txpower_sku(struct mt7915_phy *phy); 480 int mt7915_mcu_get_txpower_sku(struct mt7915_phy *phy, s8 *txpower, int len); 481 int mt7915_mcu_set_txpower_frame_min(struct mt7915_phy *phy, s8 txpower); 482 int mt7915_mcu_set_txpower_frame(struct mt7915_phy *phy, 483 struct ieee80211_vif *vif, 484 struct ieee80211_sta *sta, s8 txpower); 485 int mt7915_mcu_set_txbf(struct mt7915_dev *dev, u8 action); 486 int mt7915_mcu_set_fcc5_lpn(struct mt7915_dev *dev, int val); 487 int mt7915_mcu_set_pulse_th(struct mt7915_dev *dev, 488 const struct mt7915_dfs_pulse *pulse); 489 int mt7915_mcu_set_radar_th(struct mt7915_dev *dev, int index, 490 const struct mt7915_dfs_pattern *pattern); 491 int mt7915_mcu_set_muru_ctrl(struct mt7915_dev *dev, u32 cmd, u32 val); 492 int mt7915_mcu_apply_group_cal(struct mt7915_dev *dev); 493 int mt7915_mcu_apply_tx_dpd(struct mt7915_phy *phy); 494 int mt7915_mcu_get_chan_mib_info(struct mt7915_phy *phy, bool chan_switch); 495 int mt7915_mcu_get_temperature(struct mt7915_phy *phy); 496 int mt7915_mcu_set_thermal_throttling(struct mt7915_phy *phy, u8 state); 497 int mt7915_mcu_set_thermal_protect(struct mt7915_phy *phy); 498 int mt7915_mcu_get_rx_rate(struct mt7915_phy *phy, struct ieee80211_vif *vif, 499 struct ieee80211_sta *sta, struct rate_info *rate); 500 int mt7915_mcu_rdd_background_enable(struct mt7915_phy *phy, 501 struct cfg80211_chan_def *chandef); 502 int mt7915_mcu_wed_wa_tx_stats(struct mt7915_dev *dev, u16 wcid); 503 int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set); 504 int mt7915_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); 505 int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 type, u8 ctrl); 506 int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level); 507 void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb); 508 void mt7915_mcu_exit(struct mt7915_dev *dev); 509 510 static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev) 511 { 512 return is_mt7915(&dev->mt76) ? MT7915_WTBL_SIZE : MT7916_WTBL_SIZE; 513 } 514 515 static inline u16 mt7915_eeprom_size(struct mt7915_dev *dev) 516 { 517 return is_mt7915(&dev->mt76) ? MT7915_EEPROM_SIZE : MT7916_EEPROM_SIZE; 518 } 519 520 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, bool write_reg, 521 u32 clear, u32 set); 522 523 static inline void mt7915_irq_enable(struct mt7915_dev *dev, u32 mask) 524 { 525 if (dev->hif2) 526 mt7915_dual_hif_set_irq_mask(dev, false, 0, mask); 527 else 528 mt76_set_irq_mask(&dev->mt76, 0, 0, mask); 529 530 tasklet_schedule(&dev->mt76.irq_tasklet); 531 } 532 533 static inline void mt7915_irq_disable(struct mt7915_dev *dev, u32 mask) 534 { 535 if (dev->hif2) 536 mt7915_dual_hif_set_irq_mask(dev, true, mask, 0); 537 else 538 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); 539 } 540 541 void mt7915_memcpy_fromio(struct mt7915_dev *dev, void *buf, u32 offset, 542 size_t len); 543 544 void mt7915_mac_init(struct mt7915_dev *dev); 545 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw); 546 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask); 547 void mt7915_mac_reset_counters(struct mt7915_phy *phy); 548 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy); 549 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy); 550 void mt7915_mac_enable_rtscts(struct mt7915_dev *dev, 551 struct ieee80211_vif *vif, bool enable); 552 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 553 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 554 struct ieee80211_key_conf *key, 555 enum mt76_txq_id qid, u32 changed); 556 void mt7915_mac_set_timing(struct mt7915_phy *phy); 557 int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, 558 struct ieee80211_sta *sta); 559 void mt7915_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, 560 struct ieee80211_sta *sta); 561 void mt7915_mac_work(struct work_struct *work); 562 void mt7915_mac_reset_work(struct work_struct *work); 563 void mt7915_mac_dump_work(struct work_struct *work); 564 void mt7915_mac_sta_rc_work(struct work_struct *work); 565 void mt7915_mac_update_stats(struct mt7915_phy *phy); 566 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 567 struct mt7915_sta *msta, 568 u8 flowid); 569 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 570 struct ieee80211_sta *sta, 571 struct ieee80211_twt_setup *twt); 572 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 573 enum mt76_txq_id qid, struct mt76_wcid *wcid, 574 struct ieee80211_sta *sta, 575 struct mt76_tx_info *tx_info); 576 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 577 struct sk_buff *skb, u32 *info); 578 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len); 579 void mt7915_stats_work(struct work_struct *work); 580 int mt76_dfs_start_rdd(struct mt7915_dev *dev, bool force); 581 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy); 582 void mt7915_set_stream_he_caps(struct mt7915_phy *phy); 583 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy); 584 void mt7915_update_channel(struct mt76_phy *mphy); 585 int mt7915_mcu_muru_debug_set(struct mt7915_dev *dev, bool enable); 586 int mt7915_mcu_muru_debug_get(struct mt7915_phy *phy); 587 int mt7915_mcu_wed_enable_rx_stats(struct mt7915_dev *dev); 588 int mt7915_init_debugfs(struct mt7915_phy *phy); 589 void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int len); 590 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len); 591 #ifdef CONFIG_MAC80211_DEBUGFS 592 void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 593 struct ieee80211_sta *sta, struct dentry *dir); 594 #endif 595 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr, 596 bool pci, int *irq); 597 598 #endif 599