1aadf0953SShayne Chen // SPDX-License-Identifier: ISC
2aadf0953SShayne Chen /* Copyright (C) 2020 MediaTek Inc. */
3aadf0953SShayne Chen
4aadf0953SShayne Chen #include "mt7915.h"
5aadf0953SShayne Chen #include "mac.h"
6aadf0953SShayne Chen #include "mcu.h"
7aadf0953SShayne Chen #include "testmode.h"
8aadf0953SShayne Chen
9e0852d90SShayne Chen enum {
10e0852d90SShayne Chen TM_CHANGED_TXPOWER,
11ed3c9072SShayne Chen TM_CHANGED_FREQ_OFFSET,
12e0852d90SShayne Chen
13e0852d90SShayne Chen /* must be last */
14e0852d90SShayne Chen NUM_TM_CHANGED
15e0852d90SShayne Chen };
16e0852d90SShayne Chen
17e0852d90SShayne Chen static const u8 tm_change_map[] = {
18e0852d90SShayne Chen [TM_CHANGED_TXPOWER] = MT76_TM_ATTR_TX_POWER,
19ed3c9072SShayne Chen [TM_CHANGED_FREQ_OFFSET] = MT76_TM_ATTR_FREQ_OFFSET,
20e0852d90SShayne Chen };
21e0852d90SShayne Chen
22aadf0953SShayne Chen struct reg_band {
23aadf0953SShayne Chen u32 band[2];
24aadf0953SShayne Chen };
25aadf0953SShayne Chen
26cd4c314aSBo Jiao #define REG_BAND(_list, _reg) \
27cd4c314aSBo Jiao { _list.band[0] = MT_##_reg(0); \
28cd4c314aSBo Jiao _list.band[1] = MT_##_reg(1); }
29cd4c314aSBo Jiao #define REG_BAND_IDX(_list, _reg, _idx) \
30cd4c314aSBo Jiao { _list.band[0] = MT_##_reg(0, _idx); \
31cd4c314aSBo Jiao _list.band[1] = MT_##_reg(1, _idx); }
32aadf0953SShayne Chen
33cd4c314aSBo Jiao #define TM_REG_MAX_ID 17
34cd4c314aSBo Jiao static struct reg_band reg_backup_list[TM_REG_MAX_ID];
35cd4c314aSBo Jiao
36aadf0953SShayne Chen
37aadf0953SShayne Chen static int
mt7915_tm_set_tx_power(struct mt7915_phy * phy)38e0852d90SShayne Chen mt7915_tm_set_tx_power(struct mt7915_phy *phy)
39e0852d90SShayne Chen {
40e0852d90SShayne Chen struct mt7915_dev *dev = phy->dev;
41e0852d90SShayne Chen struct mt76_phy *mphy = phy->mt76;
42e0852d90SShayne Chen struct cfg80211_chan_def *chandef = &mphy->chandef;
43e0852d90SShayne Chen int freq = chandef->center_freq1;
44e0852d90SShayne Chen int ret;
45e0852d90SShayne Chen struct {
46e0852d90SShayne Chen u8 format_id;
476f917bbaSRyder Lee u8 band_idx;
48e0852d90SShayne Chen s8 tx_power;
49e0852d90SShayne Chen u8 ant_idx; /* Only 0 is valid */
50e0852d90SShayne Chen u8 center_chan;
51e0852d90SShayne Chen u8 rsv[3];
52e0852d90SShayne Chen } __packed req = {
53e0852d90SShayne Chen .format_id = 0xf,
54*3eb50cc9SRyder Lee .band_idx = phy->mt76->band_idx,
55e0852d90SShayne Chen .center_chan = ieee80211_frequency_to_channel(freq),
56e0852d90SShayne Chen };
57e0852d90SShayne Chen u8 *tx_power = NULL;
58e0852d90SShayne Chen
59c918c74dSShayne Chen if (phy->mt76->test.state != MT76_TM_STATE_OFF)
60c918c74dSShayne Chen tx_power = phy->mt76->test.tx_power;
61e0852d90SShayne Chen
62e0852d90SShayne Chen /* Tx power of the other antennas are the same as antenna 0 */
63e0852d90SShayne Chen if (tx_power && tx_power[0])
64e0852d90SShayne Chen req.tx_power = tx_power[0];
65e0852d90SShayne Chen
66e0852d90SShayne Chen ret = mt76_mcu_send_msg(&dev->mt76,
67c203dd62SFelix Fietkau MCU_EXT_CMD(TX_POWER_FEATURE_CTRL),
68e0852d90SShayne Chen &req, sizeof(req), false);
69e0852d90SShayne Chen
70e0852d90SShayne Chen return ret;
71e0852d90SShayne Chen }
72e0852d90SShayne Chen
73e0852d90SShayne Chen static int
mt7915_tm_set_freq_offset(struct mt7915_phy * phy,bool en,u32 val)74c918c74dSShayne Chen mt7915_tm_set_freq_offset(struct mt7915_phy *phy, bool en, u32 val)
75ed3c9072SShayne Chen {
76c918c74dSShayne Chen struct mt7915_dev *dev = phy->dev;
77ed3c9072SShayne Chen struct mt7915_tm_cmd req = {
78ed3c9072SShayne Chen .testmode_en = en,
79ed3c9072SShayne Chen .param_idx = MCU_ATE_SET_FREQ_OFFSET,
80*3eb50cc9SRyder Lee .param.freq.band = phy->mt76->band_idx,
81ed3c9072SShayne Chen .param.freq.freq_offset = cpu_to_le32(val),
82ed3c9072SShayne Chen };
83ed3c9072SShayne Chen
84c203dd62SFelix Fietkau return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
85ed3c9072SShayne Chen sizeof(req), false);
86ed3c9072SShayne Chen }
87ed3c9072SShayne Chen
88ed3c9072SShayne Chen static int
mt7915_tm_mode_ctrl(struct mt7915_dev * dev,bool enable)89aadf0953SShayne Chen mt7915_tm_mode_ctrl(struct mt7915_dev *dev, bool enable)
90aadf0953SShayne Chen {
91aadf0953SShayne Chen struct {
92aadf0953SShayne Chen u8 format_id;
93aadf0953SShayne Chen bool enable;
94aadf0953SShayne Chen u8 rsv[2];
95aadf0953SShayne Chen } __packed req = {
96aadf0953SShayne Chen .format_id = 0x6,
97aadf0953SShayne Chen .enable = enable,
98aadf0953SShayne Chen };
99aadf0953SShayne Chen
100aadf0953SShayne Chen return mt76_mcu_send_msg(&dev->mt76,
101c203dd62SFelix Fietkau MCU_EXT_CMD(TX_POWER_FEATURE_CTRL),
102aadf0953SShayne Chen &req, sizeof(req), false);
103aadf0953SShayne Chen }
104aadf0953SShayne Chen
105aadf0953SShayne Chen static int
mt7915_tm_set_trx(struct mt7915_phy * phy,int type,bool en)106c918c74dSShayne Chen mt7915_tm_set_trx(struct mt7915_phy *phy, int type, bool en)
107aadf0953SShayne Chen {
108c918c74dSShayne Chen struct mt7915_dev *dev = phy->dev;
109aadf0953SShayne Chen struct mt7915_tm_cmd req = {
110aadf0953SShayne Chen .testmode_en = 1,
111aadf0953SShayne Chen .param_idx = MCU_ATE_SET_TRX,
112aadf0953SShayne Chen .param.trx.type = type,
113aadf0953SShayne Chen .param.trx.enable = en,
114*3eb50cc9SRyder Lee .param.trx.band = phy->mt76->band_idx,
115aadf0953SShayne Chen };
116aadf0953SShayne Chen
117c203dd62SFelix Fietkau return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
118aadf0953SShayne Chen sizeof(req), false);
119aadf0953SShayne Chen }
120aadf0953SShayne Chen
121c2d3b192SShayne Chen static int
mt7915_tm_clean_hwq(struct mt7915_phy * phy,u8 wcid)1228efe387cSShayne Chen mt7915_tm_clean_hwq(struct mt7915_phy *phy, u8 wcid)
1238efe387cSShayne Chen {
1248efe387cSShayne Chen struct mt7915_dev *dev = phy->dev;
1258efe387cSShayne Chen struct mt7915_tm_cmd req = {
1268efe387cSShayne Chen .testmode_en = 1,
1278efe387cSShayne Chen .param_idx = MCU_ATE_CLEAN_TXQUEUE,
1288efe387cSShayne Chen .param.clean.wcid = wcid,
129*3eb50cc9SRyder Lee .param.clean.band = phy->mt76->band_idx,
1308efe387cSShayne Chen };
1318efe387cSShayne Chen
132c203dd62SFelix Fietkau return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
1338efe387cSShayne Chen sizeof(req), false);
1348efe387cSShayne Chen }
1358efe387cSShayne Chen
1368efe387cSShayne Chen static int
mt7915_tm_set_slot_time(struct mt7915_phy * phy,u8 slot_time,u8 sifs)137c2d3b192SShayne Chen mt7915_tm_set_slot_time(struct mt7915_phy *phy, u8 slot_time, u8 sifs)
138c2d3b192SShayne Chen {
139c2d3b192SShayne Chen struct mt7915_dev *dev = phy->dev;
140c2d3b192SShayne Chen struct mt7915_tm_cmd req = {
141c2d3b192SShayne Chen .testmode_en = !(phy->mt76->test.state == MT76_TM_STATE_OFF),
142c2d3b192SShayne Chen .param_idx = MCU_ATE_SET_SLOT_TIME,
143c2d3b192SShayne Chen .param.slot.slot_time = slot_time,
144c2d3b192SShayne Chen .param.slot.sifs = sifs,
145c2d3b192SShayne Chen .param.slot.rifs = 2,
146c2d3b192SShayne Chen .param.slot.eifs = cpu_to_le16(60),
147*3eb50cc9SRyder Lee .param.slot.band = phy->mt76->band_idx,
148c2d3b192SShayne Chen };
149c2d3b192SShayne Chen
150c203dd62SFelix Fietkau return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
151c2d3b192SShayne Chen sizeof(req), false);
152c2d3b192SShayne Chen }
153c2d3b192SShayne Chen
154c2d3b192SShayne Chen static int
mt7915_tm_set_tam_arb(struct mt7915_phy * phy,bool enable,bool mu)155978fdd66SShayne Chen mt7915_tm_set_tam_arb(struct mt7915_phy *phy, bool enable, bool mu)
156978fdd66SShayne Chen {
157978fdd66SShayne Chen struct mt7915_dev *dev = phy->dev;
158e5a9f383SShayne Chen u32 op_mode;
159978fdd66SShayne Chen
160978fdd66SShayne Chen if (!enable)
161e5a9f383SShayne Chen op_mode = TAM_ARB_OP_MODE_NORMAL;
162978fdd66SShayne Chen else if (mu)
163e5a9f383SShayne Chen op_mode = TAM_ARB_OP_MODE_TEST;
164978fdd66SShayne Chen else
165e5a9f383SShayne Chen op_mode = TAM_ARB_OP_MODE_FORCE_SU;
166978fdd66SShayne Chen
167e5a9f383SShayne Chen return mt7915_mcu_set_muru_ctrl(dev, MURU_SET_ARB_OP_MODE, op_mode);
168978fdd66SShayne Chen }
169978fdd66SShayne Chen
170978fdd66SShayne Chen static int
mt7915_tm_set_wmm_qid(struct mt7915_phy * phy,u8 qid,u8 aifs,u8 cw_min,u16 cw_max,u16 txop)1716e744cfeSShayne Chen mt7915_tm_set_wmm_qid(struct mt7915_phy *phy, u8 qid, u8 aifs, u8 cw_min,
172c2d3b192SShayne Chen u16 cw_max, u16 txop)
173c2d3b192SShayne Chen {
1746e744cfeSShayne Chen struct mt7915_vif *mvif = (struct mt7915_vif *)phy->monitor_vif->drv_priv;
175c2d3b192SShayne Chen struct mt7915_mcu_tx req = { .total = 1 };
176c2d3b192SShayne Chen struct edca *e = &req.edca[0];
177c2d3b192SShayne Chen
1786e744cfeSShayne Chen e->queue = qid + mvif->mt76.wmm_idx * MT76_CONNAC_MAX_WMM_SETS;
179c2d3b192SShayne Chen e->set = WMM_PARAM_SET;
180c2d3b192SShayne Chen
181c2d3b192SShayne Chen e->aifs = aifs;
182c2d3b192SShayne Chen e->cw_min = cw_min;
183c2d3b192SShayne Chen e->cw_max = cpu_to_le16(cw_max);
184c2d3b192SShayne Chen e->txop = cpu_to_le16(txop);
185c2d3b192SShayne Chen
1866e744cfeSShayne Chen return mt7915_mcu_update_edca(phy->dev, &req);
187c2d3b192SShayne Chen }
188c2d3b192SShayne Chen
189c2d3b192SShayne Chen static int
mt7915_tm_set_ipg_params(struct mt7915_phy * phy,u32 ipg,u8 mode)190c2d3b192SShayne Chen mt7915_tm_set_ipg_params(struct mt7915_phy *phy, u32 ipg, u8 mode)
191c2d3b192SShayne Chen {
192c2d3b192SShayne Chen #define TM_DEFAULT_SIFS 10
193c2d3b192SShayne Chen #define TM_MAX_SIFS 127
194c2d3b192SShayne Chen #define TM_MAX_AIFSN 0xf
195c2d3b192SShayne Chen #define TM_MIN_AIFSN 0x1
196c2d3b192SShayne Chen #define BBP_PROC_TIME 1500
197c2d3b192SShayne Chen struct mt7915_dev *dev = phy->dev;
198c2d3b192SShayne Chen u8 sig_ext = (mode == MT76_TM_TX_MODE_CCK) ? 0 : 6;
199c2d3b192SShayne Chen u8 slot_time = 9, sifs = TM_DEFAULT_SIFS;
200c2d3b192SShayne Chen u8 aifsn = TM_MIN_AIFSN;
201*3eb50cc9SRyder Lee u8 band = phy->mt76->band_idx;
202c2d3b192SShayne Chen u32 i2t_time, tr2t_time, txv_time;
203c2d3b192SShayne Chen u16 cw = 0;
204c2d3b192SShayne Chen
205c2d3b192SShayne Chen if (ipg < sig_ext + slot_time + sifs)
206c2d3b192SShayne Chen ipg = 0;
207c2d3b192SShayne Chen
208c2d3b192SShayne Chen if (!ipg)
209c2d3b192SShayne Chen goto done;
210c2d3b192SShayne Chen
211c2d3b192SShayne Chen ipg -= sig_ext;
212c2d3b192SShayne Chen
213c2d3b192SShayne Chen if (ipg <= (TM_MAX_SIFS + slot_time)) {
214c2d3b192SShayne Chen sifs = ipg - slot_time;
215c2d3b192SShayne Chen } else {
216c2d3b192SShayne Chen u32 val = (ipg + slot_time) / slot_time;
217c2d3b192SShayne Chen
218c2d3b192SShayne Chen while (val >>= 1)
219c2d3b192SShayne Chen cw++;
220c2d3b192SShayne Chen
221c2d3b192SShayne Chen if (cw > 16)
222c2d3b192SShayne Chen cw = 16;
223c2d3b192SShayne Chen
224c2d3b192SShayne Chen ipg -= ((1 << cw) - 1) * slot_time;
225c2d3b192SShayne Chen
226c2d3b192SShayne Chen aifsn = ipg / slot_time;
227c2d3b192SShayne Chen if (aifsn > TM_MAX_AIFSN)
228c2d3b192SShayne Chen aifsn = TM_MAX_AIFSN;
229c2d3b192SShayne Chen
230c2d3b192SShayne Chen ipg -= aifsn * slot_time;
231c2d3b192SShayne Chen
23277787358SChangcheng Deng if (ipg > TM_DEFAULT_SIFS)
23377787358SChangcheng Deng sifs = min_t(u32, ipg, TM_MAX_SIFS);
234c2d3b192SShayne Chen }
235c2d3b192SShayne Chen done:
236*3eb50cc9SRyder Lee txv_time = mt76_get_field(dev, MT_TMAC_ATCR(band),
237c2d3b192SShayne Chen MT_TMAC_ATCR_TXV_TOUT);
238c2d3b192SShayne Chen txv_time *= 50; /* normal clock time */
239c2d3b192SShayne Chen
240c2d3b192SShayne Chen i2t_time = (slot_time * 1000 - txv_time - BBP_PROC_TIME) / 50;
241c2d3b192SShayne Chen tr2t_time = (sifs * 1000 - txv_time - BBP_PROC_TIME) / 50;
242c2d3b192SShayne Chen
243*3eb50cc9SRyder Lee mt76_set(dev, MT_TMAC_TRCR0(band),
244c2d3b192SShayne Chen FIELD_PREP(MT_TMAC_TRCR0_TR2T_CHK, tr2t_time) |
245c2d3b192SShayne Chen FIELD_PREP(MT_TMAC_TRCR0_I2T_CHK, i2t_time));
246c2d3b192SShayne Chen
247c2d3b192SShayne Chen mt7915_tm_set_slot_time(phy, slot_time, sifs);
248c2d3b192SShayne Chen
2496e744cfeSShayne Chen return mt7915_tm_set_wmm_qid(phy,
2504a74ecc8SLorenzo Bianconi mt76_connac_lmac_mapping(IEEE80211_AC_BE),
251c2d3b192SShayne Chen aifsn, cw, cw, 0);
252c2d3b192SShayne Chen }
253c2d3b192SShayne Chen
254c46df37fSShayne Chen static int
mt7915_tm_set_tx_len(struct mt7915_phy * phy,u32 tx_time)255c46df37fSShayne Chen mt7915_tm_set_tx_len(struct mt7915_phy *phy, u32 tx_time)
256c46df37fSShayne Chen {
257c46df37fSShayne Chen struct mt76_phy *mphy = phy->mt76;
258c46df37fSShayne Chen struct mt76_testmode_data *td = &mphy->test;
259c46df37fSShayne Chen struct ieee80211_supported_band *sband;
260c46df37fSShayne Chen struct rate_info rate = {};
261c46df37fSShayne Chen u16 flags = 0, tx_len;
262c46df37fSShayne Chen u32 bitrate;
263e6678f9dSShayne Chen int ret;
264c46df37fSShayne Chen
265e6678f9dSShayne Chen if (!tx_time)
266c46df37fSShayne Chen return 0;
267c46df37fSShayne Chen
268c46df37fSShayne Chen rate.mcs = td->tx_rate_idx;
269c46df37fSShayne Chen rate.nss = td->tx_rate_nss;
270c46df37fSShayne Chen
271c46df37fSShayne Chen switch (td->tx_rate_mode) {
272c46df37fSShayne Chen case MT76_TM_TX_MODE_CCK:
273c46df37fSShayne Chen case MT76_TM_TX_MODE_OFDM:
274c46df37fSShayne Chen if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
275c46df37fSShayne Chen sband = &mphy->sband_5g.sband;
276b4d093e3SMeiChia Chiu else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ)
277b4d093e3SMeiChia Chiu sband = &mphy->sband_6g.sband;
278c46df37fSShayne Chen else
279c46df37fSShayne Chen sband = &mphy->sband_2g.sband;
280c46df37fSShayne Chen
281c46df37fSShayne Chen rate.legacy = sband->bitrates[rate.mcs].bitrate;
282c46df37fSShayne Chen break;
283c46df37fSShayne Chen case MT76_TM_TX_MODE_HT:
284c46df37fSShayne Chen rate.mcs += rate.nss * 8;
285c46df37fSShayne Chen flags |= RATE_INFO_FLAGS_MCS;
286c46df37fSShayne Chen
287c46df37fSShayne Chen if (td->tx_rate_sgi)
288c46df37fSShayne Chen flags |= RATE_INFO_FLAGS_SHORT_GI;
289c46df37fSShayne Chen break;
290c46df37fSShayne Chen case MT76_TM_TX_MODE_VHT:
291c46df37fSShayne Chen flags |= RATE_INFO_FLAGS_VHT_MCS;
292c46df37fSShayne Chen
293c46df37fSShayne Chen if (td->tx_rate_sgi)
294c46df37fSShayne Chen flags |= RATE_INFO_FLAGS_SHORT_GI;
295c46df37fSShayne Chen break;
296c46df37fSShayne Chen case MT76_TM_TX_MODE_HE_SU:
297c46df37fSShayne Chen case MT76_TM_TX_MODE_HE_EXT_SU:
298c46df37fSShayne Chen case MT76_TM_TX_MODE_HE_TB:
299c46df37fSShayne Chen case MT76_TM_TX_MODE_HE_MU:
300c46df37fSShayne Chen rate.he_gi = td->tx_rate_sgi;
301c46df37fSShayne Chen flags |= RATE_INFO_FLAGS_HE_MCS;
302c46df37fSShayne Chen break;
303c46df37fSShayne Chen default:
304c46df37fSShayne Chen break;
305c46df37fSShayne Chen }
306c46df37fSShayne Chen rate.flags = flags;
307c46df37fSShayne Chen
308c46df37fSShayne Chen switch (mphy->chandef.width) {
309c46df37fSShayne Chen case NL80211_CHAN_WIDTH_160:
310c46df37fSShayne Chen case NL80211_CHAN_WIDTH_80P80:
311c46df37fSShayne Chen rate.bw = RATE_INFO_BW_160;
312c46df37fSShayne Chen break;
313c46df37fSShayne Chen case NL80211_CHAN_WIDTH_80:
314c46df37fSShayne Chen rate.bw = RATE_INFO_BW_80;
315c46df37fSShayne Chen break;
316c46df37fSShayne Chen case NL80211_CHAN_WIDTH_40:
317c46df37fSShayne Chen rate.bw = RATE_INFO_BW_40;
318c46df37fSShayne Chen break;
319c46df37fSShayne Chen default:
320c46df37fSShayne Chen rate.bw = RATE_INFO_BW_20;
321c46df37fSShayne Chen break;
322c46df37fSShayne Chen }
323c46df37fSShayne Chen
324c46df37fSShayne Chen bitrate = cfg80211_calculate_bitrate(&rate);
325c46df37fSShayne Chen tx_len = bitrate * tx_time / 10 / 8;
326c46df37fSShayne Chen
327e6678f9dSShayne Chen ret = mt76_testmode_alloc_skb(phy->mt76, tx_len);
328e6678f9dSShayne Chen if (ret)
329e6678f9dSShayne Chen return ret;
330c46df37fSShayne Chen
331c46df37fSShayne Chen return 0;
332c46df37fSShayne Chen }
333c46df37fSShayne Chen
334aadf0953SShayne Chen static void
mt7915_tm_reg_backup_restore(struct mt7915_phy * phy)335c918c74dSShayne Chen mt7915_tm_reg_backup_restore(struct mt7915_phy *phy)
336aadf0953SShayne Chen {
337aadf0953SShayne Chen int n_regs = ARRAY_SIZE(reg_backup_list);
338c918c74dSShayne Chen struct mt7915_dev *dev = phy->dev;
33978fc30a2SShayne Chen u32 *b = phy->test.reg_backup;
340*3eb50cc9SRyder Lee u8 band = phy->mt76->band_idx;
341aadf0953SShayne Chen int i;
342aadf0953SShayne Chen
343cd4c314aSBo Jiao REG_BAND_IDX(reg_backup_list[0], AGG_PCR0, 0);
344cd4c314aSBo Jiao REG_BAND_IDX(reg_backup_list[1], AGG_PCR0, 1);
345cd4c314aSBo Jiao REG_BAND_IDX(reg_backup_list[2], AGG_AWSCR0, 0);
346cd4c314aSBo Jiao REG_BAND_IDX(reg_backup_list[3], AGG_AWSCR0, 1);
347cd4c314aSBo Jiao REG_BAND_IDX(reg_backup_list[4], AGG_AWSCR0, 2);
348cd4c314aSBo Jiao REG_BAND_IDX(reg_backup_list[5], AGG_AWSCR0, 3);
349cd4c314aSBo Jiao REG_BAND(reg_backup_list[6], AGG_MRCR);
350cd4c314aSBo Jiao REG_BAND(reg_backup_list[7], TMAC_TFCR0);
351cd4c314aSBo Jiao REG_BAND(reg_backup_list[8], TMAC_TCR0);
352cd4c314aSBo Jiao REG_BAND(reg_backup_list[9], AGG_ATCR1);
353cd4c314aSBo Jiao REG_BAND(reg_backup_list[10], AGG_ATCR3);
354cd4c314aSBo Jiao REG_BAND(reg_backup_list[11], TMAC_TRCR0);
355cd4c314aSBo Jiao REG_BAND(reg_backup_list[12], TMAC_ICR0);
356cd4c314aSBo Jiao REG_BAND_IDX(reg_backup_list[13], ARB_DRNGR0, 0);
357cd4c314aSBo Jiao REG_BAND_IDX(reg_backup_list[14], ARB_DRNGR0, 1);
358cd4c314aSBo Jiao REG_BAND(reg_backup_list[15], WF_RFCR);
359cd4c314aSBo Jiao REG_BAND(reg_backup_list[16], WF_RFCR1);
360cd4c314aSBo Jiao
36178fc30a2SShayne Chen if (phy->mt76->test.state == MT76_TM_STATE_OFF) {
362aadf0953SShayne Chen for (i = 0; i < n_regs; i++)
363*3eb50cc9SRyder Lee mt76_wr(dev, reg_backup_list[i].band[band], b[i]);
364aadf0953SShayne Chen return;
365aadf0953SShayne Chen }
366aadf0953SShayne Chen
367edc08318SShayne Chen if (!b) {
368aadf0953SShayne Chen b = devm_kzalloc(dev->mt76.dev, 4 * n_regs, GFP_KERNEL);
369aadf0953SShayne Chen if (!b)
370aadf0953SShayne Chen return;
371aadf0953SShayne Chen
37278fc30a2SShayne Chen phy->test.reg_backup = b;
373aadf0953SShayne Chen for (i = 0; i < n_regs; i++)
374*3eb50cc9SRyder Lee b[i] = mt76_rr(dev, reg_backup_list[i].band[band]);
375edc08318SShayne Chen }
376aadf0953SShayne Chen
377*3eb50cc9SRyder Lee mt76_clear(dev, MT_AGG_PCR0(band, 0), MT_AGG_PCR0_MM_PROT |
378aadf0953SShayne Chen MT_AGG_PCR0_GF_PROT | MT_AGG_PCR0_ERP_PROT |
379aadf0953SShayne Chen MT_AGG_PCR0_VHT_PROT | MT_AGG_PCR0_BW20_PROT |
380aadf0953SShayne Chen MT_AGG_PCR0_BW40_PROT | MT_AGG_PCR0_BW80_PROT);
381*3eb50cc9SRyder Lee mt76_set(dev, MT_AGG_PCR0(band, 0), MT_AGG_PCR0_PTA_WIN_DIS);
382aadf0953SShayne Chen
383*3eb50cc9SRyder Lee mt76_wr(dev, MT_AGG_PCR0(band, 1), MT_AGG_PCR1_RTS0_NUM_THRES |
384aadf0953SShayne Chen MT_AGG_PCR1_RTS0_LEN_THRES);
385aadf0953SShayne Chen
386*3eb50cc9SRyder Lee mt76_clear(dev, MT_AGG_MRCR(band), MT_AGG_MRCR_BAR_CNT_LIMIT |
387aadf0953SShayne Chen MT_AGG_MRCR_LAST_RTS_CTS_RN | MT_AGG_MRCR_RTS_FAIL_LIMIT |
388aadf0953SShayne Chen MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT);
389aadf0953SShayne Chen
390*3eb50cc9SRyder Lee mt76_rmw(dev, MT_AGG_MRCR(band), MT_AGG_MRCR_RTS_FAIL_LIMIT |
391aadf0953SShayne Chen MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT,
392aadf0953SShayne Chen FIELD_PREP(MT_AGG_MRCR_RTS_FAIL_LIMIT, 1) |
393aadf0953SShayne Chen FIELD_PREP(MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT, 1));
394aadf0953SShayne Chen
395*3eb50cc9SRyder Lee mt76_wr(dev, MT_TMAC_TFCR0(band), 0);
396*3eb50cc9SRyder Lee mt76_clear(dev, MT_TMAC_TCR0(band), MT_TMAC_TCR0_TBTT_STOP_CTRL);
3975d8a83f0SShayne Chen
3985d8a83f0SShayne Chen /* config rx filter for testmode rx */
399*3eb50cc9SRyder Lee mt76_wr(dev, MT_WF_RFCR(band), 0xcf70a);
400*3eb50cc9SRyder Lee mt76_wr(dev, MT_WF_RFCR1(band), 0);
401aadf0953SShayne Chen }
402aadf0953SShayne Chen
403aadf0953SShayne Chen static void
mt7915_tm_init(struct mt7915_phy * phy,bool en)40439e48823SShayne Chen mt7915_tm_init(struct mt7915_phy *phy, bool en)
405aadf0953SShayne Chen {
406c918c74dSShayne Chen struct mt7915_dev *dev = phy->dev;
407aadf0953SShayne Chen
408c918c74dSShayne Chen if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
409aadf0953SShayne Chen return;
410aadf0953SShayne Chen
41106e0bbe1SShayne Chen mt7915_mcu_set_sku_en(phy, !en);
41206e0bbe1SShayne Chen
413aadf0953SShayne Chen mt7915_tm_mode_ctrl(dev, en);
414c918c74dSShayne Chen mt7915_tm_reg_backup_restore(phy);
415c918c74dSShayne Chen mt7915_tm_set_trx(phy, TM_MAC_TXRX, !en);
416dae0dc2bSShayne Chen
417c918c74dSShayne Chen mt7915_mcu_add_bss_info(phy, phy->monitor_vif, en);
418978fdd66SShayne Chen mt7915_mcu_add_sta(dev, phy->monitor_vif, NULL, en);
419978fdd66SShayne Chen
420978fdd66SShayne Chen if (!en)
421978fdd66SShayne Chen mt7915_tm_set_tam_arb(phy, en, 0);
422aadf0953SShayne Chen }
423aadf0953SShayne Chen
424aadf0953SShayne Chen static void
mt7915_tm_update_channel(struct mt7915_phy * phy)4253f0caa3cSShayne Chen mt7915_tm_update_channel(struct mt7915_phy *phy)
4263f0caa3cSShayne Chen {
4273f0caa3cSShayne Chen mutex_unlock(&phy->dev->mt76.mutex);
4283f0caa3cSShayne Chen mt7915_set_channel(phy);
4293f0caa3cSShayne Chen mutex_lock(&phy->dev->mt76.mutex);
4303f0caa3cSShayne Chen
431c203dd62SFelix Fietkau mt7915_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH));
4323f0caa3cSShayne Chen }
4333f0caa3cSShayne Chen
4343f0caa3cSShayne Chen static void
mt7915_tm_set_tx_frames(struct mt7915_phy * phy,bool en)435c918c74dSShayne Chen mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en)
436aadf0953SShayne Chen {
437fdc9c18eSShayne Chen struct mt76_testmode_data *td = &phy->mt76->test;
438c918c74dSShayne Chen struct mt7915_dev *dev = phy->dev;
439aadf0953SShayne Chen struct ieee80211_tx_info *info;
440c2d3b192SShayne Chen u8 duty_cycle = td->tx_duty_cycle;
441c2d3b192SShayne Chen u32 tx_time = td->tx_time;
442c2d3b192SShayne Chen u32 ipg = td->tx_ipg;
443aadf0953SShayne Chen
444c918c74dSShayne Chen mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
4458efe387cSShayne Chen mt7915_tm_clean_hwq(phy, dev->mt76.global_wcid.idx);
446aadf0953SShayne Chen
447aadf0953SShayne Chen if (en) {
4483f0caa3cSShayne Chen mt7915_tm_update_channel(phy);
449c918c74dSShayne Chen
450b61699d2SShayne Chen if (td->tx_spe_idx)
451fdc9c18eSShayne Chen phy->test.spe_idx = td->tx_spe_idx;
452b61699d2SShayne Chen else
4537a9a957bSShayne Chen phy->test.spe_idx = mt76_connac_spe_idx(td->tx_antenna_mask);
454fdc9c18eSShayne Chen }
455aadf0953SShayne Chen
456978fdd66SShayne Chen mt7915_tm_set_tam_arb(phy, en,
457978fdd66SShayne Chen td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU);
458978fdd66SShayne Chen
459c2d3b192SShayne Chen /* if all three params are set, duty_cycle will be ignored */
460c2d3b192SShayne Chen if (duty_cycle && tx_time && !ipg) {
461c2d3b192SShayne Chen ipg = tx_time * 100 / duty_cycle - tx_time;
462c2d3b192SShayne Chen } else if (duty_cycle && !tx_time && ipg) {
463c2d3b192SShayne Chen if (duty_cycle < 100)
464c2d3b192SShayne Chen tx_time = duty_cycle * ipg / (100 - duty_cycle);
465c2d3b192SShayne Chen }
466c2d3b192SShayne Chen
467c2d3b192SShayne Chen mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode);
468c46df37fSShayne Chen mt7915_tm_set_tx_len(phy, tx_time);
469c2d3b192SShayne Chen
470c2d3b192SShayne Chen if (ipg)
471c2d3b192SShayne Chen td->tx_queued_limit = MT76_TM_TIMEOUT * 1000000 / ipg / 2;
472aadf0953SShayne Chen
473c46df37fSShayne Chen if (!en || !td->tx_skb)
474aadf0953SShayne Chen return;
475aadf0953SShayne Chen
476c46df37fSShayne Chen info = IEEE80211_SKB_CB(td->tx_skb);
477c918c74dSShayne Chen info->control.vif = phy->monitor_vif;
478c2d3b192SShayne Chen
479c2d3b192SShayne Chen mt7915_tm_set_trx(phy, TM_MAC_TX, en);
480aadf0953SShayne Chen }
481aadf0953SShayne Chen
4825d8a83f0SShayne Chen static void
mt7915_tm_set_rx_frames(struct mt7915_phy * phy,bool en)483c918c74dSShayne Chen mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en)
4845d8a83f0SShayne Chen {
48589043529SShayne Chen mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
48689043529SShayne Chen
48789043529SShayne Chen if (en) {
48889043529SShayne Chen struct mt7915_dev *dev = phy->dev;
48989043529SShayne Chen
4903f0caa3cSShayne Chen mt7915_tm_update_channel(phy);
4915d8a83f0SShayne Chen
49289043529SShayne Chen /* read-clear */
493*3eb50cc9SRyder Lee mt76_rr(dev, MT_MIB_SDR3(phy->mt76->band_idx));
494c918c74dSShayne Chen mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en);
4955d8a83f0SShayne Chen }
49689043529SShayne Chen }
4975d8a83f0SShayne Chen
4983f0caa3cSShayne Chen static int
mt7915_tm_rf_switch_mode(struct mt7915_dev * dev,u32 oper)4993f0caa3cSShayne Chen mt7915_tm_rf_switch_mode(struct mt7915_dev *dev, u32 oper)
5003f0caa3cSShayne Chen {
5013f0caa3cSShayne Chen struct mt7915_tm_rf_test req = {
5023f0caa3cSShayne Chen .op.op_mode = cpu_to_le32(oper),
5033f0caa3cSShayne Chen };
5043f0caa3cSShayne Chen
505c203dd62SFelix Fietkau return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req,
5063f0caa3cSShayne Chen sizeof(req), true);
5073f0caa3cSShayne Chen }
5083f0caa3cSShayne Chen
5093f0caa3cSShayne Chen static int
mt7915_tm_set_tx_cont(struct mt7915_phy * phy,bool en)5103f0caa3cSShayne Chen mt7915_tm_set_tx_cont(struct mt7915_phy *phy, bool en)
5113f0caa3cSShayne Chen {
5123f0caa3cSShayne Chen #define TX_CONT_START 0x05
5133f0caa3cSShayne Chen #define TX_CONT_STOP 0x06
5143f0caa3cSShayne Chen struct mt7915_dev *dev = phy->dev;
5153f0caa3cSShayne Chen struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
5163f0caa3cSShayne Chen int freq1 = ieee80211_frequency_to_channel(chandef->center_freq1);
5173f0caa3cSShayne Chen struct mt76_testmode_data *td = &phy->mt76->test;
5183f0caa3cSShayne Chen u32 func_idx = en ? TX_CONT_START : TX_CONT_STOP;
5193f0caa3cSShayne Chen u8 rate_idx = td->tx_rate_idx, mode;
520*3eb50cc9SRyder Lee u8 band = phy->mt76->band_idx;
5213f0caa3cSShayne Chen u16 rateval;
5223f0caa3cSShayne Chen struct mt7915_tm_rf_test req = {
5233f0caa3cSShayne Chen .action = 1,
5243f0caa3cSShayne Chen .icap_len = 120,
5253f0caa3cSShayne Chen .op.rf.func_idx = cpu_to_le32(func_idx),
5263f0caa3cSShayne Chen };
5273f0caa3cSShayne Chen struct tm_tx_cont *tx_cont = &req.op.rf.param.tx_cont;
5283f0caa3cSShayne Chen
5293f0caa3cSShayne Chen tx_cont->control_ch = chandef->chan->hw_value;
5303f0caa3cSShayne Chen tx_cont->center_ch = freq1;
5313f0caa3cSShayne Chen tx_cont->tx_ant = td->tx_antenna_mask;
532*3eb50cc9SRyder Lee tx_cont->band = band;
5333f0caa3cSShayne Chen
5343f0caa3cSShayne Chen switch (chandef->width) {
5353f0caa3cSShayne Chen case NL80211_CHAN_WIDTH_40:
5363f0caa3cSShayne Chen tx_cont->bw = CMD_CBW_40MHZ;
5373f0caa3cSShayne Chen break;
5383f0caa3cSShayne Chen case NL80211_CHAN_WIDTH_80:
5393f0caa3cSShayne Chen tx_cont->bw = CMD_CBW_80MHZ;
5403f0caa3cSShayne Chen break;
5413f0caa3cSShayne Chen case NL80211_CHAN_WIDTH_80P80:
5423f0caa3cSShayne Chen tx_cont->bw = CMD_CBW_8080MHZ;
5433f0caa3cSShayne Chen break;
5443f0caa3cSShayne Chen case NL80211_CHAN_WIDTH_160:
5453f0caa3cSShayne Chen tx_cont->bw = CMD_CBW_160MHZ;
5463f0caa3cSShayne Chen break;
5473f0caa3cSShayne Chen case NL80211_CHAN_WIDTH_5:
5483f0caa3cSShayne Chen tx_cont->bw = CMD_CBW_5MHZ;
5493f0caa3cSShayne Chen break;
5503f0caa3cSShayne Chen case NL80211_CHAN_WIDTH_10:
5513f0caa3cSShayne Chen tx_cont->bw = CMD_CBW_10MHZ;
5523f0caa3cSShayne Chen break;
5533f0caa3cSShayne Chen case NL80211_CHAN_WIDTH_20:
5543f0caa3cSShayne Chen tx_cont->bw = CMD_CBW_20MHZ;
5553f0caa3cSShayne Chen break;
5563f0caa3cSShayne Chen case NL80211_CHAN_WIDTH_20_NOHT:
5573f0caa3cSShayne Chen tx_cont->bw = CMD_CBW_20MHZ;
5583f0caa3cSShayne Chen break;
5593f0caa3cSShayne Chen default:
560c490492fSArnd Bergmann return -EINVAL;
5613f0caa3cSShayne Chen }
5623f0caa3cSShayne Chen
5633f0caa3cSShayne Chen if (!en) {
564*3eb50cc9SRyder Lee req.op.rf.param.func_data = cpu_to_le32(band);
5653f0caa3cSShayne Chen goto out;
5663f0caa3cSShayne Chen }
5673f0caa3cSShayne Chen
5683f0caa3cSShayne Chen if (td->tx_rate_mode <= MT76_TM_TX_MODE_OFDM) {
5693f0caa3cSShayne Chen struct ieee80211_supported_band *sband;
5703f0caa3cSShayne Chen u8 idx = rate_idx;
5713f0caa3cSShayne Chen
5723f0caa3cSShayne Chen if (chandef->chan->band == NL80211_BAND_5GHZ)
5733f0caa3cSShayne Chen sband = &phy->mt76->sband_5g.sband;
574b4d093e3SMeiChia Chiu else if (chandef->chan->band == NL80211_BAND_6GHZ)
575b4d093e3SMeiChia Chiu sband = &phy->mt76->sband_6g.sband;
5763f0caa3cSShayne Chen else
5773f0caa3cSShayne Chen sband = &phy->mt76->sband_2g.sband;
5783f0caa3cSShayne Chen
5793f0caa3cSShayne Chen if (td->tx_rate_mode == MT76_TM_TX_MODE_OFDM)
5803f0caa3cSShayne Chen idx += 4;
5813f0caa3cSShayne Chen rate_idx = sband->bitrates[idx].hw_value & 0xff;
5823f0caa3cSShayne Chen }
5833f0caa3cSShayne Chen
5843f0caa3cSShayne Chen switch (td->tx_rate_mode) {
5853f0caa3cSShayne Chen case MT76_TM_TX_MODE_CCK:
5863f0caa3cSShayne Chen mode = MT_PHY_TYPE_CCK;
5873f0caa3cSShayne Chen break;
5883f0caa3cSShayne Chen case MT76_TM_TX_MODE_OFDM:
5893f0caa3cSShayne Chen mode = MT_PHY_TYPE_OFDM;
5903f0caa3cSShayne Chen break;
5913f0caa3cSShayne Chen case MT76_TM_TX_MODE_HT:
5923f0caa3cSShayne Chen mode = MT_PHY_TYPE_HT;
5933f0caa3cSShayne Chen break;
5943f0caa3cSShayne Chen case MT76_TM_TX_MODE_VHT:
5953f0caa3cSShayne Chen mode = MT_PHY_TYPE_VHT;
5963f0caa3cSShayne Chen break;
5973f0caa3cSShayne Chen case MT76_TM_TX_MODE_HE_SU:
5983f0caa3cSShayne Chen mode = MT_PHY_TYPE_HE_SU;
5993f0caa3cSShayne Chen break;
6003f0caa3cSShayne Chen case MT76_TM_TX_MODE_HE_EXT_SU:
6013f0caa3cSShayne Chen mode = MT_PHY_TYPE_HE_EXT_SU;
6023f0caa3cSShayne Chen break;
6033f0caa3cSShayne Chen case MT76_TM_TX_MODE_HE_TB:
6043f0caa3cSShayne Chen mode = MT_PHY_TYPE_HE_TB;
6053f0caa3cSShayne Chen break;
6063f0caa3cSShayne Chen case MT76_TM_TX_MODE_HE_MU:
6073f0caa3cSShayne Chen mode = MT_PHY_TYPE_HE_MU;
6083f0caa3cSShayne Chen break;
6093f0caa3cSShayne Chen default:
610c490492fSArnd Bergmann return -EINVAL;
6113f0caa3cSShayne Chen }
6123f0caa3cSShayne Chen
6133f0caa3cSShayne Chen rateval = mode << 6 | rate_idx;
6143f0caa3cSShayne Chen tx_cont->rateval = cpu_to_le16(rateval);
6153f0caa3cSShayne Chen
6163f0caa3cSShayne Chen out:
6173f0caa3cSShayne Chen if (!en) {
6183f0caa3cSShayne Chen int ret;
6193f0caa3cSShayne Chen
620c203dd62SFelix Fietkau ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req,
6213f0caa3cSShayne Chen sizeof(req), true);
6223f0caa3cSShayne Chen if (ret)
6233f0caa3cSShayne Chen return ret;
6243f0caa3cSShayne Chen
6253f0caa3cSShayne Chen return mt7915_tm_rf_switch_mode(dev, RF_OPER_NORMAL);
6263f0caa3cSShayne Chen }
6273f0caa3cSShayne Chen
6283f0caa3cSShayne Chen mt7915_tm_rf_switch_mode(dev, RF_OPER_RF_TEST);
6293f0caa3cSShayne Chen mt7915_tm_update_channel(phy);
6303f0caa3cSShayne Chen
631c203dd62SFelix Fietkau return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req,
6323f0caa3cSShayne Chen sizeof(req), true);
6333f0caa3cSShayne Chen }
6343f0caa3cSShayne Chen
635e0852d90SShayne Chen static void
mt7915_tm_update_params(struct mt7915_phy * phy,u32 changed)636c918c74dSShayne Chen mt7915_tm_update_params(struct mt7915_phy *phy, u32 changed)
637e0852d90SShayne Chen {
638c918c74dSShayne Chen struct mt76_testmode_data *td = &phy->mt76->test;
639c918c74dSShayne Chen bool en = phy->mt76->test.state != MT76_TM_STATE_OFF;
640ed3c9072SShayne Chen
641ed3c9072SShayne Chen if (changed & BIT(TM_CHANGED_FREQ_OFFSET))
642c918c74dSShayne Chen mt7915_tm_set_freq_offset(phy, en, en ? td->freq_offset : 0);
643e0852d90SShayne Chen if (changed & BIT(TM_CHANGED_TXPOWER))
644c918c74dSShayne Chen mt7915_tm_set_tx_power(phy);
645e0852d90SShayne Chen }
646e0852d90SShayne Chen
647aadf0953SShayne Chen static int
mt7915_tm_set_state(struct mt76_phy * mphy,enum mt76_testmode_state state)648c918c74dSShayne Chen mt7915_tm_set_state(struct mt76_phy *mphy, enum mt76_testmode_state state)
649aadf0953SShayne Chen {
650c918c74dSShayne Chen struct mt76_testmode_data *td = &mphy->test;
651c918c74dSShayne Chen struct mt7915_phy *phy = mphy->priv;
652aadf0953SShayne Chen enum mt76_testmode_state prev_state = td->state;
653aadf0953SShayne Chen
654c918c74dSShayne Chen mphy->test.state = state;
655aadf0953SShayne Chen
65639e48823SShayne Chen if (prev_state == MT76_TM_STATE_TX_FRAMES ||
65739e48823SShayne Chen state == MT76_TM_STATE_TX_FRAMES)
65839e48823SShayne Chen mt7915_tm_set_tx_frames(phy, state == MT76_TM_STATE_TX_FRAMES);
65939e48823SShayne Chen else if (prev_state == MT76_TM_STATE_RX_FRAMES ||
66039e48823SShayne Chen state == MT76_TM_STATE_RX_FRAMES)
66139e48823SShayne Chen mt7915_tm_set_rx_frames(phy, state == MT76_TM_STATE_RX_FRAMES);
6623f0caa3cSShayne Chen else if (prev_state == MT76_TM_STATE_TX_CONT ||
6633f0caa3cSShayne Chen state == MT76_TM_STATE_TX_CONT)
6643f0caa3cSShayne Chen mt7915_tm_set_tx_cont(phy, state == MT76_TM_STATE_TX_CONT);
66539e48823SShayne Chen else if (prev_state == MT76_TM_STATE_OFF ||
66639e48823SShayne Chen state == MT76_TM_STATE_OFF)
66739e48823SShayne Chen mt7915_tm_init(phy, !(state == MT76_TM_STATE_OFF));
668aadf0953SShayne Chen
669e0852d90SShayne Chen if ((state == MT76_TM_STATE_IDLE &&
670e0852d90SShayne Chen prev_state == MT76_TM_STATE_OFF) ||
671e0852d90SShayne Chen (state == MT76_TM_STATE_OFF &&
672e0852d90SShayne Chen prev_state == MT76_TM_STATE_IDLE)) {
673e0852d90SShayne Chen u32 changed = 0;
674e0852d90SShayne Chen int i;
675e0852d90SShayne Chen
676e0852d90SShayne Chen for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) {
677e0852d90SShayne Chen u16 cur = tm_change_map[i];
678e0852d90SShayne Chen
679e0852d90SShayne Chen if (td->param_set[cur / 32] & BIT(cur % 32))
680e0852d90SShayne Chen changed |= BIT(i);
681e0852d90SShayne Chen }
682e0852d90SShayne Chen
683c918c74dSShayne Chen mt7915_tm_update_params(phy, changed);
684e0852d90SShayne Chen }
685e0852d90SShayne Chen
686e0852d90SShayne Chen return 0;
687e0852d90SShayne Chen }
688e0852d90SShayne Chen
689e0852d90SShayne Chen static int
mt7915_tm_set_params(struct mt76_phy * mphy,struct nlattr ** tb,enum mt76_testmode_state new_state)690c918c74dSShayne Chen mt7915_tm_set_params(struct mt76_phy *mphy, struct nlattr **tb,
691e0852d90SShayne Chen enum mt76_testmode_state new_state)
692e0852d90SShayne Chen {
693c918c74dSShayne Chen struct mt76_testmode_data *td = &mphy->test;
694c918c74dSShayne Chen struct mt7915_phy *phy = mphy->priv;
695b61699d2SShayne Chen struct mt7915_dev *dev = phy->dev;
696b61699d2SShayne Chen u32 chainmask = mphy->chainmask, changed = 0;
697b61699d2SShayne Chen bool ext_phy = phy != &dev->phy;
698e0852d90SShayne Chen int i;
699e0852d90SShayne Chen
700e0852d90SShayne Chen BUILD_BUG_ON(NUM_TM_CHANGED >= 32);
701e0852d90SShayne Chen
702e0852d90SShayne Chen if (new_state == MT76_TM_STATE_OFF ||
703e0852d90SShayne Chen td->state == MT76_TM_STATE_OFF)
704e0852d90SShayne Chen return 0;
705e0852d90SShayne Chen
706b61699d2SShayne Chen chainmask = ext_phy ? chainmask >> dev->chainshift : chainmask;
707b61699d2SShayne Chen if (td->tx_antenna_mask > chainmask)
708e0852d90SShayne Chen return -EINVAL;
709e0852d90SShayne Chen
710e0852d90SShayne Chen for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) {
711e0852d90SShayne Chen if (tb[tm_change_map[i]])
712e0852d90SShayne Chen changed |= BIT(i);
713e0852d90SShayne Chen }
714e0852d90SShayne Chen
715c918c74dSShayne Chen mt7915_tm_update_params(phy, changed);
716e0852d90SShayne Chen
717aadf0953SShayne Chen return 0;
718aadf0953SShayne Chen }
719aadf0953SShayne Chen
7205d8a83f0SShayne Chen static int
mt7915_tm_dump_stats(struct mt76_phy * mphy,struct sk_buff * msg)721c918c74dSShayne Chen mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
7225d8a83f0SShayne Chen {
723c918c74dSShayne Chen struct mt7915_phy *phy = mphy->priv;
72489043529SShayne Chen struct mt7915_dev *dev = phy->dev;
72589043529SShayne Chen enum mt76_rxq_id q;
7265d8a83f0SShayne Chen void *rx, *rssi;
72789043529SShayne Chen u16 fcs_err;
7285d8a83f0SShayne Chen int i;
729cd4c314aSBo Jiao u32 cnt;
7305d8a83f0SShayne Chen
7315d8a83f0SShayne Chen rx = nla_nest_start(msg, MT76_TM_STATS_ATTR_LAST_RX);
7325d8a83f0SShayne Chen if (!rx)
7335d8a83f0SShayne Chen return -ENOMEM;
7345d8a83f0SShayne Chen
73578fc30a2SShayne Chen if (nla_put_s32(msg, MT76_TM_RX_ATTR_FREQ_OFFSET, phy->test.last_freq_offset))
7365d8a83f0SShayne Chen return -ENOMEM;
7375d8a83f0SShayne Chen
7385d8a83f0SShayne Chen rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_RCPI);
7395d8a83f0SShayne Chen if (!rssi)
7405d8a83f0SShayne Chen return -ENOMEM;
7415d8a83f0SShayne Chen
74278fc30a2SShayne Chen for (i = 0; i < ARRAY_SIZE(phy->test.last_rcpi); i++)
74378fc30a2SShayne Chen if (nla_put_u8(msg, i, phy->test.last_rcpi[i]))
7445d8a83f0SShayne Chen return -ENOMEM;
7455d8a83f0SShayne Chen
7465d8a83f0SShayne Chen nla_nest_end(msg, rssi);
7475d8a83f0SShayne Chen
7485d8a83f0SShayne Chen rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_IB_RSSI);
7495d8a83f0SShayne Chen if (!rssi)
7505d8a83f0SShayne Chen return -ENOMEM;
7515d8a83f0SShayne Chen
75278fc30a2SShayne Chen for (i = 0; i < ARRAY_SIZE(phy->test.last_ib_rssi); i++)
75378fc30a2SShayne Chen if (nla_put_s8(msg, i, phy->test.last_ib_rssi[i]))
7545d8a83f0SShayne Chen return -ENOMEM;
7555d8a83f0SShayne Chen
7565d8a83f0SShayne Chen nla_nest_end(msg, rssi);
7575d8a83f0SShayne Chen
7585d8a83f0SShayne Chen rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_WB_RSSI);
7595d8a83f0SShayne Chen if (!rssi)
7605d8a83f0SShayne Chen return -ENOMEM;
7615d8a83f0SShayne Chen
76278fc30a2SShayne Chen for (i = 0; i < ARRAY_SIZE(phy->test.last_wb_rssi); i++)
76378fc30a2SShayne Chen if (nla_put_s8(msg, i, phy->test.last_wb_rssi[i]))
7645d8a83f0SShayne Chen return -ENOMEM;
7655d8a83f0SShayne Chen
7665d8a83f0SShayne Chen nla_nest_end(msg, rssi);
7675d8a83f0SShayne Chen
76878fc30a2SShayne Chen if (nla_put_u8(msg, MT76_TM_RX_ATTR_SNR, phy->test.last_snr))
7695d8a83f0SShayne Chen return -ENOMEM;
7705d8a83f0SShayne Chen
7715d8a83f0SShayne Chen nla_nest_end(msg, rx);
7725d8a83f0SShayne Chen
773*3eb50cc9SRyder Lee cnt = mt76_rr(dev, MT_MIB_SDR3(phy->mt76->band_idx));
774cd4c314aSBo Jiao fcs_err = is_mt7915(&dev->mt76) ? FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) :
775cd4c314aSBo Jiao FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt);
776cd4c314aSBo Jiao
777*3eb50cc9SRyder Lee q = phy->mt76->band_idx ? MT_RXQ_BAND1 : MT_RXQ_MAIN;
77889043529SShayne Chen mphy->test.rx_stats.packets[q] += fcs_err;
77989043529SShayne Chen mphy->test.rx_stats.fcs_error[q] += fcs_err;
78089043529SShayne Chen
7815d8a83f0SShayne Chen return 0;
7825d8a83f0SShayne Chen }
7835d8a83f0SShayne Chen
784aadf0953SShayne Chen const struct mt76_testmode_ops mt7915_testmode_ops = {
785aadf0953SShayne Chen .set_state = mt7915_tm_set_state,
786e0852d90SShayne Chen .set_params = mt7915_tm_set_params,
7875d8a83f0SShayne Chen .dump_stats = mt7915_tm_dump_stats,
788aadf0953SShayne Chen };
789