1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 	Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 	Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
5 	Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
6 	Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 
8 	Based on the original rt2800pci.c and rt2800usb.c.
9 	  Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
10 	  Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
11 	  Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
12 	  Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
13 	  Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
14 	  Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
15 	  <http://rt2x00.serialmonkey.com>
16 
17  */
18 
19 /*
20 	Module: rt2800lib
21 	Abstract: rt2800 generic device routines.
22  */
23 
24 #include <linux/crc-ccitt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 
29 #include "rt2x00.h"
30 #include "rt2800lib.h"
31 #include "rt2800.h"
32 
33 static bool modparam_watchdog;
34 module_param_named(watchdog, modparam_watchdog, bool, S_IRUGO);
35 MODULE_PARM_DESC(watchdog, "Enable watchdog to detect tx/rx hangs and reset hardware if detected");
36 
37 /*
38  * Register access.
39  * All access to the CSR registers will go through the methods
40  * rt2800_register_read and rt2800_register_write.
41  * BBP and RF register require indirect register access,
42  * and use the CSR registers BBPCSR and RFCSR to achieve this.
43  * These indirect registers work with busy bits,
44  * and we will try maximal REGISTER_BUSY_COUNT times to access
45  * the register while taking a REGISTER_BUSY_DELAY us delay
46  * between each attampt. When the busy bit is still set at that time,
47  * the access attempt is considered to have failed,
48  * and we will print an error.
49  * The _lock versions must be used if you already hold the csr_mutex
50  */
51 #define WAIT_FOR_BBP(__dev, __reg) \
52 	rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
53 #define WAIT_FOR_RFCSR(__dev, __reg) \
54 	rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
55 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
56 	rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
57 			    (__reg))
58 #define WAIT_FOR_RF(__dev, __reg) \
59 	rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
60 #define WAIT_FOR_MCU(__dev, __reg) \
61 	rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
62 			    H2M_MAILBOX_CSR_OWNER, (__reg))
63 
64 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
65 {
66 	/* check for rt2872 on SoC */
67 	if (!rt2x00_is_soc(rt2x00dev) ||
68 	    !rt2x00_rt(rt2x00dev, RT2872))
69 		return false;
70 
71 	/* we know for sure that these rf chipsets are used on rt305x boards */
72 	if (rt2x00_rf(rt2x00dev, RF3020) ||
73 	    rt2x00_rf(rt2x00dev, RF3021) ||
74 	    rt2x00_rf(rt2x00dev, RF3022))
75 		return true;
76 
77 	rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
78 	return false;
79 }
80 
81 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
82 			     const unsigned int word, const u8 value)
83 {
84 	u32 reg;
85 
86 	mutex_lock(&rt2x00dev->csr_mutex);
87 
88 	/*
89 	 * Wait until the BBP becomes available, afterwards we
90 	 * can safely write the new data into the register.
91 	 */
92 	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
93 		reg = 0;
94 		rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
95 		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
96 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
97 		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
98 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
99 
100 		rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
101 	}
102 
103 	mutex_unlock(&rt2x00dev->csr_mutex);
104 }
105 
106 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
107 {
108 	u32 reg;
109 	u8 value;
110 
111 	mutex_lock(&rt2x00dev->csr_mutex);
112 
113 	/*
114 	 * Wait until the BBP becomes available, afterwards we
115 	 * can safely write the read request into the register.
116 	 * After the data has been written, we wait until hardware
117 	 * returns the correct value, if at any time the register
118 	 * doesn't become available in time, reg will be 0xffffffff
119 	 * which means we return 0xff to the caller.
120 	 */
121 	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
122 		reg = 0;
123 		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
124 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
125 		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
126 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
127 
128 		rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
129 
130 		WAIT_FOR_BBP(rt2x00dev, &reg);
131 	}
132 
133 	value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
134 
135 	mutex_unlock(&rt2x00dev->csr_mutex);
136 
137 	return value;
138 }
139 
140 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
141 			       const unsigned int word, const u8 value)
142 {
143 	u32 reg;
144 
145 	mutex_lock(&rt2x00dev->csr_mutex);
146 
147 	/*
148 	 * Wait until the RFCSR becomes available, afterwards we
149 	 * can safely write the new data into the register.
150 	 */
151 	switch (rt2x00dev->chip.rt) {
152 	case RT6352:
153 		if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
154 			reg = 0;
155 			rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
156 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
157 					   word);
158 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
159 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
160 
161 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
162 		}
163 		break;
164 
165 	default:
166 		if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
167 			reg = 0;
168 			rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
169 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
170 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
171 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
172 
173 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
174 		}
175 		break;
176 	}
177 
178 	mutex_unlock(&rt2x00dev->csr_mutex);
179 }
180 
181 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
182 				    const unsigned int reg, const u8 value)
183 {
184 	rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
185 }
186 
187 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
188 				       const unsigned int reg, const u8 value)
189 {
190 	rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
191 	rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
192 }
193 
194 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
195 				     const unsigned int reg, const u8 value)
196 {
197 	rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
198 	rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
199 }
200 
201 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
202 			    const unsigned int word)
203 {
204 	u32 reg;
205 	u8 value;
206 
207 	mutex_lock(&rt2x00dev->csr_mutex);
208 
209 	/*
210 	 * Wait until the RFCSR becomes available, afterwards we
211 	 * can safely write the read request into the register.
212 	 * After the data has been written, we wait until hardware
213 	 * returns the correct value, if at any time the register
214 	 * doesn't become available in time, reg will be 0xffffffff
215 	 * which means we return 0xff to the caller.
216 	 */
217 	switch (rt2x00dev->chip.rt) {
218 	case RT6352:
219 		if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
220 			reg = 0;
221 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
222 					   word);
223 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
224 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
225 
226 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
227 
228 			WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
229 		}
230 
231 		value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
232 		break;
233 
234 	default:
235 		if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
236 			reg = 0;
237 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
238 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
239 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
240 
241 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
242 
243 			WAIT_FOR_RFCSR(rt2x00dev, &reg);
244 		}
245 
246 		value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
247 		break;
248 	}
249 
250 	mutex_unlock(&rt2x00dev->csr_mutex);
251 
252 	return value;
253 }
254 
255 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
256 				 const unsigned int reg)
257 {
258 	return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
259 }
260 
261 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
262 			    const unsigned int word, const u32 value)
263 {
264 	u32 reg;
265 
266 	mutex_lock(&rt2x00dev->csr_mutex);
267 
268 	/*
269 	 * Wait until the RF becomes available, afterwards we
270 	 * can safely write the new data into the register.
271 	 */
272 	if (WAIT_FOR_RF(rt2x00dev, &reg)) {
273 		reg = 0;
274 		rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
275 		rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
276 		rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
277 		rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
278 
279 		rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
280 		rt2x00_rf_write(rt2x00dev, word, value);
281 	}
282 
283 	mutex_unlock(&rt2x00dev->csr_mutex);
284 }
285 
286 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
287 	[EEPROM_CHIP_ID]		= 0x0000,
288 	[EEPROM_VERSION]		= 0x0001,
289 	[EEPROM_MAC_ADDR_0]		= 0x0002,
290 	[EEPROM_MAC_ADDR_1]		= 0x0003,
291 	[EEPROM_MAC_ADDR_2]		= 0x0004,
292 	[EEPROM_NIC_CONF0]		= 0x001a,
293 	[EEPROM_NIC_CONF1]		= 0x001b,
294 	[EEPROM_FREQ]			= 0x001d,
295 	[EEPROM_LED_AG_CONF]		= 0x001e,
296 	[EEPROM_LED_ACT_CONF]		= 0x001f,
297 	[EEPROM_LED_POLARITY]		= 0x0020,
298 	[EEPROM_NIC_CONF2]		= 0x0021,
299 	[EEPROM_LNA]			= 0x0022,
300 	[EEPROM_RSSI_BG]		= 0x0023,
301 	[EEPROM_RSSI_BG2]		= 0x0024,
302 	[EEPROM_TXMIXER_GAIN_BG]	= 0x0024, /* overlaps with RSSI_BG2 */
303 	[EEPROM_RSSI_A]			= 0x0025,
304 	[EEPROM_RSSI_A2]		= 0x0026,
305 	[EEPROM_TXMIXER_GAIN_A]		= 0x0026, /* overlaps with RSSI_A2 */
306 	[EEPROM_EIRP_MAX_TX_POWER]	= 0x0027,
307 	[EEPROM_TXPOWER_DELTA]		= 0x0028,
308 	[EEPROM_TXPOWER_BG1]		= 0x0029,
309 	[EEPROM_TXPOWER_BG2]		= 0x0030,
310 	[EEPROM_TSSI_BOUND_BG1]		= 0x0037,
311 	[EEPROM_TSSI_BOUND_BG2]		= 0x0038,
312 	[EEPROM_TSSI_BOUND_BG3]		= 0x0039,
313 	[EEPROM_TSSI_BOUND_BG4]		= 0x003a,
314 	[EEPROM_TSSI_BOUND_BG5]		= 0x003b,
315 	[EEPROM_TXPOWER_A1]		= 0x003c,
316 	[EEPROM_TXPOWER_A2]		= 0x0053,
317 	[EEPROM_TXPOWER_INIT]		= 0x0068,
318 	[EEPROM_TSSI_BOUND_A1]		= 0x006a,
319 	[EEPROM_TSSI_BOUND_A2]		= 0x006b,
320 	[EEPROM_TSSI_BOUND_A3]		= 0x006c,
321 	[EEPROM_TSSI_BOUND_A4]		= 0x006d,
322 	[EEPROM_TSSI_BOUND_A5]		= 0x006e,
323 	[EEPROM_TXPOWER_BYRATE]		= 0x006f,
324 	[EEPROM_BBP_START]		= 0x0078,
325 };
326 
327 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
328 	[EEPROM_CHIP_ID]		= 0x0000,
329 	[EEPROM_VERSION]		= 0x0001,
330 	[EEPROM_MAC_ADDR_0]		= 0x0002,
331 	[EEPROM_MAC_ADDR_1]		= 0x0003,
332 	[EEPROM_MAC_ADDR_2]		= 0x0004,
333 	[EEPROM_NIC_CONF0]		= 0x001a,
334 	[EEPROM_NIC_CONF1]		= 0x001b,
335 	[EEPROM_NIC_CONF2]		= 0x001c,
336 	[EEPROM_EIRP_MAX_TX_POWER]	= 0x0020,
337 	[EEPROM_FREQ]			= 0x0022,
338 	[EEPROM_LED_AG_CONF]		= 0x0023,
339 	[EEPROM_LED_ACT_CONF]		= 0x0024,
340 	[EEPROM_LED_POLARITY]		= 0x0025,
341 	[EEPROM_LNA]			= 0x0026,
342 	[EEPROM_EXT_LNA2]		= 0x0027,
343 	[EEPROM_RSSI_BG]		= 0x0028,
344 	[EEPROM_RSSI_BG2]		= 0x0029,
345 	[EEPROM_RSSI_A]			= 0x002a,
346 	[EEPROM_RSSI_A2]		= 0x002b,
347 	[EEPROM_TXPOWER_BG1]		= 0x0030,
348 	[EEPROM_TXPOWER_BG2]		= 0x0037,
349 	[EEPROM_EXT_TXPOWER_BG3]	= 0x003e,
350 	[EEPROM_TSSI_BOUND_BG1]		= 0x0045,
351 	[EEPROM_TSSI_BOUND_BG2]		= 0x0046,
352 	[EEPROM_TSSI_BOUND_BG3]		= 0x0047,
353 	[EEPROM_TSSI_BOUND_BG4]		= 0x0048,
354 	[EEPROM_TSSI_BOUND_BG5]		= 0x0049,
355 	[EEPROM_TXPOWER_A1]		= 0x004b,
356 	[EEPROM_TXPOWER_A2]		= 0x0065,
357 	[EEPROM_EXT_TXPOWER_A3]		= 0x007f,
358 	[EEPROM_TSSI_BOUND_A1]		= 0x009a,
359 	[EEPROM_TSSI_BOUND_A2]		= 0x009b,
360 	[EEPROM_TSSI_BOUND_A3]		= 0x009c,
361 	[EEPROM_TSSI_BOUND_A4]		= 0x009d,
362 	[EEPROM_TSSI_BOUND_A5]		= 0x009e,
363 	[EEPROM_TXPOWER_BYRATE]		= 0x00a0,
364 };
365 
366 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
367 					     const enum rt2800_eeprom_word word)
368 {
369 	const unsigned int *map;
370 	unsigned int index;
371 
372 	if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
373 		      "%s: invalid EEPROM word %d\n",
374 		      wiphy_name(rt2x00dev->hw->wiphy), word))
375 		return 0;
376 
377 	if (rt2x00_rt(rt2x00dev, RT3593) ||
378 	    rt2x00_rt(rt2x00dev, RT3883))
379 		map = rt2800_eeprom_map_ext;
380 	else
381 		map = rt2800_eeprom_map;
382 
383 	index = map[word];
384 
385 	/* Index 0 is valid only for EEPROM_CHIP_ID.
386 	 * Otherwise it means that the offset of the
387 	 * given word is not initialized in the map,
388 	 * or that the field is not usable on the
389 	 * actual chipset.
390 	 */
391 	WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
392 		  "%s: invalid access of EEPROM word %d\n",
393 		  wiphy_name(rt2x00dev->hw->wiphy), word);
394 
395 	return index;
396 }
397 
398 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
399 				const enum rt2800_eeprom_word word)
400 {
401 	unsigned int index;
402 
403 	index = rt2800_eeprom_word_index(rt2x00dev, word);
404 	return rt2x00_eeprom_addr(rt2x00dev, index);
405 }
406 
407 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
408 			      const enum rt2800_eeprom_word word)
409 {
410 	unsigned int index;
411 
412 	index = rt2800_eeprom_word_index(rt2x00dev, word);
413 	return rt2x00_eeprom_read(rt2x00dev, index);
414 }
415 
416 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
417 				const enum rt2800_eeprom_word word, u16 data)
418 {
419 	unsigned int index;
420 
421 	index = rt2800_eeprom_word_index(rt2x00dev, word);
422 	rt2x00_eeprom_write(rt2x00dev, index, data);
423 }
424 
425 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
426 					 const enum rt2800_eeprom_word array,
427 					 unsigned int offset)
428 {
429 	unsigned int index;
430 
431 	index = rt2800_eeprom_word_index(rt2x00dev, array);
432 	return rt2x00_eeprom_read(rt2x00dev, index + offset);
433 }
434 
435 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
436 {
437 	u32 reg;
438 	int i, count;
439 
440 	reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
441 	rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
442 	rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
443 	rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
444 	rt2x00_set_field32(&reg, WLAN_EN, 1);
445 	rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
446 
447 	udelay(REGISTER_BUSY_DELAY);
448 
449 	count = 0;
450 	do {
451 		/*
452 		 * Check PLL_LD & XTAL_RDY.
453 		 */
454 		for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
455 			reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
456 			if (rt2x00_get_field32(reg, PLL_LD) &&
457 			    rt2x00_get_field32(reg, XTAL_RDY))
458 				break;
459 			udelay(REGISTER_BUSY_DELAY);
460 		}
461 
462 		if (i >= REGISTER_BUSY_COUNT) {
463 
464 			if (count >= 10)
465 				return -EIO;
466 
467 			rt2800_register_write(rt2x00dev, 0x58, 0x018);
468 			udelay(REGISTER_BUSY_DELAY);
469 			rt2800_register_write(rt2x00dev, 0x58, 0x418);
470 			udelay(REGISTER_BUSY_DELAY);
471 			rt2800_register_write(rt2x00dev, 0x58, 0x618);
472 			udelay(REGISTER_BUSY_DELAY);
473 			count++;
474 		} else {
475 			count = 0;
476 		}
477 
478 		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
479 		rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
480 		rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
481 		rt2x00_set_field32(&reg, WLAN_RESET, 1);
482 		rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
483 		udelay(10);
484 		rt2x00_set_field32(&reg, WLAN_RESET, 0);
485 		rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
486 		udelay(10);
487 		rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
488 	} while (count != 0);
489 
490 	return 0;
491 }
492 
493 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
494 			const u8 command, const u8 token,
495 			const u8 arg0, const u8 arg1)
496 {
497 	u32 reg;
498 
499 	/*
500 	 * SOC devices don't support MCU requests.
501 	 */
502 	if (rt2x00_is_soc(rt2x00dev))
503 		return;
504 
505 	mutex_lock(&rt2x00dev->csr_mutex);
506 
507 	/*
508 	 * Wait until the MCU becomes available, afterwards we
509 	 * can safely write the new data into the register.
510 	 */
511 	if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
512 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
513 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
514 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
515 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
516 		rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
517 
518 		reg = 0;
519 		rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
520 		rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
521 	}
522 
523 	mutex_unlock(&rt2x00dev->csr_mutex);
524 }
525 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
526 
527 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
528 {
529 	unsigned int i = 0;
530 	u32 reg;
531 
532 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
533 		reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
534 		if (reg && reg != ~0)
535 			return 0;
536 		msleep(1);
537 	}
538 
539 	rt2x00_err(rt2x00dev, "Unstable hardware\n");
540 	return -EBUSY;
541 }
542 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
543 
544 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
545 {
546 	unsigned int i;
547 	u32 reg;
548 
549 	/*
550 	 * Some devices are really slow to respond here. Wait a whole second
551 	 * before timing out.
552 	 */
553 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
554 		reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
555 		if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
556 		    !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
557 			return 0;
558 
559 		msleep(10);
560 	}
561 
562 	rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
563 	return -EACCES;
564 }
565 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
566 
567 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
568 {
569 	u32 reg;
570 
571 	reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
572 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
573 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
574 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
575 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
576 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
577 	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
578 }
579 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
580 
581 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
582 			       unsigned short *txwi_size,
583 			       unsigned short *rxwi_size)
584 {
585 	switch (rt2x00dev->chip.rt) {
586 	case RT3593:
587 	case RT3883:
588 		*txwi_size = TXWI_DESC_SIZE_4WORDS;
589 		*rxwi_size = RXWI_DESC_SIZE_5WORDS;
590 		break;
591 
592 	case RT5592:
593 	case RT6352:
594 		*txwi_size = TXWI_DESC_SIZE_5WORDS;
595 		*rxwi_size = RXWI_DESC_SIZE_6WORDS;
596 		break;
597 
598 	default:
599 		*txwi_size = TXWI_DESC_SIZE_4WORDS;
600 		*rxwi_size = RXWI_DESC_SIZE_4WORDS;
601 		break;
602 	}
603 }
604 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
605 
606 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
607 {
608 	u16 fw_crc;
609 	u16 crc;
610 
611 	/*
612 	 * The last 2 bytes in the firmware array are the crc checksum itself,
613 	 * this means that we should never pass those 2 bytes to the crc
614 	 * algorithm.
615 	 */
616 	fw_crc = (data[len - 2] << 8 | data[len - 1]);
617 
618 	/*
619 	 * Use the crc ccitt algorithm.
620 	 * This will return the same value as the legacy driver which
621 	 * used bit ordering reversion on the both the firmware bytes
622 	 * before input input as well as on the final output.
623 	 * Obviously using crc ccitt directly is much more efficient.
624 	 */
625 	crc = crc_ccitt(~0, data, len - 2);
626 
627 	/*
628 	 * There is a small difference between the crc-itu-t + bitrev and
629 	 * the crc-ccitt crc calculation. In the latter method the 2 bytes
630 	 * will be swapped, use swab16 to convert the crc to the correct
631 	 * value.
632 	 */
633 	crc = swab16(crc);
634 
635 	return fw_crc == crc;
636 }
637 
638 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
639 			  const u8 *data, const size_t len)
640 {
641 	size_t offset = 0;
642 	size_t fw_len;
643 	bool multiple;
644 
645 	/*
646 	 * PCI(e) & SOC devices require firmware with a length
647 	 * of 8kb. USB devices require firmware files with a length
648 	 * of 4kb. Certain USB chipsets however require different firmware,
649 	 * which Ralink only provides attached to the original firmware
650 	 * file. Thus for USB devices, firmware files have a length
651 	 * which is a multiple of 4kb. The firmware for rt3290 chip also
652 	 * have a length which is a multiple of 4kb.
653 	 */
654 	if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
655 		fw_len = 4096;
656 	else
657 		fw_len = 8192;
658 
659 	multiple = true;
660 	/*
661 	 * Validate the firmware length
662 	 */
663 	if (len != fw_len && (!multiple || (len % fw_len) != 0))
664 		return FW_BAD_LENGTH;
665 
666 	/*
667 	 * Check if the chipset requires one of the upper parts
668 	 * of the firmware.
669 	 */
670 	if (rt2x00_is_usb(rt2x00dev) &&
671 	    !rt2x00_rt(rt2x00dev, RT2860) &&
672 	    !rt2x00_rt(rt2x00dev, RT2872) &&
673 	    !rt2x00_rt(rt2x00dev, RT3070) &&
674 	    ((len / fw_len) == 1))
675 		return FW_BAD_VERSION;
676 
677 	/*
678 	 * 8kb firmware files must be checked as if it were
679 	 * 2 separate firmware files.
680 	 */
681 	while (offset < len) {
682 		if (!rt2800_check_firmware_crc(data + offset, fw_len))
683 			return FW_BAD_CRC;
684 
685 		offset += fw_len;
686 	}
687 
688 	return FW_OK;
689 }
690 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
691 
692 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
693 			 const u8 *data, const size_t len)
694 {
695 	unsigned int i;
696 	u32 reg;
697 	int retval;
698 
699 	if (rt2x00_rt(rt2x00dev, RT3290)) {
700 		retval = rt2800_enable_wlan_rt3290(rt2x00dev);
701 		if (retval)
702 			return -EBUSY;
703 	}
704 
705 	/*
706 	 * If driver doesn't wake up firmware here,
707 	 * rt2800_load_firmware will hang forever when interface is up again.
708 	 */
709 	rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
710 
711 	/*
712 	 * Wait for stable hardware.
713 	 */
714 	if (rt2800_wait_csr_ready(rt2x00dev))
715 		return -EBUSY;
716 
717 	if (rt2x00_is_pci(rt2x00dev)) {
718 		if (rt2x00_rt(rt2x00dev, RT3290) ||
719 		    rt2x00_rt(rt2x00dev, RT3572) ||
720 		    rt2x00_rt(rt2x00dev, RT5390) ||
721 		    rt2x00_rt(rt2x00dev, RT5392)) {
722 			reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
723 			rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
724 			rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
725 			rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
726 		}
727 		rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
728 	}
729 
730 	rt2800_disable_wpdma(rt2x00dev);
731 
732 	/*
733 	 * Write firmware to the device.
734 	 */
735 	rt2800_drv_write_firmware(rt2x00dev, data, len);
736 
737 	/*
738 	 * Wait for device to stabilize.
739 	 */
740 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
741 		reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
742 		if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
743 			break;
744 		msleep(1);
745 	}
746 
747 	if (i == REGISTER_BUSY_COUNT) {
748 		rt2x00_err(rt2x00dev, "PBF system register not ready\n");
749 		return -EBUSY;
750 	}
751 
752 	/*
753 	 * Disable DMA, will be reenabled later when enabling
754 	 * the radio.
755 	 */
756 	rt2800_disable_wpdma(rt2x00dev);
757 
758 	/*
759 	 * Initialize firmware.
760 	 */
761 	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
762 	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
763 	if (rt2x00_is_usb(rt2x00dev)) {
764 		rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
765 		rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
766 	}
767 	msleep(1);
768 
769 	return 0;
770 }
771 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
772 
773 void rt2800_write_tx_data(struct queue_entry *entry,
774 			  struct txentry_desc *txdesc)
775 {
776 	__le32 *txwi = rt2800_drv_get_txwi(entry);
777 	u32 word;
778 	int i;
779 
780 	/*
781 	 * Initialize TX Info descriptor
782 	 */
783 	word = rt2x00_desc_read(txwi, 0);
784 	rt2x00_set_field32(&word, TXWI_W0_FRAG,
785 			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
786 	rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
787 			   test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
788 	rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
789 	rt2x00_set_field32(&word, TXWI_W0_TS,
790 			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
791 	rt2x00_set_field32(&word, TXWI_W0_AMPDU,
792 			   test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
793 	rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
794 			   txdesc->u.ht.mpdu_density);
795 	rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
796 	rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
797 	rt2x00_set_field32(&word, TXWI_W0_BW,
798 			   test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
799 	rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
800 			   test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
801 	rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
802 	rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
803 	rt2x00_desc_write(txwi, 0, word);
804 
805 	word = rt2x00_desc_read(txwi, 1);
806 	rt2x00_set_field32(&word, TXWI_W1_ACK,
807 			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));
808 	rt2x00_set_field32(&word, TXWI_W1_NSEQ,
809 			   test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
810 	rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
811 	rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
812 			   test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
813 			   txdesc->key_idx : txdesc->u.ht.wcid);
814 	rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
815 			   txdesc->length);
816 	rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
817 	rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
818 	rt2x00_desc_write(txwi, 1, word);
819 
820 	/*
821 	 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
822 	 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
823 	 * When TXD_W3_WIV is set to 1 it will use the IV data
824 	 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
825 	 * crypto entry in the registers should be used to encrypt the frame.
826 	 *
827 	 * Nulify all remaining words as well, we don't know how to program them.
828 	 */
829 	for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
830 		_rt2x00_desc_write(txwi, i, 0);
831 }
832 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
833 
834 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
835 {
836 	s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
837 	s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
838 	s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
839 	u16 eeprom;
840 	u8 offset0;
841 	u8 offset1;
842 	u8 offset2;
843 
844 	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
845 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
846 		offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
847 		offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
848 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
849 		offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
850 	} else {
851 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
852 		offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
853 		offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
854 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
855 		offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
856 	}
857 
858 	/*
859 	 * Convert the value from the descriptor into the RSSI value
860 	 * If the value in the descriptor is 0, it is considered invalid
861 	 * and the default (extremely low) rssi value is assumed
862 	 */
863 	rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
864 	rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
865 	rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
866 
867 	/*
868 	 * mac80211 only accepts a single RSSI value. Calculating the
869 	 * average doesn't deliver a fair answer either since -60:-60 would
870 	 * be considered equally good as -50:-70 while the second is the one
871 	 * which gives less energy...
872 	 */
873 	rssi0 = max(rssi0, rssi1);
874 	return (int)max(rssi0, rssi2);
875 }
876 
877 void rt2800_process_rxwi(struct queue_entry *entry,
878 			 struct rxdone_entry_desc *rxdesc)
879 {
880 	__le32 *rxwi = (__le32 *) entry->skb->data;
881 	u32 word;
882 
883 	word = rt2x00_desc_read(rxwi, 0);
884 
885 	rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
886 	rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
887 
888 	word = rt2x00_desc_read(rxwi, 1);
889 
890 	if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
891 		rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
892 
893 	if (rt2x00_get_field32(word, RXWI_W1_BW))
894 		rxdesc->bw = RATE_INFO_BW_40;
895 
896 	/*
897 	 * Detect RX rate, always use MCS as signal type.
898 	 */
899 	rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
900 	rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
901 	rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
902 
903 	/*
904 	 * Mask of 0x8 bit to remove the short preamble flag.
905 	 */
906 	if (rxdesc->rate_mode == RATE_MODE_CCK)
907 		rxdesc->signal &= ~0x8;
908 
909 	word = rt2x00_desc_read(rxwi, 2);
910 
911 	/*
912 	 * Convert descriptor AGC value to RSSI value.
913 	 */
914 	rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
915 	/*
916 	 * Remove RXWI descriptor from start of the buffer.
917 	 */
918 	skb_pull(entry->skb, entry->queue->winfo_size);
919 }
920 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
921 
922 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
923 				    u32 status, enum nl80211_band band)
924 {
925 	u8 flags = 0;
926 	u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
927 
928 	switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
929 	case RATE_MODE_HT_GREENFIELD:
930 		flags |= IEEE80211_TX_RC_GREEN_FIELD;
931 		fallthrough;
932 	case RATE_MODE_HT_MIX:
933 		flags |= IEEE80211_TX_RC_MCS;
934 		break;
935 	case RATE_MODE_OFDM:
936 		if (band == NL80211_BAND_2GHZ)
937 			idx += 4;
938 		break;
939 	case RATE_MODE_CCK:
940 		if (idx >= 8)
941 			idx -= 8;
942 		break;
943 	}
944 
945 	if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
946 		flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
947 
948 	if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
949 		flags |= IEEE80211_TX_RC_SHORT_GI;
950 
951 	skbdesc->tx_rate_idx = idx;
952 	skbdesc->tx_rate_flags = flags;
953 }
954 
955 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
956 {
957 	__le32 *txwi;
958 	u32 word;
959 	int wcid, ack, pid;
960 	int tx_wcid, tx_ack, tx_pid, is_agg;
961 
962 	/*
963 	 * This frames has returned with an IO error,
964 	 * so the status report is not intended for this
965 	 * frame.
966 	 */
967 	if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
968 		return false;
969 
970 	wcid	= rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
971 	ack	= rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
972 	pid	= rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
973 	is_agg	= rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE);
974 
975 	/*
976 	 * Validate if this TX status report is intended for
977 	 * this entry by comparing the WCID/ACK/PID fields.
978 	 */
979 	txwi = rt2800_drv_get_txwi(entry);
980 
981 	word = rt2x00_desc_read(txwi, 1);
982 	tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
983 	tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
984 	tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
985 
986 	if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) {
987 		rt2x00_dbg(entry->queue->rt2x00dev,
988 			   "TX status report missed for queue %d entry %d\n",
989 			   entry->queue->qid, entry->entry_idx);
990 		return false;
991 	}
992 
993 	return true;
994 }
995 
996 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
997 			 bool match)
998 {
999 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1000 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1001 	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1002 	struct txdone_entry_desc txdesc;
1003 	u32 word;
1004 	u16 mcs, real_mcs;
1005 	int aggr, ampdu, wcid, ack_req;
1006 
1007 	/*
1008 	 * Obtain the status about this packet.
1009 	 */
1010 	txdesc.flags = 0;
1011 	word = rt2x00_desc_read(txwi, 0);
1012 
1013 	mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1014 	ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
1015 
1016 	real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
1017 	aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
1018 	wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
1019 	ack_req	= rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
1020 
1021 	/*
1022 	 * If a frame was meant to be sent as a single non-aggregated MPDU
1023 	 * but ended up in an aggregate the used tx rate doesn't correlate
1024 	 * with the one specified in the TXWI as the whole aggregate is sent
1025 	 * with the same rate.
1026 	 *
1027 	 * For example: two frames are sent to rt2x00, the first one sets
1028 	 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
1029 	 * and requests MCS15. If the hw aggregates both frames into one
1030 	 * AMDPU the tx status for both frames will contain MCS7 although
1031 	 * the frame was sent successfully.
1032 	 *
1033 	 * Hence, replace the requested rate with the real tx rate to not
1034 	 * confuse the rate control algortihm by providing clearly wrong
1035 	 * data.
1036 	 *
1037 	 * FIXME: if we do not find matching entry, we tell that frame was
1038 	 * posted without any retries. We need to find a way to fix that
1039 	 * and provide retry count.
1040 	 */
1041 	if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
1042 		rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1043 		mcs = real_mcs;
1044 	}
1045 
1046 	if (aggr == 1 || ampdu == 1)
1047 		__set_bit(TXDONE_AMPDU, &txdesc.flags);
1048 
1049 	if (!ack_req)
1050 		__set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
1051 
1052 	/*
1053 	 * Ralink has a retry mechanism using a global fallback
1054 	 * table. We setup this fallback table to try the immediate
1055 	 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
1056 	 * always contains the MCS used for the last transmission, be
1057 	 * it successful or not.
1058 	 */
1059 	if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
1060 		/*
1061 		 * Transmission succeeded. The number of retries is
1062 		 * mcs - real_mcs
1063 		 */
1064 		__set_bit(TXDONE_SUCCESS, &txdesc.flags);
1065 		txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1066 	} else {
1067 		/*
1068 		 * Transmission failed. The number of retries is
1069 		 * always 7 in this case (for a total number of 8
1070 		 * frames sent).
1071 		 */
1072 		__set_bit(TXDONE_FAILURE, &txdesc.flags);
1073 		txdesc.retry = rt2x00dev->long_retry;
1074 	}
1075 
1076 	/*
1077 	 * the frame was retried at least once
1078 	 * -> hw used fallback rates
1079 	 */
1080 	if (txdesc.retry)
1081 		__set_bit(TXDONE_FALLBACK, &txdesc.flags);
1082 
1083 	if (!match) {
1084 		/* RCU assures non-null sta will not be freed by mac80211. */
1085 		rcu_read_lock();
1086 		if (likely(wcid >= WCID_START && wcid <= WCID_END))
1087 			skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1088 		else
1089 			skbdesc->sta = NULL;
1090 		rt2x00lib_txdone_nomatch(entry, &txdesc);
1091 		rcu_read_unlock();
1092 	} else {
1093 		rt2x00lib_txdone(entry, &txdesc);
1094 	}
1095 }
1096 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1097 
1098 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota)
1099 {
1100 	struct data_queue *queue;
1101 	struct queue_entry *entry;
1102 	u32 reg;
1103 	u8 qid;
1104 	bool match;
1105 
1106 	while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, &reg)) {
1107 		/*
1108 		 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is
1109 		 * guaranteed to be one of the TX QIDs .
1110 		 */
1111 		qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
1112 		queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
1113 
1114 		if (unlikely(rt2x00queue_empty(queue))) {
1115 			rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
1116 				   qid);
1117 			break;
1118 		}
1119 
1120 		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1121 
1122 		if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1123 			     !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) {
1124 			rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n",
1125 				    entry->entry_idx, qid);
1126 			break;
1127 		}
1128 
1129 		match = rt2800_txdone_entry_check(entry, reg);
1130 		rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match);
1131 	}
1132 }
1133 EXPORT_SYMBOL_GPL(rt2800_txdone);
1134 
1135 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev,
1136 						 struct queue_entry *entry)
1137 {
1138 	bool ret;
1139 	unsigned long tout;
1140 
1141 	if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1142 		return false;
1143 
1144 	if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))
1145 		tout = msecs_to_jiffies(50);
1146 	else
1147 		tout = msecs_to_jiffies(2000);
1148 
1149 	ret = time_after(jiffies, entry->last_action + tout);
1150 	if (unlikely(ret))
1151 		rt2x00_dbg(entry->queue->rt2x00dev,
1152 			   "TX status timeout for entry %d in queue %d\n",
1153 			   entry->entry_idx, entry->queue->qid);
1154 	return ret;
1155 }
1156 
1157 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev)
1158 {
1159 	struct data_queue *queue;
1160 	struct queue_entry *entry;
1161 
1162 	tx_queue_for_each(rt2x00dev, queue) {
1163 		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1164 		if (rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1165 			return true;
1166 	}
1167 
1168 	return false;
1169 }
1170 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout);
1171 
1172 /*
1173  * test if there is an entry in any TX queue for which DMA is done
1174  * but the TX status has not been returned yet
1175  */
1176 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev)
1177 {
1178 	struct data_queue *queue;
1179 
1180 	tx_queue_for_each(rt2x00dev, queue) {
1181 		if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) !=
1182 		    rt2x00queue_get_entry(queue, Q_INDEX_DONE))
1183 			return true;
1184 	}
1185 	return false;
1186 }
1187 EXPORT_SYMBOL_GPL(rt2800_txstatus_pending);
1188 
1189 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev)
1190 {
1191 	struct data_queue *queue;
1192 	struct queue_entry *entry;
1193 
1194 	/*
1195 	 * Process any trailing TX status reports for IO failures,
1196 	 * we loop until we find the first non-IO error entry. This
1197 	 * can either be a frame which is free, is being uploaded,
1198 	 * or has completed the upload but didn't have an entry
1199 	 * in the TX_STAT_FIFO register yet.
1200 	 */
1201 	tx_queue_for_each(rt2x00dev, queue) {
1202 		while (!rt2x00queue_empty(queue)) {
1203 			entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1204 
1205 			if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1206 			    !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1207 				break;
1208 
1209 			if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) ||
1210 			    rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1211 				rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
1212 			else
1213 				break;
1214 		}
1215 	}
1216 }
1217 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus);
1218 
1219 static int rt2800_check_hung(struct data_queue *queue)
1220 {
1221 	unsigned int cur_idx = rt2800_drv_get_dma_done(queue);
1222 
1223 	if (queue->wd_idx != cur_idx)
1224 		queue->wd_count = 0;
1225 	else
1226 		queue->wd_count++;
1227 
1228 	return queue->wd_count > 16;
1229 }
1230 
1231 static void rt2800_update_survey(struct rt2x00_dev *rt2x00dev)
1232 {
1233 	struct ieee80211_channel *chan = rt2x00dev->hw->conf.chandef.chan;
1234 	struct rt2x00_chan_survey *chan_survey =
1235 		   &rt2x00dev->chan_survey[chan->hw_value];
1236 
1237 	chan_survey->time_idle += rt2800_register_read(rt2x00dev, CH_IDLE_STA);
1238 	chan_survey->time_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA);
1239 	chan_survey->time_ext_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
1240 }
1241 
1242 void rt2800_watchdog(struct rt2x00_dev *rt2x00dev)
1243 {
1244 	struct data_queue *queue;
1245 	bool hung_tx = false;
1246 	bool hung_rx = false;
1247 
1248 	if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags))
1249 		return;
1250 
1251 	rt2800_update_survey(rt2x00dev);
1252 
1253 	queue_for_each(rt2x00dev, queue) {
1254 		switch (queue->qid) {
1255 		case QID_AC_VO:
1256 		case QID_AC_VI:
1257 		case QID_AC_BE:
1258 		case QID_AC_BK:
1259 		case QID_MGMT:
1260 			if (rt2x00queue_empty(queue))
1261 				continue;
1262 			hung_tx = rt2800_check_hung(queue);
1263 			break;
1264 		case QID_RX:
1265 			/* For station mode we should reactive at least
1266 			 * beacons. TODO: need to find good way detect
1267 			 * RX hung for AP mode.
1268 			 */
1269 			if (rt2x00dev->intf_sta_count == 0)
1270 				continue;
1271 			hung_rx = rt2800_check_hung(queue);
1272 			break;
1273 		default:
1274 			break;
1275 		}
1276 	}
1277 
1278 	if (hung_tx)
1279 		rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n");
1280 
1281 	if (hung_rx)
1282 		rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n");
1283 
1284 	if (hung_tx || hung_rx)
1285 		ieee80211_restart_hw(rt2x00dev->hw);
1286 }
1287 EXPORT_SYMBOL_GPL(rt2800_watchdog);
1288 
1289 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1290 					  unsigned int index)
1291 {
1292 	return HW_BEACON_BASE(index);
1293 }
1294 
1295 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1296 					  unsigned int index)
1297 {
1298 	return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1299 }
1300 
1301 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1302 {
1303 	struct data_queue *queue = rt2x00dev->bcn;
1304 	struct queue_entry *entry;
1305 	int i, bcn_num = 0;
1306 	u64 off, reg = 0;
1307 	u32 bssid_dw1;
1308 
1309 	/*
1310 	 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
1311 	 */
1312 	for (i = 0; i < queue->limit; i++) {
1313 		entry = &queue->entries[i];
1314 		if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1315 			continue;
1316 		off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1317 		reg |= off << (8 * bcn_num);
1318 		bcn_num++;
1319 	}
1320 
1321 	rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1322 	rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1323 
1324 	/*
1325 	 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
1326 	 */
1327 	bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1328 	rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
1329 			   bcn_num > 0 ? bcn_num - 1 : 0);
1330 	rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1331 }
1332 
1333 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1334 {
1335 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1336 	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1337 	unsigned int beacon_base;
1338 	unsigned int padding_len;
1339 	u32 orig_reg, reg;
1340 	const int txwi_desc_size = entry->queue->winfo_size;
1341 
1342 	/*
1343 	 * Disable beaconing while we are reloading the beacon data,
1344 	 * otherwise we might be sending out invalid data.
1345 	 */
1346 	reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1347 	orig_reg = reg;
1348 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1349 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1350 
1351 	/*
1352 	 * Add space for the TXWI in front of the skb.
1353 	 */
1354 	memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1355 
1356 	/*
1357 	 * Register descriptor details in skb frame descriptor.
1358 	 */
1359 	skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1360 	skbdesc->desc = entry->skb->data;
1361 	skbdesc->desc_len = txwi_desc_size;
1362 
1363 	/*
1364 	 * Add the TXWI for the beacon to the skb.
1365 	 */
1366 	rt2800_write_tx_data(entry, txdesc);
1367 
1368 	/*
1369 	 * Dump beacon to userspace through debugfs.
1370 	 */
1371 	rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1372 
1373 	/*
1374 	 * Write entire beacon with TXWI and padding to register.
1375 	 */
1376 	padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1377 	if (padding_len && skb_pad(entry->skb, padding_len)) {
1378 		rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1379 		/* skb freed by skb_pad() on failure */
1380 		entry->skb = NULL;
1381 		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1382 		return;
1383 	}
1384 
1385 	beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1386 
1387 	rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1388 				   entry->skb->len + padding_len);
1389 	__set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1390 
1391 	/*
1392 	 * Change global beacons settings.
1393 	 */
1394 	rt2800_update_beacons_setup(rt2x00dev);
1395 
1396 	/*
1397 	 * Restore beaconing state.
1398 	 */
1399 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1400 
1401 	/*
1402 	 * Clean up beacon skb.
1403 	 */
1404 	dev_kfree_skb_any(entry->skb);
1405 	entry->skb = NULL;
1406 }
1407 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1408 
1409 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1410 						unsigned int index)
1411 {
1412 	int i;
1413 	const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1414 	unsigned int beacon_base;
1415 
1416 	beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1417 
1418 	/*
1419 	 * For the Beacon base registers we only need to clear
1420 	 * the whole TXWI which (when set to 0) will invalidate
1421 	 * the entire beacon.
1422 	 */
1423 	for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1424 		rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1425 }
1426 
1427 void rt2800_clear_beacon(struct queue_entry *entry)
1428 {
1429 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1430 	u32 orig_reg, reg;
1431 
1432 	/*
1433 	 * Disable beaconing while we are reloading the beacon data,
1434 	 * otherwise we might be sending out invalid data.
1435 	 */
1436 	orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1437 	reg = orig_reg;
1438 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1439 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1440 
1441 	/*
1442 	 * Clear beacon.
1443 	 */
1444 	rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1445 	__clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1446 
1447 	/*
1448 	 * Change global beacons settings.
1449 	 */
1450 	rt2800_update_beacons_setup(rt2x00dev);
1451 	/*
1452 	 * Restore beaconing state.
1453 	 */
1454 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1455 }
1456 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1457 
1458 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1459 const struct rt2x00debug rt2800_rt2x00debug = {
1460 	.owner	= THIS_MODULE,
1461 	.csr	= {
1462 		.read		= rt2800_register_read,
1463 		.write		= rt2800_register_write,
1464 		.flags		= RT2X00DEBUGFS_OFFSET,
1465 		.word_base	= CSR_REG_BASE,
1466 		.word_size	= sizeof(u32),
1467 		.word_count	= CSR_REG_SIZE / sizeof(u32),
1468 	},
1469 	.eeprom	= {
1470 		/* NOTE: The local EEPROM access functions can't
1471 		 * be used here, use the generic versions instead.
1472 		 */
1473 		.read		= rt2x00_eeprom_read,
1474 		.write		= rt2x00_eeprom_write,
1475 		.word_base	= EEPROM_BASE,
1476 		.word_size	= sizeof(u16),
1477 		.word_count	= EEPROM_SIZE / sizeof(u16),
1478 	},
1479 	.bbp	= {
1480 		.read		= rt2800_bbp_read,
1481 		.write		= rt2800_bbp_write,
1482 		.word_base	= BBP_BASE,
1483 		.word_size	= sizeof(u8),
1484 		.word_count	= BBP_SIZE / sizeof(u8),
1485 	},
1486 	.rf	= {
1487 		.read		= rt2x00_rf_read,
1488 		.write		= rt2800_rf_write,
1489 		.word_base	= RF_BASE,
1490 		.word_size	= sizeof(u32),
1491 		.word_count	= RF_SIZE / sizeof(u32),
1492 	},
1493 	.rfcsr	= {
1494 		.read		= rt2800_rfcsr_read,
1495 		.write		= rt2800_rfcsr_write,
1496 		.word_base	= RFCSR_BASE,
1497 		.word_size	= sizeof(u8),
1498 		.word_count	= RFCSR_SIZE / sizeof(u8),
1499 	},
1500 };
1501 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1502 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1503 
1504 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1505 {
1506 	u32 reg;
1507 
1508 	if (rt2x00_rt(rt2x00dev, RT3290)) {
1509 		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1510 		return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1511 	} else {
1512 		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1513 		return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1514 	}
1515 }
1516 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1517 
1518 #ifdef CONFIG_RT2X00_LIB_LEDS
1519 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1520 				  enum led_brightness brightness)
1521 {
1522 	struct rt2x00_led *led =
1523 	    container_of(led_cdev, struct rt2x00_led, led_dev);
1524 	unsigned int enabled = brightness != LED_OFF;
1525 	unsigned int bg_mode =
1526 	    (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1527 	unsigned int polarity =
1528 		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1529 				   EEPROM_FREQ_LED_POLARITY);
1530 	unsigned int ledmode =
1531 		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1532 				   EEPROM_FREQ_LED_MODE);
1533 	u32 reg;
1534 
1535 	/* Check for SoC (SOC devices don't support MCU requests) */
1536 	if (rt2x00_is_soc(led->rt2x00dev)) {
1537 		reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1538 
1539 		/* Set LED Polarity */
1540 		rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1541 
1542 		/* Set LED Mode */
1543 		if (led->type == LED_TYPE_RADIO) {
1544 			rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1545 					   enabled ? 3 : 0);
1546 		} else if (led->type == LED_TYPE_ASSOC) {
1547 			rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1548 					   enabled ? 3 : 0);
1549 		} else if (led->type == LED_TYPE_QUALITY) {
1550 			rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1551 					   enabled ? 3 : 0);
1552 		}
1553 
1554 		rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1555 
1556 	} else {
1557 		if (led->type == LED_TYPE_RADIO) {
1558 			rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1559 					      enabled ? 0x20 : 0);
1560 		} else if (led->type == LED_TYPE_ASSOC) {
1561 			rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1562 					      enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1563 		} else if (led->type == LED_TYPE_QUALITY) {
1564 			/*
1565 			 * The brightness is divided into 6 levels (0 - 5),
1566 			 * The specs tell us the following levels:
1567 			 *	0, 1 ,3, 7, 15, 31
1568 			 * to determine the level in a simple way we can simply
1569 			 * work with bitshifting:
1570 			 *	(1 << level) - 1
1571 			 */
1572 			rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1573 					      (1 << brightness / (LED_FULL / 6)) - 1,
1574 					      polarity);
1575 		}
1576 	}
1577 }
1578 
1579 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1580 		     struct rt2x00_led *led, enum led_type type)
1581 {
1582 	led->rt2x00dev = rt2x00dev;
1583 	led->type = type;
1584 	led->led_dev.brightness_set = rt2800_brightness_set;
1585 	led->flags = LED_INITIALIZED;
1586 }
1587 #endif /* CONFIG_RT2X00_LIB_LEDS */
1588 
1589 /*
1590  * Configuration handlers.
1591  */
1592 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1593 			       const u8 *address,
1594 			       int wcid)
1595 {
1596 	struct mac_wcid_entry wcid_entry;
1597 	u32 offset;
1598 
1599 	offset = MAC_WCID_ENTRY(wcid);
1600 
1601 	memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1602 	if (address)
1603 		memcpy(wcid_entry.mac, address, ETH_ALEN);
1604 
1605 	rt2800_register_multiwrite(rt2x00dev, offset,
1606 				      &wcid_entry, sizeof(wcid_entry));
1607 }
1608 
1609 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1610 {
1611 	u32 offset;
1612 	offset = MAC_WCID_ATTR_ENTRY(wcid);
1613 	rt2800_register_write(rt2x00dev, offset, 0);
1614 }
1615 
1616 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1617 					   int wcid, u32 bssidx)
1618 {
1619 	u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1620 	u32 reg;
1621 
1622 	/*
1623 	 * The BSS Idx numbers is split in a main value of 3 bits,
1624 	 * and a extended field for adding one additional bit to the value.
1625 	 */
1626 	reg = rt2800_register_read(rt2x00dev, offset);
1627 	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1628 	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1629 			   (bssidx & 0x8) >> 3);
1630 	rt2800_register_write(rt2x00dev, offset, reg);
1631 }
1632 
1633 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1634 					   struct rt2x00lib_crypto *crypto,
1635 					   struct ieee80211_key_conf *key)
1636 {
1637 	struct mac_iveiv_entry iveiv_entry;
1638 	u32 offset;
1639 	u32 reg;
1640 
1641 	offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1642 
1643 	if (crypto->cmd == SET_KEY) {
1644 		reg = rt2800_register_read(rt2x00dev, offset);
1645 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1646 				   !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1647 		/*
1648 		 * Both the cipher as the BSS Idx numbers are split in a main
1649 		 * value of 3 bits, and a extended field for adding one additional
1650 		 * bit to the value.
1651 		 */
1652 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1653 				   (crypto->cipher & 0x7));
1654 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1655 				   (crypto->cipher & 0x8) >> 3);
1656 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1657 		rt2800_register_write(rt2x00dev, offset, reg);
1658 	} else {
1659 		/* Delete the cipher without touching the bssidx */
1660 		reg = rt2800_register_read(rt2x00dev, offset);
1661 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1662 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1663 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1664 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1665 		rt2800_register_write(rt2x00dev, offset, reg);
1666 	}
1667 
1668 	if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
1669 		return;
1670 
1671 	offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1672 
1673 	memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1674 	if ((crypto->cipher == CIPHER_TKIP) ||
1675 	    (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1676 	    (crypto->cipher == CIPHER_AES))
1677 		iveiv_entry.iv[3] |= 0x20;
1678 	iveiv_entry.iv[3] |= key->keyidx << 6;
1679 	rt2800_register_multiwrite(rt2x00dev, offset,
1680 				   &iveiv_entry, sizeof(iveiv_entry));
1681 }
1682 
1683 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1684 			     struct rt2x00lib_crypto *crypto,
1685 			     struct ieee80211_key_conf *key)
1686 {
1687 	struct hw_key_entry key_entry;
1688 	struct rt2x00_field32 field;
1689 	u32 offset;
1690 	u32 reg;
1691 
1692 	if (crypto->cmd == SET_KEY) {
1693 		key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1694 
1695 		memcpy(key_entry.key, crypto->key,
1696 		       sizeof(key_entry.key));
1697 		memcpy(key_entry.tx_mic, crypto->tx_mic,
1698 		       sizeof(key_entry.tx_mic));
1699 		memcpy(key_entry.rx_mic, crypto->rx_mic,
1700 		       sizeof(key_entry.rx_mic));
1701 
1702 		offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1703 		rt2800_register_multiwrite(rt2x00dev, offset,
1704 					      &key_entry, sizeof(key_entry));
1705 	}
1706 
1707 	/*
1708 	 * The cipher types are stored over multiple registers
1709 	 * starting with SHARED_KEY_MODE_BASE each word will have
1710 	 * 32 bits and contains the cipher types for 2 bssidx each.
1711 	 * Using the correct defines correctly will cause overhead,
1712 	 * so just calculate the correct offset.
1713 	 */
1714 	field.bit_offset = 4 * (key->hw_key_idx % 8);
1715 	field.bit_mask = 0x7 << field.bit_offset;
1716 
1717 	offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1718 
1719 	reg = rt2800_register_read(rt2x00dev, offset);
1720 	rt2x00_set_field32(&reg, field,
1721 			   (crypto->cmd == SET_KEY) * crypto->cipher);
1722 	rt2800_register_write(rt2x00dev, offset, reg);
1723 
1724 	/*
1725 	 * Update WCID information
1726 	 */
1727 	rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1728 	rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1729 				       crypto->bssidx);
1730 	rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1731 
1732 	return 0;
1733 }
1734 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1735 
1736 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1737 			       struct rt2x00lib_crypto *crypto,
1738 			       struct ieee80211_key_conf *key)
1739 {
1740 	struct hw_key_entry key_entry;
1741 	u32 offset;
1742 
1743 	if (crypto->cmd == SET_KEY) {
1744 		/*
1745 		 * Allow key configuration only for STAs that are
1746 		 * known by the hw.
1747 		 */
1748 		if (crypto->wcid > WCID_END)
1749 			return -ENOSPC;
1750 		key->hw_key_idx = crypto->wcid;
1751 
1752 		memcpy(key_entry.key, crypto->key,
1753 		       sizeof(key_entry.key));
1754 		memcpy(key_entry.tx_mic, crypto->tx_mic,
1755 		       sizeof(key_entry.tx_mic));
1756 		memcpy(key_entry.rx_mic, crypto->rx_mic,
1757 		       sizeof(key_entry.rx_mic));
1758 
1759 		offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1760 		rt2800_register_multiwrite(rt2x00dev, offset,
1761 					      &key_entry, sizeof(key_entry));
1762 	}
1763 
1764 	/*
1765 	 * Update WCID information
1766 	 */
1767 	rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1768 
1769 	return 0;
1770 }
1771 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1772 
1773 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1774 {
1775 	u8 i, max_psdu;
1776 	u32 reg;
1777 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1778 
1779 	for (i = 0; i < 3; i++)
1780 		if (drv_data->ampdu_factor_cnt[i] > 0)
1781 			break;
1782 
1783 	max_psdu = min(drv_data->max_psdu, i);
1784 
1785 	reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1786 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1787 	rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1788 }
1789 
1790 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1791 		   struct ieee80211_sta *sta)
1792 {
1793 	struct rt2x00_dev *rt2x00dev = hw->priv;
1794 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1795 	struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1796 	int wcid;
1797 
1798 	/*
1799 	 * Limit global maximum TX AMPDU length to smallest value of all
1800 	 * connected stations. In AP mode this can be suboptimal, but we
1801 	 * do not have a choice if some connected STA is not capable to
1802 	 * receive the same amount of data like the others.
1803 	 */
1804 	if (sta->deflink.ht_cap.ht_supported) {
1805 		drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]++;
1806 		rt2800_set_max_psdu_len(rt2x00dev);
1807 	}
1808 
1809 	/*
1810 	 * Search for the first free WCID entry and return the corresponding
1811 	 * index.
1812 	 */
1813 	wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
1814 
1815 	/*
1816 	 * Store selected wcid even if it is invalid so that we can
1817 	 * later decide if the STA is uploaded into the hw.
1818 	 */
1819 	sta_priv->wcid = wcid;
1820 
1821 	/*
1822 	 * No space left in the device, however, we can still communicate
1823 	 * with the STA -> No error.
1824 	 */
1825 	if (wcid > WCID_END)
1826 		return 0;
1827 
1828 	__set_bit(wcid - WCID_START, drv_data->sta_ids);
1829 	drv_data->wcid_to_sta[wcid - WCID_START] = sta;
1830 
1831 	/*
1832 	 * Clean up WCID attributes and write STA address to the device.
1833 	 */
1834 	rt2800_delete_wcid_attr(rt2x00dev, wcid);
1835 	rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1836 	rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1837 				       rt2x00lib_get_bssidx(rt2x00dev, vif));
1838 	return 0;
1839 }
1840 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1841 
1842 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1843 		      struct ieee80211_sta *sta)
1844 {
1845 	struct rt2x00_dev *rt2x00dev = hw->priv;
1846 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1847 	struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1848 	int wcid = sta_priv->wcid;
1849 
1850 	if (sta->deflink.ht_cap.ht_supported) {
1851 		drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]--;
1852 		rt2800_set_max_psdu_len(rt2x00dev);
1853 	}
1854 
1855 	if (wcid > WCID_END)
1856 		return 0;
1857 	/*
1858 	 * Remove WCID entry, no need to clean the attributes as they will
1859 	 * get renewed when the WCID is reused.
1860 	 */
1861 	rt2800_config_wcid(rt2x00dev, NULL, wcid);
1862 	drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1863 	__clear_bit(wcid - WCID_START, drv_data->sta_ids);
1864 
1865 	return 0;
1866 }
1867 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1868 
1869 void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev)
1870 {
1871 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1872 	struct data_queue *queue = rt2x00dev->bcn;
1873 	struct queue_entry *entry;
1874 	int i, wcid;
1875 
1876 	for (wcid = WCID_START; wcid < WCID_END; wcid++) {
1877 		drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1878 		__clear_bit(wcid - WCID_START, drv_data->sta_ids);
1879 	}
1880 
1881 	for (i = 0; i < queue->limit; i++) {
1882 		entry = &queue->entries[i];
1883 		clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags);
1884 	}
1885 }
1886 EXPORT_SYMBOL_GPL(rt2800_pre_reset_hw);
1887 
1888 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1889 			  const unsigned int filter_flags)
1890 {
1891 	u32 reg;
1892 
1893 	/*
1894 	 * Start configuration steps.
1895 	 * Note that the version error will always be dropped
1896 	 * and broadcast frames will always be accepted since
1897 	 * there is no filter for it at this time.
1898 	 */
1899 	reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1900 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1901 			   !(filter_flags & FIF_FCSFAIL));
1902 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1903 			   !(filter_flags & FIF_PLCPFAIL));
1904 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1905 			   !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
1906 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1907 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1908 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1909 			   !(filter_flags & FIF_ALLMULTI));
1910 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1911 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1912 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1913 			   !(filter_flags & FIF_CONTROL));
1914 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1915 			   !(filter_flags & FIF_CONTROL));
1916 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1917 			   !(filter_flags & FIF_CONTROL));
1918 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1919 			   !(filter_flags & FIF_CONTROL));
1920 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1921 			   !(filter_flags & FIF_CONTROL));
1922 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1923 			   !(filter_flags & FIF_PSPOLL));
1924 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1925 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1926 			   !(filter_flags & FIF_CONTROL));
1927 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1928 			   !(filter_flags & FIF_CONTROL));
1929 	rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1930 }
1931 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1932 
1933 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1934 			struct rt2x00intf_conf *conf, const unsigned int flags)
1935 {
1936 	u32 reg;
1937 	bool update_bssid = false;
1938 
1939 	if (flags & CONFIG_UPDATE_TYPE) {
1940 		/*
1941 		 * Enable synchronisation.
1942 		 */
1943 		reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1944 		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1945 		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1946 
1947 		if (conf->sync == TSF_SYNC_AP_NONE) {
1948 			/*
1949 			 * Tune beacon queue transmit parameters for AP mode
1950 			 */
1951 			reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1952 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1953 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1954 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1955 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1956 			rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1957 		} else {
1958 			reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1959 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1960 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1961 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1962 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1963 			rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1964 		}
1965 	}
1966 
1967 	if (flags & CONFIG_UPDATE_MAC) {
1968 		if (flags & CONFIG_UPDATE_TYPE &&
1969 		    conf->sync == TSF_SYNC_AP_NONE) {
1970 			/*
1971 			 * The BSSID register has to be set to our own mac
1972 			 * address in AP mode.
1973 			 */
1974 			memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1975 			update_bssid = true;
1976 		}
1977 
1978 		if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1979 			reg = le32_to_cpu(conf->mac[1]);
1980 			rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1981 			conf->mac[1] = cpu_to_le32(reg);
1982 		}
1983 
1984 		rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1985 					      conf->mac, sizeof(conf->mac));
1986 	}
1987 
1988 	if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1989 		if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1990 			reg = le32_to_cpu(conf->bssid[1]);
1991 			rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1992 			rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
1993 			conf->bssid[1] = cpu_to_le32(reg);
1994 		}
1995 
1996 		rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1997 					      conf->bssid, sizeof(conf->bssid));
1998 	}
1999 }
2000 EXPORT_SYMBOL_GPL(rt2800_config_intf);
2001 
2002 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
2003 				    struct rt2x00lib_erp *erp)
2004 {
2005 	bool any_sta_nongf = !!(erp->ht_opmode &
2006 				IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
2007 	u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
2008 	u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
2009 	u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
2010 	u32 reg;
2011 
2012 	/* default protection rate for HT20: OFDM 24M */
2013 	mm20_rate = gf20_rate = 0x4004;
2014 
2015 	/* default protection rate for HT40: duplicate OFDM 24M */
2016 	mm40_rate = gf40_rate = 0x4084;
2017 
2018 	switch (protection) {
2019 	case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
2020 		/*
2021 		 * All STAs in this BSS are HT20/40 but there might be
2022 		 * STAs not supporting greenfield mode.
2023 		 * => Disable protection for HT transmissions.
2024 		 */
2025 		mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
2026 
2027 		break;
2028 	case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2029 		/*
2030 		 * All STAs in this BSS are HT20 or HT20/40 but there
2031 		 * might be STAs not supporting greenfield mode.
2032 		 * => Protect all HT40 transmissions.
2033 		 */
2034 		mm20_mode = gf20_mode = 0;
2035 		mm40_mode = gf40_mode = 1;
2036 
2037 		break;
2038 	case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
2039 		/*
2040 		 * Nonmember protection:
2041 		 * According to 802.11n we _should_ protect all
2042 		 * HT transmissions (but we don't have to).
2043 		 *
2044 		 * But if cts_protection is enabled we _shall_ protect
2045 		 * all HT transmissions using a CCK rate.
2046 		 *
2047 		 * And if any station is non GF we _shall_ protect
2048 		 * GF transmissions.
2049 		 *
2050 		 * We decide to protect everything
2051 		 * -> fall through to mixed mode.
2052 		 */
2053 	case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2054 		/*
2055 		 * Legacy STAs are present
2056 		 * => Protect all HT transmissions.
2057 		 */
2058 		mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
2059 
2060 		/*
2061 		 * If erp protection is needed we have to protect HT
2062 		 * transmissions with CCK 11M long preamble.
2063 		 */
2064 		if (erp->cts_protection) {
2065 			/* don't duplicate RTS/CTS in CCK mode */
2066 			mm20_rate = mm40_rate = 0x0003;
2067 			gf20_rate = gf40_rate = 0x0003;
2068 		}
2069 		break;
2070 	}
2071 
2072 	/* check for STAs not supporting greenfield mode */
2073 	if (any_sta_nongf)
2074 		gf20_mode = gf40_mode = 1;
2075 
2076 	/* Update HT protection config */
2077 	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
2078 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
2079 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
2080 	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2081 
2082 	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
2083 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
2084 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
2085 	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2086 
2087 	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
2088 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
2089 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
2090 	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2091 
2092 	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
2093 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
2094 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
2095 	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2096 }
2097 
2098 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
2099 		       u32 changed)
2100 {
2101 	u32 reg;
2102 
2103 	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2104 		reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
2105 		rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
2106 				   !!erp->short_preamble);
2107 		rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2108 	}
2109 
2110 	if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2111 		reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
2112 		rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
2113 				   erp->cts_protection ? 2 : 0);
2114 		rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2115 	}
2116 
2117 	if (changed & BSS_CHANGED_BASIC_RATES) {
2118 		rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
2119 				      0xff0 | erp->basic_rates);
2120 		rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2121 	}
2122 
2123 	if (changed & BSS_CHANGED_ERP_SLOT) {
2124 		reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
2125 		rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
2126 				   erp->slot_time);
2127 		rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2128 
2129 		reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
2130 		rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
2131 		rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2132 	}
2133 
2134 	if (changed & BSS_CHANGED_BEACON_INT) {
2135 		reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
2136 		rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
2137 				   erp->beacon_int * 16);
2138 		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2139 	}
2140 
2141 	if (changed & BSS_CHANGED_HT)
2142 		rt2800_config_ht_opmode(rt2x00dev, erp);
2143 }
2144 EXPORT_SYMBOL_GPL(rt2800_config_erp);
2145 
2146 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
2147 {
2148 	u32 reg;
2149 	u16 eeprom;
2150 	u8 led_ctrl, led_g_mode, led_r_mode;
2151 
2152 	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
2153 	if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
2154 		rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
2155 		rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
2156 	} else {
2157 		rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
2158 		rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
2159 	}
2160 	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2161 
2162 	reg = rt2800_register_read(rt2x00dev, LED_CFG);
2163 	led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
2164 	led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
2165 	if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
2166 	    led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
2167 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
2168 		led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
2169 		if (led_ctrl == 0 || led_ctrl > 0x40) {
2170 			rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
2171 			rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
2172 			rt2800_register_write(rt2x00dev, LED_CFG, reg);
2173 		} else {
2174 			rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
2175 					   (led_g_mode << 2) | led_r_mode, 1);
2176 		}
2177 	}
2178 }
2179 
2180 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
2181 				     enum antenna ant)
2182 {
2183 	u32 reg;
2184 	u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
2185 	u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
2186 
2187 	if (rt2x00_is_pci(rt2x00dev)) {
2188 		reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
2189 		rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
2190 		rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
2191 	} else if (rt2x00_is_usb(rt2x00dev))
2192 		rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
2193 				   eesk_pin, 0);
2194 
2195 	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2196 	rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
2197 	rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
2198 	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2199 }
2200 
2201 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
2202 {
2203 	u8 r1;
2204 	u8 r3;
2205 	u16 eeprom;
2206 
2207 	r1 = rt2800_bbp_read(rt2x00dev, 1);
2208 	r3 = rt2800_bbp_read(rt2x00dev, 3);
2209 
2210 	if (rt2x00_rt(rt2x00dev, RT3572) &&
2211 	    rt2x00_has_cap_bt_coexist(rt2x00dev))
2212 		rt2800_config_3572bt_ant(rt2x00dev);
2213 
2214 	/*
2215 	 * Configure the TX antenna.
2216 	 */
2217 	switch (ant->tx_chain_num) {
2218 	case 1:
2219 		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
2220 		break;
2221 	case 2:
2222 		if (rt2x00_rt(rt2x00dev, RT3572) &&
2223 		    rt2x00_has_cap_bt_coexist(rt2x00dev))
2224 			rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
2225 		else
2226 			rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2227 		break;
2228 	case 3:
2229 		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2230 		break;
2231 	}
2232 
2233 	/*
2234 	 * Configure the RX antenna.
2235 	 */
2236 	switch (ant->rx_chain_num) {
2237 	case 1:
2238 		if (rt2x00_rt(rt2x00dev, RT3070) ||
2239 		    rt2x00_rt(rt2x00dev, RT3090) ||
2240 		    rt2x00_rt(rt2x00dev, RT3352) ||
2241 		    rt2x00_rt(rt2x00dev, RT3390)) {
2242 			eeprom = rt2800_eeprom_read(rt2x00dev,
2243 						    EEPROM_NIC_CONF1);
2244 			if (rt2x00_get_field16(eeprom,
2245 						EEPROM_NIC_CONF1_ANT_DIVERSITY))
2246 				rt2800_set_ant_diversity(rt2x00dev,
2247 						rt2x00dev->default_ant.rx);
2248 		}
2249 		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
2250 		break;
2251 	case 2:
2252 		if (rt2x00_rt(rt2x00dev, RT3572) &&
2253 		    rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2254 			rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
2255 			rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
2256 				rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2257 			rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2258 		} else {
2259 			rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
2260 		}
2261 		break;
2262 	case 3:
2263 		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
2264 		break;
2265 	}
2266 
2267 	rt2800_bbp_write(rt2x00dev, 3, r3);
2268 	rt2800_bbp_write(rt2x00dev, 1, r1);
2269 
2270 	if (rt2x00_rt(rt2x00dev, RT3593) ||
2271 	    rt2x00_rt(rt2x00dev, RT3883)) {
2272 		if (ant->rx_chain_num == 1)
2273 			rt2800_bbp_write(rt2x00dev, 86, 0x00);
2274 		else
2275 			rt2800_bbp_write(rt2x00dev, 86, 0x46);
2276 	}
2277 }
2278 EXPORT_SYMBOL_GPL(rt2800_config_ant);
2279 
2280 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2281 				   struct rt2x00lib_conf *libconf)
2282 {
2283 	u16 eeprom;
2284 	short lna_gain;
2285 
2286 	if (libconf->rf.channel <= 14) {
2287 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2288 		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
2289 	} else if (libconf->rf.channel <= 64) {
2290 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2291 		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
2292 	} else if (libconf->rf.channel <= 128) {
2293 		if (rt2x00_rt(rt2x00dev, RT3593) ||
2294 		    rt2x00_rt(rt2x00dev, RT3883)) {
2295 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2296 			lna_gain = rt2x00_get_field16(eeprom,
2297 						      EEPROM_EXT_LNA2_A1);
2298 		} else {
2299 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2300 			lna_gain = rt2x00_get_field16(eeprom,
2301 						      EEPROM_RSSI_BG2_LNA_A1);
2302 		}
2303 	} else {
2304 		if (rt2x00_rt(rt2x00dev, RT3593) ||
2305 		    rt2x00_rt(rt2x00dev, RT3883)) {
2306 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2307 			lna_gain = rt2x00_get_field16(eeprom,
2308 						      EEPROM_EXT_LNA2_A2);
2309 		} else {
2310 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2311 			lna_gain = rt2x00_get_field16(eeprom,
2312 						      EEPROM_RSSI_A2_LNA_A2);
2313 		}
2314 	}
2315 
2316 	rt2x00dev->lna_gain = lna_gain;
2317 }
2318 
2319 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2320 {
2321 	return clk_get_rate(rt2x00dev->clk) == 20000000;
2322 }
2323 
2324 #define FREQ_OFFSET_BOUND	0x5f
2325 
2326 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2327 {
2328 	u8 freq_offset, prev_freq_offset;
2329 	u8 rfcsr, prev_rfcsr;
2330 
2331 	freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2332 	freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2333 
2334 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2335 	prev_rfcsr = rfcsr;
2336 
2337 	rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2338 	if (rfcsr == prev_rfcsr)
2339 		return;
2340 
2341 	if (rt2x00_is_usb(rt2x00dev)) {
2342 		rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2343 				   freq_offset, prev_rfcsr);
2344 		return;
2345 	}
2346 
2347 	prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
2348 	while (prev_freq_offset != freq_offset) {
2349 		if (prev_freq_offset < freq_offset)
2350 			prev_freq_offset++;
2351 		else
2352 			prev_freq_offset--;
2353 
2354 		rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2355 		rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2356 
2357 		usleep_range(1000, 1500);
2358 	}
2359 }
2360 
2361 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2362 					 struct ieee80211_conf *conf,
2363 					 struct rf_channel *rf,
2364 					 struct channel_info *info)
2365 {
2366 	rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2367 
2368 	if (rt2x00dev->default_ant.tx_chain_num == 1)
2369 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2370 
2371 	if (rt2x00dev->default_ant.rx_chain_num == 1) {
2372 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2373 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2374 	} else if (rt2x00dev->default_ant.rx_chain_num == 2)
2375 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2376 
2377 	if (rf->channel > 14) {
2378 		/*
2379 		 * When TX power is below 0, we should increase it by 7 to
2380 		 * make it a positive value (Minimum value is -7).
2381 		 * However this means that values between 0 and 7 have
2382 		 * double meaning, and we should set a 7DBm boost flag.
2383 		 */
2384 		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
2385 				   (info->default_power1 >= 0));
2386 
2387 		if (info->default_power1 < 0)
2388 			info->default_power1 += 7;
2389 
2390 		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
2391 
2392 		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
2393 				   (info->default_power2 >= 0));
2394 
2395 		if (info->default_power2 < 0)
2396 			info->default_power2 += 7;
2397 
2398 		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
2399 	} else {
2400 		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2401 		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
2402 	}
2403 
2404 	rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2405 
2406 	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2407 	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2408 	rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2409 	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2410 
2411 	udelay(200);
2412 
2413 	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2414 	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2415 	rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2416 	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2417 
2418 	udelay(200);
2419 
2420 	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2421 	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2422 	rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2423 	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2424 }
2425 
2426 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2427 					 struct ieee80211_conf *conf,
2428 					 struct rf_channel *rf,
2429 					 struct channel_info *info)
2430 {
2431 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2432 	u8 rfcsr, calib_tx, calib_rx;
2433 
2434 	rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2435 
2436 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2437 	rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2438 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2439 
2440 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2441 	rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2442 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2443 
2444 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2445 	rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2446 	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2447 
2448 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2449 	rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2450 	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2451 
2452 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2453 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2454 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2455 			  rt2x00dev->default_ant.rx_chain_num <= 1);
2456 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2457 			  rt2x00dev->default_ant.rx_chain_num <= 2);
2458 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2459 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2460 			  rt2x00dev->default_ant.tx_chain_num <= 1);
2461 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2462 			  rt2x00dev->default_ant.tx_chain_num <= 2);
2463 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2464 
2465 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2466 	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2467 	rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2468 
2469 	if (rt2x00_rt(rt2x00dev, RT3390)) {
2470 		calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2471 		calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2472 	} else {
2473 		if (conf_is_ht40(conf)) {
2474 			calib_tx = drv_data->calibration_bw40;
2475 			calib_rx = drv_data->calibration_bw40;
2476 		} else {
2477 			calib_tx = drv_data->calibration_bw20;
2478 			calib_rx = drv_data->calibration_bw20;
2479 		}
2480 	}
2481 
2482 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2483 	rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2484 	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2485 
2486 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2487 	rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2488 	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2489 
2490 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2491 	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2492 	rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2493 
2494 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2495 	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2496 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2497 
2498 	usleep_range(1000, 1500);
2499 
2500 	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2501 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2502 }
2503 
2504 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2505 					 struct ieee80211_conf *conf,
2506 					 struct rf_channel *rf,
2507 					 struct channel_info *info)
2508 {
2509 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2510 	u8 rfcsr;
2511 	u32 reg;
2512 
2513 	if (rf->channel <= 14) {
2514 		rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2515 		rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2516 	} else {
2517 		rt2800_bbp_write(rt2x00dev, 25, 0x09);
2518 		rt2800_bbp_write(rt2x00dev, 26, 0xff);
2519 	}
2520 
2521 	rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2522 	rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2523 
2524 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2525 	rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2526 	if (rf->channel <= 14)
2527 		rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2528 	else
2529 		rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2530 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2531 
2532 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2533 	if (rf->channel <= 14)
2534 		rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2535 	else
2536 		rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2537 	rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2538 
2539 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2540 	if (rf->channel <= 14) {
2541 		rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2542 		rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2543 				  info->default_power1);
2544 	} else {
2545 		rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2546 		rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2547 				(info->default_power1 & 0x3) |
2548 				((info->default_power1 & 0xC) << 1));
2549 	}
2550 	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2551 
2552 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2553 	if (rf->channel <= 14) {
2554 		rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2555 		rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2556 				  info->default_power2);
2557 	} else {
2558 		rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2559 		rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2560 				(info->default_power2 & 0x3) |
2561 				((info->default_power2 & 0xC) << 1));
2562 	}
2563 	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2564 
2565 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2566 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2567 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2568 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2569 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2570 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2571 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2572 	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2573 		if (rf->channel <= 14) {
2574 			rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2575 			rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2576 		}
2577 		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2578 		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2579 	} else {
2580 		switch (rt2x00dev->default_ant.tx_chain_num) {
2581 		case 1:
2582 			rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2583 			fallthrough;
2584 		case 2:
2585 			rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2586 			break;
2587 		}
2588 
2589 		switch (rt2x00dev->default_ant.rx_chain_num) {
2590 		case 1:
2591 			rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2592 			fallthrough;
2593 		case 2:
2594 			rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2595 			break;
2596 		}
2597 	}
2598 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2599 
2600 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2601 	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2602 	rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2603 
2604 	if (conf_is_ht40(conf)) {
2605 		rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2606 		rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2607 	} else {
2608 		rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2609 		rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2610 	}
2611 
2612 	if (rf->channel <= 14) {
2613 		rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2614 		rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2615 		rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2616 		rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2617 		rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2618 		rfcsr = 0x4c;
2619 		rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2620 				  drv_data->txmixer_gain_24g);
2621 		rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2622 		rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2623 		rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2624 		rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2625 		rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2626 		rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2627 		rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2628 		rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2629 	} else {
2630 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2631 		rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2632 		rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2633 		rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2634 		rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2635 		rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2636 		rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2637 		rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2638 		rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2639 		rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2640 		rfcsr = 0x7a;
2641 		rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2642 				  drv_data->txmixer_gain_5g);
2643 		rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2644 		rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2645 		if (rf->channel <= 64) {
2646 			rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2647 			rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2648 			rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2649 		} else if (rf->channel <= 128) {
2650 			rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2651 			rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2652 			rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2653 		} else {
2654 			rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2655 			rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2656 			rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2657 		}
2658 		rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2659 		rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2660 		rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2661 	}
2662 
2663 	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2664 	rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2665 	if (rf->channel <= 14)
2666 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2667 	else
2668 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2669 	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2670 
2671 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2672 	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2673 	rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2674 }
2675 
2676 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2677 					 struct ieee80211_conf *conf,
2678 					 struct rf_channel *rf,
2679 					 struct channel_info *info)
2680 {
2681 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2682 	u8 txrx_agc_fc;
2683 	u8 txrx_h20m;
2684 	u8 rfcsr;
2685 	u8 bbp;
2686 	const bool txbf_enabled = false; /* TODO */
2687 
2688 	/* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2689 	bbp = rt2800_bbp_read(rt2x00dev, 109);
2690 	rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2691 	rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2692 	rt2800_bbp_write(rt2x00dev, 109, bbp);
2693 
2694 	bbp = rt2800_bbp_read(rt2x00dev, 110);
2695 	rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2696 	rt2800_bbp_write(rt2x00dev, 110, bbp);
2697 
2698 	if (rf->channel <= 14) {
2699 		/* Restore BBP 25 & 26 for 2.4 GHz */
2700 		rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2701 		rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2702 	} else {
2703 		/* Hard code BBP 25 & 26 for 5GHz */
2704 
2705 		/* Enable IQ Phase correction */
2706 		rt2800_bbp_write(rt2x00dev, 25, 0x09);
2707 		/* Setup IQ Phase correction value */
2708 		rt2800_bbp_write(rt2x00dev, 26, 0xff);
2709 	}
2710 
2711 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2712 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2713 
2714 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2715 	rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2716 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2717 
2718 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2719 	rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2720 	if (rf->channel <= 14)
2721 		rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2722 	else
2723 		rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2724 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2725 
2726 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2727 	if (rf->channel <= 14) {
2728 		rfcsr = 0;
2729 		rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2730 				  info->default_power1 & 0x1f);
2731 	} else {
2732 		if (rt2x00_is_usb(rt2x00dev))
2733 			rfcsr = 0x40;
2734 
2735 		rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2736 				  ((info->default_power1 & 0x18) << 1) |
2737 				  (info->default_power1 & 7));
2738 	}
2739 	rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2740 
2741 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2742 	if (rf->channel <= 14) {
2743 		rfcsr = 0;
2744 		rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2745 				  info->default_power2 & 0x1f);
2746 	} else {
2747 		if (rt2x00_is_usb(rt2x00dev))
2748 			rfcsr = 0x40;
2749 
2750 		rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2751 				  ((info->default_power2 & 0x18) << 1) |
2752 				  (info->default_power2 & 7));
2753 	}
2754 	rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2755 
2756 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2757 	if (rf->channel <= 14) {
2758 		rfcsr = 0;
2759 		rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2760 				  info->default_power3 & 0x1f);
2761 	} else {
2762 		if (rt2x00_is_usb(rt2x00dev))
2763 			rfcsr = 0x40;
2764 
2765 		rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2766 				  ((info->default_power3 & 0x18) << 1) |
2767 				  (info->default_power3 & 7));
2768 	}
2769 	rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2770 
2771 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2772 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2773 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2774 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2775 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2776 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2777 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2778 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2779 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2780 
2781 	switch (rt2x00dev->default_ant.tx_chain_num) {
2782 	case 3:
2783 		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2784 		fallthrough;
2785 	case 2:
2786 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2787 		fallthrough;
2788 	case 1:
2789 		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2790 		break;
2791 	}
2792 
2793 	switch (rt2x00dev->default_ant.rx_chain_num) {
2794 	case 3:
2795 		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2796 		fallthrough;
2797 	case 2:
2798 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2799 		fallthrough;
2800 	case 1:
2801 		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2802 		break;
2803 	}
2804 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2805 
2806 	rt2800_freq_cal_mode1(rt2x00dev);
2807 
2808 	if (conf_is_ht40(conf)) {
2809 		txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2810 						RFCSR24_TX_AGC_FC);
2811 		txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2812 					      RFCSR24_TX_H20M);
2813 	} else {
2814 		txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2815 						RFCSR24_TX_AGC_FC);
2816 		txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2817 					      RFCSR24_TX_H20M);
2818 	}
2819 
2820 	/* NOTE: the reference driver does not writes the new value
2821 	 * back to RFCSR 32
2822 	 */
2823 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2824 	rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2825 
2826 	if (rf->channel <= 14)
2827 		rfcsr = 0xa0;
2828 	else
2829 		rfcsr = 0x80;
2830 	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2831 
2832 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2833 	rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2834 	rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2835 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2836 
2837 	/* Band selection */
2838 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2839 	if (rf->channel <= 14)
2840 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2841 	else
2842 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2843 	rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2844 
2845 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2846 	if (rf->channel <= 14)
2847 		rfcsr = 0x3c;
2848 	else
2849 		rfcsr = 0x20;
2850 	rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2851 
2852 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2853 	if (rf->channel <= 14)
2854 		rfcsr = 0x1a;
2855 	else
2856 		rfcsr = 0x12;
2857 	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2858 
2859 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2860 	if (rf->channel >= 1 && rf->channel <= 14)
2861 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2862 	else if (rf->channel >= 36 && rf->channel <= 64)
2863 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2864 	else if (rf->channel >= 100 && rf->channel <= 128)
2865 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2866 	else
2867 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2868 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2869 
2870 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2871 	rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2872 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2873 
2874 	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2875 
2876 	if (rf->channel <= 14) {
2877 		rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2878 		rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2879 	} else {
2880 		rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2881 		rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2882 	}
2883 
2884 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2885 	rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2886 	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2887 
2888 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2889 	if (rf->channel <= 14) {
2890 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2891 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2892 	} else {
2893 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2894 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2895 	}
2896 	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2897 
2898 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2899 	if (rf->channel <= 14)
2900 		rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2901 	else
2902 		rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2903 
2904 	if (txbf_enabled)
2905 		rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2906 
2907 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2908 
2909 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2910 	rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2911 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2912 
2913 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
2914 	if (rf->channel <= 14)
2915 		rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2916 	else
2917 		rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2918 	rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2919 
2920 	if (rf->channel <= 14) {
2921 		rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2922 		rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2923 	} else {
2924 		rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2925 		rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2926 	}
2927 
2928 	/* Initiate VCO calibration */
2929 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2930 	if (rf->channel <= 14) {
2931 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2932 	} else {
2933 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2934 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2935 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2936 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2937 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2938 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2939 	}
2940 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2941 
2942 	if (rf->channel >= 1 && rf->channel <= 14) {
2943 		rfcsr = 0x23;
2944 		if (txbf_enabled)
2945 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2946 		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2947 
2948 		rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2949 	} else if (rf->channel >= 36 && rf->channel <= 64) {
2950 		rfcsr = 0x36;
2951 		if (txbf_enabled)
2952 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2953 		rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2954 
2955 		rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2956 	} else if (rf->channel >= 100 && rf->channel <= 128) {
2957 		rfcsr = 0x32;
2958 		if (txbf_enabled)
2959 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2960 		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2961 
2962 		rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2963 	} else {
2964 		rfcsr = 0x30;
2965 		if (txbf_enabled)
2966 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2967 		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2968 
2969 		rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2970 	}
2971 }
2972 
2973 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
2974 					 struct ieee80211_conf *conf,
2975 					 struct rf_channel *rf,
2976 					 struct channel_info *info)
2977 {
2978 	u8 rfcsr;
2979 	u8 bbp;
2980 	u8 pwr1, pwr2, pwr3;
2981 
2982 	const bool txbf_enabled = false; /* TODO */
2983 
2984 	/* TODO: add band selection */
2985 
2986 	if (rf->channel <= 14)
2987 		rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
2988 	else if (rf->channel < 132)
2989 		rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
2990 	else
2991 		rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
2992 
2993 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2994 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2995 
2996 	if (rf->channel <= 14)
2997 		rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
2998 	else
2999 		rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
3000 
3001 	if (rf->channel <= 14)
3002 		rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
3003 	else
3004 		rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3005 
3006 	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
3007 
3008 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3009 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3010 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3011 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
3012 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
3013 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3014 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3015 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3016 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3017 
3018 	switch (rt2x00dev->default_ant.tx_chain_num) {
3019 	case 3:
3020 		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
3021 		fallthrough;
3022 	case 2:
3023 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3024 		fallthrough;
3025 	case 1:
3026 		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3027 		break;
3028 	}
3029 
3030 	switch (rt2x00dev->default_ant.rx_chain_num) {
3031 	case 3:
3032 		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
3033 		fallthrough;
3034 	case 2:
3035 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3036 		fallthrough;
3037 	case 1:
3038 		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3039 		break;
3040 	}
3041 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3042 
3043 	rt2800_freq_cal_mode1(rt2x00dev);
3044 
3045 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3046 	if (!conf_is_ht40(conf))
3047 		rfcsr &= ~(0x06);
3048 	else
3049 		rfcsr |= 0x06;
3050 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3051 
3052 	if (rf->channel <= 14)
3053 		rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
3054 	else
3055 		rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3056 
3057 	if (conf_is_ht40(conf))
3058 		rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3059 	else
3060 		rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
3061 
3062 	if (rf->channel <= 14)
3063 		rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
3064 	else
3065 		rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
3066 
3067 	/* loopback RF_BS */
3068 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
3069 	if (rf->channel <= 14)
3070 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
3071 	else
3072 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
3073 	rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
3074 
3075 	if (rf->channel <= 14)
3076 		rfcsr = 0x23;
3077 	else if (rf->channel < 100)
3078 		rfcsr = 0x36;
3079 	else if (rf->channel < 132)
3080 		rfcsr = 0x32;
3081 	else
3082 		rfcsr = 0x30;
3083 
3084 	if (txbf_enabled)
3085 		rfcsr |= 0x40;
3086 
3087 	rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3088 
3089 	if (rf->channel <= 14)
3090 		rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
3091 	else
3092 		rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
3093 
3094 	if (rf->channel <= 14)
3095 		rfcsr = 0xbb;
3096 	else if (rf->channel < 100)
3097 		rfcsr = 0xeb;
3098 	else if (rf->channel < 132)
3099 		rfcsr = 0xb3;
3100 	else
3101 		rfcsr = 0x9b;
3102 	rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
3103 
3104 	if (rf->channel <= 14)
3105 		rfcsr = 0x8e;
3106 	else
3107 		rfcsr = 0x8a;
3108 
3109 	if (txbf_enabled)
3110 		rfcsr |= 0x20;
3111 
3112 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3113 
3114 	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
3115 
3116 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3117 	if (rf->channel <= 14)
3118 		rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
3119 	else
3120 		rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
3121 
3122 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
3123 	if (rf->channel <= 14)
3124 		rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
3125 	else
3126 		rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
3127 
3128 	if (rf->channel <= 14) {
3129 		pwr1 = info->default_power1 & 0x1f;
3130 		pwr2 = info->default_power2 & 0x1f;
3131 		pwr3 = info->default_power3 & 0x1f;
3132 	} else {
3133 		pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) |
3134 			(info->default_power1 & 0x7);
3135 		pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) |
3136 			(info->default_power2 & 0x7);
3137 		pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) |
3138 			(info->default_power3 & 0x7);
3139 	}
3140 
3141 	rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
3142 	rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
3143 	rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
3144 
3145 	rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
3146 		   rf->channel, pwr1, pwr2, pwr3);
3147 
3148 	bbp = (info->default_power1 >> 5) |
3149 	      ((info->default_power2 & 0xe0) >> 1);
3150 	rt2800_bbp_write(rt2x00dev, 109, bbp);
3151 
3152 	bbp = rt2800_bbp_read(rt2x00dev, 110);
3153 	bbp &= 0x0f;
3154 	bbp |= (info->default_power3 & 0xe0) >> 1;
3155 	rt2800_bbp_write(rt2x00dev, 110, bbp);
3156 
3157 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3158 	if (rf->channel <= 14)
3159 		rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
3160 	else
3161 		rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
3162 
3163 	/* Enable RF tuning */
3164 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3165 	rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3166 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3167 
3168 	udelay(2000);
3169 
3170 	bbp = rt2800_bbp_read(rt2x00dev, 49);
3171 	/* clear update flag */
3172 	rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
3173 	rt2800_bbp_write(rt2x00dev, 49, bbp);
3174 
3175 	/* TODO: add calibration for TxBF */
3176 }
3177 
3178 #define POWER_BOUND		0x27
3179 #define POWER_BOUND_5G		0x2b
3180 
3181 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
3182 					 struct ieee80211_conf *conf,
3183 					 struct rf_channel *rf,
3184 					 struct channel_info *info)
3185 {
3186 	u8 rfcsr;
3187 
3188 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3189 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3190 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3191 	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3192 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3193 
3194 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3195 	if (info->default_power1 > POWER_BOUND)
3196 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3197 	else
3198 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3199 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3200 
3201 	rt2800_freq_cal_mode1(rt2x00dev);
3202 
3203 	if (rf->channel <= 14) {
3204 		if (rf->channel == 6)
3205 			rt2800_bbp_write(rt2x00dev, 68, 0x0c);
3206 		else
3207 			rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3208 
3209 		if (rf->channel >= 1 && rf->channel <= 6)
3210 			rt2800_bbp_write(rt2x00dev, 59, 0x0f);
3211 		else if (rf->channel >= 7 && rf->channel <= 11)
3212 			rt2800_bbp_write(rt2x00dev, 59, 0x0e);
3213 		else if (rf->channel >= 12 && rf->channel <= 14)
3214 			rt2800_bbp_write(rt2x00dev, 59, 0x0d);
3215 	}
3216 }
3217 
3218 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
3219 					 struct ieee80211_conf *conf,
3220 					 struct rf_channel *rf,
3221 					 struct channel_info *info)
3222 {
3223 	u8 rfcsr;
3224 
3225 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3226 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3227 
3228 	rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
3229 	rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
3230 	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
3231 
3232 	if (info->default_power1 > POWER_BOUND)
3233 		rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
3234 	else
3235 		rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
3236 
3237 	if (info->default_power2 > POWER_BOUND)
3238 		rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
3239 	else
3240 		rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
3241 
3242 	rt2800_freq_cal_mode1(rt2x00dev);
3243 
3244 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3245 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3246 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3247 
3248 	if ( rt2x00dev->default_ant.tx_chain_num == 2 )
3249 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3250 	else
3251 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
3252 
3253 	if ( rt2x00dev->default_ant.rx_chain_num == 2 )
3254 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3255 	else
3256 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
3257 
3258 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3259 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3260 
3261 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3262 
3263 	rt2800_rfcsr_write(rt2x00dev, 31, 80);
3264 }
3265 
3266 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
3267 					 struct ieee80211_conf *conf,
3268 					 struct rf_channel *rf,
3269 					 struct channel_info *info)
3270 {
3271 	u8 rfcsr;
3272 	int idx = rf->channel-1;
3273 
3274 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3275 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3276 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3277 	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3278 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3279 
3280 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3281 	if (info->default_power1 > POWER_BOUND)
3282 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3283 	else
3284 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3285 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3286 
3287 	if (rt2x00_rt(rt2x00dev, RT5392)) {
3288 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3289 		if (info->default_power2 > POWER_BOUND)
3290 			rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
3291 		else
3292 			rt2x00_set_field8(&rfcsr, RFCSR50_TX,
3293 					  info->default_power2);
3294 		rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3295 	}
3296 
3297 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3298 	if (rt2x00_rt(rt2x00dev, RT5392)) {
3299 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3300 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3301 	}
3302 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3303 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3304 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3305 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3306 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3307 
3308 	rt2800_freq_cal_mode1(rt2x00dev);
3309 
3310 	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
3311 		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3312 			/* r55/r59 value array of channel 1~14 */
3313 			static const char r55_bt_rev[] = {0x83, 0x83,
3314 				0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
3315 				0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
3316 			static const char r59_bt_rev[] = {0x0e, 0x0e,
3317 				0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
3318 				0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
3319 
3320 			rt2800_rfcsr_write(rt2x00dev, 55,
3321 					   r55_bt_rev[idx]);
3322 			rt2800_rfcsr_write(rt2x00dev, 59,
3323 					   r59_bt_rev[idx]);
3324 		} else {
3325 			static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
3326 				0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
3327 				0x88, 0x88, 0x86, 0x85, 0x84};
3328 
3329 			rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
3330 		}
3331 	} else {
3332 		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3333 			static const char r55_nonbt_rev[] = {0x23, 0x23,
3334 				0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
3335 				0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
3336 			static const char r59_nonbt_rev[] = {0x07, 0x07,
3337 				0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
3338 				0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
3339 
3340 			rt2800_rfcsr_write(rt2x00dev, 55,
3341 					   r55_nonbt_rev[idx]);
3342 			rt2800_rfcsr_write(rt2x00dev, 59,
3343 					   r59_nonbt_rev[idx]);
3344 		} else if (rt2x00_rt(rt2x00dev, RT5390) ||
3345 			   rt2x00_rt(rt2x00dev, RT5392) ||
3346 			   rt2x00_rt(rt2x00dev, RT6352)) {
3347 			static const char r59_non_bt[] = {0x8f, 0x8f,
3348 				0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
3349 				0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
3350 
3351 			rt2800_rfcsr_write(rt2x00dev, 59,
3352 					   r59_non_bt[idx]);
3353 		} else if (rt2x00_rt(rt2x00dev, RT5350)) {
3354 			static const char r59_non_bt[] = {0x0b, 0x0b,
3355 				0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
3356 				0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
3357 
3358 			rt2800_rfcsr_write(rt2x00dev, 59,
3359 					   r59_non_bt[idx]);
3360 		}
3361 	}
3362 }
3363 
3364 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
3365 					 struct ieee80211_conf *conf,
3366 					 struct rf_channel *rf,
3367 					 struct channel_info *info)
3368 {
3369 	u8 rfcsr, ep_reg;
3370 	u32 reg;
3371 	int power_bound;
3372 
3373 	/* TODO */
3374 	const bool is_11b = false;
3375 	const bool is_type_ep = false;
3376 
3377 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
3378 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
3379 			   (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
3380 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3381 
3382 	/* Order of values on rf_channel entry: N, K, mod, R */
3383 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
3384 
3385 	rfcsr = rt2800_rfcsr_read(rt2x00dev,  9);
3386 	rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
3387 	rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
3388 	rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
3389 	rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
3390 
3391 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3392 	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
3393 	rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
3394 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3395 
3396 	if (rf->channel <= 14) {
3397 		rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
3398 		/* FIXME: RF11 owerwrite ? */
3399 		rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
3400 		rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3401 		rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3402 		rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3403 		rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
3404 		rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3405 		rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3406 		rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
3407 		rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3408 		rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3409 		rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
3410 		rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
3411 		rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
3412 		rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
3413 		rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
3414 		rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
3415 		rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
3416 		rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
3417 		rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3418 		rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
3419 		rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3420 		rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3421 		rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
3422 		rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3423 		rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3424 		rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3425 		rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3426 		rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3427 
3428 		/* TODO RF27 <- tssi */
3429 
3430 		rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
3431 		rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
3432 		rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
3433 
3434 		if (is_11b) {
3435 			/* CCK */
3436 			rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
3437 			rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
3438 			if (is_type_ep)
3439 				rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
3440 			else
3441 				rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
3442 		} else {
3443 			/* OFDM */
3444 			if (is_type_ep)
3445 				rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
3446 			else
3447 				rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3448 		}
3449 
3450 		power_bound = POWER_BOUND;
3451 		ep_reg = 0x2;
3452 	} else {
3453 		rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
3454 		/* FIMXE: RF11 overwrite */
3455 		rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
3456 		rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
3457 		rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3458 		rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3459 		rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3460 		rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3461 		rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3462 		rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3463 		rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3464 		rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3465 		rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3466 		rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3467 		rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3468 		rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3469 
3470 		/* TODO RF27 <- tssi */
3471 
3472 		if (rf->channel >= 36 && rf->channel <= 64) {
3473 
3474 			rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3475 			rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3476 			rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3477 			rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3478 			if (rf->channel <= 50)
3479 				rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3480 			else if (rf->channel >= 52)
3481 				rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3482 			rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3483 			rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3484 			rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3485 			rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3486 			rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3487 			rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3488 			rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3489 			if (rf->channel <= 50) {
3490 				rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3491 				rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3492 			} else if (rf->channel >= 52) {
3493 				rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3494 				rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3495 			}
3496 
3497 			rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3498 			rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3499 			rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3500 
3501 		} else if (rf->channel >= 100 && rf->channel <= 165) {
3502 
3503 			rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3504 			rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3505 			rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3506 			if (rf->channel <= 153) {
3507 				rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3508 				rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3509 			} else if (rf->channel >= 155) {
3510 				rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3511 				rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3512 			}
3513 			if (rf->channel <= 138) {
3514 				rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3515 				rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3516 				rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3517 				rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3518 			} else if (rf->channel >= 140) {
3519 				rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3520 				rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3521 				rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3522 				rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3523 			}
3524 			if (rf->channel <= 124)
3525 				rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3526 			else if (rf->channel >= 126)
3527 				rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3528 			if (rf->channel <= 138)
3529 				rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3530 			else if (rf->channel >= 140)
3531 				rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3532 			rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3533 			if (rf->channel <= 138)
3534 				rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3535 			else if (rf->channel >= 140)
3536 				rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3537 			if (rf->channel <= 128)
3538 				rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3539 			else if (rf->channel >= 130)
3540 				rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3541 			if (rf->channel <= 116)
3542 				rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3543 			else if (rf->channel >= 118)
3544 				rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3545 			if (rf->channel <= 138)
3546 				rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3547 			else if (rf->channel >= 140)
3548 				rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3549 			if (rf->channel <= 116)
3550 				rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3551 			else if (rf->channel >= 118)
3552 				rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3553 		}
3554 
3555 		power_bound = POWER_BOUND_5G;
3556 		ep_reg = 0x3;
3557 	}
3558 
3559 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3560 	if (info->default_power1 > power_bound)
3561 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3562 	else
3563 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3564 	if (is_type_ep)
3565 		rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3566 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3567 
3568 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3569 	if (info->default_power2 > power_bound)
3570 		rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3571 	else
3572 		rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3573 	if (is_type_ep)
3574 		rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3575 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3576 
3577 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3578 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3579 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3580 
3581 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3582 			  rt2x00dev->default_ant.tx_chain_num >= 1);
3583 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3584 			  rt2x00dev->default_ant.tx_chain_num == 2);
3585 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3586 
3587 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3588 			  rt2x00dev->default_ant.rx_chain_num >= 1);
3589 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3590 			  rt2x00dev->default_ant.rx_chain_num == 2);
3591 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3592 
3593 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3594 	rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3595 
3596 	if (conf_is_ht40(conf))
3597 		rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3598 	else
3599 		rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3600 
3601 	if (!is_11b) {
3602 		rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3603 		rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3604 	}
3605 
3606 	/* TODO proper frequency adjustment */
3607 	rt2800_freq_cal_mode1(rt2x00dev);
3608 
3609 	/* TODO merge with others */
3610 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3611 	rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3612 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3613 
3614 	/* BBP settings */
3615 	rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3616 	rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3617 	rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3618 
3619 	rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3620 	rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3621 	rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3622 	rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3623 
3624 	/* GLRT band configuration */
3625 	rt2800_bbp_write(rt2x00dev, 195, 128);
3626 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3627 	rt2800_bbp_write(rt2x00dev, 195, 129);
3628 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3629 	rt2800_bbp_write(rt2x00dev, 195, 130);
3630 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3631 	rt2800_bbp_write(rt2x00dev, 195, 131);
3632 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3633 	rt2800_bbp_write(rt2x00dev, 195, 133);
3634 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3635 	rt2800_bbp_write(rt2x00dev, 195, 124);
3636 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3637 }
3638 
3639 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3640 					 struct ieee80211_conf *conf,
3641 					 struct rf_channel *rf,
3642 					 struct channel_info *info)
3643 {
3644 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3645 	u8 rx_agc_fc, tx_agc_fc;
3646 	u8 rfcsr;
3647 
3648 	/* Frequeny plan setting */
3649 	/* Rdiv setting (set 0x03 if Xtal==20)
3650 	 * R13[1:0]
3651 	 */
3652 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3653 	rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3654 			  rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3655 	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3656 
3657 	/* N setting
3658 	 * R20[7:0] in rf->rf1
3659 	 * R21[0] always 0
3660 	 */
3661 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3662 	rfcsr = (rf->rf1 & 0x00ff);
3663 	rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3664 
3665 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3666 	rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3667 	rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3668 
3669 	/* K setting (always 0)
3670 	 * R16[3:0] (RF PLL freq selection)
3671 	 */
3672 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3673 	rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3674 	rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3675 
3676 	/* D setting (always 0)
3677 	 * R22[2:0] (D=15, R22[2:0]=<111>)
3678 	 */
3679 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3680 	rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3681 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3682 
3683 	/* Ksd setting
3684 	 * Ksd: R17<7:0> in rf->rf2
3685 	 *      R18<7:0> in rf->rf3
3686 	 *      R19<1:0> in rf->rf4
3687 	 */
3688 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3689 	rfcsr = rf->rf2;
3690 	rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3691 
3692 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3693 	rfcsr = rf->rf3;
3694 	rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3695 
3696 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3697 	rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3698 	rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3699 
3700 	/* Default: XO=20MHz , SDM mode */
3701 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3702 	rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3703 	rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3704 
3705 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3706 	rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3707 	rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3708 
3709 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3710 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3711 			  rt2x00dev->default_ant.tx_chain_num != 1);
3712 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3713 
3714 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3715 	rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3716 			  rt2x00dev->default_ant.tx_chain_num != 1);
3717 	rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3718 			  rt2x00dev->default_ant.rx_chain_num != 1);
3719 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3720 
3721 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3722 	rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3723 			  rt2x00dev->default_ant.tx_chain_num != 1);
3724 	rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3725 
3726 	/* RF for DC Cal BW */
3727 	if (conf_is_ht40(conf)) {
3728 		rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3729 		rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3730 		rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3731 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3732 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3733 	} else {
3734 		rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3735 		rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3736 		rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3737 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3738 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3739 	}
3740 
3741 	if (conf_is_ht40(conf)) {
3742 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3743 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3744 	} else {
3745 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3746 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3747 	}
3748 
3749 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3750 	rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3751 			  conf_is_ht40(conf) && (rf->channel == 11));
3752 	rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3753 
3754 	if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3755 		if (conf_is_ht40(conf)) {
3756 			rx_agc_fc = drv_data->rx_calibration_bw40;
3757 			tx_agc_fc = drv_data->tx_calibration_bw40;
3758 		} else {
3759 			rx_agc_fc = drv_data->rx_calibration_bw20;
3760 			tx_agc_fc = drv_data->tx_calibration_bw20;
3761 		}
3762 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3763 		rfcsr &= (~0x3F);
3764 		rfcsr |= rx_agc_fc;
3765 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3766 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3767 		rfcsr &= (~0x3F);
3768 		rfcsr |= rx_agc_fc;
3769 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3770 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3771 		rfcsr &= (~0x3F);
3772 		rfcsr |= rx_agc_fc;
3773 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3774 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3775 		rfcsr &= (~0x3F);
3776 		rfcsr |= rx_agc_fc;
3777 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3778 
3779 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3780 		rfcsr &= (~0x3F);
3781 		rfcsr |= tx_agc_fc;
3782 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3783 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3784 		rfcsr &= (~0x3F);
3785 		rfcsr |= tx_agc_fc;
3786 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3787 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3788 		rfcsr &= (~0x3F);
3789 		rfcsr |= tx_agc_fc;
3790 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3791 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3792 		rfcsr &= (~0x3F);
3793 		rfcsr |= tx_agc_fc;
3794 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3795 	}
3796 }
3797 
3798 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
3799 			      struct ieee80211_channel *chan,
3800 			      int power_level) {
3801 	u16 eeprom, target_power, max_power;
3802 	u32 mac_sys_ctrl, mac_status;
3803 	u32 reg;
3804 	u8 bbp;
3805 	int i;
3806 
3807 	/* hardware unit is 0.5dBm, limited to 23.5dBm */
3808 	power_level *= 2;
3809 	if (power_level > 0x2f)
3810 		power_level = 0x2f;
3811 
3812 	max_power = chan->max_power * 2;
3813 	if (max_power > 0x2f)
3814 		max_power = 0x2f;
3815 
3816 	reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3817 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
3818 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
3819 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
3820 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
3821 
3822 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3823 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
3824 		/* init base power by eeprom target power */
3825 		target_power = rt2800_eeprom_read(rt2x00dev,
3826 						  EEPROM_TXPOWER_INIT);
3827 		rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
3828 		rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
3829 	}
3830 	rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3831 
3832 	reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3833 	rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
3834 	rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3835 
3836 	/* Save MAC SYS CTRL registers */
3837 	mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3838 	/* Disable Tx/Rx */
3839 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3840 	/* Check MAC Tx/Rx idle */
3841 	for (i = 0; i < 10000; i++) {
3842 		mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
3843 		if (mac_status & 0x3)
3844 			usleep_range(50, 200);
3845 		else
3846 			break;
3847 	}
3848 
3849 	if (i == 10000)
3850 		rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
3851 
3852 	if (chan->center_freq > 2457) {
3853 		bbp = rt2800_bbp_read(rt2x00dev, 30);
3854 		bbp = 0x40;
3855 		rt2800_bbp_write(rt2x00dev, 30, bbp);
3856 		rt2800_rfcsr_write(rt2x00dev, 39, 0);
3857 		if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3858 			rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3859 		else
3860 			rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3861 	} else {
3862 		bbp = rt2800_bbp_read(rt2x00dev, 30);
3863 		bbp = 0x1f;
3864 		rt2800_bbp_write(rt2x00dev, 30, bbp);
3865 		rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3866 		if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3867 			rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3868 		else
3869 			rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3870 	}
3871 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
3872 
3873 	rt2800_vco_calibration(rt2x00dev);
3874 }
3875 
3876 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3877 					   const unsigned int word,
3878 					   const u8 value)
3879 {
3880 	u8 chain, reg;
3881 
3882 	for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3883 		reg = rt2800_bbp_read(rt2x00dev, 27);
3884 		rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
3885 		rt2800_bbp_write(rt2x00dev, 27, reg);
3886 
3887 		rt2800_bbp_write(rt2x00dev, word, value);
3888 	}
3889 }
3890 
3891 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3892 {
3893 	u8 cal;
3894 
3895 	/* TX0 IQ Gain */
3896 	rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3897 	if (channel <= 14)
3898 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3899 	else if (channel >= 36 && channel <= 64)
3900 		cal = rt2x00_eeprom_byte(rt2x00dev,
3901 					 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3902 	else if (channel >= 100 && channel <= 138)
3903 		cal = rt2x00_eeprom_byte(rt2x00dev,
3904 					 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3905 	else if (channel >= 140 && channel <= 165)
3906 		cal = rt2x00_eeprom_byte(rt2x00dev,
3907 					 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3908 	else
3909 		cal = 0;
3910 	rt2800_bbp_write(rt2x00dev, 159, cal);
3911 
3912 	/* TX0 IQ Phase */
3913 	rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3914 	if (channel <= 14)
3915 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3916 	else if (channel >= 36 && channel <= 64)
3917 		cal = rt2x00_eeprom_byte(rt2x00dev,
3918 					 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3919 	else if (channel >= 100 && channel <= 138)
3920 		cal = rt2x00_eeprom_byte(rt2x00dev,
3921 					 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3922 	else if (channel >= 140 && channel <= 165)
3923 		cal = rt2x00_eeprom_byte(rt2x00dev,
3924 					 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3925 	else
3926 		cal = 0;
3927 	rt2800_bbp_write(rt2x00dev, 159, cal);
3928 
3929 	/* TX1 IQ Gain */
3930 	rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3931 	if (channel <= 14)
3932 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3933 	else if (channel >= 36 && channel <= 64)
3934 		cal = rt2x00_eeprom_byte(rt2x00dev,
3935 					 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3936 	else if (channel >= 100 && channel <= 138)
3937 		cal = rt2x00_eeprom_byte(rt2x00dev,
3938 					 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3939 	else if (channel >= 140 && channel <= 165)
3940 		cal = rt2x00_eeprom_byte(rt2x00dev,
3941 					 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3942 	else
3943 		cal = 0;
3944 	rt2800_bbp_write(rt2x00dev, 159, cal);
3945 
3946 	/* TX1 IQ Phase */
3947 	rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3948 	if (channel <= 14)
3949 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3950 	else if (channel >= 36 && channel <= 64)
3951 		cal = rt2x00_eeprom_byte(rt2x00dev,
3952 					 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3953 	else if (channel >= 100 && channel <= 138)
3954 		cal = rt2x00_eeprom_byte(rt2x00dev,
3955 					 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3956 	else if (channel >= 140 && channel <= 165)
3957 		cal = rt2x00_eeprom_byte(rt2x00dev,
3958 					 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3959 	else
3960 		cal = 0;
3961 	rt2800_bbp_write(rt2x00dev, 159, cal);
3962 
3963 	/* FIXME: possible RX0, RX1 callibration ? */
3964 
3965 	/* RF IQ compensation control */
3966 	rt2800_bbp_write(rt2x00dev, 158, 0x04);
3967 	cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3968 	rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3969 
3970 	/* RF IQ imbalance compensation control */
3971 	rt2800_bbp_write(rt2x00dev, 158, 0x03);
3972 	cal = rt2x00_eeprom_byte(rt2x00dev,
3973 				 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3974 	rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3975 }
3976 
3977 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3978 				  unsigned int channel,
3979 				  char txpower)
3980 {
3981 	if (rt2x00_rt(rt2x00dev, RT3593) ||
3982 	    rt2x00_rt(rt2x00dev, RT3883))
3983 		txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3984 
3985 	if (channel <= 14)
3986 		return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3987 
3988 	if (rt2x00_rt(rt2x00dev, RT3593) ||
3989 	    rt2x00_rt(rt2x00dev, RT3883))
3990 		return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3991 			       MAX_A_TXPOWER_3593);
3992 	else
3993 		return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3994 }
3995 
3996 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
3997 			      struct rf_channel *rf)
3998 {
3999 	u8 bbp;
4000 
4001 	bbp = (rf->channel > 14) ? 0x48 : 0x38;
4002 	rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
4003 
4004 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
4005 
4006 	if (rf->channel <= 14) {
4007 		rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4008 	} else {
4009 		/* Disable CCK packet detection */
4010 		rt2800_bbp_write(rt2x00dev, 70, 0x00);
4011 	}
4012 
4013 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
4014 
4015 	if (rf->channel > 14) {
4016 		rt2800_bbp_write(rt2x00dev, 62, 0x1d);
4017 		rt2800_bbp_write(rt2x00dev, 63, 0x1d);
4018 		rt2800_bbp_write(rt2x00dev, 64, 0x1d);
4019 	} else {
4020 		rt2800_bbp_write(rt2x00dev, 62, 0x2d);
4021 		rt2800_bbp_write(rt2x00dev, 63, 0x2d);
4022 		rt2800_bbp_write(rt2x00dev, 64, 0x2d);
4023 	}
4024 }
4025 
4026 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
4027 				  struct ieee80211_conf *conf,
4028 				  struct rf_channel *rf,
4029 				  struct channel_info *info)
4030 {
4031 	u32 reg;
4032 	u32 tx_pin;
4033 	u8 bbp, rfcsr;
4034 
4035 	info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4036 						     info->default_power1);
4037 	info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4038 						     info->default_power2);
4039 	if (rt2x00dev->default_ant.tx_chain_num > 2)
4040 		info->default_power3 =
4041 			rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4042 					      info->default_power3);
4043 
4044 	switch (rt2x00dev->chip.rt) {
4045 	case RT3883:
4046 		rt3883_bbp_adjust(rt2x00dev, rf);
4047 		break;
4048 	}
4049 
4050 	switch (rt2x00dev->chip.rf) {
4051 	case RF2020:
4052 	case RF3020:
4053 	case RF3021:
4054 	case RF3022:
4055 	case RF3320:
4056 		rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
4057 		break;
4058 	case RF3052:
4059 		rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
4060 		break;
4061 	case RF3053:
4062 		rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
4063 		break;
4064 	case RF3290:
4065 		rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
4066 		break;
4067 	case RF3322:
4068 		rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
4069 		break;
4070 	case RF3853:
4071 		rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
4072 		break;
4073 	case RF3070:
4074 	case RF5350:
4075 	case RF5360:
4076 	case RF5362:
4077 	case RF5370:
4078 	case RF5372:
4079 	case RF5390:
4080 	case RF5392:
4081 		rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
4082 		break;
4083 	case RF5592:
4084 		rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
4085 		break;
4086 	case RF7620:
4087 		rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
4088 		break;
4089 	default:
4090 		rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
4091 	}
4092 
4093 	if (rt2x00_rf(rt2x00dev, RF3070) ||
4094 	    rt2x00_rf(rt2x00dev, RF3290) ||
4095 	    rt2x00_rf(rt2x00dev, RF3322) ||
4096 	    rt2x00_rf(rt2x00dev, RF5350) ||
4097 	    rt2x00_rf(rt2x00dev, RF5360) ||
4098 	    rt2x00_rf(rt2x00dev, RF5362) ||
4099 	    rt2x00_rf(rt2x00dev, RF5370) ||
4100 	    rt2x00_rf(rt2x00dev, RF5372) ||
4101 	    rt2x00_rf(rt2x00dev, RF5390) ||
4102 	    rt2x00_rf(rt2x00dev, RF5392)) {
4103 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
4104 		if (rt2x00_rf(rt2x00dev, RF3322)) {
4105 			rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
4106 					  conf_is_ht40(conf));
4107 			rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
4108 					  conf_is_ht40(conf));
4109 		} else {
4110 			rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
4111 					  conf_is_ht40(conf));
4112 			rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
4113 					  conf_is_ht40(conf));
4114 		}
4115 		rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4116 
4117 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4118 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4119 		rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4120 	}
4121 
4122 	/*
4123 	 * Change BBP settings
4124 	 */
4125 
4126 	if (rt2x00_rt(rt2x00dev, RT3352)) {
4127 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4128 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4129 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4130 
4131 		rt2800_bbp_write(rt2x00dev, 27, 0x0);
4132 		rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4133 		rt2800_bbp_write(rt2x00dev, 27, 0x20);
4134 		rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4135 		rt2800_bbp_write(rt2x00dev, 86, 0x38);
4136 		rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4137 	} else if (rt2x00_rt(rt2x00dev, RT3593)) {
4138 		if (rf->channel > 14) {
4139 			/* Disable CCK Packet detection on 5GHz */
4140 			rt2800_bbp_write(rt2x00dev, 70, 0x00);
4141 		} else {
4142 			rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4143 		}
4144 
4145 		if (conf_is_ht40(conf))
4146 			rt2800_bbp_write(rt2x00dev, 105, 0x04);
4147 		else
4148 			rt2800_bbp_write(rt2x00dev, 105, 0x34);
4149 
4150 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4151 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4152 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4153 		rt2800_bbp_write(rt2x00dev, 77, 0x98);
4154 	} else if (rt2x00_rt(rt2x00dev, RT3883)) {
4155 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4156 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4157 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4158 
4159 		if (rt2x00dev->default_ant.rx_chain_num > 1)
4160 			rt2800_bbp_write(rt2x00dev, 86, 0x46);
4161 		else
4162 			rt2800_bbp_write(rt2x00dev, 86, 0);
4163 	} else {
4164 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4165 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4166 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4167 		rt2800_bbp_write(rt2x00dev, 86, 0);
4168 	}
4169 
4170 	if (rf->channel <= 14) {
4171 		if (!rt2x00_rt(rt2x00dev, RT5390) &&
4172 		    !rt2x00_rt(rt2x00dev, RT5392) &&
4173 		    !rt2x00_rt(rt2x00dev, RT6352)) {
4174 			if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4175 				rt2800_bbp_write(rt2x00dev, 82, 0x62);
4176 				rt2800_bbp_write(rt2x00dev, 82, 0x62);
4177 				rt2800_bbp_write(rt2x00dev, 75, 0x46);
4178 			} else {
4179 				if (rt2x00_rt(rt2x00dev, RT3593))
4180 					rt2800_bbp_write(rt2x00dev, 82, 0x62);
4181 				else
4182 					rt2800_bbp_write(rt2x00dev, 82, 0x84);
4183 				rt2800_bbp_write(rt2x00dev, 75, 0x50);
4184 			}
4185 			if (rt2x00_rt(rt2x00dev, RT3593) ||
4186 			    rt2x00_rt(rt2x00dev, RT3883))
4187 				rt2800_bbp_write(rt2x00dev, 83, 0x8a);
4188 		}
4189 
4190 	} else {
4191 		if (rt2x00_rt(rt2x00dev, RT3572))
4192 			rt2800_bbp_write(rt2x00dev, 82, 0x94);
4193 		else if (rt2x00_rt(rt2x00dev, RT3593) ||
4194 			 rt2x00_rt(rt2x00dev, RT3883))
4195 			rt2800_bbp_write(rt2x00dev, 82, 0x82);
4196 		else if (!rt2x00_rt(rt2x00dev, RT6352))
4197 			rt2800_bbp_write(rt2x00dev, 82, 0xf2);
4198 
4199 		if (rt2x00_rt(rt2x00dev, RT3593) ||
4200 		    rt2x00_rt(rt2x00dev, RT3883))
4201 			rt2800_bbp_write(rt2x00dev, 83, 0x9a);
4202 
4203 		if (rt2x00_has_cap_external_lna_a(rt2x00dev))
4204 			rt2800_bbp_write(rt2x00dev, 75, 0x46);
4205 		else
4206 			rt2800_bbp_write(rt2x00dev, 75, 0x50);
4207 	}
4208 
4209 	reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
4210 	rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
4211 	rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
4212 	rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
4213 	rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
4214 
4215 	if (rt2x00_rt(rt2x00dev, RT3572))
4216 		rt2800_rfcsr_write(rt2x00dev, 8, 0);
4217 
4218 	if (rt2x00_rt(rt2x00dev, RT6352)) {
4219 		tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4220 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1);
4221 	} else {
4222 		tx_pin = 0;
4223 	}
4224 
4225 	switch (rt2x00dev->default_ant.tx_chain_num) {
4226 	case 3:
4227 		/* Turn on tertiary PAs */
4228 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
4229 				   rf->channel > 14);
4230 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
4231 				   rf->channel <= 14);
4232 		fallthrough;
4233 	case 2:
4234 		/* Turn on secondary PAs */
4235 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
4236 				   rf->channel > 14);
4237 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
4238 				   rf->channel <= 14);
4239 		fallthrough;
4240 	case 1:
4241 		/* Turn on primary PAs */
4242 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
4243 				   rf->channel > 14);
4244 		if (rt2x00_has_cap_bt_coexist(rt2x00dev))
4245 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4246 		else
4247 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
4248 					   rf->channel <= 14);
4249 		break;
4250 	}
4251 
4252 	switch (rt2x00dev->default_ant.rx_chain_num) {
4253 	case 3:
4254 		/* Turn on tertiary LNAs */
4255 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
4256 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
4257 		fallthrough;
4258 	case 2:
4259 		/* Turn on secondary LNAs */
4260 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
4261 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
4262 		fallthrough;
4263 	case 1:
4264 		/* Turn on primary LNAs */
4265 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
4266 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
4267 		break;
4268 	}
4269 
4270 	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
4271 	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
4272 
4273 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4274 
4275 	if (rt2x00_rt(rt2x00dev, RT3572)) {
4276 		rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
4277 
4278 		/* AGC init */
4279 		if (rf->channel <= 14)
4280 			reg = 0x1c + (2 * rt2x00dev->lna_gain);
4281 		else
4282 			reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4283 
4284 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4285 	}
4286 
4287 	if (rt2x00_rt(rt2x00dev, RT3593)) {
4288 		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
4289 
4290 		/* Band selection */
4291 		if (rt2x00_is_usb(rt2x00dev) ||
4292 		    rt2x00_is_pcie(rt2x00dev)) {
4293 			/* GPIO #8 controls all paths */
4294 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
4295 			if (rf->channel <= 14)
4296 				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
4297 			else
4298 				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
4299 		}
4300 
4301 		/* LNA PE control. */
4302 		if (rt2x00_is_usb(rt2x00dev)) {
4303 			/* GPIO #4 controls PE0 and PE1,
4304 			 * GPIO #7 controls PE2
4305 			 */
4306 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
4307 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
4308 
4309 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
4310 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
4311 		} else if (rt2x00_is_pcie(rt2x00dev)) {
4312 			/* GPIO #4 controls PE0, PE1 and PE2 */
4313 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
4314 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
4315 		}
4316 
4317 		rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4318 
4319 		/* AGC init */
4320 		if (rf->channel <= 14)
4321 			reg = 0x1c + 2 * rt2x00dev->lna_gain;
4322 		else
4323 			reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4324 
4325 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4326 
4327 		usleep_range(1000, 1500);
4328 	}
4329 
4330 	if (rt2x00_rt(rt2x00dev, RT3883)) {
4331 		if (!conf_is_ht40(conf))
4332 			rt2800_bbp_write(rt2x00dev, 105, 0x34);
4333 		else
4334 			rt2800_bbp_write(rt2x00dev, 105, 0x04);
4335 
4336 		/* AGC init */
4337 		if (rf->channel <= 14)
4338 			reg = 0x2e + rt2x00dev->lna_gain;
4339 		else
4340 			reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
4341 
4342 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4343 
4344 		usleep_range(1000, 1500);
4345 	}
4346 
4347 	if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
4348 		reg = 0x10;
4349 		if (!conf_is_ht40(conf)) {
4350 			if (rt2x00_rt(rt2x00dev, RT6352) &&
4351 			    rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4352 				reg |= 0x5;
4353 			} else {
4354 				reg |= 0xa;
4355 			}
4356 		}
4357 		rt2800_bbp_write(rt2x00dev, 195, 141);
4358 		rt2800_bbp_write(rt2x00dev, 196, reg);
4359 
4360 		/* AGC init.
4361 		 * Despite the vendor driver using different values here for
4362 		 * RT6352 chip, we use 0x1c for now. This may have to be changed
4363 		 * once TSSI got implemented.
4364 		 */
4365 		reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
4366 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4367 
4368 		rt2800_iq_calibrate(rt2x00dev, rf->channel);
4369 	}
4370 
4371 	bbp = rt2800_bbp_read(rt2x00dev, 4);
4372 	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
4373 	rt2800_bbp_write(rt2x00dev, 4, bbp);
4374 
4375 	bbp = rt2800_bbp_read(rt2x00dev, 3);
4376 	rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
4377 	rt2800_bbp_write(rt2x00dev, 3, bbp);
4378 
4379 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4380 		if (conf_is_ht40(conf)) {
4381 			rt2800_bbp_write(rt2x00dev, 69, 0x1a);
4382 			rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4383 			rt2800_bbp_write(rt2x00dev, 73, 0x16);
4384 		} else {
4385 			rt2800_bbp_write(rt2x00dev, 69, 0x16);
4386 			rt2800_bbp_write(rt2x00dev, 70, 0x08);
4387 			rt2800_bbp_write(rt2x00dev, 73, 0x11);
4388 		}
4389 	}
4390 
4391 	usleep_range(1000, 1500);
4392 
4393 	/*
4394 	 * Clear channel statistic counters
4395 	 */
4396 	reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
4397 	reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
4398 	reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
4399 
4400 	/*
4401 	 * Clear update flag
4402 	 */
4403 	if (rt2x00_rt(rt2x00dev, RT3352) ||
4404 	    rt2x00_rt(rt2x00dev, RT5350)) {
4405 		bbp = rt2800_bbp_read(rt2x00dev, 49);
4406 		rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
4407 		rt2800_bbp_write(rt2x00dev, 49, bbp);
4408 	}
4409 }
4410 
4411 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
4412 {
4413 	u8 tssi_bounds[9];
4414 	u8 current_tssi;
4415 	u16 eeprom;
4416 	u8 step;
4417 	int i;
4418 
4419 	/*
4420 	 * First check if temperature compensation is supported.
4421 	 */
4422 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
4423 	if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
4424 		return 0;
4425 
4426 	/*
4427 	 * Read TSSI boundaries for temperature compensation from
4428 	 * the EEPROM.
4429 	 *
4430 	 * Array idx               0    1    2    3    4    5    6    7    8
4431 	 * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
4432 	 * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
4433 	 */
4434 	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
4435 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
4436 		tssi_bounds[0] = rt2x00_get_field16(eeprom,
4437 					EEPROM_TSSI_BOUND_BG1_MINUS4);
4438 		tssi_bounds[1] = rt2x00_get_field16(eeprom,
4439 					EEPROM_TSSI_BOUND_BG1_MINUS3);
4440 
4441 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
4442 		tssi_bounds[2] = rt2x00_get_field16(eeprom,
4443 					EEPROM_TSSI_BOUND_BG2_MINUS2);
4444 		tssi_bounds[3] = rt2x00_get_field16(eeprom,
4445 					EEPROM_TSSI_BOUND_BG2_MINUS1);
4446 
4447 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
4448 		tssi_bounds[4] = rt2x00_get_field16(eeprom,
4449 					EEPROM_TSSI_BOUND_BG3_REF);
4450 		tssi_bounds[5] = rt2x00_get_field16(eeprom,
4451 					EEPROM_TSSI_BOUND_BG3_PLUS1);
4452 
4453 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
4454 		tssi_bounds[6] = rt2x00_get_field16(eeprom,
4455 					EEPROM_TSSI_BOUND_BG4_PLUS2);
4456 		tssi_bounds[7] = rt2x00_get_field16(eeprom,
4457 					EEPROM_TSSI_BOUND_BG4_PLUS3);
4458 
4459 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
4460 		tssi_bounds[8] = rt2x00_get_field16(eeprom,
4461 					EEPROM_TSSI_BOUND_BG5_PLUS4);
4462 
4463 		step = rt2x00_get_field16(eeprom,
4464 					  EEPROM_TSSI_BOUND_BG5_AGC_STEP);
4465 	} else {
4466 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
4467 		tssi_bounds[0] = rt2x00_get_field16(eeprom,
4468 					EEPROM_TSSI_BOUND_A1_MINUS4);
4469 		tssi_bounds[1] = rt2x00_get_field16(eeprom,
4470 					EEPROM_TSSI_BOUND_A1_MINUS3);
4471 
4472 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
4473 		tssi_bounds[2] = rt2x00_get_field16(eeprom,
4474 					EEPROM_TSSI_BOUND_A2_MINUS2);
4475 		tssi_bounds[3] = rt2x00_get_field16(eeprom,
4476 					EEPROM_TSSI_BOUND_A2_MINUS1);
4477 
4478 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
4479 		tssi_bounds[4] = rt2x00_get_field16(eeprom,
4480 					EEPROM_TSSI_BOUND_A3_REF);
4481 		tssi_bounds[5] = rt2x00_get_field16(eeprom,
4482 					EEPROM_TSSI_BOUND_A3_PLUS1);
4483 
4484 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
4485 		tssi_bounds[6] = rt2x00_get_field16(eeprom,
4486 					EEPROM_TSSI_BOUND_A4_PLUS2);
4487 		tssi_bounds[7] = rt2x00_get_field16(eeprom,
4488 					EEPROM_TSSI_BOUND_A4_PLUS3);
4489 
4490 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
4491 		tssi_bounds[8] = rt2x00_get_field16(eeprom,
4492 					EEPROM_TSSI_BOUND_A5_PLUS4);
4493 
4494 		step = rt2x00_get_field16(eeprom,
4495 					  EEPROM_TSSI_BOUND_A5_AGC_STEP);
4496 	}
4497 
4498 	/*
4499 	 * Check if temperature compensation is supported.
4500 	 */
4501 	if (tssi_bounds[4] == 0xff || step == 0xff)
4502 		return 0;
4503 
4504 	/*
4505 	 * Read current TSSI (BBP 49).
4506 	 */
4507 	current_tssi = rt2800_bbp_read(rt2x00dev, 49);
4508 
4509 	/*
4510 	 * Compare TSSI value (BBP49) with the compensation boundaries
4511 	 * from the EEPROM and increase or decrease tx power.
4512 	 */
4513 	for (i = 0; i <= 3; i++) {
4514 		if (current_tssi > tssi_bounds[i])
4515 			break;
4516 	}
4517 
4518 	if (i == 4) {
4519 		for (i = 8; i >= 5; i--) {
4520 			if (current_tssi < tssi_bounds[i])
4521 				break;
4522 		}
4523 	}
4524 
4525 	return (i - 4) * step;
4526 }
4527 
4528 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
4529 				      enum nl80211_band band)
4530 {
4531 	u16 eeprom;
4532 	u8 comp_en;
4533 	u8 comp_type;
4534 	int comp_value = 0;
4535 
4536 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4537 
4538 	/*
4539 	 * HT40 compensation not required.
4540 	 */
4541 	if (eeprom == 0xffff ||
4542 	    !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4543 		return 0;
4544 
4545 	if (band == NL80211_BAND_2GHZ) {
4546 		comp_en = rt2x00_get_field16(eeprom,
4547 				 EEPROM_TXPOWER_DELTA_ENABLE_2G);
4548 		if (comp_en) {
4549 			comp_type = rt2x00_get_field16(eeprom,
4550 					   EEPROM_TXPOWER_DELTA_TYPE_2G);
4551 			comp_value = rt2x00_get_field16(eeprom,
4552 					    EEPROM_TXPOWER_DELTA_VALUE_2G);
4553 			if (!comp_type)
4554 				comp_value = -comp_value;
4555 		}
4556 	} else {
4557 		comp_en = rt2x00_get_field16(eeprom,
4558 				 EEPROM_TXPOWER_DELTA_ENABLE_5G);
4559 		if (comp_en) {
4560 			comp_type = rt2x00_get_field16(eeprom,
4561 					   EEPROM_TXPOWER_DELTA_TYPE_5G);
4562 			comp_value = rt2x00_get_field16(eeprom,
4563 					    EEPROM_TXPOWER_DELTA_VALUE_5G);
4564 			if (!comp_type)
4565 				comp_value = -comp_value;
4566 		}
4567 	}
4568 
4569 	return comp_value;
4570 }
4571 
4572 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4573 					int power_level, int max_power)
4574 {
4575 	int delta;
4576 
4577 	if (rt2x00_has_cap_power_limit(rt2x00dev))
4578 		return 0;
4579 
4580 	/*
4581 	 * XXX: We don't know the maximum transmit power of our hardware since
4582 	 * the EEPROM doesn't expose it. We only know that we are calibrated
4583 	 * to 100% tx power.
4584 	 *
4585 	 * Hence, we assume the regulatory limit that cfg80211 calulated for
4586 	 * the current channel is our maximum and if we are requested to lower
4587 	 * the value we just reduce our tx power accordingly.
4588 	 */
4589 	delta = power_level - max_power;
4590 	return min(delta, 0);
4591 }
4592 
4593 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4594 				   enum nl80211_band band, int power_level,
4595 				   u8 txpower, int delta)
4596 {
4597 	u16 eeprom;
4598 	u8 criterion;
4599 	u8 eirp_txpower;
4600 	u8 eirp_txpower_criterion;
4601 	u8 reg_limit;
4602 
4603 	if (rt2x00_rt(rt2x00dev, RT3593))
4604 		return min_t(u8, txpower, 0xc);
4605 
4606 	if (rt2x00_rt(rt2x00dev, RT3883))
4607 		return min_t(u8, txpower, 0xf);
4608 
4609 	if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4610 		/*
4611 		 * Check if eirp txpower exceed txpower_limit.
4612 		 * We use OFDM 6M as criterion and its eirp txpower
4613 		 * is stored at EEPROM_EIRP_MAX_TX_POWER.
4614 		 * .11b data rate need add additional 4dbm
4615 		 * when calculating eirp txpower.
4616 		 */
4617 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4618 						       EEPROM_TXPOWER_BYRATE,
4619 						       1);
4620 		criterion = rt2x00_get_field16(eeprom,
4621 					       EEPROM_TXPOWER_BYRATE_RATE0);
4622 
4623 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4624 
4625 		if (band == NL80211_BAND_2GHZ)
4626 			eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4627 						 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
4628 		else
4629 			eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4630 						 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
4631 
4632 		eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
4633 			       (is_rate_b ? 4 : 0) + delta;
4634 
4635 		reg_limit = (eirp_txpower > power_level) ?
4636 					(eirp_txpower - power_level) : 0;
4637 	} else
4638 		reg_limit = 0;
4639 
4640 	txpower = max(0, txpower + delta - reg_limit);
4641 	return min_t(u8, txpower, 0xc);
4642 }
4643 
4644 
4645 enum {
4646 	TX_PWR_CFG_0_IDX,
4647 	TX_PWR_CFG_1_IDX,
4648 	TX_PWR_CFG_2_IDX,
4649 	TX_PWR_CFG_3_IDX,
4650 	TX_PWR_CFG_4_IDX,
4651 	TX_PWR_CFG_5_IDX,
4652 	TX_PWR_CFG_6_IDX,
4653 	TX_PWR_CFG_7_IDX,
4654 	TX_PWR_CFG_8_IDX,
4655 	TX_PWR_CFG_9_IDX,
4656 	TX_PWR_CFG_0_EXT_IDX,
4657 	TX_PWR_CFG_1_EXT_IDX,
4658 	TX_PWR_CFG_2_EXT_IDX,
4659 	TX_PWR_CFG_3_EXT_IDX,
4660 	TX_PWR_CFG_4_EXT_IDX,
4661 	TX_PWR_CFG_IDX_COUNT,
4662 };
4663 
4664 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4665 					 struct ieee80211_channel *chan,
4666 					 int power_level)
4667 {
4668 	u8 txpower;
4669 	u16 eeprom;
4670 	u32 regs[TX_PWR_CFG_IDX_COUNT];
4671 	unsigned int offset;
4672 	enum nl80211_band band = chan->band;
4673 	int delta;
4674 	int i;
4675 
4676 	memset(regs, '\0', sizeof(regs));
4677 
4678 	/* TODO: adapt TX power reduction from the rt28xx code */
4679 
4680 	/* calculate temperature compensation delta */
4681 	delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4682 
4683 	if (band == NL80211_BAND_5GHZ)
4684 		offset = 16;
4685 	else
4686 		offset = 0;
4687 
4688 	if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4689 		offset += 8;
4690 
4691 	/* read the next four txpower values */
4692 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4693 					       offset);
4694 
4695 	/* CCK 1MBS,2MBS */
4696 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4697 	txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4698 					    txpower, delta);
4699 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4700 			   TX_PWR_CFG_0_CCK1_CH0, txpower);
4701 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4702 			   TX_PWR_CFG_0_CCK1_CH1, txpower);
4703 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4704 			   TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
4705 
4706 	/* CCK 5.5MBS,11MBS */
4707 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4708 	txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4709 					    txpower, delta);
4710 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4711 			   TX_PWR_CFG_0_CCK5_CH0, txpower);
4712 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4713 			   TX_PWR_CFG_0_CCK5_CH1, txpower);
4714 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4715 			   TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
4716 
4717 	/* OFDM 6MBS,9MBS */
4718 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4719 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4720 					    txpower, delta);
4721 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4722 			   TX_PWR_CFG_0_OFDM6_CH0, txpower);
4723 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4724 			   TX_PWR_CFG_0_OFDM6_CH1, txpower);
4725 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4726 			   TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
4727 
4728 	/* OFDM 12MBS,18MBS */
4729 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4730 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4731 					    txpower, delta);
4732 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4733 			   TX_PWR_CFG_0_OFDM12_CH0, txpower);
4734 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4735 			   TX_PWR_CFG_0_OFDM12_CH1, txpower);
4736 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4737 			   TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
4738 
4739 	/* read the next four txpower values */
4740 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4741 					       offset + 1);
4742 
4743 	/* OFDM 24MBS,36MBS */
4744 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4745 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4746 					    txpower, delta);
4747 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4748 			   TX_PWR_CFG_1_OFDM24_CH0, txpower);
4749 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4750 			   TX_PWR_CFG_1_OFDM24_CH1, txpower);
4751 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4752 			   TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
4753 
4754 	/* OFDM 48MBS */
4755 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4756 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4757 					    txpower, delta);
4758 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4759 			   TX_PWR_CFG_1_OFDM48_CH0, txpower);
4760 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4761 			   TX_PWR_CFG_1_OFDM48_CH1, txpower);
4762 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4763 			   TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
4764 
4765 	/* OFDM 54MBS */
4766 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4767 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4768 					    txpower, delta);
4769 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4770 			   TX_PWR_CFG_7_OFDM54_CH0, txpower);
4771 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4772 			   TX_PWR_CFG_7_OFDM54_CH1, txpower);
4773 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4774 			   TX_PWR_CFG_7_OFDM54_CH2, txpower);
4775 
4776 	/* read the next four txpower values */
4777 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4778 					       offset + 2);
4779 
4780 	/* MCS 0,1 */
4781 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4782 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4783 					    txpower, delta);
4784 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4785 			   TX_PWR_CFG_1_MCS0_CH0, txpower);
4786 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4787 			   TX_PWR_CFG_1_MCS0_CH1, txpower);
4788 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4789 			   TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
4790 
4791 	/* MCS 2,3 */
4792 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4793 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4794 					    txpower, delta);
4795 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4796 			   TX_PWR_CFG_1_MCS2_CH0, txpower);
4797 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4798 			   TX_PWR_CFG_1_MCS2_CH1, txpower);
4799 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4800 			   TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
4801 
4802 	/* MCS 4,5 */
4803 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4804 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4805 					    txpower, delta);
4806 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4807 			   TX_PWR_CFG_2_MCS4_CH0, txpower);
4808 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4809 			   TX_PWR_CFG_2_MCS4_CH1, txpower);
4810 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4811 			   TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
4812 
4813 	/* MCS 6 */
4814 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4815 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4816 					    txpower, delta);
4817 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4818 			   TX_PWR_CFG_2_MCS6_CH0, txpower);
4819 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4820 			   TX_PWR_CFG_2_MCS6_CH1, txpower);
4821 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4822 			   TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
4823 
4824 	/* read the next four txpower values */
4825 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4826 					       offset + 3);
4827 
4828 	/* MCS 7 */
4829 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4830 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4831 					    txpower, delta);
4832 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4833 			   TX_PWR_CFG_7_MCS7_CH0, txpower);
4834 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4835 			   TX_PWR_CFG_7_MCS7_CH1, txpower);
4836 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4837 			   TX_PWR_CFG_7_MCS7_CH2, txpower);
4838 
4839 	/* MCS 8,9 */
4840 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4841 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4842 					    txpower, delta);
4843 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4844 			   TX_PWR_CFG_2_MCS8_CH0, txpower);
4845 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4846 			   TX_PWR_CFG_2_MCS8_CH1, txpower);
4847 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4848 			   TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
4849 
4850 	/* MCS 10,11 */
4851 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4852 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4853 					    txpower, delta);
4854 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4855 			   TX_PWR_CFG_2_MCS10_CH0, txpower);
4856 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4857 			   TX_PWR_CFG_2_MCS10_CH1, txpower);
4858 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4859 			   TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
4860 
4861 	/* MCS 12,13 */
4862 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4863 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4864 					    txpower, delta);
4865 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4866 			   TX_PWR_CFG_3_MCS12_CH0, txpower);
4867 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4868 			   TX_PWR_CFG_3_MCS12_CH1, txpower);
4869 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4870 			   TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
4871 
4872 	/* read the next four txpower values */
4873 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4874 					       offset + 4);
4875 
4876 	/* MCS 14 */
4877 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4878 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4879 					    txpower, delta);
4880 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4881 			   TX_PWR_CFG_3_MCS14_CH0, txpower);
4882 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4883 			   TX_PWR_CFG_3_MCS14_CH1, txpower);
4884 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4885 			   TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
4886 
4887 	/* MCS 15 */
4888 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4889 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4890 					    txpower, delta);
4891 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4892 			   TX_PWR_CFG_8_MCS15_CH0, txpower);
4893 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4894 			   TX_PWR_CFG_8_MCS15_CH1, txpower);
4895 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4896 			   TX_PWR_CFG_8_MCS15_CH2, txpower);
4897 
4898 	/* MCS 16,17 */
4899 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4900 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4901 					    txpower, delta);
4902 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4903 			   TX_PWR_CFG_5_MCS16_CH0, txpower);
4904 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4905 			   TX_PWR_CFG_5_MCS16_CH1, txpower);
4906 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4907 			   TX_PWR_CFG_5_MCS16_CH2, txpower);
4908 
4909 	/* MCS 18,19 */
4910 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4911 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4912 					    txpower, delta);
4913 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4914 			   TX_PWR_CFG_5_MCS18_CH0, txpower);
4915 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4916 			   TX_PWR_CFG_5_MCS18_CH1, txpower);
4917 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4918 			   TX_PWR_CFG_5_MCS18_CH2, txpower);
4919 
4920 	/* read the next four txpower values */
4921 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4922 					       offset + 5);
4923 
4924 	/* MCS 20,21 */
4925 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4926 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4927 					    txpower, delta);
4928 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4929 			   TX_PWR_CFG_6_MCS20_CH0, txpower);
4930 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4931 			   TX_PWR_CFG_6_MCS20_CH1, txpower);
4932 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4933 			   TX_PWR_CFG_6_MCS20_CH2, txpower);
4934 
4935 	/* MCS 22 */
4936 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4937 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4938 					    txpower, delta);
4939 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4940 			   TX_PWR_CFG_6_MCS22_CH0, txpower);
4941 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4942 			   TX_PWR_CFG_6_MCS22_CH1, txpower);
4943 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4944 			   TX_PWR_CFG_6_MCS22_CH2, txpower);
4945 
4946 	/* MCS 23 */
4947 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4948 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4949 					    txpower, delta);
4950 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4951 			   TX_PWR_CFG_8_MCS23_CH0, txpower);
4952 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4953 			   TX_PWR_CFG_8_MCS23_CH1, txpower);
4954 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4955 			   TX_PWR_CFG_8_MCS23_CH2, txpower);
4956 
4957 	/* read the next four txpower values */
4958 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4959 					       offset + 6);
4960 
4961 	/* STBC, MCS 0,1 */
4962 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4963 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4964 					    txpower, delta);
4965 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4966 			   TX_PWR_CFG_3_STBC0_CH0, txpower);
4967 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4968 			   TX_PWR_CFG_3_STBC0_CH1, txpower);
4969 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4970 			   TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4971 
4972 	/* STBC, MCS 2,3 */
4973 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4974 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4975 					    txpower, delta);
4976 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4977 			   TX_PWR_CFG_3_STBC2_CH0, txpower);
4978 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4979 			   TX_PWR_CFG_3_STBC2_CH1, txpower);
4980 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4981 			   TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4982 
4983 	/* STBC, MCS 4,5 */
4984 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4985 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4986 					    txpower, delta);
4987 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4988 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4989 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4990 			   txpower);
4991 
4992 	/* STBC, MCS 6 */
4993 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4994 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4995 					    txpower, delta);
4996 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4997 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4998 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4999 			   txpower);
5000 
5001 	/* read the next four txpower values */
5002 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5003 					       offset + 7);
5004 
5005 	/* STBC, MCS 7 */
5006 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
5007 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5008 					    txpower, delta);
5009 	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5010 			   TX_PWR_CFG_9_STBC7_CH0, txpower);
5011 	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5012 			   TX_PWR_CFG_9_STBC7_CH1, txpower);
5013 	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5014 			   TX_PWR_CFG_9_STBC7_CH2, txpower);
5015 
5016 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
5017 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
5018 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
5019 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
5020 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
5021 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
5022 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
5023 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
5024 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
5025 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
5026 
5027 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
5028 			      regs[TX_PWR_CFG_0_EXT_IDX]);
5029 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
5030 			      regs[TX_PWR_CFG_1_EXT_IDX]);
5031 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
5032 			      regs[TX_PWR_CFG_2_EXT_IDX]);
5033 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
5034 			      regs[TX_PWR_CFG_3_EXT_IDX]);
5035 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
5036 			      regs[TX_PWR_CFG_4_EXT_IDX]);
5037 
5038 	for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
5039 		rt2x00_dbg(rt2x00dev,
5040 			   "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
5041 			   (band == NL80211_BAND_5GHZ) ? '5' : '2',
5042 			   (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
5043 								'4' : '2',
5044 			   (i > TX_PWR_CFG_9_IDX) ?
5045 					(i - TX_PWR_CFG_9_IDX - 1) : i,
5046 			   (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
5047 			   (unsigned long) regs[i]);
5048 }
5049 
5050 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
5051 					 struct ieee80211_channel *chan,
5052 					 int power_level)
5053 {
5054 	u32 reg, pwreg;
5055 	u16 eeprom;
5056 	u32 data, gdata;
5057 	u8 t, i;
5058 	enum nl80211_band band = chan->band;
5059 	int delta;
5060 
5061 	/* Warn user if bw_comp is set in EEPROM */
5062 	delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5063 
5064 	if (delta)
5065 		rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
5066 			    delta);
5067 
5068 	/* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
5069 	 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
5070 	 * driver does as well, though it looks kinda wrong.
5071 	 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
5072 	 * the hardware has a problem handling 0x20, and as the code initially
5073 	 * used a fixed offset between HT20 and HT40 rates they had to work-
5074 	 * around that issue and most likely just forgot about it later on.
5075 	 * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
5076 	 * however, the corresponding EEPROM value is not respected by the
5077 	 * vendor driver, so maybe this is rather being taken care of the
5078 	 * TXALC and the driver doesn't need to handle it...?
5079 	 * Though this is all very awkward, just do as they did, as that's what
5080 	 * board vendors expected when they populated the EEPROM...
5081 	 */
5082 	for (i = 0; i < 5; i++) {
5083 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5084 						       EEPROM_TXPOWER_BYRATE,
5085 						       i * 2);
5086 
5087 		data = eeprom;
5088 
5089 		t = eeprom & 0x3f;
5090 		if (t == 32)
5091 			t++;
5092 
5093 		gdata = t;
5094 
5095 		t = (eeprom & 0x3f00) >> 8;
5096 		if (t == 32)
5097 			t++;
5098 
5099 		gdata |= (t << 8);
5100 
5101 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5102 						       EEPROM_TXPOWER_BYRATE,
5103 						       (i * 2) + 1);
5104 
5105 		t = eeprom & 0x3f;
5106 		if (t == 32)
5107 			t++;
5108 
5109 		gdata |= (t << 16);
5110 
5111 		t = (eeprom & 0x3f00) >> 8;
5112 		if (t == 32)
5113 			t++;
5114 
5115 		gdata |= (t << 24);
5116 		data |= (eeprom << 16);
5117 
5118 		if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
5119 			/* HT20 */
5120 			if (data != 0xffffffff)
5121 				rt2800_register_write(rt2x00dev,
5122 						      TX_PWR_CFG_0 + (i * 4),
5123 						      data);
5124 		} else {
5125 			/* HT40 */
5126 			if (gdata != 0xffffffff)
5127 				rt2800_register_write(rt2x00dev,
5128 						      TX_PWR_CFG_0 + (i * 4),
5129 						      gdata);
5130 		}
5131 	}
5132 
5133 	/* Aparently Ralink ran out of space in the BYRATE calibration section
5134 	 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
5135 	 * registers. As recent 2T chips use 8-bit instead of 4-bit values for
5136 	 * power-offsets more space would be needed. Ralink decided to keep the
5137 	 * EEPROM layout untouched and rather have some shared values covering
5138 	 * multiple bitrates.
5139 	 * Populate the registers not covered by the EEPROM in the same way the
5140 	 * vendor driver does.
5141 	 */
5142 
5143 	/* For OFDM 54MBS use value from OFDM 48MBS */
5144 	pwreg = 0;
5145 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
5146 	t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
5147 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
5148 
5149 	/* For MCS 7 use value from MCS 6 */
5150 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
5151 	t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
5152 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
5153 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
5154 
5155 	/* For MCS 15 use value from MCS 14 */
5156 	pwreg = 0;
5157 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
5158 	t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
5159 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
5160 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
5161 
5162 	/* For STBC MCS 7 use value from STBC MCS 6 */
5163 	pwreg = 0;
5164 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
5165 	t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
5166 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
5167 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
5168 
5169 	rt2800_config_alc(rt2x00dev, chan, power_level);
5170 
5171 	/* TODO: temperature compensation code! */
5172 }
5173 
5174 /*
5175  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
5176  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
5177  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
5178  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
5179  * Reference per rate transmit power values are located in the EEPROM at
5180  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
5181  * current conditions (i.e. band, bandwidth, temperature, user settings).
5182  */
5183 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
5184 					 struct ieee80211_channel *chan,
5185 					 int power_level)
5186 {
5187 	u8 txpower, r1;
5188 	u16 eeprom;
5189 	u32 reg, offset;
5190 	int i, is_rate_b, delta, power_ctrl;
5191 	enum nl80211_band band = chan->band;
5192 
5193 	/*
5194 	 * Calculate HT40 compensation. For 40MHz we need to add or subtract
5195 	 * value read from EEPROM (different for 2GHz and for 5GHz).
5196 	 */
5197 	delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5198 
5199 	/*
5200 	 * Calculate temperature compensation. Depends on measurement of current
5201 	 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
5202 	 * to temperature or maybe other factors) is smaller or bigger than
5203 	 * expected. We adjust it, based on TSSI reference and boundaries values
5204 	 * provided in EEPROM.
5205 	 */
5206 	switch (rt2x00dev->chip.rt) {
5207 	case RT2860:
5208 	case RT2872:
5209 	case RT2883:
5210 	case RT3070:
5211 	case RT3071:
5212 	case RT3090:
5213 	case RT3572:
5214 		delta += rt2800_get_gain_calibration_delta(rt2x00dev);
5215 		break;
5216 	default:
5217 		/* TODO: temperature compensation code for other chips. */
5218 		break;
5219 	}
5220 
5221 	/*
5222 	 * Decrease power according to user settings, on devices with unknown
5223 	 * maximum tx power. For other devices we take user power_level into
5224 	 * consideration on rt2800_compensate_txpower().
5225 	 */
5226 	delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
5227 					      chan->max_power);
5228 
5229 	/*
5230 	 * BBP_R1 controls TX power for all rates, it allow to set the following
5231 	 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
5232 	 *
5233 	 * TODO: we do not use +6 dBm option to do not increase power beyond
5234 	 * regulatory limit, however this could be utilized for devices with
5235 	 * CAPABILITY_POWER_LIMIT.
5236 	 */
5237 	if (delta <= -12) {
5238 		power_ctrl = 2;
5239 		delta += 12;
5240 	} else if (delta <= -6) {
5241 		power_ctrl = 1;
5242 		delta += 6;
5243 	} else {
5244 		power_ctrl = 0;
5245 	}
5246 	r1 = rt2800_bbp_read(rt2x00dev, 1);
5247 	rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
5248 	rt2800_bbp_write(rt2x00dev, 1, r1);
5249 
5250 	offset = TX_PWR_CFG_0;
5251 
5252 	for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
5253 		/* just to be safe */
5254 		if (offset > TX_PWR_CFG_4)
5255 			break;
5256 
5257 		reg = rt2800_register_read(rt2x00dev, offset);
5258 
5259 		/* read the next four txpower values */
5260 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5261 						       EEPROM_TXPOWER_BYRATE,
5262 						       i);
5263 
5264 		is_rate_b = i ? 0 : 1;
5265 		/*
5266 		 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5267 		 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
5268 		 * TX_PWR_CFG_4: unknown
5269 		 */
5270 		txpower = rt2x00_get_field16(eeprom,
5271 					     EEPROM_TXPOWER_BYRATE_RATE0);
5272 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5273 					     power_level, txpower, delta);
5274 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5275 
5276 		/*
5277 		 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5278 		 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
5279 		 * TX_PWR_CFG_4: unknown
5280 		 */
5281 		txpower = rt2x00_get_field16(eeprom,
5282 					     EEPROM_TXPOWER_BYRATE_RATE1);
5283 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5284 					     power_level, txpower, delta);
5285 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5286 
5287 		/*
5288 		 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5289 		 * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
5290 		 * TX_PWR_CFG_4: unknown
5291 		 */
5292 		txpower = rt2x00_get_field16(eeprom,
5293 					     EEPROM_TXPOWER_BYRATE_RATE2);
5294 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5295 					     power_level, txpower, delta);
5296 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5297 
5298 		/*
5299 		 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5300 		 * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
5301 		 * TX_PWR_CFG_4: unknown
5302 		 */
5303 		txpower = rt2x00_get_field16(eeprom,
5304 					     EEPROM_TXPOWER_BYRATE_RATE3);
5305 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5306 					     power_level, txpower, delta);
5307 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5308 
5309 		/* read the next four txpower values */
5310 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5311 						       EEPROM_TXPOWER_BYRATE,
5312 						       i + 1);
5313 
5314 		is_rate_b = 0;
5315 		/*
5316 		 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5317 		 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
5318 		 * TX_PWR_CFG_4: unknown
5319 		 */
5320 		txpower = rt2x00_get_field16(eeprom,
5321 					     EEPROM_TXPOWER_BYRATE_RATE0);
5322 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5323 					     power_level, txpower, delta);
5324 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5325 
5326 		/*
5327 		 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5328 		 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
5329 		 * TX_PWR_CFG_4: unknown
5330 		 */
5331 		txpower = rt2x00_get_field16(eeprom,
5332 					     EEPROM_TXPOWER_BYRATE_RATE1);
5333 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5334 					     power_level, txpower, delta);
5335 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5336 
5337 		/*
5338 		 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5339 		 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
5340 		 * TX_PWR_CFG_4: unknown
5341 		 */
5342 		txpower = rt2x00_get_field16(eeprom,
5343 					     EEPROM_TXPOWER_BYRATE_RATE2);
5344 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5345 					     power_level, txpower, delta);
5346 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5347 
5348 		/*
5349 		 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5350 		 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
5351 		 * TX_PWR_CFG_4: unknown
5352 		 */
5353 		txpower = rt2x00_get_field16(eeprom,
5354 					     EEPROM_TXPOWER_BYRATE_RATE3);
5355 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5356 					     power_level, txpower, delta);
5357 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5358 
5359 		rt2800_register_write(rt2x00dev, offset, reg);
5360 
5361 		/* next TX_PWR_CFG register */
5362 		offset += 4;
5363 	}
5364 }
5365 
5366 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5367 				  struct ieee80211_channel *chan,
5368 				  int power_level)
5369 {
5370 	if (rt2x00_rt(rt2x00dev, RT3593) ||
5371 	    rt2x00_rt(rt2x00dev, RT3883))
5372 		rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
5373 	else if (rt2x00_rt(rt2x00dev, RT6352))
5374 		rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
5375 	else
5376 		rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
5377 }
5378 
5379 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
5380 {
5381 	rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
5382 			      rt2x00dev->tx_power);
5383 }
5384 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
5385 
5386 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
5387 {
5388 	u32	tx_pin;
5389 	u8	rfcsr;
5390 	unsigned long min_sleep = 0;
5391 
5392 	/*
5393 	 * A voltage-controlled oscillator(VCO) is an electronic oscillator
5394 	 * designed to be controlled in oscillation frequency by a voltage
5395 	 * input. Maybe the temperature will affect the frequency of
5396 	 * oscillation to be shifted. The VCO calibration will be called
5397 	 * periodically to adjust the frequency to be precision.
5398 	*/
5399 
5400 	tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5401 	tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
5402 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5403 
5404 	switch (rt2x00dev->chip.rf) {
5405 	case RF2020:
5406 	case RF3020:
5407 	case RF3021:
5408 	case RF3022:
5409 	case RF3320:
5410 	case RF3052:
5411 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
5412 		rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
5413 		rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
5414 		break;
5415 	case RF3053:
5416 	case RF3070:
5417 	case RF3290:
5418 	case RF3853:
5419 	case RF5350:
5420 	case RF5360:
5421 	case RF5362:
5422 	case RF5370:
5423 	case RF5372:
5424 	case RF5390:
5425 	case RF5392:
5426 	case RF5592:
5427 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
5428 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
5429 		rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
5430 		min_sleep = 1000;
5431 		break;
5432 	case RF7620:
5433 		rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
5434 		rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
5435 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
5436 		rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
5437 		rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
5438 		min_sleep = 2000;
5439 		break;
5440 	default:
5441 		WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration",
5442 			  rt2x00dev->chip.rf);
5443 		return;
5444 	}
5445 
5446 	if (min_sleep > 0)
5447 		usleep_range(min_sleep, min_sleep * 2);
5448 
5449 	tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5450 	if (rt2x00dev->rf_channel <= 14) {
5451 		switch (rt2x00dev->default_ant.tx_chain_num) {
5452 		case 3:
5453 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
5454 			fallthrough;
5455 		case 2:
5456 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
5457 			fallthrough;
5458 		case 1:
5459 		default:
5460 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
5461 			break;
5462 		}
5463 	} else {
5464 		switch (rt2x00dev->default_ant.tx_chain_num) {
5465 		case 3:
5466 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
5467 			fallthrough;
5468 		case 2:
5469 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
5470 			fallthrough;
5471 		case 1:
5472 		default:
5473 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
5474 			break;
5475 		}
5476 	}
5477 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5478 
5479 	if (rt2x00_rt(rt2x00dev, RT6352)) {
5480 		if (rt2x00dev->default_ant.rx_chain_num == 1) {
5481 			rt2800_bbp_write(rt2x00dev, 91, 0x07);
5482 			rt2800_bbp_write(rt2x00dev, 95, 0x1A);
5483 			rt2800_bbp_write(rt2x00dev, 195, 128);
5484 			rt2800_bbp_write(rt2x00dev, 196, 0xA0);
5485 			rt2800_bbp_write(rt2x00dev, 195, 170);
5486 			rt2800_bbp_write(rt2x00dev, 196, 0x12);
5487 			rt2800_bbp_write(rt2x00dev, 195, 171);
5488 			rt2800_bbp_write(rt2x00dev, 196, 0x10);
5489 		} else {
5490 			rt2800_bbp_write(rt2x00dev, 91, 0x06);
5491 			rt2800_bbp_write(rt2x00dev, 95, 0x9A);
5492 			rt2800_bbp_write(rt2x00dev, 195, 128);
5493 			rt2800_bbp_write(rt2x00dev, 196, 0xE0);
5494 			rt2800_bbp_write(rt2x00dev, 195, 170);
5495 			rt2800_bbp_write(rt2x00dev, 196, 0x30);
5496 			rt2800_bbp_write(rt2x00dev, 195, 171);
5497 			rt2800_bbp_write(rt2x00dev, 196, 0x30);
5498 		}
5499 
5500 		if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
5501 			rt2800_bbp_write(rt2x00dev, 75, 0x68);
5502 			rt2800_bbp_write(rt2x00dev, 76, 0x4C);
5503 			rt2800_bbp_write(rt2x00dev, 79, 0x1C);
5504 			rt2800_bbp_write(rt2x00dev, 80, 0x0C);
5505 			rt2800_bbp_write(rt2x00dev, 82, 0xB6);
5506 		}
5507 
5508 		/* On 11A, We should delay and wait RF/BBP to be stable
5509 		 * and the appropriate time should be 1000 micro seconds
5510 		 * 2005/06/05 - On 11G, we also need this delay time.
5511 		 * Otherwise it's difficult to pass the WHQL.
5512 		 */
5513 		usleep_range(1000, 1500);
5514 	}
5515 }
5516 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
5517 
5518 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5519 				      struct rt2x00lib_conf *libconf)
5520 {
5521 	u32 reg;
5522 
5523 	reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5524 	rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
5525 			   libconf->conf->short_frame_max_tx_count);
5526 	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
5527 			   libconf->conf->long_frame_max_tx_count);
5528 	rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5529 }
5530 
5531 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
5532 			     struct rt2x00lib_conf *libconf)
5533 {
5534 	enum dev_state state =
5535 	    (libconf->conf->flags & IEEE80211_CONF_PS) ?
5536 		STATE_SLEEP : STATE_AWAKE;
5537 	u32 reg;
5538 
5539 	if (state == STATE_SLEEP) {
5540 		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5541 
5542 		reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5543 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
5544 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
5545 				   libconf->conf->listen_interval - 1);
5546 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
5547 		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5548 
5549 		rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5550 	} else {
5551 		reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5552 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
5553 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
5554 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
5555 		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5556 
5557 		rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5558 	}
5559 }
5560 
5561 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5562 		   struct rt2x00lib_conf *libconf,
5563 		   const unsigned int flags)
5564 {
5565 	/* Always recalculate LNA gain before changing configuration */
5566 	rt2800_config_lna_gain(rt2x00dev, libconf);
5567 
5568 	if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
5569 		/*
5570 		 * To provide correct survey data for survey-based ACS algorithm
5571 		 * we have to save survey data for current channel before switching.
5572 		 */
5573 		rt2800_update_survey(rt2x00dev);
5574 
5575 		rt2800_config_channel(rt2x00dev, libconf->conf,
5576 				      &libconf->rf, &libconf->channel);
5577 		rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5578 				      libconf->conf->power_level);
5579 	}
5580 	if (flags & IEEE80211_CONF_CHANGE_POWER)
5581 		rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5582 				      libconf->conf->power_level);
5583 	if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5584 		rt2800_config_retry_limit(rt2x00dev, libconf);
5585 	if (flags & IEEE80211_CONF_CHANGE_PS)
5586 		rt2800_config_ps(rt2x00dev, libconf);
5587 }
5588 EXPORT_SYMBOL_GPL(rt2800_config);
5589 
5590 /*
5591  * Link tuning
5592  */
5593 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5594 {
5595 	u32 reg;
5596 
5597 	/*
5598 	 * Update FCS error count from register.
5599 	 */
5600 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5601 	qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5602 }
5603 EXPORT_SYMBOL_GPL(rt2800_link_stats);
5604 
5605 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5606 {
5607 	u8 vgc;
5608 
5609 	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5610 		if (rt2x00_rt(rt2x00dev, RT3070) ||
5611 		    rt2x00_rt(rt2x00dev, RT3071) ||
5612 		    rt2x00_rt(rt2x00dev, RT3090) ||
5613 		    rt2x00_rt(rt2x00dev, RT3290) ||
5614 		    rt2x00_rt(rt2x00dev, RT3390) ||
5615 		    rt2x00_rt(rt2x00dev, RT3572) ||
5616 		    rt2x00_rt(rt2x00dev, RT3593) ||
5617 		    rt2x00_rt(rt2x00dev, RT5390) ||
5618 		    rt2x00_rt(rt2x00dev, RT5392) ||
5619 		    rt2x00_rt(rt2x00dev, RT5592) ||
5620 		    rt2x00_rt(rt2x00dev, RT6352))
5621 			vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5622 		else
5623 			vgc = 0x2e + rt2x00dev->lna_gain;
5624 	} else { /* 5GHZ band */
5625 		if (rt2x00_rt(rt2x00dev, RT3593) ||
5626 		    rt2x00_rt(rt2x00dev, RT3883))
5627 			vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5628 		else if (rt2x00_rt(rt2x00dev, RT5592))
5629 			vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5630 		else {
5631 			if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5632 				vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5633 			else
5634 				vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5635 		}
5636 	}
5637 
5638 	return vgc;
5639 }
5640 
5641 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5642 				  struct link_qual *qual, u8 vgc_level)
5643 {
5644 	if (qual->vgc_level != vgc_level) {
5645 		if (rt2x00_rt(rt2x00dev, RT3572) ||
5646 		    rt2x00_rt(rt2x00dev, RT3593) ||
5647 		    rt2x00_rt(rt2x00dev, RT3883)) {
5648 			rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5649 						       vgc_level);
5650 		} else if (rt2x00_rt(rt2x00dev, RT5592)) {
5651 			rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5652 			rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5653 		} else {
5654 			rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5655 		}
5656 
5657 		qual->vgc_level = vgc_level;
5658 		qual->vgc_level_reg = vgc_level;
5659 	}
5660 }
5661 
5662 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5663 {
5664 	rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5665 }
5666 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
5667 
5668 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5669 		       const u32 count)
5670 {
5671 	u8 vgc;
5672 
5673 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5674 		return;
5675 
5676 	/* When RSSI is better than a certain threshold, increase VGC
5677 	 * with a chip specific value in order to improve the balance
5678 	 * between sensibility and noise isolation.
5679 	 */
5680 
5681 	vgc = rt2800_get_default_vgc(rt2x00dev);
5682 
5683 	switch (rt2x00dev->chip.rt) {
5684 	case RT3572:
5685 	case RT3593:
5686 		if (qual->rssi > -65) {
5687 			if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5688 				vgc += 0x20;
5689 			else
5690 				vgc += 0x10;
5691 		}
5692 		break;
5693 
5694 	case RT3883:
5695 		if (qual->rssi > -65)
5696 			vgc += 0x10;
5697 		break;
5698 
5699 	case RT5592:
5700 		if (qual->rssi > -65)
5701 			vgc += 0x20;
5702 		break;
5703 
5704 	default:
5705 		if (qual->rssi > -80)
5706 			vgc += 0x10;
5707 		break;
5708 	}
5709 
5710 	rt2800_set_vgc(rt2x00dev, qual, vgc);
5711 }
5712 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
5713 
5714 /*
5715  * Initialization functions.
5716  */
5717 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5718 {
5719 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5720 	u32 reg;
5721 	u16 eeprom;
5722 	unsigned int i;
5723 	int ret;
5724 
5725 	rt2800_disable_wpdma(rt2x00dev);
5726 
5727 	ret = rt2800_drv_init_registers(rt2x00dev);
5728 	if (ret)
5729 		return ret;
5730 
5731 	rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5732 	rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5733 
5734 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5735 
5736 	reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5737 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
5738 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
5739 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
5740 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
5741 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
5742 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5743 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5744 
5745 	rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5746 
5747 	reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5748 	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
5749 	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5750 	rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5751 
5752 	if (rt2x00_rt(rt2x00dev, RT3290)) {
5753 		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5754 		if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
5755 			rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
5756 			rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5757 		}
5758 
5759 		reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5760 		if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
5761 			rt2x00_set_field32(&reg, LDO0_EN, 1);
5762 			rt2x00_set_field32(&reg, LDO_BGSEL, 3);
5763 			rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5764 		}
5765 
5766 		reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5767 		rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
5768 		rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
5769 		rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
5770 		rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5771 
5772 		reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5773 		rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
5774 		rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5775 
5776 		reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5777 		rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
5778 		rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
5779 		rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
5780 		rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
5781 		rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5782 
5783 		reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5784 		rt2x00_set_field32(&reg, PLL_CONTROL, 1);
5785 		rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5786 	}
5787 
5788 	if (rt2x00_rt(rt2x00dev, RT3071) ||
5789 	    rt2x00_rt(rt2x00dev, RT3090) ||
5790 	    rt2x00_rt(rt2x00dev, RT3290) ||
5791 	    rt2x00_rt(rt2x00dev, RT3390)) {
5792 
5793 		if (rt2x00_rt(rt2x00dev, RT3290))
5794 			rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5795 					      0x00000404);
5796 		else
5797 			rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5798 					      0x00000400);
5799 
5800 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5801 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5802 		    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5803 		    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5804 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5805 			if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5806 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5807 						      0x0000002c);
5808 			else
5809 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5810 						      0x0000000f);
5811 		} else {
5812 			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5813 		}
5814 	} else if (rt2x00_rt(rt2x00dev, RT3070)) {
5815 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5816 
5817 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5818 			rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5819 			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5820 		} else {
5821 			rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5822 			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5823 		}
5824 	} else if (rt2800_is_305x_soc(rt2x00dev)) {
5825 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5826 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5827 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5828 	} else if (rt2x00_rt(rt2x00dev, RT3352)) {
5829 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5830 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5831 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5832 	} else if (rt2x00_rt(rt2x00dev, RT3572)) {
5833 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5834 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5835 	} else if (rt2x00_rt(rt2x00dev, RT3593)) {
5836 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5837 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5838 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5839 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5840 			if (rt2x00_get_field16(eeprom,
5841 					       EEPROM_NIC_CONF1_DAC_TEST))
5842 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5843 						      0x0000001f);
5844 			else
5845 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5846 						      0x0000000f);
5847 		} else {
5848 			rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5849 					      0x00000000);
5850 		}
5851 	} else if (rt2x00_rt(rt2x00dev, RT3883)) {
5852 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5853 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5854 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
5855 		rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
5856 		rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
5857 	} else if (rt2x00_rt(rt2x00dev, RT5390) ||
5858 		   rt2x00_rt(rt2x00dev, RT5392)) {
5859 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5860 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5861 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5862 	} else if (rt2x00_rt(rt2x00dev, RT5592)) {
5863 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5864 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5865 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5866 	} else if (rt2x00_rt(rt2x00dev, RT5350)) {
5867 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5868 	} else if (rt2x00_rt(rt2x00dev, RT6352)) {
5869 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5870 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
5871 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5872 		rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
5873 		rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
5874 		rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
5875 		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
5876 		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
5877 		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
5878 				      0x3630363A);
5879 		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
5880 				      0x3630363A);
5881 		reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
5882 		rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
5883 		rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
5884 	} else {
5885 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
5886 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5887 	}
5888 
5889 	reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
5890 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5891 	rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
5892 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5893 	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
5894 	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
5895 	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5896 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
5897 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
5898 	rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
5899 
5900 	reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
5901 	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
5902 	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
5903 	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
5904 	rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5905 
5906 	reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
5907 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
5908 	if (rt2x00_is_usb(rt2x00dev)) {
5909 		drv_data->max_psdu = 3;
5910 	} else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
5911 		   rt2x00_rt(rt2x00dev, RT2883) ||
5912 		   rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
5913 		drv_data->max_psdu = 2;
5914 	} else {
5915 		drv_data->max_psdu = 1;
5916 	}
5917 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
5918 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 10);
5919 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 10);
5920 	rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5921 
5922 	reg = rt2800_register_read(rt2x00dev, LED_CFG);
5923 	rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
5924 	rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
5925 	rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
5926 	rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
5927 	rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
5928 	rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
5929 	rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
5930 	rt2800_register_write(rt2x00dev, LED_CFG, reg);
5931 
5932 	rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5933 
5934 	reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5935 	rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
5936 	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
5937 	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
5938 	rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
5939 	rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
5940 	rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
5941 	rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5942 
5943 	reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
5944 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
5945 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
5946 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
5947 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
5948 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
5949 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
5950 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
5951 	rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5952 
5953 	reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
5954 	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
5955 	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
5956 	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
5957 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5958 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5959 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5960 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5961 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5962 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5963 	rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
5964 	rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5965 
5966 	reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
5967 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
5968 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
5969 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
5970 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5971 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5972 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5973 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5974 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5975 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5976 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
5977 	rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5978 
5979 	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
5980 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
5981 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
5982 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5983 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5984 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5985 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5986 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5987 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5988 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5989 	rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
5990 	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5991 
5992 	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
5993 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
5994 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
5995 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5996 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5997 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5998 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5999 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
6000 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6001 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
6002 	rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
6003 	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6004 
6005 	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
6006 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
6007 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
6008 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
6009 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
6010 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6011 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6012 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
6013 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6014 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
6015 	rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
6016 	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6017 
6018 	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
6019 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
6020 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
6021 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
6022 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
6023 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6024 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6025 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
6026 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6027 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
6028 	rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
6029 	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6030 
6031 	if (rt2x00_is_usb(rt2x00dev)) {
6032 		rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
6033 
6034 		reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
6035 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
6036 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
6037 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
6038 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
6039 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
6040 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
6041 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
6042 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
6043 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
6044 		rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6045 	}
6046 
6047 	/*
6048 	 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
6049 	 * although it is reserved.
6050 	 */
6051 	reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
6052 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
6053 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
6054 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
6055 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
6056 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
6057 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
6058 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
6059 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
6060 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
6061 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
6062 	rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
6063 
6064 	reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
6065 	rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
6066 
6067 	if (rt2x00_rt(rt2x00dev, RT3883)) {
6068 		rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008);
6069 		rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413);
6070 	}
6071 
6072 	reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
6073 	rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
6074 	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
6075 			   IEEE80211_MAX_RTS_THRESHOLD);
6076 	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 1);
6077 	rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6078 
6079 	rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
6080 
6081 	/*
6082 	 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
6083 	 * time should be set to 16. However, the original Ralink driver uses
6084 	 * 16 for both and indeed using a value of 10 for CCK SIFS results in
6085 	 * connection problems with 11g + CTS protection. Hence, use the same
6086 	 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
6087 	 */
6088 	reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
6089 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
6090 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
6091 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
6092 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
6093 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
6094 	rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
6095 
6096 	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
6097 
6098 	/*
6099 	 * ASIC will keep garbage value after boot, clear encryption keys.
6100 	 */
6101 	for (i = 0; i < 4; i++)
6102 		rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0);
6103 
6104 	for (i = 0; i < 256; i++) {
6105 		rt2800_config_wcid(rt2x00dev, NULL, i);
6106 		rt2800_delete_wcid_attr(rt2x00dev, i);
6107 	}
6108 
6109 	/*
6110 	 * Clear encryption initialization vectors on start, but keep them
6111 	 * for watchdog reset. Otherwise we will have wrong IVs and not be
6112 	 * able to keep connections after reset.
6113 	 */
6114 	if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
6115 		for (i = 0; i < 256; i++)
6116 			rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
6117 
6118 	/*
6119 	 * Clear all beacons
6120 	 */
6121 	for (i = 0; i < 8; i++)
6122 		rt2800_clear_beacon_register(rt2x00dev, i);
6123 
6124 	if (rt2x00_is_usb(rt2x00dev)) {
6125 		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6126 		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
6127 		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6128 	} else if (rt2x00_is_pcie(rt2x00dev)) {
6129 		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6130 		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
6131 		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6132 	}
6133 
6134 	reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
6135 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
6136 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
6137 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
6138 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
6139 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
6140 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
6141 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
6142 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
6143 	rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
6144 
6145 	reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
6146 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
6147 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
6148 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
6149 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
6150 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
6151 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
6152 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
6153 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
6154 	rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
6155 
6156 	reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
6157 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
6158 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
6159 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
6160 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
6161 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
6162 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
6163 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
6164 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
6165 	rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
6166 
6167 	reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
6168 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
6169 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
6170 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
6171 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
6172 	rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
6173 
6174 	/*
6175 	 * Do not force the BA window size, we use the TXWI to set it
6176 	 */
6177 	reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
6178 	rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
6179 	rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
6180 	rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
6181 
6182 	/*
6183 	 * We must clear the error counters.
6184 	 * These registers are cleared on read,
6185 	 * so we may pass a useless variable to store the value.
6186 	 */
6187 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
6188 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
6189 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
6190 	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
6191 	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
6192 	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
6193 
6194 	/*
6195 	 * Setup leadtime for pre tbtt interrupt to 6ms
6196 	 */
6197 	reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
6198 	rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
6199 	rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
6200 
6201 	/*
6202 	 * Set up channel statistics timer
6203 	 */
6204 	reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
6205 	rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
6206 	rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
6207 	rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
6208 	rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
6209 	rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
6210 	rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
6211 
6212 	return 0;
6213 }
6214 
6215 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
6216 {
6217 	unsigned int i;
6218 	u32 reg;
6219 
6220 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
6221 		reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
6222 		if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
6223 			return 0;
6224 
6225 		udelay(REGISTER_BUSY_DELAY);
6226 	}
6227 
6228 	rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
6229 	return -EACCES;
6230 }
6231 
6232 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
6233 {
6234 	unsigned int i;
6235 	u8 value;
6236 
6237 	/*
6238 	 * BBP was enabled after firmware was loaded,
6239 	 * but we need to reactivate it now.
6240 	 */
6241 	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6242 	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6243 	msleep(1);
6244 
6245 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
6246 		value = rt2800_bbp_read(rt2x00dev, 0);
6247 		if ((value != 0xff) && (value != 0x00))
6248 			return 0;
6249 		udelay(REGISTER_BUSY_DELAY);
6250 	}
6251 
6252 	rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
6253 	return -EACCES;
6254 }
6255 
6256 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
6257 {
6258 	u8 value;
6259 
6260 	value = rt2800_bbp_read(rt2x00dev, 4);
6261 	rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
6262 	rt2800_bbp_write(rt2x00dev, 4, value);
6263 }
6264 
6265 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
6266 {
6267 	rt2800_bbp_write(rt2x00dev, 142, 1);
6268 	rt2800_bbp_write(rt2x00dev, 143, 57);
6269 }
6270 
6271 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
6272 {
6273 	static const u8 glrt_table[] = {
6274 		0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
6275 		0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
6276 		0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
6277 		0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
6278 		0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
6279 		0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
6280 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
6281 		0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
6282 		0x2E, 0x36, 0x30, 0x6E,					    /* 208 ~ 211 */
6283 	};
6284 	int i;
6285 
6286 	for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
6287 		rt2800_bbp_write(rt2x00dev, 195, 128 + i);
6288 		rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
6289 	}
6290 };
6291 
6292 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
6293 {
6294 	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6295 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6296 	rt2800_bbp_write(rt2x00dev, 68, 0x0B);
6297 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6298 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6299 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6300 	rt2800_bbp_write(rt2x00dev, 81, 0x37);
6301 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6302 	rt2800_bbp_write(rt2x00dev, 83, 0x6A);
6303 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6304 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6305 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6306 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6307 	rt2800_bbp_write(rt2x00dev, 103, 0x00);
6308 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6309 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6310 }
6311 
6312 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
6313 {
6314 	u16 eeprom;
6315 	u8 value;
6316 
6317 	value = rt2800_bbp_read(rt2x00dev, 138);
6318 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6319 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6320 		value |= 0x20;
6321 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6322 		value &= ~0x02;
6323 	rt2800_bbp_write(rt2x00dev, 138, value);
6324 }
6325 
6326 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
6327 {
6328 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6329 
6330 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6331 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6332 
6333 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6334 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6335 
6336 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6337 
6338 	rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6339 	rt2800_bbp_write(rt2x00dev, 80, 0x08);
6340 
6341 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6342 
6343 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6344 
6345 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6346 
6347 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6348 
6349 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6350 
6351 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6352 
6353 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6354 
6355 	rt2800_bbp_write(rt2x00dev, 105, 0x01);
6356 
6357 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6358 }
6359 
6360 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
6361 {
6362 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6363 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6364 
6365 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
6366 		rt2800_bbp_write(rt2x00dev, 69, 0x16);
6367 		rt2800_bbp_write(rt2x00dev, 73, 0x12);
6368 	} else {
6369 		rt2800_bbp_write(rt2x00dev, 69, 0x12);
6370 		rt2800_bbp_write(rt2x00dev, 73, 0x10);
6371 	}
6372 
6373 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6374 
6375 	rt2800_bbp_write(rt2x00dev, 81, 0x37);
6376 
6377 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6378 
6379 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6380 
6381 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
6382 		rt2800_bbp_write(rt2x00dev, 84, 0x19);
6383 	else
6384 		rt2800_bbp_write(rt2x00dev, 84, 0x99);
6385 
6386 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6387 
6388 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6389 
6390 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6391 
6392 	rt2800_bbp_write(rt2x00dev, 103, 0x00);
6393 
6394 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6395 
6396 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6397 }
6398 
6399 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
6400 {
6401 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6402 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6403 
6404 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6405 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6406 
6407 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6408 
6409 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6410 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6411 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6412 
6413 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6414 
6415 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6416 
6417 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6418 
6419 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6420 
6421 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6422 
6423 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6424 
6425 	if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
6426 	    rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
6427 	    rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
6428 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6429 	else
6430 		rt2800_bbp_write(rt2x00dev, 103, 0x00);
6431 
6432 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6433 
6434 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6435 
6436 	if (rt2x00_rt(rt2x00dev, RT3071) ||
6437 	    rt2x00_rt(rt2x00dev, RT3090))
6438 		rt2800_disable_unused_dac_adc(rt2x00dev);
6439 }
6440 
6441 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
6442 {
6443 	u8 value;
6444 
6445 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6446 
6447 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6448 
6449 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6450 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6451 
6452 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6453 
6454 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6455 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6456 	rt2800_bbp_write(rt2x00dev, 75, 0x46);
6457 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6458 
6459 	rt2800_bbp_write(rt2x00dev, 77, 0x58);
6460 
6461 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6462 
6463 	rt2800_bbp_write(rt2x00dev, 74, 0x0b);
6464 	rt2800_bbp_write(rt2x00dev, 79, 0x18);
6465 	rt2800_bbp_write(rt2x00dev, 80, 0x09);
6466 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6467 
6468 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6469 
6470 	rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6471 
6472 	rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6473 
6474 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6475 
6476 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6477 
6478 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6479 
6480 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6481 
6482 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6483 
6484 	rt2800_bbp_write(rt2x00dev, 105, 0x1c);
6485 
6486 	rt2800_bbp_write(rt2x00dev, 106, 0x03);
6487 
6488 	rt2800_bbp_write(rt2x00dev, 128, 0x12);
6489 
6490 	rt2800_bbp_write(rt2x00dev, 67, 0x24);
6491 	rt2800_bbp_write(rt2x00dev, 143, 0x04);
6492 	rt2800_bbp_write(rt2x00dev, 142, 0x99);
6493 	rt2800_bbp_write(rt2x00dev, 150, 0x30);
6494 	rt2800_bbp_write(rt2x00dev, 151, 0x2e);
6495 	rt2800_bbp_write(rt2x00dev, 152, 0x20);
6496 	rt2800_bbp_write(rt2x00dev, 153, 0x34);
6497 	rt2800_bbp_write(rt2x00dev, 154, 0x40);
6498 	rt2800_bbp_write(rt2x00dev, 155, 0x3b);
6499 	rt2800_bbp_write(rt2x00dev, 253, 0x04);
6500 
6501 	value = rt2800_bbp_read(rt2x00dev, 47);
6502 	rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
6503 	rt2800_bbp_write(rt2x00dev, 47, value);
6504 
6505 	/* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
6506 	value = rt2800_bbp_read(rt2x00dev, 3);
6507 	rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
6508 	rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
6509 	rt2800_bbp_write(rt2x00dev, 3, value);
6510 }
6511 
6512 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
6513 {
6514 	rt2800_bbp_write(rt2x00dev, 3, 0x00);
6515 	rt2800_bbp_write(rt2x00dev, 4, 0x50);
6516 
6517 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6518 
6519 	rt2800_bbp_write(rt2x00dev, 47, 0x48);
6520 
6521 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6522 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6523 
6524 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6525 
6526 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6527 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6528 	rt2800_bbp_write(rt2x00dev, 75, 0x46);
6529 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6530 
6531 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
6532 
6533 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6534 
6535 	rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6536 	rt2800_bbp_write(rt2x00dev, 80, 0x08);
6537 	rt2800_bbp_write(rt2x00dev, 81, 0x37);
6538 
6539 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6540 
6541 	if (rt2x00_rt(rt2x00dev, RT5350)) {
6542 		rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6543 		rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6544 	} else {
6545 		rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6546 		rt2800_bbp_write(rt2x00dev, 84, 0x99);
6547 	}
6548 
6549 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6550 
6551 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
6552 
6553 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6554 
6555 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6556 
6557 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6558 
6559 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6560 
6561 	if (rt2x00_rt(rt2x00dev, RT5350)) {
6562 		rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6563 		rt2800_bbp_write(rt2x00dev, 106, 0x03);
6564 	} else {
6565 		rt2800_bbp_write(rt2x00dev, 105, 0x34);
6566 		rt2800_bbp_write(rt2x00dev, 106, 0x05);
6567 	}
6568 
6569 	rt2800_bbp_write(rt2x00dev, 120, 0x50);
6570 
6571 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6572 
6573 	rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6574 	/* Set ITxBF timeout to 0x9c40=1000msec */
6575 	rt2800_bbp_write(rt2x00dev, 179, 0x02);
6576 	rt2800_bbp_write(rt2x00dev, 180, 0x00);
6577 	rt2800_bbp_write(rt2x00dev, 182, 0x40);
6578 	rt2800_bbp_write(rt2x00dev, 180, 0x01);
6579 	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6580 	rt2800_bbp_write(rt2x00dev, 179, 0x00);
6581 	/* Reprogram the inband interface to put right values in RXWI */
6582 	rt2800_bbp_write(rt2x00dev, 142, 0x04);
6583 	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6584 	rt2800_bbp_write(rt2x00dev, 142, 0x06);
6585 	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6586 	rt2800_bbp_write(rt2x00dev, 142, 0x07);
6587 	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6588 	rt2800_bbp_write(rt2x00dev, 142, 0x08);
6589 	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6590 
6591 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6592 
6593 	if (rt2x00_rt(rt2x00dev, RT5350)) {
6594 		/* Antenna Software OFDM */
6595 		rt2800_bbp_write(rt2x00dev, 150, 0x40);
6596 		/* Antenna Software CCK */
6597 		rt2800_bbp_write(rt2x00dev, 151, 0x30);
6598 		rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6599 		/* Clear previously selected antenna */
6600 		rt2800_bbp_write(rt2x00dev, 154, 0);
6601 	}
6602 }
6603 
6604 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6605 {
6606 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6607 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6608 
6609 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6610 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6611 
6612 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6613 
6614 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6615 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6616 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6617 
6618 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6619 
6620 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6621 
6622 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6623 
6624 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6625 
6626 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6627 
6628 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6629 
6630 	if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6631 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6632 	else
6633 		rt2800_bbp_write(rt2x00dev, 103, 0x00);
6634 
6635 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6636 
6637 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6638 
6639 	rt2800_disable_unused_dac_adc(rt2x00dev);
6640 }
6641 
6642 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6643 {
6644 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6645 
6646 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6647 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6648 
6649 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6650 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6651 
6652 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6653 
6654 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6655 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6656 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6657 
6658 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6659 
6660 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6661 
6662 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6663 
6664 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6665 
6666 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6667 
6668 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6669 
6670 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6671 
6672 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6673 
6674 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6675 
6676 	rt2800_disable_unused_dac_adc(rt2x00dev);
6677 }
6678 
6679 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6680 {
6681 	rt2800_init_bbp_early(rt2x00dev);
6682 
6683 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6684 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6685 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6686 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6687 
6688 	rt2800_bbp_write(rt2x00dev, 84, 0x19);
6689 
6690 	/* Enable DC filter */
6691 	if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6692 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6693 }
6694 
6695 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev)
6696 {
6697 	rt2800_init_bbp_early(rt2x00dev);
6698 
6699 	rt2800_bbp_write(rt2x00dev, 4, 0x50);
6700 	rt2800_bbp_write(rt2x00dev, 47, 0x48);
6701 
6702 	rt2800_bbp_write(rt2x00dev, 86, 0x46);
6703 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
6704 
6705 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6706 
6707 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6708 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6709 	rt2800_bbp_write(rt2x00dev, 105, 0x34);
6710 	rt2800_bbp_write(rt2x00dev, 106, 0x12);
6711 	rt2800_bbp_write(rt2x00dev, 120, 0x50);
6712 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6713 	rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6714 
6715 	/* Set ITxBF timeout to 0x9C40=1000msec */
6716 	rt2800_bbp_write(rt2x00dev, 179, 0x02);
6717 	rt2800_bbp_write(rt2x00dev, 180, 0x00);
6718 	rt2800_bbp_write(rt2x00dev, 182, 0x40);
6719 	rt2800_bbp_write(rt2x00dev, 180, 0x01);
6720 	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6721 
6722 	rt2800_bbp_write(rt2x00dev, 179, 0x00);
6723 
6724 	/* Reprogram the inband interface to put right values in RXWI */
6725 	rt2800_bbp_write(rt2x00dev, 142, 0x04);
6726 	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6727 	rt2800_bbp_write(rt2x00dev, 142, 0x06);
6728 	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6729 	rt2800_bbp_write(rt2x00dev, 142, 0x07);
6730 	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6731 	rt2800_bbp_write(rt2x00dev, 142, 0x08);
6732 	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6733 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6734 }
6735 
6736 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6737 {
6738 	int ant, div_mode;
6739 	u16 eeprom;
6740 	u8 value;
6741 
6742 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6743 
6744 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6745 
6746 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6747 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6748 
6749 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6750 
6751 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6752 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6753 	rt2800_bbp_write(rt2x00dev, 75, 0x46);
6754 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6755 
6756 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
6757 
6758 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6759 
6760 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6761 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6762 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6763 
6764 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6765 
6766 	rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6767 
6768 	rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6769 
6770 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6771 
6772 	if (rt2x00_rt(rt2x00dev, RT5392))
6773 		rt2800_bbp_write(rt2x00dev, 88, 0x90);
6774 
6775 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6776 
6777 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6778 
6779 	if (rt2x00_rt(rt2x00dev, RT5392)) {
6780 		rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6781 		rt2800_bbp_write(rt2x00dev, 98, 0x12);
6782 	}
6783 
6784 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6785 
6786 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6787 
6788 	rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6789 
6790 	if (rt2x00_rt(rt2x00dev, RT5390))
6791 		rt2800_bbp_write(rt2x00dev, 106, 0x03);
6792 	else if (rt2x00_rt(rt2x00dev, RT5392))
6793 		rt2800_bbp_write(rt2x00dev, 106, 0x12);
6794 	else
6795 		WARN_ON(1);
6796 
6797 	rt2800_bbp_write(rt2x00dev, 128, 0x12);
6798 
6799 	if (rt2x00_rt(rt2x00dev, RT5392)) {
6800 		rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6801 		rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6802 	}
6803 
6804 	rt2800_disable_unused_dac_adc(rt2x00dev);
6805 
6806 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6807 	div_mode = rt2x00_get_field16(eeprom,
6808 				      EEPROM_NIC_CONF1_ANT_DIVERSITY);
6809 	ant = (div_mode == 3) ? 1 : 0;
6810 
6811 	/* check if this is a Bluetooth combo card */
6812 	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6813 		u32 reg;
6814 
6815 		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6816 		rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
6817 		rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
6818 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
6819 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
6820 		if (ant == 0)
6821 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
6822 		else if (ant == 1)
6823 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
6824 		rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6825 	}
6826 
6827 	/* These chips have hardware RX antenna diversity */
6828 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
6829 	    rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
6830 		rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6831 		rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6832 		rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6833 	}
6834 
6835 	value = rt2800_bbp_read(rt2x00dev, 152);
6836 	if (ant == 0)
6837 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6838 	else
6839 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6840 	rt2800_bbp_write(rt2x00dev, 152, value);
6841 
6842 	rt2800_init_freq_calibration(rt2x00dev);
6843 }
6844 
6845 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6846 {
6847 	int ant, div_mode;
6848 	u16 eeprom;
6849 	u8 value;
6850 
6851 	rt2800_init_bbp_early(rt2x00dev);
6852 
6853 	value = rt2800_bbp_read(rt2x00dev, 105);
6854 	rt2x00_set_field8(&value, BBP105_MLD,
6855 			  rt2x00dev->default_ant.rx_chain_num == 2);
6856 	rt2800_bbp_write(rt2x00dev, 105, value);
6857 
6858 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6859 
6860 	rt2800_bbp_write(rt2x00dev, 20, 0x06);
6861 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6862 	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6863 	rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6864 	rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6865 	rt2800_bbp_write(rt2x00dev, 70, 0x05);
6866 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6867 	rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6868 	rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6869 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6870 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
6871 	rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6872 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6873 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
6874 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6875 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6876 	rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6877 	rt2800_bbp_write(rt2x00dev, 98, 0x12);
6878 	rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6879 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6880 	/* FIXME BBP105 owerwrite */
6881 	rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6882 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6883 	rt2800_bbp_write(rt2x00dev, 128, 0x12);
6884 	rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6885 	rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6886 	rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6887 
6888 	/* Initialize GLRT (Generalized Likehood Radio Test) */
6889 	rt2800_init_bbp_5592_glrt(rt2x00dev);
6890 
6891 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6892 
6893 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6894 	div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
6895 	ant = (div_mode == 3) ? 1 : 0;
6896 	value = rt2800_bbp_read(rt2x00dev, 152);
6897 	if (ant == 0) {
6898 		/* Main antenna */
6899 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6900 	} else {
6901 		/* Auxiliary antenna */
6902 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6903 	}
6904 	rt2800_bbp_write(rt2x00dev, 152, value);
6905 
6906 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
6907 		value = rt2800_bbp_read(rt2x00dev, 254);
6908 		rt2x00_set_field8(&value, BBP254_BIT7, 1);
6909 		rt2800_bbp_write(rt2x00dev, 254, value);
6910 	}
6911 
6912 	rt2800_init_freq_calibration(rt2x00dev);
6913 
6914 	rt2800_bbp_write(rt2x00dev, 84, 0x19);
6915 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6916 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6917 }
6918 
6919 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
6920 				  const u8 reg, const u8 value)
6921 {
6922 	rt2800_bbp_write(rt2x00dev, 195, reg);
6923 	rt2800_bbp_write(rt2x00dev, 196, value);
6924 }
6925 
6926 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
6927 				  const u8 reg, const u8 value)
6928 {
6929 	rt2800_bbp_write(rt2x00dev, 158, reg);
6930 	rt2800_bbp_write(rt2x00dev, 159, value);
6931 }
6932 
6933 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
6934 {
6935 	rt2800_bbp_write(rt2x00dev, 158, reg);
6936 	return rt2800_bbp_read(rt2x00dev, 159);
6937 }
6938 
6939 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
6940 {
6941 	u8 bbp;
6942 
6943 	/* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
6944 	bbp = rt2800_bbp_read(rt2x00dev, 105);
6945 	rt2x00_set_field8(&bbp, BBP105_MLD,
6946 			  rt2x00dev->default_ant.rx_chain_num == 2);
6947 	rt2800_bbp_write(rt2x00dev, 105, bbp);
6948 
6949 	/* Avoid data loss and CRC errors */
6950 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6951 
6952 	/* Fix I/Q swap issue */
6953 	bbp = rt2800_bbp_read(rt2x00dev, 1);
6954 	bbp |= 0x04;
6955 	rt2800_bbp_write(rt2x00dev, 1, bbp);
6956 
6957 	/* BBP for G band */
6958 	rt2800_bbp_write(rt2x00dev, 3, 0x08);
6959 	rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
6960 	rt2800_bbp_write(rt2x00dev, 6, 0x08);
6961 	rt2800_bbp_write(rt2x00dev, 14, 0x09);
6962 	rt2800_bbp_write(rt2x00dev, 15, 0xFF);
6963 	rt2800_bbp_write(rt2x00dev, 16, 0x01);
6964 	rt2800_bbp_write(rt2x00dev, 20, 0x06);
6965 	rt2800_bbp_write(rt2x00dev, 21, 0x00);
6966 	rt2800_bbp_write(rt2x00dev, 22, 0x00);
6967 	rt2800_bbp_write(rt2x00dev, 27, 0x00);
6968 	rt2800_bbp_write(rt2x00dev, 28, 0x00);
6969 	rt2800_bbp_write(rt2x00dev, 30, 0x00);
6970 	rt2800_bbp_write(rt2x00dev, 31, 0x48);
6971 	rt2800_bbp_write(rt2x00dev, 47, 0x40);
6972 	rt2800_bbp_write(rt2x00dev, 62, 0x00);
6973 	rt2800_bbp_write(rt2x00dev, 63, 0x00);
6974 	rt2800_bbp_write(rt2x00dev, 64, 0x00);
6975 	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6976 	rt2800_bbp_write(rt2x00dev, 66, 0x1C);
6977 	rt2800_bbp_write(rt2x00dev, 67, 0x20);
6978 	rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6979 	rt2800_bbp_write(rt2x00dev, 69, 0x10);
6980 	rt2800_bbp_write(rt2x00dev, 70, 0x05);
6981 	rt2800_bbp_write(rt2x00dev, 73, 0x18);
6982 	rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6983 	rt2800_bbp_write(rt2x00dev, 75, 0x60);
6984 	rt2800_bbp_write(rt2x00dev, 76, 0x44);
6985 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
6986 	rt2800_bbp_write(rt2x00dev, 78, 0x1E);
6987 	rt2800_bbp_write(rt2x00dev, 79, 0x1C);
6988 	rt2800_bbp_write(rt2x00dev, 80, 0x0C);
6989 	rt2800_bbp_write(rt2x00dev, 81, 0x3A);
6990 	rt2800_bbp_write(rt2x00dev, 82, 0xB6);
6991 	rt2800_bbp_write(rt2x00dev, 83, 0x9A);
6992 	rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6993 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6994 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
6995 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6996 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6997 	rt2800_bbp_write(rt2x00dev, 95, 0x9A);
6998 	rt2800_bbp_write(rt2x00dev, 96, 0x00);
6999 	rt2800_bbp_write(rt2x00dev, 103, 0xC0);
7000 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
7001 	/* FIXME BBP105 owerwrite */
7002 	rt2800_bbp_write(rt2x00dev, 105, 0x3C);
7003 	rt2800_bbp_write(rt2x00dev, 106, 0x12);
7004 	rt2800_bbp_write(rt2x00dev, 109, 0x00);
7005 	rt2800_bbp_write(rt2x00dev, 134, 0x10);
7006 	rt2800_bbp_write(rt2x00dev, 135, 0xA6);
7007 	rt2800_bbp_write(rt2x00dev, 137, 0x04);
7008 	rt2800_bbp_write(rt2x00dev, 142, 0x30);
7009 	rt2800_bbp_write(rt2x00dev, 143, 0xF7);
7010 	rt2800_bbp_write(rt2x00dev, 160, 0xEC);
7011 	rt2800_bbp_write(rt2x00dev, 161, 0xC4);
7012 	rt2800_bbp_write(rt2x00dev, 162, 0x77);
7013 	rt2800_bbp_write(rt2x00dev, 163, 0xF9);
7014 	rt2800_bbp_write(rt2x00dev, 164, 0x00);
7015 	rt2800_bbp_write(rt2x00dev, 165, 0x00);
7016 	rt2800_bbp_write(rt2x00dev, 186, 0x00);
7017 	rt2800_bbp_write(rt2x00dev, 187, 0x00);
7018 	rt2800_bbp_write(rt2x00dev, 188, 0x00);
7019 	rt2800_bbp_write(rt2x00dev, 186, 0x00);
7020 	rt2800_bbp_write(rt2x00dev, 187, 0x01);
7021 	rt2800_bbp_write(rt2x00dev, 188, 0x00);
7022 	rt2800_bbp_write(rt2x00dev, 189, 0x00);
7023 
7024 	rt2800_bbp_write(rt2x00dev, 91, 0x06);
7025 	rt2800_bbp_write(rt2x00dev, 92, 0x04);
7026 	rt2800_bbp_write(rt2x00dev, 93, 0x54);
7027 	rt2800_bbp_write(rt2x00dev, 99, 0x50);
7028 	rt2800_bbp_write(rt2x00dev, 148, 0x84);
7029 	rt2800_bbp_write(rt2x00dev, 167, 0x80);
7030 	rt2800_bbp_write(rt2x00dev, 178, 0xFF);
7031 	rt2800_bbp_write(rt2x00dev, 106, 0x13);
7032 
7033 	/* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
7034 	rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
7035 	rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
7036 	rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
7037 	rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
7038 	rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
7039 	rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
7040 	rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
7041 	rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
7042 	rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
7043 	rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
7044 	rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
7045 	rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
7046 	rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
7047 	rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
7048 	rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
7049 	rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
7050 	rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
7051 	rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
7052 	rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
7053 	rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
7054 	rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
7055 	rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
7056 	rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
7057 	rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
7058 	rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
7059 	rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
7060 	rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
7061 	rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
7062 	rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
7063 	rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
7064 	rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
7065 	rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
7066 	rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
7067 	rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
7068 	rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
7069 	rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
7070 	rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
7071 	rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
7072 	rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
7073 	rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
7074 	rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
7075 	rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
7076 	rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
7077 	rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
7078 	rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
7079 	rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
7080 	rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
7081 	rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
7082 	rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
7083 	rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
7084 	rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
7085 	rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
7086 	rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
7087 	rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
7088 	rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
7089 	rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
7090 	rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
7091 	rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
7092 	rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
7093 	rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
7094 	rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
7095 	rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
7096 	rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
7097 	rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
7098 	rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
7099 	rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
7100 	rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
7101 	rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
7102 	rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
7103 	rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
7104 	rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
7105 	rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
7106 	rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
7107 	rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
7108 	rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
7109 	rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
7110 	rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
7111 	rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
7112 	rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
7113 	rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
7114 	rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
7115 	rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
7116 	rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
7117 
7118 	/* BBP for G band DCOC function */
7119 	rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
7120 	rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
7121 	rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
7122 	rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
7123 	rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
7124 	rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
7125 	rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
7126 	rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
7127 	rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
7128 	rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
7129 	rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
7130 	rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
7131 	rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
7132 	rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
7133 	rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
7134 	rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
7135 	rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
7136 	rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
7137 	rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
7138 	rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
7139 
7140 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7141 }
7142 
7143 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
7144 {
7145 	unsigned int i;
7146 	u16 eeprom;
7147 	u8 reg_id;
7148 	u8 value;
7149 
7150 	if (rt2800_is_305x_soc(rt2x00dev))
7151 		rt2800_init_bbp_305x_soc(rt2x00dev);
7152 
7153 	switch (rt2x00dev->chip.rt) {
7154 	case RT2860:
7155 	case RT2872:
7156 	case RT2883:
7157 		rt2800_init_bbp_28xx(rt2x00dev);
7158 		break;
7159 	case RT3070:
7160 	case RT3071:
7161 	case RT3090:
7162 		rt2800_init_bbp_30xx(rt2x00dev);
7163 		break;
7164 	case RT3290:
7165 		rt2800_init_bbp_3290(rt2x00dev);
7166 		break;
7167 	case RT3352:
7168 	case RT5350:
7169 		rt2800_init_bbp_3352(rt2x00dev);
7170 		break;
7171 	case RT3390:
7172 		rt2800_init_bbp_3390(rt2x00dev);
7173 		break;
7174 	case RT3572:
7175 		rt2800_init_bbp_3572(rt2x00dev);
7176 		break;
7177 	case RT3593:
7178 		rt2800_init_bbp_3593(rt2x00dev);
7179 		return;
7180 	case RT3883:
7181 		rt2800_init_bbp_3883(rt2x00dev);
7182 		return;
7183 	case RT5390:
7184 	case RT5392:
7185 		rt2800_init_bbp_53xx(rt2x00dev);
7186 		break;
7187 	case RT5592:
7188 		rt2800_init_bbp_5592(rt2x00dev);
7189 		return;
7190 	case RT6352:
7191 		rt2800_init_bbp_6352(rt2x00dev);
7192 		break;
7193 	}
7194 
7195 	for (i = 0; i < EEPROM_BBP_SIZE; i++) {
7196 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
7197 						       EEPROM_BBP_START, i);
7198 
7199 		if (eeprom != 0xffff && eeprom != 0x0000) {
7200 			reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
7201 			value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
7202 			rt2800_bbp_write(rt2x00dev, reg_id, value);
7203 		}
7204 	}
7205 }
7206 
7207 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
7208 {
7209 	u32 reg;
7210 
7211 	reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
7212 	rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
7213 	rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
7214 }
7215 
7216 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
7217 				u8 filter_target)
7218 {
7219 	unsigned int i;
7220 	u8 bbp;
7221 	u8 rfcsr;
7222 	u8 passband;
7223 	u8 stopband;
7224 	u8 overtuned = 0;
7225 	u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
7226 
7227 	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7228 
7229 	bbp = rt2800_bbp_read(rt2x00dev, 4);
7230 	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
7231 	rt2800_bbp_write(rt2x00dev, 4, bbp);
7232 
7233 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
7234 	rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
7235 	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
7236 
7237 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7238 	rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
7239 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7240 
7241 	/*
7242 	 * Set power & frequency of passband test tone
7243 	 */
7244 	rt2800_bbp_write(rt2x00dev, 24, 0);
7245 
7246 	for (i = 0; i < 100; i++) {
7247 		rt2800_bbp_write(rt2x00dev, 25, 0x90);
7248 		msleep(1);
7249 
7250 		passband = rt2800_bbp_read(rt2x00dev, 55);
7251 		if (passband)
7252 			break;
7253 	}
7254 
7255 	/*
7256 	 * Set power & frequency of stopband test tone
7257 	 */
7258 	rt2800_bbp_write(rt2x00dev, 24, 0x06);
7259 
7260 	for (i = 0; i < 100; i++) {
7261 		rt2800_bbp_write(rt2x00dev, 25, 0x90);
7262 		msleep(1);
7263 
7264 		stopband = rt2800_bbp_read(rt2x00dev, 55);
7265 
7266 		if ((passband - stopband) <= filter_target) {
7267 			rfcsr24++;
7268 			overtuned += ((passband - stopband) == filter_target);
7269 		} else
7270 			break;
7271 
7272 		rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7273 	}
7274 
7275 	rfcsr24 -= !!overtuned;
7276 
7277 	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7278 	return rfcsr24;
7279 }
7280 
7281 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
7282 				       const unsigned int rf_reg)
7283 {
7284 	u8 rfcsr;
7285 
7286 	rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
7287 	rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
7288 	rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7289 	msleep(1);
7290 	rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
7291 	rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7292 }
7293 
7294 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
7295 {
7296 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7297 	u8 filter_tgt_bw20;
7298 	u8 filter_tgt_bw40;
7299 	u8 rfcsr, bbp;
7300 
7301 	/*
7302 	 * TODO: sync filter_tgt values with vendor driver
7303 	 */
7304 	if (rt2x00_rt(rt2x00dev, RT3070)) {
7305 		filter_tgt_bw20 = 0x16;
7306 		filter_tgt_bw40 = 0x19;
7307 	} else {
7308 		filter_tgt_bw20 = 0x13;
7309 		filter_tgt_bw40 = 0x15;
7310 	}
7311 
7312 	drv_data->calibration_bw20 =
7313 		rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
7314 	drv_data->calibration_bw40 =
7315 		rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
7316 
7317 	/*
7318 	 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
7319 	 */
7320 	drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7321 	drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7322 
7323 	/*
7324 	 * Set back to initial state
7325 	 */
7326 	rt2800_bbp_write(rt2x00dev, 24, 0);
7327 
7328 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7329 	rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
7330 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7331 
7332 	/*
7333 	 * Set BBP back to BW20
7334 	 */
7335 	bbp = rt2800_bbp_read(rt2x00dev, 4);
7336 	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
7337 	rt2800_bbp_write(rt2x00dev, 4, bbp);
7338 }
7339 
7340 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
7341 {
7342 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7343 	u8 min_gain, rfcsr, bbp;
7344 	u16 eeprom;
7345 
7346 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
7347 
7348 	rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
7349 	if (rt2x00_rt(rt2x00dev, RT3070) ||
7350 	    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7351 	    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
7352 	    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7353 		if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
7354 			rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
7355 	}
7356 
7357 	min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
7358 	if (drv_data->txmixer_gain_24g >= min_gain) {
7359 		rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
7360 				  drv_data->txmixer_gain_24g);
7361 	}
7362 
7363 	rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
7364 
7365 	if (rt2x00_rt(rt2x00dev, RT3090)) {
7366 		/*  Turn off unused DAC1 and ADC1 to reduce power consumption */
7367 		bbp = rt2800_bbp_read(rt2x00dev, 138);
7368 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7369 		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7370 			rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
7371 		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7372 			rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
7373 		rt2800_bbp_write(rt2x00dev, 138, bbp);
7374 	}
7375 
7376 	if (rt2x00_rt(rt2x00dev, RT3070)) {
7377 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
7378 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
7379 			rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
7380 		else
7381 			rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
7382 		rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
7383 		rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
7384 		rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
7385 		rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
7386 	} else if (rt2x00_rt(rt2x00dev, RT3071) ||
7387 		   rt2x00_rt(rt2x00dev, RT3090) ||
7388 		   rt2x00_rt(rt2x00dev, RT3390)) {
7389 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7390 		rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7391 		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7392 		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7393 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
7394 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
7395 		rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7396 
7397 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
7398 		rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
7399 		rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
7400 
7401 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
7402 		rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
7403 		rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
7404 
7405 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
7406 		rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
7407 		rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
7408 	}
7409 }
7410 
7411 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
7412 {
7413 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7414 	u8 rfcsr;
7415 	u8 tx_gain;
7416 
7417 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
7418 	rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
7419 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7420 
7421 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
7422 	tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
7423 				    RFCSR17_TXMIXER_GAIN);
7424 	rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
7425 	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
7426 
7427 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
7428 	rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
7429 	rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
7430 
7431 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
7432 	rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
7433 	rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
7434 
7435 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7436 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7437 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
7438 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7439 
7440 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
7441 	rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
7442 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
7443 
7444 	/* TODO: enable stream mode */
7445 }
7446 
7447 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
7448 {
7449 	u8 reg;
7450 	u16 eeprom;
7451 
7452 	/*  Turn off unused DAC1 and ADC1 to reduce power consumption */
7453 	reg = rt2800_bbp_read(rt2x00dev, 138);
7454 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7455 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7456 		rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
7457 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7458 		rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
7459 	rt2800_bbp_write(rt2x00dev, 138, reg);
7460 
7461 	reg = rt2800_rfcsr_read(rt2x00dev, 38);
7462 	rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
7463 	rt2800_rfcsr_write(rt2x00dev, 38, reg);
7464 
7465 	reg = rt2800_rfcsr_read(rt2x00dev, 39);
7466 	rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
7467 	rt2800_rfcsr_write(rt2x00dev, 39, reg);
7468 
7469 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7470 
7471 	reg = rt2800_rfcsr_read(rt2x00dev, 30);
7472 	rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
7473 	rt2800_rfcsr_write(rt2x00dev, 30, reg);
7474 }
7475 
7476 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
7477 {
7478 	rt2800_rf_init_calibration(rt2x00dev, 30);
7479 
7480 	rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
7481 	rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
7482 	rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
7483 	rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
7484 	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7485 	rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7486 	rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7487 	rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
7488 	rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
7489 	rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7490 	rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
7491 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7492 	rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
7493 	rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
7494 	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7495 	rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7496 	rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7497 	rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7498 	rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7499 	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7500 	rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7501 	rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7502 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7503 	rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
7504 	rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7505 	rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
7506 	rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
7507 	rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
7508 	rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
7509 	rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
7510 	rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
7511 	rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
7512 }
7513 
7514 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
7515 {
7516 	u8 rfcsr;
7517 	u16 eeprom;
7518 	u32 reg;
7519 
7520 	/* XXX vendor driver do this only for 3070 */
7521 	rt2800_rf_init_calibration(rt2x00dev, 30);
7522 
7523 	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7524 	rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7525 	rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7526 	rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
7527 	rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7528 	rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
7529 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7530 	rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
7531 	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7532 	rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7533 	rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7534 	rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7535 	rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7536 	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7537 	rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7538 	rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7539 	rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7540 	rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
7541 	rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
7542 
7543 	if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
7544 		reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7545 		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7546 		rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7547 		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7548 	} else if (rt2x00_rt(rt2x00dev, RT3071) ||
7549 		   rt2x00_rt(rt2x00dev, RT3090)) {
7550 		rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
7551 
7552 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7553 		rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7554 		rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7555 
7556 		reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7557 		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7558 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7559 		    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
7560 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7561 			if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
7562 				rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7563 			else
7564 				rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7565 		}
7566 		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7567 
7568 		reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7569 		rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7570 		rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7571 	}
7572 
7573 	rt2800_rx_filter_calibration(rt2x00dev);
7574 
7575 	if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
7576 	    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7577 	    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
7578 		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7579 
7580 	rt2800_led_open_drain_enable(rt2x00dev);
7581 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7582 }
7583 
7584 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
7585 {
7586 	u8 rfcsr;
7587 
7588 	rt2800_rf_init_calibration(rt2x00dev, 2);
7589 
7590 	rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7591 	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7592 	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7593 	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7594 	rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7595 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
7596 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7597 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7598 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7599 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7600 	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7601 	rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7602 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7603 	rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7604 	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7605 	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7606 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7607 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7608 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7609 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7610 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7611 	rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7612 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7613 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7614 	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7615 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7616 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7617 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7618 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7619 	rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7620 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7621 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7622 	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7623 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7624 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7625 	rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7626 	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7627 	rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7628 	rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7629 	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7630 	rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7631 	rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7632 	rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7633 	rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7634 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7635 	rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7636 
7637 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7638 	rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7639 	rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7640 
7641 	rt2800_led_open_drain_enable(rt2x00dev);
7642 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7643 }
7644 
7645 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7646 {
7647 	int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
7648 				  &rt2x00dev->cap_flags);
7649 	int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
7650 				  &rt2x00dev->cap_flags);
7651 	u8 rfcsr;
7652 
7653 	rt2800_rf_init_calibration(rt2x00dev, 30);
7654 
7655 	rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7656 	rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7657 	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7658 	rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7659 	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7660 	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7661 	rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7662 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7663 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7664 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7665 	rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7666 	rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7667 	rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7668 	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7669 	rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7670 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7671 	rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7672 	rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7673 	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7674 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7675 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7676 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7677 	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7678 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7679 	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7680 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7681 	rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7682 	rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7683 	rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7684 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7685 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7686 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7687 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7688 	rfcsr = 0x01;
7689 	if (tx0_ext_pa)
7690 		rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
7691 	if (tx1_ext_pa)
7692 		rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7693 	rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7694 	rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7695 	rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7696 	rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7697 	rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7698 	rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7699 	rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7700 	rfcsr = 0x52;
7701 	if (!tx0_ext_pa) {
7702 		rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7703 		rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7704 	}
7705 	rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7706 	rfcsr = 0x52;
7707 	if (!tx1_ext_pa) {
7708 		rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7709 		rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7710 	}
7711 	rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7712 	rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7713 	rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7714 	rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7715 	rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7716 	rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7717 	rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7718 	rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7719 	rfcsr = 0x2d;
7720 	if (tx0_ext_pa)
7721 		rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
7722 	if (tx1_ext_pa)
7723 		rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7724 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7725 	rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7726 	rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7727 	rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7728 	rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7729 	rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7730 	rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7731 	rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7732 	rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7733 	rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7734 	rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7735 	rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7736 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7737 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7738 
7739 	rt2800_rx_filter_calibration(rt2x00dev);
7740 	rt2800_led_open_drain_enable(rt2x00dev);
7741 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7742 }
7743 
7744 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7745 {
7746 	u32 reg;
7747 
7748 	rt2800_rf_init_calibration(rt2x00dev, 30);
7749 
7750 	rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7751 	rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7752 	rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7753 	rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7754 	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7755 	rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7756 	rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7757 	rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7758 	rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7759 	rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7760 	rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7761 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7762 	rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7763 	rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7764 	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7765 	rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7766 	rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7767 	rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7768 	rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7769 	rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7770 	rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7771 	rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7772 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7773 	rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7774 	rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7775 	rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7776 	rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7777 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7778 	rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7779 	rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7780 	rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7781 	rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7782 
7783 	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7784 	rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7785 	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7786 
7787 	rt2800_rx_filter_calibration(rt2x00dev);
7788 
7789 	if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7790 		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7791 
7792 	rt2800_led_open_drain_enable(rt2x00dev);
7793 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7794 }
7795 
7796 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7797 {
7798 	u8 rfcsr;
7799 	u32 reg;
7800 
7801 	rt2800_rf_init_calibration(rt2x00dev, 30);
7802 
7803 	rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7804 	rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7805 	rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7806 	rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7807 	rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7808 	rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7809 	rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7810 	rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7811 	rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7812 	rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7813 	rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7814 	rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7815 	rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7816 	rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7817 	rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7818 	rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7819 	rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7820 	rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7821 	rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7822 	rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7823 	rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7824 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7825 	rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7826 	rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7827 	rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7828 	rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7829 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7830 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7831 	rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7832 	rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7833 	rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7834 
7835 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7836 	rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7837 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7838 
7839 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7840 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7841 	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7842 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7843 	msleep(1);
7844 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7845 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7846 	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7847 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7848 
7849 	rt2800_rx_filter_calibration(rt2x00dev);
7850 	rt2800_led_open_drain_enable(rt2x00dev);
7851 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7852 }
7853 
7854 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7855 {
7856 	u8 bbp;
7857 	bool txbf_enabled = false; /* FIXME */
7858 
7859 	bbp = rt2800_bbp_read(rt2x00dev, 105);
7860 	if (rt2x00dev->default_ant.rx_chain_num == 1)
7861 		rt2x00_set_field8(&bbp, BBP105_MLD, 0);
7862 	else
7863 		rt2x00_set_field8(&bbp, BBP105_MLD, 1);
7864 	rt2800_bbp_write(rt2x00dev, 105, bbp);
7865 
7866 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7867 
7868 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
7869 	rt2800_bbp_write(rt2x00dev, 82, 0x82);
7870 	rt2800_bbp_write(rt2x00dev, 106, 0x05);
7871 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
7872 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
7873 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7874 	rt2800_bbp_write(rt2x00dev, 47, 0x48);
7875 	rt2800_bbp_write(rt2x00dev, 120, 0x50);
7876 
7877 	if (txbf_enabled)
7878 		rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7879 	else
7880 		rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7881 
7882 	/* SNR mapping */
7883 	rt2800_bbp_write(rt2x00dev, 142, 6);
7884 	rt2800_bbp_write(rt2x00dev, 143, 160);
7885 	rt2800_bbp_write(rt2x00dev, 142, 7);
7886 	rt2800_bbp_write(rt2x00dev, 143, 161);
7887 	rt2800_bbp_write(rt2x00dev, 142, 8);
7888 	rt2800_bbp_write(rt2x00dev, 143, 162);
7889 
7890 	/* ADC/DAC control */
7891 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
7892 
7893 	/* RX AGC energy lower bound in log2 */
7894 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7895 
7896 	/* FIXME: BBP 105 owerwrite? */
7897 	rt2800_bbp_write(rt2x00dev, 105, 0x04);
7898 
7899 }
7900 
7901 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7902 {
7903 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7904 	u32 reg;
7905 	u8 rfcsr;
7906 
7907 	/* Disable GPIO #4 and #7 function for LAN PE control */
7908 	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7909 	rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
7910 	rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
7911 	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7912 
7913 	/* Initialize default register values */
7914 	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7915 	rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
7916 	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7917 	rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7918 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7919 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7920 	rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7921 	rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
7922 	rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
7923 	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7924 	rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7925 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7926 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7927 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7928 	rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
7929 	rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
7930 	rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
7931 	rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
7932 	rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
7933 	rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
7934 	rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
7935 	rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
7936 	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
7937 	rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
7938 	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
7939 	rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
7940 	rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
7941 	rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
7942 	rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
7943 	rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
7944 	rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
7945 	rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
7946 
7947 	/* Initiate calibration */
7948 	/* TODO: use rt2800_rf_init_calibration ? */
7949 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
7950 	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
7951 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
7952 
7953 	rt2800_freq_cal_mode1(rt2x00dev);
7954 
7955 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
7956 	rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
7957 	rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
7958 
7959 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7960 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7961 	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7962 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7963 	usleep_range(1000, 1500);
7964 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7965 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7966 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7967 
7968 	/* Set initial values for RX filter calibration */
7969 	drv_data->calibration_bw20 = 0x1f;
7970 	drv_data->calibration_bw40 = 0x2f;
7971 
7972 	/* Save BBP 25 & 26 values for later use in channel switching */
7973 	drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7974 	drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7975 
7976 	rt2800_led_open_drain_enable(rt2x00dev);
7977 	rt2800_normal_mode_setup_3593(rt2x00dev);
7978 
7979 	rt3593_post_bbp_init(rt2x00dev);
7980 
7981 	/* TODO: enable stream mode support */
7982 }
7983 
7984 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
7985 {
7986 	rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7987 	rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7988 	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7989 	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7990 	rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
7991 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7992 	rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7993 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7994 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7995 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7996 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7997 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7998 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7999 	if (rt2800_clk_is_20mhz(rt2x00dev))
8000 		rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
8001 	else
8002 		rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8003 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8004 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8005 	rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
8006 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8007 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8008 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8009 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8010 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8011 	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8012 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8013 	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8014 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8015 	rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8016 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8017 	rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
8018 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8019 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8020 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8021 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8022 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8023 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8024 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8025 	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8026 	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8027 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8028 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8029 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8030 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8031 	rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8032 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
8033 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
8034 	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8035 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8036 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8037 	rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
8038 	rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
8039 	rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
8040 	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8041 	rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8042 	rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8043 	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8044 	rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
8045 	rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8046 	rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8047 	rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
8048 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8049 	rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8050 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8051 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8052 }
8053 
8054 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
8055 {
8056 	u8 rfcsr;
8057 
8058 	/* TODO: get the actual ECO value from the SoC */
8059 	const unsigned int eco = 5;
8060 
8061 	rt2800_rf_init_calibration(rt2x00dev, 2);
8062 
8063 	rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
8064 	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8065 	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
8066 	rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
8067 	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
8068 	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
8069 	rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
8070 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8071 	rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
8072 	rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
8073 	rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
8074 	rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
8075 	rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
8076 	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
8077 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8078 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8079 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8080 
8081 	/* RFCSR 17 will be initialized later based on the
8082 	 * frequency offset stored in the EEPROM
8083 	 */
8084 
8085 	rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
8086 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8087 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8088 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8089 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8090 	rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
8091 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8092 	rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8093 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8094 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8095 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8096 	rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
8097 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8098 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8099 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8100 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8101 	rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
8102 	rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8103 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8104 	rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8105 	rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
8106 	rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
8107 	rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8108 	rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
8109 	rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
8110 	rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8111 	rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
8112 	rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8113 	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8114 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8115 	rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
8116 	rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8117 	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8118 	rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
8119 	rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
8120 	rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
8121 	rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
8122 	rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
8123 	rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8124 	rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
8125 	rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
8126 	rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
8127 	rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
8128 	rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
8129 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8130 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8131 
8132 	/* TODO: rx filter calibration? */
8133 
8134 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
8135 
8136 	rt2800_bbp_write(rt2x00dev, 163, 0x9d);
8137 
8138 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
8139 
8140 	rt2800_bbp_write(rt2x00dev, 179, 0x02);
8141 	rt2800_bbp_write(rt2x00dev, 180, 0x00);
8142 	rt2800_bbp_write(rt2x00dev, 182, 0x40);
8143 	rt2800_bbp_write(rt2x00dev, 180, 0x01);
8144 	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
8145 
8146 	rt2800_bbp_write(rt2x00dev, 179, 0x00);
8147 
8148 	rt2800_bbp_write(rt2x00dev, 142, 0x04);
8149 	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
8150 	rt2800_bbp_write(rt2x00dev, 142, 0x06);
8151 	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
8152 	rt2800_bbp_write(rt2x00dev, 142, 0x07);
8153 	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
8154 	rt2800_bbp_write(rt2x00dev, 142, 0x08);
8155 	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
8156 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
8157 
8158 	if (eco == 5) {
8159 		rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
8160 		rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
8161 	}
8162 
8163 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8164 	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0);
8165 	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
8166 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8167 	msleep(1);
8168 	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
8169 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8170 
8171 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
8172 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
8173 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
8174 
8175 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
8176 	rfcsr |= 0xc0;
8177 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
8178 
8179 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
8180 	rfcsr |= 0x20;
8181 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
8182 
8183 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
8184 	rfcsr |= 0x20;
8185 	rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
8186 
8187 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
8188 	rfcsr &= ~0xee;
8189 	rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
8190 }
8191 
8192 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
8193 {
8194 	rt2800_rf_init_calibration(rt2x00dev, 2);
8195 
8196 	rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
8197 	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8198 	rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8199 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8200 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8201 		rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8202 	else
8203 		rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
8204 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8205 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8206 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8207 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8208 	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8209 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8210 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8211 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8212 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8213 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8214 
8215 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8216 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8217 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8218 	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8219 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8220 	if (rt2x00_is_usb(rt2x00dev) &&
8221 	    rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8222 		rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8223 	else
8224 		rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
8225 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8226 	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8227 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8228 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8229 
8230 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8231 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8232 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8233 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8234 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8235 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8236 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8237 	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8238 	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8239 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8240 
8241 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8242 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8243 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
8244 	rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
8245 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8246 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8247 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8248 		rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8249 	else
8250 		rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
8251 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8252 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8253 	rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8254 
8255 	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8256 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8257 		rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8258 	else
8259 		rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
8260 	rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
8261 	rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
8262 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8263 		rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
8264 	else
8265 		rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
8266 	rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
8267 	rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
8268 	rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
8269 
8270 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8271 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
8272 		if (rt2x00_is_usb(rt2x00dev))
8273 			rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8274 		else
8275 			rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
8276 	} else {
8277 		if (rt2x00_is_usb(rt2x00dev))
8278 			rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
8279 		else
8280 			rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
8281 	}
8282 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8283 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8284 
8285 	rt2800_normal_mode_setup_5xxx(rt2x00dev);
8286 
8287 	rt2800_led_open_drain_enable(rt2x00dev);
8288 }
8289 
8290 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
8291 {
8292 	rt2800_rf_init_calibration(rt2x00dev, 2);
8293 
8294 	rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
8295 	rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8296 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8297 	rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8298 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8299 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8300 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8301 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8302 	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8303 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8304 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8305 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8306 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8307 	rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
8308 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8309 	rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
8310 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8311 	rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
8312 	rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
8313 	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8314 	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8315 	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8316 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8317 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8318 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8319 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8320 	rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
8321 	rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8322 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8323 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8324 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8325 	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8326 	rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
8327 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8328 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
8329 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8330 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8331 	rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8332 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8333 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8334 	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8335 	rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
8336 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8337 	rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8338 	rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
8339 	rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
8340 	rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
8341 	rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
8342 	rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8343 	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8344 	rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
8345 	rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8346 	rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8347 	rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
8348 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8349 	rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
8350 	rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
8351 	rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8352 
8353 	rt2800_normal_mode_setup_5xxx(rt2x00dev);
8354 
8355 	rt2800_led_open_drain_enable(rt2x00dev);
8356 }
8357 
8358 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
8359 {
8360 	rt2800_rf_init_calibration(rt2x00dev, 30);
8361 
8362 	rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
8363 	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8364 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8365 	rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
8366 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8367 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8368 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8369 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8370 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8371 	rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
8372 	rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
8373 	rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
8374 	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8375 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8376 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8377 	rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8378 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8379 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8380 	rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
8381 	rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
8382 	rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8383 
8384 	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8385 	msleep(1);
8386 
8387 	rt2800_freq_cal_mode1(rt2x00dev);
8388 
8389 	/* Enable DC filter */
8390 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
8391 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
8392 
8393 	rt2800_normal_mode_setup_5xxx(rt2x00dev);
8394 
8395 	if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
8396 		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8397 
8398 	rt2800_led_open_drain_enable(rt2x00dev);
8399 }
8400 
8401 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
8402 				       bool set_bw, bool is_ht40)
8403 {
8404 	u8 bbp_val;
8405 
8406 	bbp_val = rt2800_bbp_read(rt2x00dev, 21);
8407 	bbp_val |= 0x1;
8408 	rt2800_bbp_write(rt2x00dev, 21, bbp_val);
8409 	usleep_range(100, 200);
8410 
8411 	if (set_bw) {
8412 		bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8413 		rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
8414 		rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8415 		usleep_range(100, 200);
8416 	}
8417 
8418 	bbp_val = rt2800_bbp_read(rt2x00dev, 21);
8419 	bbp_val &= (~0x1);
8420 	rt2800_bbp_write(rt2x00dev, 21, bbp_val);
8421 	usleep_range(100, 200);
8422 }
8423 
8424 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
8425 {
8426 	u8 rf_val;
8427 
8428 	if (btxcal)
8429 		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
8430 	else
8431 		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
8432 
8433 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
8434 
8435 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8436 	rf_val |= 0x80;
8437 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
8438 
8439 	if (btxcal) {
8440 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
8441 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
8442 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
8443 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8444 		rf_val &= (~0x3F);
8445 		rf_val |= 0x3F;
8446 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
8447 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8448 		rf_val &= (~0x3F);
8449 		rf_val |= 0x3F;
8450 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
8451 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
8452 	} else {
8453 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
8454 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
8455 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
8456 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8457 		rf_val &= (~0x3F);
8458 		rf_val |= 0x34;
8459 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
8460 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8461 		rf_val &= (~0x3F);
8462 		rf_val |= 0x34;
8463 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
8464 	}
8465 
8466 	return 0;
8467 }
8468 
8469 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
8470 {
8471 	unsigned int cnt;
8472 	u8 bbp_val;
8473 	char cal_val;
8474 
8475 	rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
8476 
8477 	cnt = 0;
8478 	do {
8479 		usleep_range(500, 2000);
8480 		bbp_val = rt2800_bbp_read(rt2x00dev, 159);
8481 		if (bbp_val == 0x02 || cnt == 20)
8482 			break;
8483 
8484 		cnt++;
8485 	} while (cnt < 20);
8486 
8487 	bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
8488 	cal_val = bbp_val & 0x7F;
8489 	if (cal_val >= 0x40)
8490 		cal_val -= 128;
8491 
8492 	return cal_val;
8493 }
8494 
8495 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
8496 					 bool btxcal)
8497 {
8498 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8499 	u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
8500 	u8 filter_target;
8501 	u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
8502 	u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
8503 	int loop = 0, is_ht40, cnt;
8504 	u8 bbp_val, rf_val;
8505 	char cal_r32_init, cal_r32_val, cal_diff;
8506 	u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
8507 	u8 saverfb5r06, saverfb5r07;
8508 	u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
8509 	u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
8510 	u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
8511 	u8 saverfb5r58, saverfb5r59;
8512 	u8 savebbp159r0, savebbp159r2, savebbpr23;
8513 	u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
8514 
8515 	/* Save MAC registers */
8516 	MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8517 	MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8518 
8519 	/* save BBP registers */
8520 	savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
8521 
8522 	savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
8523 	savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8524 
8525 	/* Save RF registers */
8526 	saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8527 	saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8528 	saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8529 	saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8530 	saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
8531 	saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8532 	saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8533 	saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
8534 	saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8535 	saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8536 	saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8537 	saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8538 
8539 	saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
8540 	saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
8541 	saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
8542 	saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
8543 	saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
8544 	saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
8545 	saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
8546 	saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
8547 	saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
8548 	saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
8549 
8550 	saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8551 	saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8552 
8553 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8554 	rf_val |= 0x3;
8555 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
8556 
8557 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8558 	rf_val |= 0x1;
8559 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
8560 
8561 	cnt = 0;
8562 	do {
8563 		usleep_range(500, 2000);
8564 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8565 		if (((rf_val & 0x1) == 0x00) || (cnt == 40))
8566 			break;
8567 		cnt++;
8568 	} while (cnt < 40);
8569 
8570 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8571 	rf_val &= (~0x3);
8572 	rf_val |= 0x1;
8573 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
8574 
8575 	/* I-3 */
8576 	bbp_val = rt2800_bbp_read(rt2x00dev, 23);
8577 	bbp_val &= (~0x1F);
8578 	bbp_val |= 0x10;
8579 	rt2800_bbp_write(rt2x00dev, 23, bbp_val);
8580 
8581 	do {
8582 		/* I-4,5,6,7,8,9 */
8583 		if (loop == 0) {
8584 			is_ht40 = false;
8585 
8586 			if (btxcal)
8587 				filter_target = tx_filter_target_20m;
8588 			else
8589 				filter_target = rx_filter_target_20m;
8590 		} else {
8591 			is_ht40 = true;
8592 
8593 			if (btxcal)
8594 				filter_target = tx_filter_target_40m;
8595 			else
8596 				filter_target = rx_filter_target_40m;
8597 		}
8598 
8599 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
8600 		rf_val &= (~0x04);
8601 		if (loop == 1)
8602 			rf_val |= 0x4;
8603 
8604 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
8605 
8606 		rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
8607 
8608 		rt2800_rf_lp_config(rt2x00dev, btxcal);
8609 		if (btxcal) {
8610 			tx_agc_fc = 0;
8611 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8612 			rf_val &= (~0x7F);
8613 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8614 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8615 			rf_val &= (~0x7F);
8616 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8617 		} else {
8618 			rx_agc_fc = 0;
8619 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8620 			rf_val &= (~0x7F);
8621 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8622 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8623 			rf_val &= (~0x7F);
8624 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8625 		}
8626 
8627 		usleep_range(1000, 2000);
8628 
8629 		bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8630 		bbp_val &= (~0x6);
8631 		rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8632 
8633 		rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8634 
8635 		cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8636 
8637 		bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8638 		bbp_val |= 0x6;
8639 		rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8640 do_cal:
8641 		if (btxcal) {
8642 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8643 			rf_val &= (~0x7F);
8644 			rf_val |= tx_agc_fc;
8645 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8646 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8647 			rf_val &= (~0x7F);
8648 			rf_val |= tx_agc_fc;
8649 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8650 		} else {
8651 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8652 			rf_val &= (~0x7F);
8653 			rf_val |= rx_agc_fc;
8654 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8655 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8656 			rf_val &= (~0x7F);
8657 			rf_val |= rx_agc_fc;
8658 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8659 		}
8660 
8661 		usleep_range(500, 1000);
8662 
8663 		rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8664 
8665 		cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8666 
8667 		cal_diff = cal_r32_init - cal_r32_val;
8668 
8669 		if (btxcal)
8670 			cmm_agc_fc = tx_agc_fc;
8671 		else
8672 			cmm_agc_fc = rx_agc_fc;
8673 
8674 		if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
8675 		    ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
8676 			if (btxcal)
8677 				tx_agc_fc = 0;
8678 			else
8679 				rx_agc_fc = 0;
8680 		} else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
8681 			if (btxcal)
8682 				tx_agc_fc++;
8683 			else
8684 				rx_agc_fc++;
8685 			goto do_cal;
8686 		}
8687 
8688 		if (btxcal) {
8689 			if (loop == 0)
8690 				drv_data->tx_calibration_bw20 = tx_agc_fc;
8691 			else
8692 				drv_data->tx_calibration_bw40 = tx_agc_fc;
8693 		} else {
8694 			if (loop == 0)
8695 				drv_data->rx_calibration_bw20 = rx_agc_fc;
8696 			else
8697 				drv_data->rx_calibration_bw40 = rx_agc_fc;
8698 		}
8699 
8700 		loop++;
8701 	} while (loop <= 1);
8702 
8703 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
8704 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
8705 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
8706 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
8707 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
8708 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
8709 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
8710 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
8711 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
8712 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
8713 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
8714 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
8715 
8716 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
8717 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
8718 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
8719 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
8720 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
8721 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
8722 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
8723 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
8724 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
8725 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
8726 
8727 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
8728 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
8729 
8730 	rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
8731 
8732 	rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
8733 	rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
8734 
8735 	bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8736 	rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
8737 			  2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
8738 	rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8739 
8740 	rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8741 	rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8742 }
8743 
8744 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
8745 {
8746 	/* Initialize RF central register to default value */
8747 	rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
8748 	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8749 	rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
8750 	rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
8751 	rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
8752 	rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
8753 	rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
8754 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8755 	rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
8756 	rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
8757 	rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
8758 	rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
8759 	rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
8760 	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8761 	rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
8762 	rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
8763 	rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
8764 	rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
8765 	rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
8766 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8767 	rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
8768 	rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
8769 	rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
8770 	rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
8771 	rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
8772 	rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
8773 	rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
8774 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8775 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8776 	rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
8777 	rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
8778 	rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
8779 	rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
8780 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8781 	rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
8782 	rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8783 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8784 	rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8785 	rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
8786 	rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
8787 	rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8788 	rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
8789 	rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
8790 	rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8791 
8792 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
8793 	if (rt2800_clk_is_20mhz(rt2x00dev))
8794 		rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
8795 	else
8796 		rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8797 	rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
8798 	rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
8799 	rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
8800 	rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
8801 	rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
8802 	rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
8803 	rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
8804 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
8805 	rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
8806 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8807 	rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8808 	rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
8809 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8810 	rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
8811 	rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
8812 	rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
8813 
8814 	rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
8815 	rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
8816 	rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
8817 
8818 	/* Initialize RF channel register to default value */
8819 	rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
8820 	rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
8821 	rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
8822 	rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
8823 	rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
8824 	rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
8825 	rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
8826 	rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
8827 	rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
8828 	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
8829 	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
8830 	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8831 	rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
8832 	rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
8833 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8834 	rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
8835 	rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
8836 	rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
8837 	rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
8838 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8839 	rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
8840 	rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
8841 	rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
8842 	rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
8843 	rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
8844 	rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
8845 	rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
8846 	rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
8847 	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
8848 	rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
8849 	rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
8850 	rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
8851 	rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
8852 	rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
8853 	rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
8854 	rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
8855 	rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
8856 	rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
8857 	rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
8858 	rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
8859 	rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
8860 	rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
8861 	rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
8862 	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
8863 	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
8864 	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8865 	rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
8866 	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
8867 	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
8868 	rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
8869 	rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
8870 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
8871 	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
8872 	rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
8873 	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
8874 	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
8875 	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
8876 	rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
8877 	rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
8878 	rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
8879 
8880 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
8881 
8882 	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
8883 	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
8884 	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
8885 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
8886 	rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
8887 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
8888 	rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
8889 	rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
8890 	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
8891 	rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
8892 	rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
8893 	rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
8894 	rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
8895 	rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
8896 	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8897 	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
8898 	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8899 	rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
8900 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
8901 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
8902 	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
8903 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
8904 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
8905 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8906 	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
8907 	rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
8908 	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
8909 	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8910 	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
8911 	rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
8912 
8913 	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
8914 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8915 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8916 	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
8917 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
8918 	rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
8919 	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
8920 	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8921 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
8922 
8923 	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
8924 	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
8925 	rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
8926 	rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
8927 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8928 	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8929 
8930 	/* Initialize RF channel register for DRQFN */
8931 	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8932 	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
8933 	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
8934 	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
8935 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
8936 	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
8937 	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
8938 	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
8939 
8940 	/* Initialize RF DC calibration register to default value */
8941 	rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
8942 	rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
8943 	rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
8944 	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
8945 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
8946 	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8947 	rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
8948 	rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
8949 	rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
8950 	rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
8951 	rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
8952 	rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
8953 	rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
8954 	rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
8955 	rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
8956 	rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
8957 	rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
8958 	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
8959 	rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
8960 	rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
8961 	rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8962 	rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
8963 	rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
8964 	rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
8965 	rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
8966 	rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
8967 	rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
8968 	rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
8969 	rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
8970 	rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
8971 	rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
8972 	rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
8973 	rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
8974 	rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
8975 	rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
8976 	rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
8977 	rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
8978 	rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
8979 	rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
8980 	rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
8981 	rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
8982 	rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
8983 	rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
8984 	rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
8985 	rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
8986 	rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
8987 	rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
8988 	rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
8989 	rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
8990 	rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
8991 	rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
8992 	rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
8993 	rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
8994 	rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
8995 	rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
8996 	rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
8997 	rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
8998 	rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
8999 	rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
9000 
9001 	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
9002 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
9003 	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
9004 
9005 	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
9006 	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
9007 
9008 	rt2800_bw_filter_calibration(rt2x00dev, true);
9009 	rt2800_bw_filter_calibration(rt2x00dev, false);
9010 }
9011 
9012 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
9013 {
9014 	if (rt2800_is_305x_soc(rt2x00dev)) {
9015 		rt2800_init_rfcsr_305x_soc(rt2x00dev);
9016 		return;
9017 	}
9018 
9019 	switch (rt2x00dev->chip.rt) {
9020 	case RT3070:
9021 	case RT3071:
9022 	case RT3090:
9023 		rt2800_init_rfcsr_30xx(rt2x00dev);
9024 		break;
9025 	case RT3290:
9026 		rt2800_init_rfcsr_3290(rt2x00dev);
9027 		break;
9028 	case RT3352:
9029 		rt2800_init_rfcsr_3352(rt2x00dev);
9030 		break;
9031 	case RT3390:
9032 		rt2800_init_rfcsr_3390(rt2x00dev);
9033 		break;
9034 	case RT3883:
9035 		rt2800_init_rfcsr_3883(rt2x00dev);
9036 		break;
9037 	case RT3572:
9038 		rt2800_init_rfcsr_3572(rt2x00dev);
9039 		break;
9040 	case RT3593:
9041 		rt2800_init_rfcsr_3593(rt2x00dev);
9042 		break;
9043 	case RT5350:
9044 		rt2800_init_rfcsr_5350(rt2x00dev);
9045 		break;
9046 	case RT5390:
9047 		rt2800_init_rfcsr_5390(rt2x00dev);
9048 		break;
9049 	case RT5392:
9050 		rt2800_init_rfcsr_5392(rt2x00dev);
9051 		break;
9052 	case RT5592:
9053 		rt2800_init_rfcsr_5592(rt2x00dev);
9054 		break;
9055 	case RT6352:
9056 		rt2800_init_rfcsr_6352(rt2x00dev);
9057 		break;
9058 	}
9059 }
9060 
9061 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
9062 {
9063 	u32 reg;
9064 	u16 word;
9065 
9066 	/*
9067 	 * Initialize MAC registers.
9068 	 */
9069 	if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
9070 		     rt2800_init_registers(rt2x00dev)))
9071 		return -EIO;
9072 
9073 	/*
9074 	 * Wait BBP/RF to wake up.
9075 	 */
9076 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
9077 		return -EIO;
9078 
9079 	/*
9080 	 * Send signal during boot time to initialize firmware.
9081 	 */
9082 	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
9083 	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
9084 	if (rt2x00_is_usb(rt2x00dev))
9085 		rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
9086 	rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
9087 	msleep(1);
9088 
9089 	/*
9090 	 * Make sure BBP is up and running.
9091 	 */
9092 	if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
9093 		return -EIO;
9094 
9095 	/*
9096 	 * Initialize BBP/RF registers.
9097 	 */
9098 	rt2800_init_bbp(rt2x00dev);
9099 	rt2800_init_rfcsr(rt2x00dev);
9100 
9101 	if (rt2x00_is_usb(rt2x00dev) &&
9102 	    (rt2x00_rt(rt2x00dev, RT3070) ||
9103 	     rt2x00_rt(rt2x00dev, RT3071) ||
9104 	     rt2x00_rt(rt2x00dev, RT3572))) {
9105 		udelay(200);
9106 		rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
9107 		udelay(10);
9108 	}
9109 
9110 	/*
9111 	 * Enable RX.
9112 	 */
9113 	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9114 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
9115 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9116 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9117 
9118 	udelay(50);
9119 
9120 	reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
9121 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
9122 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
9123 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9124 	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
9125 
9126 	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9127 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
9128 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9129 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9130 
9131 	/*
9132 	 * Initialize LED control
9133 	 */
9134 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
9135 	rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
9136 			   word & 0xff, (word >> 8) & 0xff);
9137 
9138 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
9139 	rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
9140 			   word & 0xff, (word >> 8) & 0xff);
9141 
9142 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
9143 	rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
9144 			   word & 0xff, (word >> 8) & 0xff);
9145 
9146 	return 0;
9147 }
9148 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
9149 
9150 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
9151 {
9152 	u32 reg;
9153 
9154 	rt2800_disable_wpdma(rt2x00dev);
9155 
9156 	/* Wait for DMA, ignore error */
9157 	rt2800_wait_wpdma_ready(rt2x00dev);
9158 
9159 	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9160 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
9161 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9162 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9163 }
9164 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
9165 
9166 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
9167 {
9168 	u32 reg;
9169 	u16 efuse_ctrl_reg;
9170 
9171 	if (rt2x00_rt(rt2x00dev, RT3290))
9172 		efuse_ctrl_reg = EFUSE_CTRL_3290;
9173 	else
9174 		efuse_ctrl_reg = EFUSE_CTRL;
9175 
9176 	reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
9177 	return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
9178 }
9179 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
9180 
9181 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
9182 {
9183 	u32 reg;
9184 	u16 efuse_ctrl_reg;
9185 	u16 efuse_data0_reg;
9186 	u16 efuse_data1_reg;
9187 	u16 efuse_data2_reg;
9188 	u16 efuse_data3_reg;
9189 
9190 	if (rt2x00_rt(rt2x00dev, RT3290)) {
9191 		efuse_ctrl_reg = EFUSE_CTRL_3290;
9192 		efuse_data0_reg = EFUSE_DATA0_3290;
9193 		efuse_data1_reg = EFUSE_DATA1_3290;
9194 		efuse_data2_reg = EFUSE_DATA2_3290;
9195 		efuse_data3_reg = EFUSE_DATA3_3290;
9196 	} else {
9197 		efuse_ctrl_reg = EFUSE_CTRL;
9198 		efuse_data0_reg = EFUSE_DATA0;
9199 		efuse_data1_reg = EFUSE_DATA1;
9200 		efuse_data2_reg = EFUSE_DATA2;
9201 		efuse_data3_reg = EFUSE_DATA3;
9202 	}
9203 	mutex_lock(&rt2x00dev->csr_mutex);
9204 
9205 	reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
9206 	rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
9207 	rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
9208 	rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
9209 	rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
9210 
9211 	/* Wait until the EEPROM has been loaded */
9212 	rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
9213 	/* Apparently the data is read from end to start */
9214 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
9215 	/* The returned value is in CPU order, but eeprom is le */
9216 	*(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
9217 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
9218 	*(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
9219 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
9220 	*(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
9221 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
9222 	*(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
9223 
9224 	mutex_unlock(&rt2x00dev->csr_mutex);
9225 }
9226 
9227 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
9228 {
9229 	unsigned int i;
9230 
9231 	for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
9232 		rt2800_efuse_read(rt2x00dev, i);
9233 
9234 	return 0;
9235 }
9236 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
9237 
9238 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
9239 {
9240 	u16 word;
9241 
9242 	if (rt2x00_rt(rt2x00dev, RT3593) ||
9243 	    rt2x00_rt(rt2x00dev, RT3883))
9244 		return 0;
9245 
9246 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
9247 	if ((word & 0x00ff) != 0x00ff)
9248 		return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
9249 
9250 	return 0;
9251 }
9252 
9253 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
9254 {
9255 	u16 word;
9256 
9257 	if (rt2x00_rt(rt2x00dev, RT3593) ||
9258 	    rt2x00_rt(rt2x00dev, RT3883))
9259 		return 0;
9260 
9261 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
9262 	if ((word & 0x00ff) != 0x00ff)
9263 		return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
9264 
9265 	return 0;
9266 }
9267 
9268 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
9269 {
9270 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
9271 	u16 word;
9272 	u8 *mac;
9273 	u8 default_lna_gain;
9274 	int retval;
9275 
9276 	/*
9277 	 * Read the EEPROM.
9278 	 */
9279 	retval = rt2800_read_eeprom(rt2x00dev);
9280 	if (retval)
9281 		return retval;
9282 
9283 	/*
9284 	 * Start validation of the data that has been read.
9285 	 */
9286 	mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
9287 	rt2x00lib_set_mac_address(rt2x00dev, mac);
9288 
9289 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
9290 	if (word == 0xffff) {
9291 		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
9292 		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
9293 		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
9294 		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
9295 		rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
9296 	} else if (rt2x00_rt(rt2x00dev, RT2860) ||
9297 		   rt2x00_rt(rt2x00dev, RT2872)) {
9298 		/*
9299 		 * There is a max of 2 RX streams for RT28x0 series
9300 		 */
9301 		if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
9302 			rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
9303 		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
9304 	}
9305 
9306 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9307 	if (word == 0xffff) {
9308 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
9309 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
9310 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
9311 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
9312 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
9313 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
9314 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
9315 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
9316 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
9317 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
9318 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
9319 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
9320 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
9321 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
9322 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
9323 		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
9324 		rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
9325 	}
9326 
9327 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
9328 	if ((word & 0x00ff) == 0x00ff) {
9329 		rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
9330 		rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
9331 		rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
9332 	}
9333 	if ((word & 0xff00) == 0xff00) {
9334 		rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
9335 				   LED_MODE_TXRX_ACTIVITY);
9336 		rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
9337 		rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
9338 		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
9339 		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
9340 		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
9341 		rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
9342 	}
9343 
9344 	/*
9345 	 * During the LNA validation we are going to use
9346 	 * lna0 as correct value. Note that EEPROM_LNA
9347 	 * is never validated.
9348 	 */
9349 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
9350 	default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
9351 
9352 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
9353 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
9354 		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
9355 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
9356 		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
9357 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
9358 
9359 	drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
9360 
9361 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
9362 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
9363 		rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
9364 	if (!rt2x00_rt(rt2x00dev, RT3593) &&
9365 	    !rt2x00_rt(rt2x00dev, RT3883)) {
9366 		if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
9367 		    rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
9368 			rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
9369 					   default_lna_gain);
9370 	}
9371 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
9372 
9373 	drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
9374 
9375 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
9376 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
9377 		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
9378 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
9379 		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
9380 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
9381 
9382 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
9383 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
9384 		rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
9385 	if (!rt2x00_rt(rt2x00dev, RT3593) &&
9386 	    !rt2x00_rt(rt2x00dev, RT3883)) {
9387 		if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
9388 		    rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
9389 			rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
9390 					   default_lna_gain);
9391 	}
9392 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
9393 
9394 	if (rt2x00_rt(rt2x00dev, RT3593) ||
9395 	    rt2x00_rt(rt2x00dev, RT3883)) {
9396 		word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
9397 		if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
9398 		    rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
9399 			rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
9400 					   default_lna_gain);
9401 		if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
9402 		    rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
9403 			rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
9404 					   default_lna_gain);
9405 		rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
9406 	}
9407 
9408 	return 0;
9409 }
9410 
9411 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
9412 {
9413 	u16 value;
9414 	u16 eeprom;
9415 	u16 rf;
9416 
9417 	/*
9418 	 * Read EEPROM word for configuration.
9419 	 */
9420 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
9421 
9422 	/*
9423 	 * Identify RF chipset by EEPROM value
9424 	 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
9425 	 * RT53xx: defined in "EEPROM_CHIP_ID" field
9426 	 */
9427 	if (rt2x00_rt(rt2x00dev, RT3290) ||
9428 	    rt2x00_rt(rt2x00dev, RT5390) ||
9429 	    rt2x00_rt(rt2x00dev, RT5392) ||
9430 	    rt2x00_rt(rt2x00dev, RT6352))
9431 		rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
9432 	else if (rt2x00_rt(rt2x00dev, RT3352))
9433 		rf = RF3322;
9434 	else if (rt2x00_rt(rt2x00dev, RT3883))
9435 		rf = RF3853;
9436 	else if (rt2x00_rt(rt2x00dev, RT5350))
9437 		rf = RF5350;
9438 	else
9439 		rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
9440 
9441 	switch (rf) {
9442 	case RF2820:
9443 	case RF2850:
9444 	case RF2720:
9445 	case RF2750:
9446 	case RF3020:
9447 	case RF2020:
9448 	case RF3021:
9449 	case RF3022:
9450 	case RF3052:
9451 	case RF3053:
9452 	case RF3070:
9453 	case RF3290:
9454 	case RF3320:
9455 	case RF3322:
9456 	case RF3853:
9457 	case RF5350:
9458 	case RF5360:
9459 	case RF5362:
9460 	case RF5370:
9461 	case RF5372:
9462 	case RF5390:
9463 	case RF5392:
9464 	case RF5592:
9465 	case RF7620:
9466 		break;
9467 	default:
9468 		rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
9469 			   rf);
9470 		return -ENODEV;
9471 	}
9472 
9473 	rt2x00_set_rf(rt2x00dev, rf);
9474 
9475 	/*
9476 	 * Identify default antenna configuration.
9477 	 */
9478 	rt2x00dev->default_ant.tx_chain_num =
9479 	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
9480 	rt2x00dev->default_ant.rx_chain_num =
9481 	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
9482 
9483 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9484 
9485 	if (rt2x00_rt(rt2x00dev, RT3070) ||
9486 	    rt2x00_rt(rt2x00dev, RT3090) ||
9487 	    rt2x00_rt(rt2x00dev, RT3352) ||
9488 	    rt2x00_rt(rt2x00dev, RT3390)) {
9489 		value = rt2x00_get_field16(eeprom,
9490 				EEPROM_NIC_CONF1_ANT_DIVERSITY);
9491 		switch (value) {
9492 		case 0:
9493 		case 1:
9494 		case 2:
9495 			rt2x00dev->default_ant.tx = ANTENNA_A;
9496 			rt2x00dev->default_ant.rx = ANTENNA_A;
9497 			break;
9498 		case 3:
9499 			rt2x00dev->default_ant.tx = ANTENNA_A;
9500 			rt2x00dev->default_ant.rx = ANTENNA_B;
9501 			break;
9502 		}
9503 	} else {
9504 		rt2x00dev->default_ant.tx = ANTENNA_A;
9505 		rt2x00dev->default_ant.rx = ANTENNA_A;
9506 	}
9507 
9508 	/* These chips have hardware RX antenna diversity */
9509 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
9510 	    rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
9511 		rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
9512 		rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
9513 	}
9514 
9515 	/*
9516 	 * Determine external LNA informations.
9517 	 */
9518 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
9519 		__set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
9520 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
9521 		__set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
9522 
9523 	/*
9524 	 * Detect if this device has an hardware controlled radio.
9525 	 */
9526 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
9527 		__set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
9528 
9529 	/*
9530 	 * Detect if this device has Bluetooth co-existence.
9531 	 */
9532 	if (!rt2x00_rt(rt2x00dev, RT3352) &&
9533 	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
9534 		__set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
9535 
9536 	/*
9537 	 * Read frequency offset and RF programming sequence.
9538 	 */
9539 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
9540 	rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
9541 
9542 	/*
9543 	 * Store led settings, for correct led behaviour.
9544 	 */
9545 #ifdef CONFIG_RT2X00_LIB_LEDS
9546 	rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
9547 	rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
9548 	rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
9549 
9550 	rt2x00dev->led_mcu_reg = eeprom;
9551 #endif /* CONFIG_RT2X00_LIB_LEDS */
9552 
9553 	/*
9554 	 * Check if support EIRP tx power limit feature.
9555 	 */
9556 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
9557 
9558 	if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
9559 					EIRP_MAX_TX_POWER_LIMIT)
9560 		__set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
9561 
9562 	/*
9563 	 * Detect if device uses internal or external PA
9564 	 */
9565 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9566 
9567 	if (rt2x00_rt(rt2x00dev, RT3352)) {
9568 		if (rt2x00_get_field16(eeprom,
9569 		    EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
9570 		    __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
9571 			      &rt2x00dev->cap_flags);
9572 		if (rt2x00_get_field16(eeprom,
9573 		    EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
9574 		    __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
9575 			      &rt2x00dev->cap_flags);
9576 	}
9577 
9578 	return 0;
9579 }
9580 
9581 /*
9582  * RF value list for rt28xx
9583  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
9584  */
9585 static const struct rf_channel rf_vals[] = {
9586 	{ 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
9587 	{ 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
9588 	{ 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
9589 	{ 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
9590 	{ 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
9591 	{ 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
9592 	{ 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
9593 	{ 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
9594 	{ 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
9595 	{ 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
9596 	{ 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
9597 	{ 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
9598 	{ 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
9599 	{ 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
9600 
9601 	/* 802.11 UNI / HyperLan 2 */
9602 	{ 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
9603 	{ 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
9604 	{ 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
9605 	{ 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
9606 	{ 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
9607 	{ 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
9608 	{ 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
9609 	{ 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
9610 	{ 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
9611 	{ 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
9612 	{ 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
9613 	{ 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
9614 
9615 	/* 802.11 HyperLan 2 */
9616 	{ 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
9617 	{ 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
9618 	{ 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
9619 	{ 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
9620 	{ 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
9621 	{ 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
9622 	{ 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
9623 	{ 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
9624 	{ 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
9625 	{ 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
9626 	{ 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
9627 	{ 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
9628 	{ 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
9629 	{ 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
9630 	{ 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
9631 	{ 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
9632 
9633 	/* 802.11 UNII */
9634 	{ 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
9635 	{ 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
9636 	{ 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
9637 	{ 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
9638 	{ 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
9639 	{ 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
9640 	{ 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
9641 	{ 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
9642 	{ 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
9643 	{ 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
9644 	{ 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
9645 
9646 	/* 802.11 Japan */
9647 	{ 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
9648 	{ 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
9649 	{ 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
9650 	{ 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
9651 	{ 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
9652 	{ 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
9653 	{ 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
9654 };
9655 
9656 /*
9657  * RF value list for rt3xxx
9658  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
9659  */
9660 static const struct rf_channel rf_vals_3x[] = {
9661 	{1,  241, 2, 2 },
9662 	{2,  241, 2, 7 },
9663 	{3,  242, 2, 2 },
9664 	{4,  242, 2, 7 },
9665 	{5,  243, 2, 2 },
9666 	{6,  243, 2, 7 },
9667 	{7,  244, 2, 2 },
9668 	{8,  244, 2, 7 },
9669 	{9,  245, 2, 2 },
9670 	{10, 245, 2, 7 },
9671 	{11, 246, 2, 2 },
9672 	{12, 246, 2, 7 },
9673 	{13, 247, 2, 2 },
9674 	{14, 248, 2, 4 },
9675 
9676 	/* 802.11 UNI / HyperLan 2 */
9677 	{36, 0x56, 0, 4},
9678 	{38, 0x56, 0, 6},
9679 	{40, 0x56, 0, 8},
9680 	{44, 0x57, 0, 0},
9681 	{46, 0x57, 0, 2},
9682 	{48, 0x57, 0, 4},
9683 	{52, 0x57, 0, 8},
9684 	{54, 0x57, 0, 10},
9685 	{56, 0x58, 0, 0},
9686 	{60, 0x58, 0, 4},
9687 	{62, 0x58, 0, 6},
9688 	{64, 0x58, 0, 8},
9689 
9690 	/* 802.11 HyperLan 2 */
9691 	{100, 0x5b, 0, 8},
9692 	{102, 0x5b, 0, 10},
9693 	{104, 0x5c, 0, 0},
9694 	{108, 0x5c, 0, 4},
9695 	{110, 0x5c, 0, 6},
9696 	{112, 0x5c, 0, 8},
9697 	{116, 0x5d, 0, 0},
9698 	{118, 0x5d, 0, 2},
9699 	{120, 0x5d, 0, 4},
9700 	{124, 0x5d, 0, 8},
9701 	{126, 0x5d, 0, 10},
9702 	{128, 0x5e, 0, 0},
9703 	{132, 0x5e, 0, 4},
9704 	{134, 0x5e, 0, 6},
9705 	{136, 0x5e, 0, 8},
9706 	{140, 0x5f, 0, 0},
9707 
9708 	/* 802.11 UNII */
9709 	{149, 0x5f, 0, 9},
9710 	{151, 0x5f, 0, 11},
9711 	{153, 0x60, 0, 1},
9712 	{157, 0x60, 0, 5},
9713 	{159, 0x60, 0, 7},
9714 	{161, 0x60, 0, 9},
9715 	{165, 0x61, 0, 1},
9716 	{167, 0x61, 0, 3},
9717 	{169, 0x61, 0, 5},
9718 	{171, 0x61, 0, 7},
9719 	{173, 0x61, 0, 9},
9720 };
9721 
9722 /*
9723  * RF value list for rt3xxx with Xtal20MHz
9724  * Supports: 2.4 GHz (all) (RF3322)
9725  */
9726 static const struct rf_channel rf_vals_3x_xtal20[] = {
9727 	{1,    0xE2,	 2,  0x14},
9728 	{2,    0xE3,	 2,  0x14},
9729 	{3,    0xE4,	 2,  0x14},
9730 	{4,    0xE5,	 2,  0x14},
9731 	{5,    0xE6,	 2,  0x14},
9732 	{6,    0xE7,	 2,  0x14},
9733 	{7,    0xE8,	 2,  0x14},
9734 	{8,    0xE9,	 2,  0x14},
9735 	{9,    0xEA,	 2,  0x14},
9736 	{10,   0xEB,	 2,  0x14},
9737 	{11,   0xEC,	 2,  0x14},
9738 	{12,   0xED,	 2,  0x14},
9739 	{13,   0xEE,	 2,  0x14},
9740 	{14,   0xF0,	 2,  0x18},
9741 };
9742 
9743 static const struct rf_channel rf_vals_3853[] = {
9744 	{1,  241, 6, 2},
9745 	{2,  241, 6, 7},
9746 	{3,  242, 6, 2},
9747 	{4,  242, 6, 7},
9748 	{5,  243, 6, 2},
9749 	{6,  243, 6, 7},
9750 	{7,  244, 6, 2},
9751 	{8,  244, 6, 7},
9752 	{9,  245, 6, 2},
9753 	{10, 245, 6, 7},
9754 	{11, 246, 6, 2},
9755 	{12, 246, 6, 7},
9756 	{13, 247, 6, 2},
9757 	{14, 248, 6, 4},
9758 
9759 	{36, 0x56, 8, 4},
9760 	{38, 0x56, 8, 6},
9761 	{40, 0x56, 8, 8},
9762 	{44, 0x57, 8, 0},
9763 	{46, 0x57, 8, 2},
9764 	{48, 0x57, 8, 4},
9765 	{52, 0x57, 8, 8},
9766 	{54, 0x57, 8, 10},
9767 	{56, 0x58, 8, 0},
9768 	{60, 0x58, 8, 4},
9769 	{62, 0x58, 8, 6},
9770 	{64, 0x58, 8, 8},
9771 
9772 	{100, 0x5b, 8, 8},
9773 	{102, 0x5b, 8, 10},
9774 	{104, 0x5c, 8, 0},
9775 	{108, 0x5c, 8, 4},
9776 	{110, 0x5c, 8, 6},
9777 	{112, 0x5c, 8, 8},
9778 	{114, 0x5c, 8, 10},
9779 	{116, 0x5d, 8, 0},
9780 	{118, 0x5d, 8, 2},
9781 	{120, 0x5d, 8, 4},
9782 	{124, 0x5d, 8, 8},
9783 	{126, 0x5d, 8, 10},
9784 	{128, 0x5e, 8, 0},
9785 	{132, 0x5e, 8, 4},
9786 	{134, 0x5e, 8, 6},
9787 	{136, 0x5e, 8, 8},
9788 	{140, 0x5f, 8, 0},
9789 
9790 	{149, 0x5f, 8, 9},
9791 	{151, 0x5f, 8, 11},
9792 	{153, 0x60, 8, 1},
9793 	{157, 0x60, 8, 5},
9794 	{159, 0x60, 8, 7},
9795 	{161, 0x60, 8, 9},
9796 	{165, 0x61, 8, 1},
9797 	{167, 0x61, 8, 3},
9798 	{169, 0x61, 8, 5},
9799 	{171, 0x61, 8, 7},
9800 	{173, 0x61, 8, 9},
9801 };
9802 
9803 static const struct rf_channel rf_vals_5592_xtal20[] = {
9804 	/* Channel, N, K, mod, R */
9805 	{1, 482, 4, 10, 3},
9806 	{2, 483, 4, 10, 3},
9807 	{3, 484, 4, 10, 3},
9808 	{4, 485, 4, 10, 3},
9809 	{5, 486, 4, 10, 3},
9810 	{6, 487, 4, 10, 3},
9811 	{7, 488, 4, 10, 3},
9812 	{8, 489, 4, 10, 3},
9813 	{9, 490, 4, 10, 3},
9814 	{10, 491, 4, 10, 3},
9815 	{11, 492, 4, 10, 3},
9816 	{12, 493, 4, 10, 3},
9817 	{13, 494, 4, 10, 3},
9818 	{14, 496, 8, 10, 3},
9819 	{36, 172, 8, 12, 1},
9820 	{38, 173, 0, 12, 1},
9821 	{40, 173, 4, 12, 1},
9822 	{42, 173, 8, 12, 1},
9823 	{44, 174, 0, 12, 1},
9824 	{46, 174, 4, 12, 1},
9825 	{48, 174, 8, 12, 1},
9826 	{50, 175, 0, 12, 1},
9827 	{52, 175, 4, 12, 1},
9828 	{54, 175, 8, 12, 1},
9829 	{56, 176, 0, 12, 1},
9830 	{58, 176, 4, 12, 1},
9831 	{60, 176, 8, 12, 1},
9832 	{62, 177, 0, 12, 1},
9833 	{64, 177, 4, 12, 1},
9834 	{100, 183, 4, 12, 1},
9835 	{102, 183, 8, 12, 1},
9836 	{104, 184, 0, 12, 1},
9837 	{106, 184, 4, 12, 1},
9838 	{108, 184, 8, 12, 1},
9839 	{110, 185, 0, 12, 1},
9840 	{112, 185, 4, 12, 1},
9841 	{114, 185, 8, 12, 1},
9842 	{116, 186, 0, 12, 1},
9843 	{118, 186, 4, 12, 1},
9844 	{120, 186, 8, 12, 1},
9845 	{122, 187, 0, 12, 1},
9846 	{124, 187, 4, 12, 1},
9847 	{126, 187, 8, 12, 1},
9848 	{128, 188, 0, 12, 1},
9849 	{130, 188, 4, 12, 1},
9850 	{132, 188, 8, 12, 1},
9851 	{134, 189, 0, 12, 1},
9852 	{136, 189, 4, 12, 1},
9853 	{138, 189, 8, 12, 1},
9854 	{140, 190, 0, 12, 1},
9855 	{149, 191, 6, 12, 1},
9856 	{151, 191, 10, 12, 1},
9857 	{153, 192, 2, 12, 1},
9858 	{155, 192, 6, 12, 1},
9859 	{157, 192, 10, 12, 1},
9860 	{159, 193, 2, 12, 1},
9861 	{161, 193, 6, 12, 1},
9862 	{165, 194, 2, 12, 1},
9863 	{184, 164, 0, 12, 1},
9864 	{188, 164, 4, 12, 1},
9865 	{192, 165, 8, 12, 1},
9866 	{196, 166, 0, 12, 1},
9867 };
9868 
9869 static const struct rf_channel rf_vals_5592_xtal40[] = {
9870 	/* Channel, N, K, mod, R */
9871 	{1, 241, 2, 10, 3},
9872 	{2, 241, 7, 10, 3},
9873 	{3, 242, 2, 10, 3},
9874 	{4, 242, 7, 10, 3},
9875 	{5, 243, 2, 10, 3},
9876 	{6, 243, 7, 10, 3},
9877 	{7, 244, 2, 10, 3},
9878 	{8, 244, 7, 10, 3},
9879 	{9, 245, 2, 10, 3},
9880 	{10, 245, 7, 10, 3},
9881 	{11, 246, 2, 10, 3},
9882 	{12, 246, 7, 10, 3},
9883 	{13, 247, 2, 10, 3},
9884 	{14, 248, 4, 10, 3},
9885 	{36, 86, 4, 12, 1},
9886 	{38, 86, 6, 12, 1},
9887 	{40, 86, 8, 12, 1},
9888 	{42, 86, 10, 12, 1},
9889 	{44, 87, 0, 12, 1},
9890 	{46, 87, 2, 12, 1},
9891 	{48, 87, 4, 12, 1},
9892 	{50, 87, 6, 12, 1},
9893 	{52, 87, 8, 12, 1},
9894 	{54, 87, 10, 12, 1},
9895 	{56, 88, 0, 12, 1},
9896 	{58, 88, 2, 12, 1},
9897 	{60, 88, 4, 12, 1},
9898 	{62, 88, 6, 12, 1},
9899 	{64, 88, 8, 12, 1},
9900 	{100, 91, 8, 12, 1},
9901 	{102, 91, 10, 12, 1},
9902 	{104, 92, 0, 12, 1},
9903 	{106, 92, 2, 12, 1},
9904 	{108, 92, 4, 12, 1},
9905 	{110, 92, 6, 12, 1},
9906 	{112, 92, 8, 12, 1},
9907 	{114, 92, 10, 12, 1},
9908 	{116, 93, 0, 12, 1},
9909 	{118, 93, 2, 12, 1},
9910 	{120, 93, 4, 12, 1},
9911 	{122, 93, 6, 12, 1},
9912 	{124, 93, 8, 12, 1},
9913 	{126, 93, 10, 12, 1},
9914 	{128, 94, 0, 12, 1},
9915 	{130, 94, 2, 12, 1},
9916 	{132, 94, 4, 12, 1},
9917 	{134, 94, 6, 12, 1},
9918 	{136, 94, 8, 12, 1},
9919 	{138, 94, 10, 12, 1},
9920 	{140, 95, 0, 12, 1},
9921 	{149, 95, 9, 12, 1},
9922 	{151, 95, 11, 12, 1},
9923 	{153, 96, 1, 12, 1},
9924 	{155, 96, 3, 12, 1},
9925 	{157, 96, 5, 12, 1},
9926 	{159, 96, 7, 12, 1},
9927 	{161, 96, 9, 12, 1},
9928 	{165, 97, 1, 12, 1},
9929 	{184, 82, 0, 12, 1},
9930 	{188, 82, 4, 12, 1},
9931 	{192, 82, 8, 12, 1},
9932 	{196, 83, 0, 12, 1},
9933 };
9934 
9935 static const struct rf_channel rf_vals_7620[] = {
9936 	{1, 0x50, 0x99, 0x99, 1},
9937 	{2, 0x50, 0x44, 0x44, 2},
9938 	{3, 0x50, 0xEE, 0xEE, 2},
9939 	{4, 0x50, 0x99, 0x99, 3},
9940 	{5, 0x51, 0x44, 0x44, 0},
9941 	{6, 0x51, 0xEE, 0xEE, 0},
9942 	{7, 0x51, 0x99, 0x99, 1},
9943 	{8, 0x51, 0x44, 0x44, 2},
9944 	{9, 0x51, 0xEE, 0xEE, 2},
9945 	{10, 0x51, 0x99, 0x99, 3},
9946 	{11, 0x52, 0x44, 0x44, 0},
9947 	{12, 0x52, 0xEE, 0xEE, 0},
9948 	{13, 0x52, 0x99, 0x99, 1},
9949 	{14, 0x52, 0x33, 0x33, 3},
9950 };
9951 
9952 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
9953 {
9954 	struct hw_mode_spec *spec = &rt2x00dev->spec;
9955 	struct channel_info *info;
9956 	char *default_power1;
9957 	char *default_power2;
9958 	char *default_power3;
9959 	unsigned int i, tx_chains, rx_chains;
9960 	u32 reg;
9961 
9962 	/*
9963 	 * Disable powersaving as default.
9964 	 */
9965 	rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
9966 
9967 	/*
9968 	 * Change default retry settings to values corresponding more closely
9969 	 * to rate[0].count setting of minstrel rate control algorithm.
9970 	 */
9971 	rt2x00dev->hw->wiphy->retry_short = 2;
9972 	rt2x00dev->hw->wiphy->retry_long = 2;
9973 
9974 	/*
9975 	 * Initialize all hw fields.
9976 	 */
9977 	ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
9978 	ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
9979 	ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
9980 	ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
9981 	ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9982 
9983 	/*
9984 	 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
9985 	 * unless we are capable of sending the buffered frames out after the
9986 	 * DTIM transmission using rt2x00lib_beacondone. This will send out
9987 	 * multicast and broadcast traffic immediately instead of buffering it
9988 	 * infinitly and thus dropping it after some time.
9989 	 */
9990 	if (!rt2x00_is_usb(rt2x00dev))
9991 		ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
9992 
9993 	ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
9994 
9995 	SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
9996 	SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
9997 				rt2800_eeprom_addr(rt2x00dev,
9998 						   EEPROM_MAC_ADDR_0));
9999 
10000 	/*
10001 	 * As rt2800 has a global fallback table we cannot specify
10002 	 * more then one tx rate per frame but since the hw will
10003 	 * try several rates (based on the fallback table) we should
10004 	 * initialize max_report_rates to the maximum number of rates
10005 	 * we are going to try. Otherwise mac80211 will truncate our
10006 	 * reported tx rates and the rc algortihm will end up with
10007 	 * incorrect data.
10008 	 */
10009 	rt2x00dev->hw->max_rates = 1;
10010 	rt2x00dev->hw->max_report_rates = 7;
10011 	rt2x00dev->hw->max_rate_tries = 1;
10012 
10013 	/*
10014 	 * Initialize hw_mode information.
10015 	 */
10016 	spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
10017 
10018 	switch (rt2x00dev->chip.rf) {
10019 	case RF2720:
10020 	case RF2820:
10021 		spec->num_channels = 14;
10022 		spec->channels = rf_vals;
10023 		break;
10024 
10025 	case RF2750:
10026 	case RF2850:
10027 		spec->num_channels = ARRAY_SIZE(rf_vals);
10028 		spec->channels = rf_vals;
10029 		break;
10030 
10031 	case RF2020:
10032 	case RF3020:
10033 	case RF3021:
10034 	case RF3022:
10035 	case RF3070:
10036 	case RF3290:
10037 	case RF3320:
10038 	case RF3322:
10039 	case RF5350:
10040 	case RF5360:
10041 	case RF5362:
10042 	case RF5370:
10043 	case RF5372:
10044 	case RF5390:
10045 	case RF5392:
10046 		spec->num_channels = 14;
10047 		if (rt2800_clk_is_20mhz(rt2x00dev))
10048 			spec->channels = rf_vals_3x_xtal20;
10049 		else
10050 			spec->channels = rf_vals_3x;
10051 		break;
10052 
10053 	case RF7620:
10054 		spec->num_channels = ARRAY_SIZE(rf_vals_7620);
10055 		spec->channels = rf_vals_7620;
10056 		break;
10057 
10058 	case RF3052:
10059 	case RF3053:
10060 		spec->num_channels = ARRAY_SIZE(rf_vals_3x);
10061 		spec->channels = rf_vals_3x;
10062 		break;
10063 
10064 	case RF3853:
10065 		spec->num_channels = ARRAY_SIZE(rf_vals_3853);
10066 		spec->channels = rf_vals_3853;
10067 		break;
10068 
10069 	case RF5592:
10070 		reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
10071 		if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
10072 			spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
10073 			spec->channels = rf_vals_5592_xtal40;
10074 		} else {
10075 			spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
10076 			spec->channels = rf_vals_5592_xtal20;
10077 		}
10078 		break;
10079 	}
10080 
10081 	if (WARN_ON_ONCE(!spec->channels))
10082 		return -ENODEV;
10083 
10084 	spec->supported_bands = SUPPORT_BAND_2GHZ;
10085 	if (spec->num_channels > 14)
10086 		spec->supported_bands |= SUPPORT_BAND_5GHZ;
10087 
10088 	/*
10089 	 * Initialize HT information.
10090 	 */
10091 	if (!rt2x00_rf(rt2x00dev, RF2020))
10092 		spec->ht.ht_supported = true;
10093 	else
10094 		spec->ht.ht_supported = false;
10095 
10096 	spec->ht.cap =
10097 	    IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
10098 	    IEEE80211_HT_CAP_GRN_FLD |
10099 	    IEEE80211_HT_CAP_SGI_20 |
10100 	    IEEE80211_HT_CAP_SGI_40;
10101 
10102 	tx_chains = rt2x00dev->default_ant.tx_chain_num;
10103 	rx_chains = rt2x00dev->default_ant.rx_chain_num;
10104 
10105 	if (tx_chains >= 2)
10106 		spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
10107 
10108 	spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
10109 
10110 	spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
10111 	spec->ht.ampdu_density = 4;
10112 	spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
10113 	if (tx_chains != rx_chains) {
10114 		spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
10115 		spec->ht.mcs.tx_params |=
10116 		    (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
10117 	}
10118 
10119 	switch (rx_chains) {
10120 	case 3:
10121 		spec->ht.mcs.rx_mask[2] = 0xff;
10122 		fallthrough;
10123 	case 2:
10124 		spec->ht.mcs.rx_mask[1] = 0xff;
10125 		fallthrough;
10126 	case 1:
10127 		spec->ht.mcs.rx_mask[0] = 0xff;
10128 		spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
10129 		break;
10130 	}
10131 
10132 	/*
10133 	 * Create channel information and survey arrays
10134 	 */
10135 	info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
10136 	if (!info)
10137 		return -ENOMEM;
10138 
10139 	rt2x00dev->chan_survey =
10140 		kcalloc(spec->num_channels, sizeof(struct rt2x00_chan_survey),
10141 			GFP_KERNEL);
10142 	if (!rt2x00dev->chan_survey) {
10143 		kfree(info);
10144 		return -ENOMEM;
10145 	}
10146 
10147 	spec->channels_info = info;
10148 
10149 	default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
10150 	default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
10151 
10152 	if (rt2x00dev->default_ant.tx_chain_num > 2)
10153 		default_power3 = rt2800_eeprom_addr(rt2x00dev,
10154 						    EEPROM_EXT_TXPOWER_BG3);
10155 	else
10156 		default_power3 = NULL;
10157 
10158 	for (i = 0; i < 14; i++) {
10159 		info[i].default_power1 = default_power1[i];
10160 		info[i].default_power2 = default_power2[i];
10161 		if (default_power3)
10162 			info[i].default_power3 = default_power3[i];
10163 	}
10164 
10165 	if (spec->num_channels > 14) {
10166 		default_power1 = rt2800_eeprom_addr(rt2x00dev,
10167 						    EEPROM_TXPOWER_A1);
10168 		default_power2 = rt2800_eeprom_addr(rt2x00dev,
10169 						    EEPROM_TXPOWER_A2);
10170 
10171 		if (rt2x00dev->default_ant.tx_chain_num > 2)
10172 			default_power3 =
10173 				rt2800_eeprom_addr(rt2x00dev,
10174 						   EEPROM_EXT_TXPOWER_A3);
10175 		else
10176 			default_power3 = NULL;
10177 
10178 		for (i = 14; i < spec->num_channels; i++) {
10179 			info[i].default_power1 = default_power1[i - 14];
10180 			info[i].default_power2 = default_power2[i - 14];
10181 			if (default_power3)
10182 				info[i].default_power3 = default_power3[i - 14];
10183 		}
10184 	}
10185 
10186 	switch (rt2x00dev->chip.rf) {
10187 	case RF2020:
10188 	case RF3020:
10189 	case RF3021:
10190 	case RF3022:
10191 	case RF3320:
10192 	case RF3052:
10193 	case RF3053:
10194 	case RF3070:
10195 	case RF3290:
10196 	case RF3853:
10197 	case RF5350:
10198 	case RF5360:
10199 	case RF5362:
10200 	case RF5370:
10201 	case RF5372:
10202 	case RF5390:
10203 	case RF5392:
10204 	case RF5592:
10205 	case RF7620:
10206 		__set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
10207 		break;
10208 	}
10209 
10210 	return 0;
10211 }
10212 
10213 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
10214 {
10215 	u32 reg;
10216 	u32 rt;
10217 	u32 rev;
10218 
10219 	if (rt2x00_rt(rt2x00dev, RT3290))
10220 		reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
10221 	else
10222 		reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
10223 
10224 	rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
10225 	rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
10226 
10227 	switch (rt) {
10228 	case RT2860:
10229 	case RT2872:
10230 	case RT2883:
10231 	case RT3070:
10232 	case RT3071:
10233 	case RT3090:
10234 	case RT3290:
10235 	case RT3352:
10236 	case RT3390:
10237 	case RT3572:
10238 	case RT3593:
10239 	case RT3883:
10240 	case RT5350:
10241 	case RT5390:
10242 	case RT5392:
10243 	case RT5592:
10244 		break;
10245 	default:
10246 		rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
10247 			   rt, rev);
10248 		return -ENODEV;
10249 	}
10250 
10251 	if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
10252 		rt = RT6352;
10253 
10254 	rt2x00_set_rt(rt2x00dev, rt, rev);
10255 
10256 	return 0;
10257 }
10258 
10259 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
10260 {
10261 	int retval;
10262 	u32 reg;
10263 
10264 	retval = rt2800_probe_rt(rt2x00dev);
10265 	if (retval)
10266 		return retval;
10267 
10268 	/*
10269 	 * Allocate eeprom data.
10270 	 */
10271 	retval = rt2800_validate_eeprom(rt2x00dev);
10272 	if (retval)
10273 		return retval;
10274 
10275 	retval = rt2800_init_eeprom(rt2x00dev);
10276 	if (retval)
10277 		return retval;
10278 
10279 	/*
10280 	 * Enable rfkill polling by setting GPIO direction of the
10281 	 * rfkill switch GPIO pin correctly.
10282 	 */
10283 	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
10284 	rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
10285 	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
10286 
10287 	/*
10288 	 * Initialize hw specifications.
10289 	 */
10290 	retval = rt2800_probe_hw_mode(rt2x00dev);
10291 	if (retval)
10292 		return retval;
10293 
10294 	/*
10295 	 * Set device capabilities.
10296 	 */
10297 	__set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
10298 	__set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
10299 	if (!rt2x00_is_usb(rt2x00dev))
10300 		__set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
10301 
10302 	/*
10303 	 * Set device requirements.
10304 	 */
10305 	if (!rt2x00_is_soc(rt2x00dev))
10306 		__set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
10307 	__set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
10308 	__set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
10309 	if (!rt2800_hwcrypt_disabled(rt2x00dev))
10310 		__set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
10311 	__set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
10312 	__set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
10313 	if (rt2x00_is_usb(rt2x00dev))
10314 		__set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
10315 	else {
10316 		__set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
10317 		__set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
10318 	}
10319 
10320 	if (modparam_watchdog) {
10321 		__set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags);
10322 		rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100);
10323 	} else {
10324 		rt2x00dev->link.watchdog_disabled = true;
10325 	}
10326 
10327 	/*
10328 	 * Set the rssi offset.
10329 	 */
10330 	rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
10331 
10332 	return 0;
10333 }
10334 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
10335 
10336 /*
10337  * IEEE80211 stack callback functions.
10338  */
10339 void rt2800_get_key_seq(struct ieee80211_hw *hw,
10340 			struct ieee80211_key_conf *key,
10341 			struct ieee80211_key_seq *seq)
10342 {
10343 	struct rt2x00_dev *rt2x00dev = hw->priv;
10344 	struct mac_iveiv_entry iveiv_entry;
10345 	u32 offset;
10346 
10347 	if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
10348 		return;
10349 
10350 	offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
10351 	rt2800_register_multiread(rt2x00dev, offset,
10352 				      &iveiv_entry, sizeof(iveiv_entry));
10353 
10354 	memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
10355 	memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
10356 }
10357 EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
10358 
10359 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
10360 {
10361 	struct rt2x00_dev *rt2x00dev = hw->priv;
10362 	u32 reg;
10363 	bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
10364 
10365 	reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
10366 	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
10367 	rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
10368 
10369 	reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
10370 	rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
10371 	rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
10372 
10373 	reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
10374 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
10375 	rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
10376 
10377 	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
10378 	rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
10379 	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
10380 
10381 	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
10382 	rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
10383 	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
10384 
10385 	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
10386 	rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
10387 	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
10388 
10389 	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
10390 	rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
10391 	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
10392 
10393 	return 0;
10394 }
10395 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
10396 
10397 int rt2800_conf_tx(struct ieee80211_hw *hw,
10398 		   struct ieee80211_vif *vif, u16 queue_idx,
10399 		   const struct ieee80211_tx_queue_params *params)
10400 {
10401 	struct rt2x00_dev *rt2x00dev = hw->priv;
10402 	struct data_queue *queue;
10403 	struct rt2x00_field32 field;
10404 	int retval;
10405 	u32 reg;
10406 	u32 offset;
10407 
10408 	/*
10409 	 * First pass the configuration through rt2x00lib, that will
10410 	 * update the queue settings and validate the input. After that
10411 	 * we are free to update the registers based on the value
10412 	 * in the queue parameter.
10413 	 */
10414 	retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
10415 	if (retval)
10416 		return retval;
10417 
10418 	/*
10419 	 * We only need to perform additional register initialization
10420 	 * for WMM queues/
10421 	 */
10422 	if (queue_idx >= 4)
10423 		return 0;
10424 
10425 	queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
10426 
10427 	/* Update WMM TXOP register */
10428 	offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
10429 	field.bit_offset = (queue_idx & 1) * 16;
10430 	field.bit_mask = 0xffff << field.bit_offset;
10431 
10432 	reg = rt2800_register_read(rt2x00dev, offset);
10433 	rt2x00_set_field32(&reg, field, queue->txop);
10434 	rt2800_register_write(rt2x00dev, offset, reg);
10435 
10436 	/* Update WMM registers */
10437 	field.bit_offset = queue_idx * 4;
10438 	field.bit_mask = 0xf << field.bit_offset;
10439 
10440 	reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
10441 	rt2x00_set_field32(&reg, field, queue->aifs);
10442 	rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
10443 
10444 	reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
10445 	rt2x00_set_field32(&reg, field, queue->cw_min);
10446 	rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
10447 
10448 	reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
10449 	rt2x00_set_field32(&reg, field, queue->cw_max);
10450 	rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
10451 
10452 	/* Update EDCA registers */
10453 	offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
10454 
10455 	reg = rt2800_register_read(rt2x00dev, offset);
10456 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
10457 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
10458 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
10459 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
10460 	rt2800_register_write(rt2x00dev, offset, reg);
10461 
10462 	return 0;
10463 }
10464 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
10465 
10466 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
10467 {
10468 	struct rt2x00_dev *rt2x00dev = hw->priv;
10469 	u64 tsf;
10470 	u32 reg;
10471 
10472 	reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
10473 	tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
10474 	reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
10475 	tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
10476 
10477 	return tsf;
10478 }
10479 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
10480 
10481 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
10482 			struct ieee80211_ampdu_params *params)
10483 {
10484 	struct ieee80211_sta *sta = params->sta;
10485 	enum ieee80211_ampdu_mlme_action action = params->action;
10486 	u16 tid = params->tid;
10487 	struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
10488 	int ret = 0;
10489 
10490 	/*
10491 	 * Don't allow aggregation for stations the hardware isn't aware
10492 	 * of because tx status reports for frames to an unknown station
10493 	 * always contain wcid=WCID_END+1 and thus we can't distinguish
10494 	 * between multiple stations which leads to unwanted situations
10495 	 * when the hw reorders frames due to aggregation.
10496 	 */
10497 	if (sta_priv->wcid > WCID_END)
10498 		return -ENOSPC;
10499 
10500 	switch (action) {
10501 	case IEEE80211_AMPDU_RX_START:
10502 	case IEEE80211_AMPDU_RX_STOP:
10503 		/*
10504 		 * The hw itself takes care of setting up BlockAck mechanisms.
10505 		 * So, we only have to allow mac80211 to nagotiate a BlockAck
10506 		 * agreement. Once that is done, the hw will BlockAck incoming
10507 		 * AMPDUs without further setup.
10508 		 */
10509 		break;
10510 	case IEEE80211_AMPDU_TX_START:
10511 		ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
10512 		break;
10513 	case IEEE80211_AMPDU_TX_STOP_CONT:
10514 	case IEEE80211_AMPDU_TX_STOP_FLUSH:
10515 	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
10516 		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
10517 		break;
10518 	case IEEE80211_AMPDU_TX_OPERATIONAL:
10519 		break;
10520 	default:
10521 		rt2x00_warn((struct rt2x00_dev *)hw->priv,
10522 			    "Unknown AMPDU action\n");
10523 	}
10524 
10525 	return ret;
10526 }
10527 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
10528 
10529 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
10530 		      struct survey_info *survey)
10531 {
10532 	struct rt2x00_dev *rt2x00dev = hw->priv;
10533 	struct rt2x00_chan_survey *chan_survey =
10534 		   &rt2x00dev->chan_survey[idx];
10535 	enum nl80211_band band = NL80211_BAND_2GHZ;
10536 
10537 	if (idx >= rt2x00dev->bands[band].n_channels) {
10538 		idx -= rt2x00dev->bands[band].n_channels;
10539 		band = NL80211_BAND_5GHZ;
10540 	}
10541 
10542 	if (idx >= rt2x00dev->bands[band].n_channels)
10543 		return -ENOENT;
10544 
10545 	if (idx == 0)
10546 		rt2800_update_survey(rt2x00dev);
10547 
10548 	survey->channel = &rt2x00dev->bands[band].channels[idx];
10549 
10550 	survey->filled = SURVEY_INFO_TIME |
10551 			 SURVEY_INFO_TIME_BUSY |
10552 			 SURVEY_INFO_TIME_EXT_BUSY;
10553 
10554 	survey->time = div_u64(chan_survey->time_idle + chan_survey->time_busy, 1000);
10555 	survey->time_busy = div_u64(chan_survey->time_busy, 1000);
10556 	survey->time_ext_busy = div_u64(chan_survey->time_ext_busy, 1000);
10557 
10558 	if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
10559 		survey->filled |= SURVEY_INFO_IN_USE;
10560 
10561 	return 0;
10562 
10563 }
10564 EXPORT_SYMBOL_GPL(rt2800_get_survey);
10565 
10566 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
10567 MODULE_VERSION(DRV_VERSION);
10568 MODULE_DESCRIPTION("Ralink RT2800 library");
10569 MODULE_LICENSE("GPL");
10570