1*1ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 233aca94dSKalle Valo /* 333aca94dSKalle Valo Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 433aca94dSKalle Valo <http://rt2x00.serialmonkey.com> 533aca94dSKalle Valo 633aca94dSKalle Valo */ 733aca94dSKalle Valo 833aca94dSKalle Valo /* 933aca94dSKalle Valo Module: rt2x00 1033aca94dSKalle Valo Abstract: rt2x00 generic register information. 1133aca94dSKalle Valo */ 1233aca94dSKalle Valo 1333aca94dSKalle Valo #ifndef RT2X00REG_H 1433aca94dSKalle Valo #define RT2X00REG_H 1533aca94dSKalle Valo 1633aca94dSKalle Valo /* 1733aca94dSKalle Valo * RX crypto status 1833aca94dSKalle Valo */ 1933aca94dSKalle Valo enum rx_crypto { 2033aca94dSKalle Valo RX_CRYPTO_SUCCESS = 0, 2133aca94dSKalle Valo RX_CRYPTO_FAIL_ICV = 1, 2233aca94dSKalle Valo RX_CRYPTO_FAIL_MIC = 2, 2333aca94dSKalle Valo RX_CRYPTO_FAIL_KEY = 3, 2433aca94dSKalle Valo }; 2533aca94dSKalle Valo 2633aca94dSKalle Valo /* 2733aca94dSKalle Valo * Antenna values 2833aca94dSKalle Valo */ 2933aca94dSKalle Valo enum antenna { 3033aca94dSKalle Valo ANTENNA_SW_DIVERSITY = 0, 3133aca94dSKalle Valo ANTENNA_A = 1, 3233aca94dSKalle Valo ANTENNA_B = 2, 3333aca94dSKalle Valo ANTENNA_HW_DIVERSITY = 3, 3433aca94dSKalle Valo }; 3533aca94dSKalle Valo 3633aca94dSKalle Valo /* 3733aca94dSKalle Valo * Led mode values. 3833aca94dSKalle Valo */ 3933aca94dSKalle Valo enum led_mode { 4033aca94dSKalle Valo LED_MODE_DEFAULT = 0, 4133aca94dSKalle Valo LED_MODE_TXRX_ACTIVITY = 1, 4233aca94dSKalle Valo LED_MODE_SIGNAL_STRENGTH = 2, 4333aca94dSKalle Valo LED_MODE_ASUS = 3, 4433aca94dSKalle Valo LED_MODE_ALPHA = 4, 4533aca94dSKalle Valo }; 4633aca94dSKalle Valo 4733aca94dSKalle Valo /* 4833aca94dSKalle Valo * TSF sync values 4933aca94dSKalle Valo */ 5033aca94dSKalle Valo enum tsf_sync { 5133aca94dSKalle Valo TSF_SYNC_NONE = 0, 5233aca94dSKalle Valo TSF_SYNC_INFRA = 1, 5333aca94dSKalle Valo TSF_SYNC_ADHOC = 2, 5433aca94dSKalle Valo TSF_SYNC_AP_NONE = 3, 5533aca94dSKalle Valo }; 5633aca94dSKalle Valo 5733aca94dSKalle Valo /* 5833aca94dSKalle Valo * Device states 5933aca94dSKalle Valo */ 6033aca94dSKalle Valo enum dev_state { 6133aca94dSKalle Valo STATE_DEEP_SLEEP = 0, 6233aca94dSKalle Valo STATE_SLEEP = 1, 6333aca94dSKalle Valo STATE_STANDBY = 2, 6433aca94dSKalle Valo STATE_AWAKE = 3, 6533aca94dSKalle Valo 6633aca94dSKalle Valo /* 6733aca94dSKalle Valo * Additional device states, these values are 6833aca94dSKalle Valo * not strict since they are not directly passed 6933aca94dSKalle Valo * into the device. 7033aca94dSKalle Valo */ 7133aca94dSKalle Valo STATE_RADIO_ON, 7233aca94dSKalle Valo STATE_RADIO_OFF, 7333aca94dSKalle Valo STATE_RADIO_IRQ_ON, 7433aca94dSKalle Valo STATE_RADIO_IRQ_OFF, 7533aca94dSKalle Valo }; 7633aca94dSKalle Valo 7733aca94dSKalle Valo /* 7833aca94dSKalle Valo * IFS backoff values 7933aca94dSKalle Valo */ 8033aca94dSKalle Valo enum ifs { 8133aca94dSKalle Valo IFS_BACKOFF = 0, 8233aca94dSKalle Valo IFS_SIFS = 1, 8333aca94dSKalle Valo IFS_NEW_BACKOFF = 2, 8433aca94dSKalle Valo IFS_NONE = 3, 8533aca94dSKalle Valo }; 8633aca94dSKalle Valo 8733aca94dSKalle Valo /* 8833aca94dSKalle Valo * IFS backoff values for HT devices 8933aca94dSKalle Valo */ 9033aca94dSKalle Valo enum txop { 9133aca94dSKalle Valo TXOP_HTTXOP = 0, 9233aca94dSKalle Valo TXOP_PIFS = 1, 9333aca94dSKalle Valo TXOP_SIFS = 2, 9433aca94dSKalle Valo TXOP_BACKOFF = 3, 9533aca94dSKalle Valo }; 9633aca94dSKalle Valo 9733aca94dSKalle Valo /* 9833aca94dSKalle Valo * Cipher types for hardware encryption 9933aca94dSKalle Valo */ 10033aca94dSKalle Valo enum cipher { 10133aca94dSKalle Valo CIPHER_NONE = 0, 10233aca94dSKalle Valo CIPHER_WEP64 = 1, 10333aca94dSKalle Valo CIPHER_WEP128 = 2, 10433aca94dSKalle Valo CIPHER_TKIP = 3, 10533aca94dSKalle Valo CIPHER_AES = 4, 10633aca94dSKalle Valo /* 10733aca94dSKalle Valo * The following fields were added by rt61pci and rt73usb. 10833aca94dSKalle Valo */ 10933aca94dSKalle Valo CIPHER_CKIP64 = 5, 11033aca94dSKalle Valo CIPHER_CKIP128 = 6, 11133aca94dSKalle Valo CIPHER_TKIP_NO_MIC = 7, /* Don't send to device */ 11233aca94dSKalle Valo 11333aca94dSKalle Valo /* 11433aca94dSKalle Valo * Max cipher type. 11533aca94dSKalle Valo * Note that CIPHER_NONE isn't counted, and CKIP64 and CKIP128 11633aca94dSKalle Valo * are excluded due to limitations in mac80211. 11733aca94dSKalle Valo */ 11833aca94dSKalle Valo CIPHER_MAX = 4, 11933aca94dSKalle Valo }; 12033aca94dSKalle Valo 12133aca94dSKalle Valo /* 12233aca94dSKalle Valo * Rate modulations 12333aca94dSKalle Valo */ 12433aca94dSKalle Valo enum rate_modulation { 12533aca94dSKalle Valo RATE_MODE_CCK = 0, 12633aca94dSKalle Valo RATE_MODE_OFDM = 1, 12733aca94dSKalle Valo RATE_MODE_HT_MIX = 2, 12833aca94dSKalle Valo RATE_MODE_HT_GREENFIELD = 3, 12933aca94dSKalle Valo }; 13033aca94dSKalle Valo 13133aca94dSKalle Valo /* 13233aca94dSKalle Valo * Firmware validation error codes 13333aca94dSKalle Valo */ 13433aca94dSKalle Valo enum firmware_errors { 13533aca94dSKalle Valo FW_OK, 13633aca94dSKalle Valo FW_BAD_CRC, 13733aca94dSKalle Valo FW_BAD_LENGTH, 13833aca94dSKalle Valo FW_BAD_VERSION, 13933aca94dSKalle Valo }; 14033aca94dSKalle Valo 14133aca94dSKalle Valo /* 14233aca94dSKalle Valo * Register handlers. 14333aca94dSKalle Valo * We store the position of a register field inside a field structure, 14433aca94dSKalle Valo * This will simplify the process of setting and reading a certain field 14533aca94dSKalle Valo * inside the register while making sure the process remains byte order safe. 14633aca94dSKalle Valo */ 14733aca94dSKalle Valo struct rt2x00_field8 { 14833aca94dSKalle Valo u8 bit_offset; 14933aca94dSKalle Valo u8 bit_mask; 15033aca94dSKalle Valo }; 15133aca94dSKalle Valo 15233aca94dSKalle Valo struct rt2x00_field16 { 15333aca94dSKalle Valo u16 bit_offset; 15433aca94dSKalle Valo u16 bit_mask; 15533aca94dSKalle Valo }; 15633aca94dSKalle Valo 15733aca94dSKalle Valo struct rt2x00_field32 { 15833aca94dSKalle Valo u32 bit_offset; 15933aca94dSKalle Valo u32 bit_mask; 16033aca94dSKalle Valo }; 16133aca94dSKalle Valo 16233aca94dSKalle Valo /* 16333aca94dSKalle Valo * Power of two check, this will check 16433aca94dSKalle Valo * if the mask that has been given contains and contiguous set of bits. 16533aca94dSKalle Valo * Note that we cannot use the is_power_of_2() function since this 16633aca94dSKalle Valo * check must be done at compile-time. 16733aca94dSKalle Valo */ 16833aca94dSKalle Valo #define is_power_of_two(x) ( !((x) & ((x)-1)) ) 16933aca94dSKalle Valo #define low_bit_mask(x) ( ((x)-1) & ~(x) ) 17033aca94dSKalle Valo #define is_valid_mask(x) is_power_of_two(1LU + (x) + low_bit_mask(x)) 17133aca94dSKalle Valo 17233aca94dSKalle Valo /* 17333aca94dSKalle Valo * Macros to find first set bit in a variable. 17433aca94dSKalle Valo * These macros behave the same as the __ffs() functions but 17533aca94dSKalle Valo * the most important difference that this is done during 17633aca94dSKalle Valo * compile-time rather then run-time. 17733aca94dSKalle Valo */ 17833aca94dSKalle Valo #define compile_ffs2(__x) \ 17933aca94dSKalle Valo __builtin_choose_expr(((__x) & 0x1), 0, 1) 18033aca94dSKalle Valo 18133aca94dSKalle Valo #define compile_ffs4(__x) \ 18233aca94dSKalle Valo __builtin_choose_expr(((__x) & 0x3), \ 18333aca94dSKalle Valo (compile_ffs2((__x))), \ 18433aca94dSKalle Valo (compile_ffs2((__x) >> 2) + 2)) 18533aca94dSKalle Valo 18633aca94dSKalle Valo #define compile_ffs8(__x) \ 18733aca94dSKalle Valo __builtin_choose_expr(((__x) & 0xf), \ 18833aca94dSKalle Valo (compile_ffs4((__x))), \ 18933aca94dSKalle Valo (compile_ffs4((__x) >> 4) + 4)) 19033aca94dSKalle Valo 19133aca94dSKalle Valo #define compile_ffs16(__x) \ 19233aca94dSKalle Valo __builtin_choose_expr(((__x) & 0xff), \ 19333aca94dSKalle Valo (compile_ffs8((__x))), \ 19433aca94dSKalle Valo (compile_ffs8((__x) >> 8) + 8)) 19533aca94dSKalle Valo 19633aca94dSKalle Valo #define compile_ffs32(__x) \ 19733aca94dSKalle Valo __builtin_choose_expr(((__x) & 0xffff), \ 19833aca94dSKalle Valo (compile_ffs16((__x))), \ 19933aca94dSKalle Valo (compile_ffs16((__x) >> 16) + 16)) 20033aca94dSKalle Valo 20133aca94dSKalle Valo /* 20233aca94dSKalle Valo * This macro will check the requirements for the FIELD{8,16,32} macros 20333aca94dSKalle Valo * The mask should be a constant non-zero contiguous set of bits which 20433aca94dSKalle Valo * does not exceed the given typelimit. 20533aca94dSKalle Valo */ 20633aca94dSKalle Valo #define FIELD_CHECK(__mask, __type) \ 20733aca94dSKalle Valo BUILD_BUG_ON(!(__mask) || \ 20833aca94dSKalle Valo !is_valid_mask(__mask) || \ 20933aca94dSKalle Valo (__mask) != (__type)(__mask)) \ 21033aca94dSKalle Valo 21133aca94dSKalle Valo #define FIELD8(__mask) \ 21233aca94dSKalle Valo ({ \ 21333aca94dSKalle Valo FIELD_CHECK(__mask, u8); \ 21433aca94dSKalle Valo (struct rt2x00_field8) { \ 21533aca94dSKalle Valo compile_ffs8(__mask), (__mask) \ 21633aca94dSKalle Valo }; \ 21733aca94dSKalle Valo }) 21833aca94dSKalle Valo 21933aca94dSKalle Valo #define FIELD16(__mask) \ 22033aca94dSKalle Valo ({ \ 22133aca94dSKalle Valo FIELD_CHECK(__mask, u16); \ 22233aca94dSKalle Valo (struct rt2x00_field16) { \ 22333aca94dSKalle Valo compile_ffs16(__mask), (__mask) \ 22433aca94dSKalle Valo }; \ 22533aca94dSKalle Valo }) 22633aca94dSKalle Valo 22733aca94dSKalle Valo #define FIELD32(__mask) \ 22833aca94dSKalle Valo ({ \ 22933aca94dSKalle Valo FIELD_CHECK(__mask, u32); \ 23033aca94dSKalle Valo (struct rt2x00_field32) { \ 23133aca94dSKalle Valo compile_ffs32(__mask), (__mask) \ 23233aca94dSKalle Valo }; \ 23333aca94dSKalle Valo }) 23433aca94dSKalle Valo 23533aca94dSKalle Valo #define SET_FIELD(__reg, __type, __field, __value)\ 23633aca94dSKalle Valo ({ \ 23733aca94dSKalle Valo typecheck(__type, __field); \ 23833aca94dSKalle Valo *(__reg) &= ~((__field).bit_mask); \ 23933aca94dSKalle Valo *(__reg) |= ((__value) << \ 24033aca94dSKalle Valo ((__field).bit_offset)) & \ 24133aca94dSKalle Valo ((__field).bit_mask); \ 24233aca94dSKalle Valo }) 24333aca94dSKalle Valo 24433aca94dSKalle Valo #define GET_FIELD(__reg, __type, __field) \ 24533aca94dSKalle Valo ({ \ 24633aca94dSKalle Valo typecheck(__type, __field); \ 24733aca94dSKalle Valo ((__reg) & ((__field).bit_mask)) >> \ 24833aca94dSKalle Valo ((__field).bit_offset); \ 24933aca94dSKalle Valo }) 25033aca94dSKalle Valo 25133aca94dSKalle Valo #define rt2x00_set_field32(__reg, __field, __value) \ 25233aca94dSKalle Valo SET_FIELD(__reg, struct rt2x00_field32, __field, __value) 25333aca94dSKalle Valo #define rt2x00_get_field32(__reg, __field) \ 25433aca94dSKalle Valo GET_FIELD(__reg, struct rt2x00_field32, __field) 25533aca94dSKalle Valo 25633aca94dSKalle Valo #define rt2x00_set_field16(__reg, __field, __value) \ 25733aca94dSKalle Valo SET_FIELD(__reg, struct rt2x00_field16, __field, __value) 25833aca94dSKalle Valo #define rt2x00_get_field16(__reg, __field) \ 25933aca94dSKalle Valo GET_FIELD(__reg, struct rt2x00_field16, __field) 26033aca94dSKalle Valo 26133aca94dSKalle Valo #define rt2x00_set_field8(__reg, __field, __value) \ 26233aca94dSKalle Valo SET_FIELD(__reg, struct rt2x00_field8, __field, __value) 26333aca94dSKalle Valo #define rt2x00_get_field8(__reg, __field) \ 26433aca94dSKalle Valo GET_FIELD(__reg, struct rt2x00_field8, __field) 26533aca94dSKalle Valo 26633aca94dSKalle Valo #endif /* RT2X00REG_H */ 267