1 2 /* Linux device driver for RTL8180 / RTL8185 / RTL8187SE 3 * 4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net> 5 * Copyright 2007,2014 Andrea Merello <andrea.merello@gmail.com> 6 * 7 * Based on the r8180 driver, which is: 8 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al. 9 * 10 * Thanks to Realtek for their support! 11 * 12 ************************************************************************ 13 * 14 * The driver was extended to the RTL8187SE in 2014 by 15 * Andrea Merello <andrea.merello@gmail.com> 16 * 17 * based also on: 18 * - portions of rtl8187se Linux staging driver, Copyright Realtek corp. 19 * (available in drivers/staging/rtl8187se directory of Linux 3.14) 20 * - other GPL, unpublished (until now), Linux driver code, 21 * Copyright Larry Finger <Larry.Finger@lwfinger.net> 22 * 23 * A huge thanks goes to Sara V. Nari who forgives me when I'm 24 * sitting in front of my laptop at evening, week-end, night... 25 * 26 * A special thanks goes to Antonio Cuni, who helped me with 27 * some python userspace stuff I used to debug RTL8187SE code, and who 28 * bought a laptop with an unsupported Wi-Fi card some years ago... 29 * 30 * Thanks to Larry Finger for writing some code for rtl8187se and for 31 * his suggestions. 32 * 33 * Thanks to Dan Carpenter for reviewing my initial patch and for his 34 * suggestions. 35 * 36 * Thanks to Bernhard Schiffner for his help in testing and for his 37 * suggestions. 38 * 39 ************************************************************************ 40 * 41 * This program is free software; you can redistribute it and/or modify 42 * it under the terms of the GNU General Public License version 2 as 43 * published by the Free Software Foundation. 44 */ 45 46 #include <linux/interrupt.h> 47 #include <linux/pci.h> 48 #include <linux/slab.h> 49 #include <linux/delay.h> 50 #include <linux/etherdevice.h> 51 #include <linux/eeprom_93cx6.h> 52 #include <linux/module.h> 53 #include <net/mac80211.h> 54 55 #include "rtl8180.h" 56 #include "rtl8225.h" 57 #include "sa2400.h" 58 #include "max2820.h" 59 #include "grf5101.h" 60 #include "rtl8225se.h" 61 62 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>"); 63 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>"); 64 MODULE_DESCRIPTION("RTL8180 / RTL8185 / RTL8187SE PCI wireless driver"); 65 MODULE_LICENSE("GPL"); 66 67 static const struct pci_device_id rtl8180_table[] = { 68 69 /* rtl8187se */ 70 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8199) }, 71 72 /* rtl8185 */ 73 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) }, 74 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) }, 75 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) }, 76 77 /* rtl8180 */ 78 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) }, 79 { PCI_DEVICE(0x1799, 0x6001) }, 80 { PCI_DEVICE(0x1799, 0x6020) }, 81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) }, 82 { PCI_DEVICE(0x1186, 0x3301) }, 83 { PCI_DEVICE(0x1432, 0x7106) }, 84 { } 85 }; 86 87 MODULE_DEVICE_TABLE(pci, rtl8180_table); 88 89 static const struct ieee80211_rate rtl818x_rates[] = { 90 { .bitrate = 10, .hw_value = 0, }, 91 { .bitrate = 20, .hw_value = 1, }, 92 { .bitrate = 55, .hw_value = 2, }, 93 { .bitrate = 110, .hw_value = 3, }, 94 { .bitrate = 60, .hw_value = 4, }, 95 { .bitrate = 90, .hw_value = 5, }, 96 { .bitrate = 120, .hw_value = 6, }, 97 { .bitrate = 180, .hw_value = 7, }, 98 { .bitrate = 240, .hw_value = 8, }, 99 { .bitrate = 360, .hw_value = 9, }, 100 { .bitrate = 480, .hw_value = 10, }, 101 { .bitrate = 540, .hw_value = 11, }, 102 }; 103 104 static const struct ieee80211_channel rtl818x_channels[] = { 105 { .center_freq = 2412 }, 106 { .center_freq = 2417 }, 107 { .center_freq = 2422 }, 108 { .center_freq = 2427 }, 109 { .center_freq = 2432 }, 110 { .center_freq = 2437 }, 111 { .center_freq = 2442 }, 112 { .center_freq = 2447 }, 113 { .center_freq = 2452 }, 114 { .center_freq = 2457 }, 115 { .center_freq = 2462 }, 116 { .center_freq = 2467 }, 117 { .center_freq = 2472 }, 118 { .center_freq = 2484 }, 119 }; 120 121 /* Queues for rtl8187se card 122 * 123 * name | reg | queue 124 * BC | 7 | 6 125 * MG | 1 | 0 126 * HI | 6 | 1 127 * VO | 5 | 2 128 * VI | 4 | 3 129 * BE | 3 | 4 130 * BK | 2 | 5 131 * 132 * The complete map for DMA kick reg using use all queue is: 133 * static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] = 134 * {1, 6, 5, 4, 3, 2, 7}; 135 * 136 * .. but.. Because for mac80211 4 queues are enough for QoS we use this 137 * 138 * name | reg | queue 139 * BC | 7 | 4 <- currently not used yet 140 * MG | 1 | x <- Not used 141 * HI | 6 | x <- Not used 142 * VO | 5 | 0 <- used 143 * VI | 4 | 1 <- used 144 * BE | 3 | 2 <- used 145 * BK | 2 | 3 <- used 146 * 147 * Beacon queue could be used, but this is not finished yet. 148 * 149 * I thougth about using the other two queues but I decided not to do this: 150 * 151 * - I'm unsure whether the mac80211 will ever try to use more than 4 queues 152 * by itself. 153 * 154 * - I could route MGMT frames (currently sent over VO queue) to the MGMT 155 * queue but since mac80211 will do not know about it, I will probably gain 156 * some HW priority whenever the VO queue is not empty, but this gain is 157 * limited by the fact that I had to stop the mac80211 queue whenever one of 158 * the VO or MGMT queues is full, stopping also submitting of MGMT frame 159 * to the driver. 160 * 161 * - I don't know how to set in the HW the contention window params for MGMT 162 * and HI-prio queues. 163 */ 164 165 static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] = {5, 4, 3, 2, 7}; 166 167 /* Queues for rtl8180/rtl8185 cards 168 * 169 * name | reg | prio 170 * BC | 7 | 3 171 * HI | 6 | 0 172 * NO | 5 | 1 173 * LO | 4 | 2 174 * 175 * The complete map for DMA kick reg using all queue is: 176 * static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {6, 5, 4, 7}; 177 * 178 * .. but .. Because the mac80211 needs at least 4 queues for QoS or 179 * otherwise QoS can't be done, we use just one. 180 * Beacon queue could be used, but this is not finished yet. 181 * Actual map is: 182 * 183 * name | reg | prio 184 * BC | 7 | 1 <- currently not used yet. 185 * HI | 6 | x <- not used 186 * NO | 5 | x <- not used 187 * LO | 4 | 0 <- used 188 */ 189 190 static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {4, 7}; 191 192 /* LNA gain table for rtl8187se */ 193 static const u8 rtl8187se_lna_gain[4] = {02, 17, 29, 39}; 194 195 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data) 196 { 197 struct rtl8180_priv *priv = dev->priv; 198 int i = 10; 199 u32 buf; 200 201 buf = (data << 8) | addr; 202 203 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80); 204 while (i--) { 205 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf); 206 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF)) 207 return; 208 } 209 } 210 211 static void rtl8180_handle_rx(struct ieee80211_hw *dev) 212 { 213 struct rtl8180_priv *priv = dev->priv; 214 struct rtl818x_rx_cmd_desc *cmd_desc; 215 unsigned int count = 32; 216 u8 agc, sq; 217 s8 signal = 1; 218 dma_addr_t mapping; 219 220 while (count--) { 221 void *entry = priv->rx_ring + priv->rx_idx * priv->rx_ring_sz; 222 struct sk_buff *skb = priv->rx_buf[priv->rx_idx]; 223 u32 flags, flags2, flags3 = 0; 224 u64 tsft; 225 226 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) { 227 struct rtl8187se_rx_desc *desc = entry; 228 229 flags = le32_to_cpu(desc->flags); 230 /* if ownership flag is set, then we can trust the 231 * HW has written other fields. We must not trust 232 * other descriptor data read before we checked (read) 233 * the ownership flag 234 */ 235 rmb(); 236 flags3 = le32_to_cpu(desc->flags3); 237 flags2 = le32_to_cpu(desc->flags2); 238 tsft = le64_to_cpu(desc->tsft); 239 } else { 240 struct rtl8180_rx_desc *desc = entry; 241 242 flags = le32_to_cpu(desc->flags); 243 /* same as above */ 244 rmb(); 245 flags2 = le32_to_cpu(desc->flags2); 246 tsft = le64_to_cpu(desc->tsft); 247 } 248 249 if (flags & RTL818X_RX_DESC_FLAG_OWN) 250 return; 251 252 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL | 253 RTL818X_RX_DESC_FLAG_FOF | 254 RTL818X_RX_DESC_FLAG_RX_ERR))) 255 goto done; 256 else { 257 struct ieee80211_rx_status rx_status = {0}; 258 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE); 259 260 if (unlikely(!new_skb)) 261 goto done; 262 263 mapping = dma_map_single(&priv->pdev->dev, 264 skb_tail_pointer(new_skb), 265 MAX_RX_SIZE, DMA_FROM_DEVICE); 266 267 if (dma_mapping_error(&priv->pdev->dev, mapping)) { 268 kfree_skb(new_skb); 269 dev_err(&priv->pdev->dev, "RX DMA map error\n"); 270 271 goto done; 272 } 273 274 dma_unmap_single(&priv->pdev->dev, 275 *((dma_addr_t *)skb->cb), 276 MAX_RX_SIZE, DMA_FROM_DEVICE); 277 skb_put(skb, flags & 0xFFF); 278 279 rx_status.antenna = (flags2 >> 15) & 1; 280 rx_status.rate_idx = (flags >> 20) & 0xF; 281 agc = (flags2 >> 17) & 0x7F; 282 283 switch (priv->chip_family) { 284 case RTL818X_CHIP_FAMILY_RTL8185: 285 if (rx_status.rate_idx > 3) 286 signal = -clamp_t(u8, agc, 25, 90) - 9; 287 else 288 signal = -clamp_t(u8, agc, 30, 95); 289 break; 290 case RTL818X_CHIP_FAMILY_RTL8180: 291 sq = flags2 & 0xff; 292 signal = priv->rf->calc_rssi(agc, sq); 293 break; 294 case RTL818X_CHIP_FAMILY_RTL8187SE: 295 /* OFDM measure reported by HW is signed, 296 * in 0.5dBm unit, with zero centered @ -41dBm 297 * input signal. 298 */ 299 if (rx_status.rate_idx > 3) { 300 signal = (s8)((flags3 >> 16) & 0xff); 301 signal = signal / 2 - 41; 302 } else { 303 int idx, bb; 304 305 idx = (agc & 0x60) >> 5; 306 bb = (agc & 0x1F) * 2; 307 /* bias + BB gain + LNA gain */ 308 signal = 4 - bb - rtl8187se_lna_gain[idx]; 309 } 310 break; 311 } 312 rx_status.signal = signal; 313 rx_status.freq = dev->conf.chandef.chan->center_freq; 314 rx_status.band = dev->conf.chandef.chan->band; 315 rx_status.mactime = tsft; 316 rx_status.flag |= RX_FLAG_MACTIME_START; 317 if (flags & RTL818X_RX_DESC_FLAG_SPLCP) 318 rx_status.enc_flags |= RX_ENC_FLAG_SHORTPRE; 319 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR) 320 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC; 321 322 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status)); 323 ieee80211_rx_irqsafe(dev, skb); 324 325 skb = new_skb; 326 priv->rx_buf[priv->rx_idx] = skb; 327 *((dma_addr_t *) skb->cb) = mapping; 328 } 329 330 done: 331 cmd_desc = entry; 332 cmd_desc->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb)); 333 cmd_desc->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN | 334 MAX_RX_SIZE); 335 if (priv->rx_idx == 31) 336 cmd_desc->flags |= 337 cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR); 338 priv->rx_idx = (priv->rx_idx + 1) % 32; 339 } 340 } 341 342 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio) 343 { 344 struct rtl8180_priv *priv = dev->priv; 345 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio]; 346 347 while (skb_queue_len(&ring->queue)) { 348 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx]; 349 struct sk_buff *skb; 350 struct ieee80211_tx_info *info; 351 u32 flags = le32_to_cpu(entry->flags); 352 353 if (flags & RTL818X_TX_DESC_FLAG_OWN) 354 return; 355 356 ring->idx = (ring->idx + 1) % ring->entries; 357 skb = __skb_dequeue(&ring->queue); 358 dma_unmap_single(&priv->pdev->dev, le32_to_cpu(entry->tx_buf), 359 skb->len, DMA_TO_DEVICE); 360 361 info = IEEE80211_SKB_CB(skb); 362 ieee80211_tx_info_clear_status(info); 363 364 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) && 365 (flags & RTL818X_TX_DESC_FLAG_TX_OK)) 366 info->flags |= IEEE80211_TX_STAT_ACK; 367 368 info->status.rates[0].count = (flags & 0xFF) + 1; 369 370 ieee80211_tx_status_irqsafe(dev, skb); 371 if (ring->entries - skb_queue_len(&ring->queue) == 2) 372 ieee80211_wake_queue(dev, prio); 373 } 374 } 375 376 static irqreturn_t rtl8187se_interrupt(int irq, void *dev_id) 377 { 378 struct ieee80211_hw *dev = dev_id; 379 struct rtl8180_priv *priv = dev->priv; 380 u32 reg; 381 unsigned long flags; 382 static int desc_err; 383 384 spin_lock_irqsave(&priv->lock, flags); 385 /* Note: 32-bit interrupt status */ 386 reg = rtl818x_ioread32(priv, &priv->map->INT_STATUS_SE); 387 if (unlikely(reg == 0xFFFFFFFF)) { 388 spin_unlock_irqrestore(&priv->lock, flags); 389 return IRQ_HANDLED; 390 } 391 392 rtl818x_iowrite32(priv, &priv->map->INT_STATUS_SE, reg); 393 394 if (reg & IMR_TIMEOUT1) 395 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0); 396 397 if (reg & (IMR_TBDOK | IMR_TBDER)) 398 rtl8180_handle_tx(dev, 4); 399 400 if (reg & (IMR_TVODOK | IMR_TVODER)) 401 rtl8180_handle_tx(dev, 0); 402 403 if (reg & (IMR_TVIDOK | IMR_TVIDER)) 404 rtl8180_handle_tx(dev, 1); 405 406 if (reg & (IMR_TBEDOK | IMR_TBEDER)) 407 rtl8180_handle_tx(dev, 2); 408 409 if (reg & (IMR_TBKDOK | IMR_TBKDER)) 410 rtl8180_handle_tx(dev, 3); 411 412 if (reg & (IMR_ROK | IMR_RER | RTL818X_INT_SE_RX_DU | IMR_RQOSOK)) 413 rtl8180_handle_rx(dev); 414 /* The interface sometimes generates several RX DMA descriptor errors 415 * at startup. Do not report these. 416 */ 417 if ((reg & RTL818X_INT_SE_RX_DU) && desc_err++ > 2) 418 if (net_ratelimit()) 419 wiphy_err(dev->wiphy, "No RX DMA Descriptor avail\n"); 420 421 spin_unlock_irqrestore(&priv->lock, flags); 422 return IRQ_HANDLED; 423 } 424 425 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id) 426 { 427 struct ieee80211_hw *dev = dev_id; 428 struct rtl8180_priv *priv = dev->priv; 429 u16 reg; 430 431 spin_lock(&priv->lock); 432 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS); 433 if (unlikely(reg == 0xFFFF)) { 434 spin_unlock(&priv->lock); 435 return IRQ_HANDLED; 436 } 437 438 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg); 439 440 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR)) 441 rtl8180_handle_tx(dev, 1); 442 443 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR)) 444 rtl8180_handle_tx(dev, 0); 445 446 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR)) 447 rtl8180_handle_rx(dev); 448 449 spin_unlock(&priv->lock); 450 451 return IRQ_HANDLED; 452 } 453 454 static void rtl8180_tx(struct ieee80211_hw *dev, 455 struct ieee80211_tx_control *control, 456 struct sk_buff *skb) 457 { 458 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 459 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 460 struct rtl8180_priv *priv = dev->priv; 461 struct rtl8180_tx_ring *ring; 462 struct rtl8180_tx_desc *entry; 463 unsigned int prio = 0; 464 unsigned long flags; 465 unsigned int idx, hw_prio; 466 467 dma_addr_t mapping; 468 u32 tx_flags; 469 u8 rc_flags; 470 u16 plcp_len = 0; 471 __le16 rts_duration = 0; 472 /* do arithmetic and then convert to le16 */ 473 u16 frame_duration = 0; 474 475 /* rtl8180/rtl8185 only has one useable tx queue */ 476 if (dev->queues > IEEE80211_AC_BK) 477 prio = skb_get_queue_mapping(skb); 478 ring = &priv->tx_ring[prio]; 479 480 mapping = dma_map_single(&priv->pdev->dev, skb->data, skb->len, 481 DMA_TO_DEVICE); 482 483 if (dma_mapping_error(&priv->pdev->dev, mapping)) { 484 kfree_skb(skb); 485 dev_err(&priv->pdev->dev, "TX DMA mapping error\n"); 486 return; 487 } 488 489 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS | 490 RTL818X_TX_DESC_FLAG_LS | 491 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) | 492 skb->len; 493 494 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) 495 tx_flags |= RTL818X_TX_DESC_FLAG_DMA | 496 RTL818X_TX_DESC_FLAG_NO_ENC; 497 498 rc_flags = info->control.rates[0].flags; 499 500 /* HW will perform RTS-CTS when only RTS flags is set. 501 * HW will perform CTS-to-self when both RTS and CTS flags are set. 502 * RTS rate and RTS duration will be used also for CTS-to-self. 503 */ 504 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 505 tx_flags |= RTL818X_TX_DESC_FLAG_RTS; 506 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19; 507 rts_duration = ieee80211_rts_duration(dev, priv->vif, 508 skb->len, info); 509 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 510 tx_flags |= RTL818X_TX_DESC_FLAG_RTS | RTL818X_TX_DESC_FLAG_CTS; 511 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19; 512 rts_duration = ieee80211_ctstoself_duration(dev, priv->vif, 513 skb->len, info); 514 } 515 516 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) { 517 unsigned int remainder; 518 519 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4), 520 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10); 521 remainder = (16 * (skb->len + 4)) % 522 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10); 523 if (remainder <= 6) 524 plcp_len |= 1 << 15; 525 } 526 527 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) { 528 __le16 duration; 529 /* SIFS time (required by HW) is already included by 530 * ieee80211_generic_frame_duration 531 */ 532 duration = ieee80211_generic_frame_duration(dev, priv->vif, 533 NL80211_BAND_2GHZ, skb->len, 534 ieee80211_get_tx_rate(dev, info)); 535 536 frame_duration = priv->ack_time + le16_to_cpu(duration); 537 } 538 539 spin_lock_irqsave(&priv->lock, flags); 540 541 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 542 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 543 priv->seqno += 0x10; 544 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 545 hdr->seq_ctrl |= cpu_to_le16(priv->seqno); 546 } 547 548 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries; 549 entry = &ring->desc[idx]; 550 551 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) { 552 entry->frame_duration = cpu_to_le16(frame_duration); 553 entry->frame_len_se = cpu_to_le16(skb->len); 554 555 /* tpc polarity */ 556 entry->flags3 = cpu_to_le16(1<<4); 557 } else 558 entry->frame_len = cpu_to_le32(skb->len); 559 560 entry->rts_duration = rts_duration; 561 entry->plcp_len = cpu_to_le16(plcp_len); 562 entry->tx_buf = cpu_to_le32(mapping); 563 564 entry->retry_limit = info->control.rates[0].count - 1; 565 566 /* We must be sure that tx_flags is written last because the HW 567 * looks at it to check if the rest of data is valid or not 568 */ 569 wmb(); 570 entry->flags = cpu_to_le32(tx_flags); 571 /* We must be sure this has been written before followings HW 572 * register write, because this write will made the HW attempts 573 * to DMA the just-written data 574 */ 575 wmb(); 576 577 __skb_queue_tail(&ring->queue, skb); 578 if (ring->entries - skb_queue_len(&ring->queue) < 2) 579 ieee80211_stop_queue(dev, prio); 580 581 spin_unlock_irqrestore(&priv->lock, flags); 582 583 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) { 584 /* just poll: rings are stopped with TPPollStop reg */ 585 hw_prio = rtl8187se_queues_map[prio]; 586 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, 587 (1 << hw_prio)); 588 } else { 589 hw_prio = rtl8180_queues_map[prio]; 590 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, 591 (1 << hw_prio) | /* ring to poll */ 592 (1<<1) | (1<<2));/* stopped rings */ 593 } 594 } 595 596 static void rtl8180_set_anaparam3(struct rtl8180_priv *priv, u16 anaparam3) 597 { 598 u8 reg; 599 600 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, 601 RTL818X_EEPROM_CMD_CONFIG); 602 603 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); 604 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 605 reg | RTL818X_CONFIG3_ANAPARAM_WRITE); 606 607 rtl818x_iowrite16(priv, &priv->map->ANAPARAM3, anaparam3); 608 609 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 610 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); 611 612 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, 613 RTL818X_EEPROM_CMD_NORMAL); 614 } 615 616 void rtl8180_set_anaparam2(struct rtl8180_priv *priv, u32 anaparam2) 617 { 618 u8 reg; 619 620 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, 621 RTL818X_EEPROM_CMD_CONFIG); 622 623 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); 624 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 625 reg | RTL818X_CONFIG3_ANAPARAM_WRITE); 626 627 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, anaparam2); 628 629 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 630 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); 631 632 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, 633 RTL818X_EEPROM_CMD_NORMAL); 634 } 635 636 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam) 637 { 638 u8 reg; 639 640 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); 641 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); 642 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 643 reg | RTL818X_CONFIG3_ANAPARAM_WRITE); 644 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam); 645 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 646 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); 647 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); 648 } 649 650 static void rtl8187se_mac_config(struct ieee80211_hw *dev) 651 { 652 struct rtl8180_priv *priv = dev->priv; 653 u8 reg; 654 655 rtl818x_iowrite32(priv, REG_ADDR4(0x1F0), 0); 656 rtl818x_ioread32(priv, REG_ADDR4(0x1F0)); 657 rtl818x_iowrite32(priv, REG_ADDR4(0x1F4), 0); 658 rtl818x_ioread32(priv, REG_ADDR4(0x1F4)); 659 rtl818x_iowrite8(priv, REG_ADDR1(0x1F8), 0); 660 rtl818x_ioread8(priv, REG_ADDR1(0x1F8)); 661 /* Enable DA10 TX power saving */ 662 reg = rtl818x_ioread8(priv, &priv->map->PHY_PR); 663 rtl818x_iowrite8(priv, &priv->map->PHY_PR, reg | 0x04); 664 /* Power */ 665 rtl818x_iowrite16(priv, PI_DATA_REG, 0x1000); 666 rtl818x_iowrite16(priv, SI_DATA_REG, 0x1000); 667 /* AFE - default to power ON */ 668 rtl818x_iowrite16(priv, REG_ADDR2(0x370), 0x0560); 669 rtl818x_iowrite16(priv, REG_ADDR2(0x372), 0x0560); 670 rtl818x_iowrite16(priv, REG_ADDR2(0x374), 0x0DA4); 671 rtl818x_iowrite16(priv, REG_ADDR2(0x376), 0x0DA4); 672 rtl818x_iowrite16(priv, REG_ADDR2(0x378), 0x0560); 673 rtl818x_iowrite16(priv, REG_ADDR2(0x37A), 0x0560); 674 rtl818x_iowrite16(priv, REG_ADDR2(0x37C), 0x00EC); 675 rtl818x_iowrite16(priv, REG_ADDR2(0x37E), 0x00EC); 676 rtl818x_iowrite8(priv, REG_ADDR1(0x24E), 0x01); 677 /* unknown, needed for suspend to RAM resume */ 678 rtl818x_iowrite8(priv, REG_ADDR1(0x0A), 0x72); 679 } 680 681 static void rtl8187se_set_antenna_config(struct ieee80211_hw *dev, u8 def_ant, 682 bool diversity) 683 { 684 struct rtl8180_priv *priv = dev->priv; 685 686 rtl8225_write_phy_cck(dev, 0x0C, 0x09); 687 if (diversity) { 688 if (def_ant == 1) { 689 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x00); 690 rtl8225_write_phy_cck(dev, 0x11, 0xBB); 691 rtl8225_write_phy_cck(dev, 0x01, 0xC7); 692 rtl8225_write_phy_ofdm(dev, 0x0D, 0x54); 693 rtl8225_write_phy_ofdm(dev, 0x18, 0xB2); 694 } else { /* main antenna */ 695 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03); 696 rtl8225_write_phy_cck(dev, 0x11, 0x9B); 697 rtl8225_write_phy_cck(dev, 0x01, 0xC7); 698 rtl8225_write_phy_ofdm(dev, 0x0D, 0x5C); 699 rtl8225_write_phy_ofdm(dev, 0x18, 0xB2); 700 } 701 } else { /* disable antenna diversity */ 702 if (def_ant == 1) { 703 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x00); 704 rtl8225_write_phy_cck(dev, 0x11, 0xBB); 705 rtl8225_write_phy_cck(dev, 0x01, 0x47); 706 rtl8225_write_phy_ofdm(dev, 0x0D, 0x54); 707 rtl8225_write_phy_ofdm(dev, 0x18, 0x32); 708 } else { /* main antenna */ 709 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03); 710 rtl8225_write_phy_cck(dev, 0x11, 0x9B); 711 rtl8225_write_phy_cck(dev, 0x01, 0x47); 712 rtl8225_write_phy_ofdm(dev, 0x0D, 0x5C); 713 rtl8225_write_phy_ofdm(dev, 0x18, 0x32); 714 } 715 } 716 /* priv->curr_ant = def_ant; */ 717 } 718 719 static void rtl8180_int_enable(struct ieee80211_hw *dev) 720 { 721 struct rtl8180_priv *priv = dev->priv; 722 723 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) { 724 rtl818x_iowrite32(priv, &priv->map->IMR, 725 IMR_TBDER | IMR_TBDOK | 726 IMR_TVODER | IMR_TVODOK | 727 IMR_TVIDER | IMR_TVIDOK | 728 IMR_TBEDER | IMR_TBEDOK | 729 IMR_TBKDER | IMR_TBKDOK | 730 IMR_RDU | IMR_RER | 731 IMR_ROK | IMR_RQOSOK); 732 } else { 733 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF); 734 } 735 } 736 737 static void rtl8180_int_disable(struct ieee80211_hw *dev) 738 { 739 struct rtl8180_priv *priv = dev->priv; 740 741 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) { 742 rtl818x_iowrite32(priv, &priv->map->IMR, 0); 743 } else { 744 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); 745 } 746 } 747 748 static void rtl8180_conf_basic_rates(struct ieee80211_hw *dev, 749 u32 basic_mask) 750 { 751 struct rtl8180_priv *priv = dev->priv; 752 u16 reg; 753 u32 resp_mask; 754 u8 basic_max; 755 u8 resp_max, resp_min; 756 757 resp_mask = basic_mask; 758 /* IEEE80211 says the response rate should be equal to the highest basic 759 * rate that is not faster than received frame. But it says also that if 760 * the basic rate set does not contains any rate for the current 761 * modulation class then mandatory rate set must be used for that 762 * modulation class. Eventually add OFDM mandatory rates.. 763 */ 764 if ((resp_mask & 0xf) == resp_mask) 765 resp_mask |= 0x150; /* 6, 12, 24Mbps */ 766 767 switch (priv->chip_family) { 768 769 case RTL818X_CHIP_FAMILY_RTL8180: 770 /* in 8180 this is NOT a BITMAP */ 771 basic_max = fls(basic_mask) - 1; 772 reg = rtl818x_ioread16(priv, &priv->map->BRSR); 773 reg &= ~3; 774 reg |= basic_max; 775 rtl818x_iowrite16(priv, &priv->map->BRSR, reg); 776 break; 777 778 case RTL818X_CHIP_FAMILY_RTL8185: 779 resp_max = fls(resp_mask) - 1; 780 resp_min = ffs(resp_mask) - 1; 781 /* in 8185 this is a BITMAP */ 782 rtl818x_iowrite16(priv, &priv->map->BRSR, basic_mask); 783 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (resp_max << 4) | 784 resp_min); 785 break; 786 787 case RTL818X_CHIP_FAMILY_RTL8187SE: 788 /* in 8187se this is a BITMAP. BRSR reg actually sets 789 * response rates. 790 */ 791 rtl818x_iowrite16(priv, &priv->map->BRSR_8187SE, resp_mask); 792 break; 793 } 794 } 795 796 static void rtl8180_config_cardbus(struct ieee80211_hw *dev) 797 { 798 struct rtl8180_priv *priv = dev->priv; 799 u16 reg16; 800 u8 reg8; 801 802 reg8 = rtl818x_ioread8(priv, &priv->map->CONFIG3); 803 reg8 |= 1 << 1; 804 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg8); 805 806 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) { 807 rtl818x_iowrite16(priv, FEMR_SE, 0xffff); 808 } else { 809 reg16 = rtl818x_ioread16(priv, &priv->map->FEMR); 810 reg16 |= (1 << 15) | (1 << 14) | (1 << 4); 811 rtl818x_iowrite16(priv, &priv->map->FEMR, reg16); 812 } 813 814 } 815 816 static int rtl8180_init_hw(struct ieee80211_hw *dev) 817 { 818 struct rtl8180_priv *priv = dev->priv; 819 u16 reg; 820 u32 reg32; 821 822 rtl818x_iowrite8(priv, &priv->map->CMD, 0); 823 rtl818x_ioread8(priv, &priv->map->CMD); 824 msleep(10); 825 826 /* reset */ 827 rtl8180_int_disable(dev); 828 rtl818x_ioread8(priv, &priv->map->CMD); 829 830 reg = rtl818x_ioread8(priv, &priv->map->CMD); 831 reg &= (1 << 1); 832 reg |= RTL818X_CMD_RESET; 833 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET); 834 rtl818x_ioread8(priv, &priv->map->CMD); 835 msleep(200); 836 837 /* check success of reset */ 838 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) { 839 wiphy_err(dev->wiphy, "reset timeout!\n"); 840 return -ETIMEDOUT; 841 } 842 843 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD); 844 rtl818x_ioread8(priv, &priv->map->CMD); 845 msleep(200); 846 847 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) { 848 rtl8180_config_cardbus(dev); 849 } 850 851 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) 852 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_ENEDCA); 853 else 854 rtl818x_iowrite8(priv, &priv->map->MSR, 0); 855 856 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) 857 rtl8180_set_anaparam(priv, priv->anaparam); 858 859 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma); 860 /* mac80211 queue have higher prio for lower index. The last queue 861 * (that mac80211 is not aware of) is reserved for beacons (and have 862 * the highest priority on the NIC) 863 */ 864 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8187SE) { 865 rtl818x_iowrite32(priv, &priv->map->TBDA, 866 priv->tx_ring[1].dma); 867 rtl818x_iowrite32(priv, &priv->map->TLPDA, 868 priv->tx_ring[0].dma); 869 } else { 870 rtl818x_iowrite32(priv, &priv->map->TBDA, 871 priv->tx_ring[4].dma); 872 rtl818x_iowrite32(priv, &priv->map->TVODA, 873 priv->tx_ring[0].dma); 874 rtl818x_iowrite32(priv, &priv->map->TVIDA, 875 priv->tx_ring[1].dma); 876 rtl818x_iowrite32(priv, &priv->map->TBEDA, 877 priv->tx_ring[2].dma); 878 rtl818x_iowrite32(priv, &priv->map->TBKDA, 879 priv->tx_ring[3].dma); 880 } 881 882 /* TODO: necessary? specs indicate not */ 883 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); 884 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2); 885 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3)); 886 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) { 887 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2); 888 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4)); 889 } 890 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); 891 892 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */ 893 894 /* TODO: turn off hw wep on rtl8180 */ 895 896 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0); 897 898 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) { 899 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0); 900 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0); 901 } else { 902 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0); 903 904 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6); 905 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C); 906 } 907 908 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) { 909 /* TODO: set ClkRun enable? necessary? */ 910 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE); 911 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6)); 912 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); 913 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); 914 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2)); 915 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); 916 /* fix eccessive IFS after CTS-to-self */ 917 if (priv->map_pio) { 918 u8 reg; 919 920 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT); 921 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1); 922 rtl818x_iowrite8(priv, REG_ADDR1(0xff), 0x35); 923 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg); 924 } else 925 rtl818x_iowrite8(priv, REG_ADDR1(0x1ff), 0x35); 926 } 927 928 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) { 929 930 /* the set auto rate fallback bitmask from 1M to 54 Mb/s */ 931 rtl818x_iowrite16(priv, ARFR, 0xFFF); 932 rtl818x_ioread16(priv, ARFR); 933 934 /* stop unused queus (no dma alloc) */ 935 rtl818x_iowrite8(priv, &priv->map->TPPOLL_STOP, 936 RTL818x_TPPOLL_STOP_MG | RTL818x_TPPOLL_STOP_HI); 937 938 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0x00); 939 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50); 940 941 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0); 942 943 /* some black magic here.. */ 944 rtl8187se_mac_config(dev); 945 946 rtl818x_iowrite16(priv, RFSW_CTRL, 0x569A); 947 rtl818x_ioread16(priv, RFSW_CTRL); 948 949 rtl8180_set_anaparam(priv, RTL8225SE_ANAPARAM_ON); 950 rtl8180_set_anaparam2(priv, RTL8225SE_ANAPARAM2_ON); 951 rtl8180_set_anaparam3(priv, RTL8225SE_ANAPARAM3); 952 953 954 rtl818x_iowrite8(priv, &priv->map->CONFIG5, 955 rtl818x_ioread8(priv, &priv->map->CONFIG5) & 0x7F); 956 957 /*probably this switch led on */ 958 rtl818x_iowrite8(priv, &priv->map->PGSELECT, 959 rtl818x_ioread8(priv, &priv->map->PGSELECT) | 0x08); 960 961 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480); 962 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1BFF); 963 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488); 964 965 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x4003); 966 967 /* the reference code mac hardcode table write 968 * this reg by doing byte-wide accesses. 969 * It does it just for lowest and highest byte.. 970 */ 971 reg32 = rtl818x_ioread32(priv, &priv->map->RF_PARA); 972 reg32 &= 0x00ffff00; 973 reg32 |= 0xb8000054; 974 rtl818x_iowrite32(priv, &priv->map->RF_PARA, reg32); 975 } else 976 /* stop unused queus (no dma alloc) */ 977 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, 978 (1<<1) | (1<<2)); 979 980 priv->rf->init(dev); 981 982 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps 983 * otherwise. bitmask 0x3 and 0x01f3 respectively. 984 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do 985 * this after rf init. 986 * TODO: try to find out whether RF code really needs to do this.. 987 */ 988 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) 989 rtl8180_conf_basic_rates(dev, 0x3); 990 else 991 rtl8180_conf_basic_rates(dev, 0x1f3); 992 993 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) 994 rtl8187se_set_antenna_config(dev, 995 priv->antenna_diversity_default, 996 priv->antenna_diversity_en); 997 return 0; 998 } 999 1000 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev) 1001 { 1002 struct rtl8180_priv *priv = dev->priv; 1003 struct rtl818x_rx_cmd_desc *entry; 1004 int i; 1005 1006 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) 1007 priv->rx_ring_sz = sizeof(struct rtl8187se_rx_desc); 1008 else 1009 priv->rx_ring_sz = sizeof(struct rtl8180_rx_desc); 1010 1011 priv->rx_ring = dma_alloc_coherent(&priv->pdev->dev, 1012 priv->rx_ring_sz * 32, 1013 &priv->rx_ring_dma, GFP_KERNEL); 1014 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) { 1015 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n"); 1016 return -ENOMEM; 1017 } 1018 1019 priv->rx_idx = 0; 1020 1021 for (i = 0; i < 32; i++) { 1022 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE); 1023 dma_addr_t *mapping; 1024 entry = priv->rx_ring + priv->rx_ring_sz*i; 1025 if (!skb) { 1026 dma_free_coherent(&priv->pdev->dev, 1027 priv->rx_ring_sz * 32, 1028 priv->rx_ring, priv->rx_ring_dma); 1029 wiphy_err(dev->wiphy, "Cannot allocate RX skb\n"); 1030 return -ENOMEM; 1031 } 1032 priv->rx_buf[i] = skb; 1033 mapping = (dma_addr_t *)skb->cb; 1034 *mapping = dma_map_single(&priv->pdev->dev, 1035 skb_tail_pointer(skb), MAX_RX_SIZE, 1036 DMA_FROM_DEVICE); 1037 1038 if (dma_mapping_error(&priv->pdev->dev, *mapping)) { 1039 kfree_skb(skb); 1040 dma_free_coherent(&priv->pdev->dev, 1041 priv->rx_ring_sz * 32, 1042 priv->rx_ring, priv->rx_ring_dma); 1043 wiphy_err(dev->wiphy, "Cannot map DMA for RX skb\n"); 1044 return -ENOMEM; 1045 } 1046 1047 entry->rx_buf = cpu_to_le32(*mapping); 1048 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN | 1049 MAX_RX_SIZE); 1050 } 1051 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR); 1052 return 0; 1053 } 1054 1055 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev) 1056 { 1057 struct rtl8180_priv *priv = dev->priv; 1058 int i; 1059 1060 for (i = 0; i < 32; i++) { 1061 struct sk_buff *skb = priv->rx_buf[i]; 1062 if (!skb) 1063 continue; 1064 1065 dma_unmap_single(&priv->pdev->dev, *((dma_addr_t *)skb->cb), 1066 MAX_RX_SIZE, DMA_FROM_DEVICE); 1067 kfree_skb(skb); 1068 } 1069 1070 dma_free_coherent(&priv->pdev->dev, priv->rx_ring_sz * 32, 1071 priv->rx_ring, priv->rx_ring_dma); 1072 priv->rx_ring = NULL; 1073 } 1074 1075 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev, 1076 unsigned int prio, unsigned int entries) 1077 { 1078 struct rtl8180_priv *priv = dev->priv; 1079 struct rtl8180_tx_desc *ring; 1080 dma_addr_t dma; 1081 int i; 1082 1083 ring = dma_alloc_coherent(&priv->pdev->dev, sizeof(*ring) * entries, 1084 &dma, GFP_KERNEL); 1085 if (!ring || (unsigned long)ring & 0xFF) { 1086 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n", 1087 prio); 1088 return -ENOMEM; 1089 } 1090 1091 priv->tx_ring[prio].desc = ring; 1092 priv->tx_ring[prio].dma = dma; 1093 priv->tx_ring[prio].idx = 0; 1094 priv->tx_ring[prio].entries = entries; 1095 skb_queue_head_init(&priv->tx_ring[prio].queue); 1096 1097 for (i = 0; i < entries; i++) 1098 ring[i].next_tx_desc = 1099 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring)); 1100 1101 return 0; 1102 } 1103 1104 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio) 1105 { 1106 struct rtl8180_priv *priv = dev->priv; 1107 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio]; 1108 1109 while (skb_queue_len(&ring->queue)) { 1110 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx]; 1111 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1112 1113 dma_unmap_single(&priv->pdev->dev, le32_to_cpu(entry->tx_buf), 1114 skb->len, DMA_TO_DEVICE); 1115 kfree_skb(skb); 1116 ring->idx = (ring->idx + 1) % ring->entries; 1117 } 1118 1119 dma_free_coherent(&priv->pdev->dev, 1120 sizeof(*ring->desc) * ring->entries, ring->desc, 1121 ring->dma); 1122 ring->desc = NULL; 1123 } 1124 1125 static int rtl8180_start(struct ieee80211_hw *dev) 1126 { 1127 struct rtl8180_priv *priv = dev->priv; 1128 int ret, i; 1129 u32 reg; 1130 1131 ret = rtl8180_init_rx_ring(dev); 1132 if (ret) 1133 return ret; 1134 1135 for (i = 0; i < (dev->queues + 1); i++) 1136 if ((ret = rtl8180_init_tx_ring(dev, i, 16))) 1137 goto err_free_rings; 1138 1139 ret = rtl8180_init_hw(dev); 1140 if (ret) 1141 goto err_free_rings; 1142 1143 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) { 1144 ret = request_irq(priv->pdev->irq, rtl8187se_interrupt, 1145 IRQF_SHARED, KBUILD_MODNAME, dev); 1146 } else { 1147 ret = request_irq(priv->pdev->irq, rtl8180_interrupt, 1148 IRQF_SHARED, KBUILD_MODNAME, dev); 1149 } 1150 1151 if (ret) { 1152 wiphy_err(dev->wiphy, "failed to register IRQ handler\n"); 1153 goto err_free_rings; 1154 } 1155 1156 rtl8180_int_enable(dev); 1157 1158 /* in rtl8187se at MAR regs offset there is the management 1159 * TX descriptor DMA addres.. 1160 */ 1161 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8187SE) { 1162 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0); 1163 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0); 1164 } 1165 1166 reg = RTL818X_RX_CONF_ONLYERLPKT | 1167 RTL818X_RX_CONF_RX_AUTORESETPHY | 1168 RTL818X_RX_CONF_MGMT | 1169 RTL818X_RX_CONF_DATA | 1170 (7 << 8 /* MAX RX DMA */) | 1171 RTL818X_RX_CONF_BROADCAST | 1172 RTL818X_RX_CONF_NICMAC; 1173 1174 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) 1175 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2; 1176 else if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) { 1177 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1) 1178 ? RTL818X_RX_CONF_CSDM1 : 0; 1179 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2) 1180 ? RTL818X_RX_CONF_CSDM2 : 0; 1181 } else { 1182 reg &= ~(RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2); 1183 } 1184 1185 priv->rx_conf = reg; 1186 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg); 1187 1188 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) { 1189 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF); 1190 1191 /* CW is not on per-packet basis. 1192 * in rtl8185 the CW_VALUE reg is used. 1193 * in rtl8187se the AC param regs are used. 1194 */ 1195 reg &= ~RTL818X_CW_CONF_PERPACKET_CW; 1196 /* retry limit IS on per-packet basis. 1197 * the short and long retry limit in TX_CONF 1198 * reg are ignored 1199 */ 1200 reg |= RTL818X_CW_CONF_PERPACKET_RETRY; 1201 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg); 1202 1203 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL); 1204 /* TX antenna and TX gain are not on per-packet basis. 1205 * TX Antenna is selected by ANTSEL reg (RX in BB regs). 1206 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs 1207 */ 1208 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN; 1209 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL; 1210 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT; 1211 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg); 1212 1213 /* disable early TX */ 1214 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f); 1215 } 1216 1217 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); 1218 reg |= (6 << 21 /* MAX TX DMA */) | 1219 RTL818X_TX_CONF_NO_ICV; 1220 1221 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) 1222 reg |= 1<<30; /* "duration procedure mode" */ 1223 1224 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) 1225 reg &= ~RTL818X_TX_CONF_PROBE_DTS; 1226 else 1227 reg &= ~RTL818X_TX_CONF_HW_SEQNUM; 1228 1229 reg &= ~RTL818X_TX_CONF_DISCW; 1230 1231 /* different meaning, same value on both rtl8185 and rtl8180 */ 1232 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP; 1233 1234 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg); 1235 1236 reg = rtl818x_ioread8(priv, &priv->map->CMD); 1237 reg |= RTL818X_CMD_RX_ENABLE; 1238 reg |= RTL818X_CMD_TX_ENABLE; 1239 rtl818x_iowrite8(priv, &priv->map->CMD, reg); 1240 1241 return 0; 1242 1243 err_free_rings: 1244 rtl8180_free_rx_ring(dev); 1245 for (i = 0; i < (dev->queues + 1); i++) 1246 if (priv->tx_ring[i].desc) 1247 rtl8180_free_tx_ring(dev, i); 1248 1249 return ret; 1250 } 1251 1252 static void rtl8180_stop(struct ieee80211_hw *dev) 1253 { 1254 struct rtl8180_priv *priv = dev->priv; 1255 u8 reg; 1256 int i; 1257 1258 rtl8180_int_disable(dev); 1259 1260 reg = rtl818x_ioread8(priv, &priv->map->CMD); 1261 reg &= ~RTL818X_CMD_TX_ENABLE; 1262 reg &= ~RTL818X_CMD_RX_ENABLE; 1263 rtl818x_iowrite8(priv, &priv->map->CMD, reg); 1264 1265 priv->rf->stop(dev); 1266 1267 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); 1268 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4); 1269 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF); 1270 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); 1271 1272 free_irq(priv->pdev->irq, dev); 1273 1274 rtl8180_free_rx_ring(dev); 1275 for (i = 0; i < (dev->queues + 1); i++) 1276 rtl8180_free_tx_ring(dev, i); 1277 } 1278 1279 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev, 1280 struct ieee80211_vif *vif) 1281 { 1282 struct rtl8180_priv *priv = dev->priv; 1283 1284 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) | 1285 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32; 1286 } 1287 1288 static void rtl8180_beacon_work(struct work_struct *work) 1289 { 1290 struct rtl8180_vif *vif_priv = 1291 container_of(work, struct rtl8180_vif, beacon_work.work); 1292 struct ieee80211_vif *vif = 1293 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv); 1294 struct ieee80211_hw *dev = vif_priv->dev; 1295 struct ieee80211_mgmt *mgmt; 1296 struct sk_buff *skb; 1297 1298 /* don't overflow the tx ring */ 1299 if (ieee80211_queue_stopped(dev, 0)) 1300 goto resched; 1301 1302 /* grab a fresh beacon */ 1303 skb = ieee80211_beacon_get(dev, vif, 0); 1304 if (!skb) 1305 goto resched; 1306 1307 /* 1308 * update beacon timestamp w/ TSF value 1309 * TODO: make hardware update beacon timestamp 1310 */ 1311 mgmt = (struct ieee80211_mgmt *)skb->data; 1312 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif)); 1313 1314 /* TODO: use actual beacon queue */ 1315 skb_set_queue_mapping(skb, 0); 1316 1317 rtl8180_tx(dev, NULL, skb); 1318 1319 resched: 1320 /* 1321 * schedule next beacon 1322 * TODO: use hardware support for beacon timing 1323 */ 1324 schedule_delayed_work(&vif_priv->beacon_work, 1325 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int)); 1326 } 1327 1328 static int rtl8180_add_interface(struct ieee80211_hw *dev, 1329 struct ieee80211_vif *vif) 1330 { 1331 struct rtl8180_priv *priv = dev->priv; 1332 struct rtl8180_vif *vif_priv; 1333 1334 /* 1335 * We only support one active interface at a time. 1336 */ 1337 if (priv->vif) 1338 return -EBUSY; 1339 1340 switch (vif->type) { 1341 case NL80211_IFTYPE_STATION: 1342 case NL80211_IFTYPE_ADHOC: 1343 break; 1344 default: 1345 return -EOPNOTSUPP; 1346 } 1347 1348 priv->vif = vif; 1349 1350 /* Initialize driver private area */ 1351 vif_priv = (struct rtl8180_vif *)&vif->drv_priv; 1352 vif_priv->dev = dev; 1353 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work); 1354 vif_priv->enable_beacon = false; 1355 1356 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); 1357 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0], 1358 le32_to_cpu(*(__le32 *)vif->addr)); 1359 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4], 1360 le16_to_cpu(*(__le16 *)(vif->addr + 4))); 1361 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); 1362 1363 return 0; 1364 } 1365 1366 static void rtl8180_remove_interface(struct ieee80211_hw *dev, 1367 struct ieee80211_vif *vif) 1368 { 1369 struct rtl8180_priv *priv = dev->priv; 1370 priv->vif = NULL; 1371 } 1372 1373 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed) 1374 { 1375 struct rtl8180_priv *priv = dev->priv; 1376 struct ieee80211_conf *conf = &dev->conf; 1377 1378 priv->rf->set_chan(dev, conf); 1379 1380 return 0; 1381 } 1382 1383 static void rtl8187se_conf_ac_parm(struct ieee80211_hw *dev, u8 queue) 1384 { 1385 const struct ieee80211_tx_queue_params *params; 1386 struct rtl8180_priv *priv = dev->priv; 1387 1388 /* hw value */ 1389 u32 ac_param; 1390 1391 u8 aifs; 1392 u8 txop; 1393 u8 cw_min, cw_max; 1394 1395 params = &priv->queue_param[queue]; 1396 1397 cw_min = fls(params->cw_min); 1398 cw_max = fls(params->cw_max); 1399 1400 aifs = 10 + params->aifs * priv->slot_time; 1401 1402 /* TODO: check if txop HW is in us (mult by 32) */ 1403 txop = params->txop; 1404 1405 ac_param = txop << AC_PARAM_TXOP_LIMIT_SHIFT | 1406 cw_max << AC_PARAM_ECW_MAX_SHIFT | 1407 cw_min << AC_PARAM_ECW_MIN_SHIFT | 1408 aifs << AC_PARAM_AIFS_SHIFT; 1409 1410 switch (queue) { 1411 case IEEE80211_AC_BK: 1412 rtl818x_iowrite32(priv, &priv->map->AC_BK_PARAM, ac_param); 1413 break; 1414 case IEEE80211_AC_BE: 1415 rtl818x_iowrite32(priv, &priv->map->AC_BE_PARAM, ac_param); 1416 break; 1417 case IEEE80211_AC_VI: 1418 rtl818x_iowrite32(priv, &priv->map->AC_VI_PARAM, ac_param); 1419 break; 1420 case IEEE80211_AC_VO: 1421 rtl818x_iowrite32(priv, &priv->map->AC_VO_PARAM, ac_param); 1422 break; 1423 } 1424 } 1425 1426 static int rtl8180_conf_tx(struct ieee80211_hw *dev, 1427 struct ieee80211_vif *vif, 1428 unsigned int link_id, u16 queue, 1429 const struct ieee80211_tx_queue_params *params) 1430 { 1431 struct rtl8180_priv *priv = dev->priv; 1432 u8 cw_min, cw_max; 1433 1434 /* nothing to do ? */ 1435 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) 1436 return 0; 1437 1438 cw_min = fls(params->cw_min); 1439 cw_max = fls(params->cw_max); 1440 1441 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) { 1442 priv->queue_param[queue] = *params; 1443 rtl8187se_conf_ac_parm(dev, queue); 1444 } else 1445 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 1446 (cw_max << 4) | cw_min); 1447 return 0; 1448 } 1449 1450 static void rtl8180_conf_erp(struct ieee80211_hw *dev, 1451 struct ieee80211_bss_conf *info) 1452 { 1453 struct rtl8180_priv *priv = dev->priv; 1454 u8 sifs, difs; 1455 int eifs; 1456 u8 hw_eifs; 1457 1458 /* TODO: should we do something ? */ 1459 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) 1460 return; 1461 1462 /* I _hope_ this means 10uS for the HW. 1463 * In reference code it is 0x22 for 1464 * both rtl8187L and rtl8187SE 1465 */ 1466 sifs = 0x22; 1467 1468 if (info->use_short_slot) 1469 priv->slot_time = 9; 1470 else 1471 priv->slot_time = 20; 1472 1473 /* 10 is SIFS time in uS */ 1474 difs = 10 + 2 * priv->slot_time; 1475 eifs = 10 + difs + priv->ack_time; 1476 1477 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/ 1478 hw_eifs = DIV_ROUND_UP(eifs, 4); 1479 1480 1481 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time); 1482 rtl818x_iowrite8(priv, &priv->map->SIFS, sifs); 1483 rtl818x_iowrite8(priv, &priv->map->DIFS, difs); 1484 1485 /* from reference code. set ack timeout reg = eifs reg */ 1486 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, hw_eifs); 1487 1488 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) 1489 rtl818x_iowrite8(priv, &priv->map->EIFS_8187SE, hw_eifs); 1490 else if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) { 1491 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed, 1492 * the HW still wait for DIFS. 1493 * HW uses 4uS units for EIFS. 1494 */ 1495 hw_eifs = DIV_ROUND_UP(eifs - difs, 4); 1496 1497 rtl818x_iowrite8(priv, &priv->map->EIFS, hw_eifs); 1498 } 1499 } 1500 1501 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev, 1502 struct ieee80211_vif *vif, 1503 struct ieee80211_bss_conf *info, 1504 u64 changed) 1505 { 1506 struct rtl8180_priv *priv = dev->priv; 1507 struct rtl8180_vif *vif_priv; 1508 int i; 1509 u8 reg; 1510 1511 vif_priv = (struct rtl8180_vif *)&vif->drv_priv; 1512 1513 if (changed & BSS_CHANGED_BSSID) { 1514 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->BSSID[0], 1515 le16_to_cpu(*(__le16 *)info->bssid)); 1516 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->BSSID[2], 1517 le32_to_cpu(*(__le32 *)(info->bssid + 2))); 1518 1519 if (is_valid_ether_addr(info->bssid)) { 1520 if (vif->type == NL80211_IFTYPE_ADHOC) 1521 reg = RTL818X_MSR_ADHOC; 1522 else 1523 reg = RTL818X_MSR_INFRA; 1524 } else 1525 reg = RTL818X_MSR_NO_LINK; 1526 1527 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) 1528 reg |= RTL818X_MSR_ENEDCA; 1529 1530 rtl818x_iowrite8(priv, &priv->map->MSR, reg); 1531 } 1532 1533 if (changed & BSS_CHANGED_BASIC_RATES) 1534 rtl8180_conf_basic_rates(dev, info->basic_rates); 1535 1536 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE)) { 1537 1538 /* when preamble changes, acktime duration changes, and erp must 1539 * be recalculated. ACK time is calculated at lowest rate. 1540 * Since mac80211 include SIFS time we remove it (-10) 1541 */ 1542 priv->ack_time = 1543 le16_to_cpu(ieee80211_generic_frame_duration(dev, 1544 priv->vif, 1545 NL80211_BAND_2GHZ, 10, 1546 &priv->rates[0])) - 10; 1547 1548 rtl8180_conf_erp(dev, info); 1549 1550 /* mac80211 supplies aifs_n to driver and calls 1551 * conf_tx callback whether aifs_n changes, NOT 1552 * when aifs changes. 1553 * Aifs should be recalculated if slot changes. 1554 */ 1555 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) { 1556 for (i = 0; i < 4; i++) 1557 rtl8187se_conf_ac_parm(dev, i); 1558 } 1559 } 1560 1561 if (changed & BSS_CHANGED_BEACON_ENABLED) 1562 vif_priv->enable_beacon = info->enable_beacon; 1563 1564 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) { 1565 cancel_delayed_work_sync(&vif_priv->beacon_work); 1566 if (vif_priv->enable_beacon) 1567 schedule_work(&vif_priv->beacon_work.work); 1568 } 1569 } 1570 1571 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev, 1572 struct netdev_hw_addr_list *mc_list) 1573 { 1574 return netdev_hw_addr_list_count(mc_list); 1575 } 1576 1577 static void rtl8180_configure_filter(struct ieee80211_hw *dev, 1578 unsigned int changed_flags, 1579 unsigned int *total_flags, 1580 u64 multicast) 1581 { 1582 struct rtl8180_priv *priv = dev->priv; 1583 1584 if (changed_flags & FIF_FCSFAIL) 1585 priv->rx_conf ^= RTL818X_RX_CONF_FCS; 1586 if (changed_flags & FIF_CONTROL) 1587 priv->rx_conf ^= RTL818X_RX_CONF_CTRL; 1588 if (changed_flags & FIF_OTHER_BSS) 1589 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR; 1590 if (*total_flags & FIF_ALLMULTI || multicast > 0) 1591 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST; 1592 else 1593 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST; 1594 1595 *total_flags = 0; 1596 1597 if (priv->rx_conf & RTL818X_RX_CONF_FCS) 1598 *total_flags |= FIF_FCSFAIL; 1599 if (priv->rx_conf & RTL818X_RX_CONF_CTRL) 1600 *total_flags |= FIF_CONTROL; 1601 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR) 1602 *total_flags |= FIF_OTHER_BSS; 1603 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST) 1604 *total_flags |= FIF_ALLMULTI; 1605 1606 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf); 1607 } 1608 1609 static const struct ieee80211_ops rtl8180_ops = { 1610 .tx = rtl8180_tx, 1611 .wake_tx_queue = ieee80211_handle_wake_tx_queue, 1612 .start = rtl8180_start, 1613 .stop = rtl8180_stop, 1614 .add_interface = rtl8180_add_interface, 1615 .remove_interface = rtl8180_remove_interface, 1616 .config = rtl8180_config, 1617 .bss_info_changed = rtl8180_bss_info_changed, 1618 .conf_tx = rtl8180_conf_tx, 1619 .prepare_multicast = rtl8180_prepare_multicast, 1620 .configure_filter = rtl8180_configure_filter, 1621 .get_tsf = rtl8180_get_tsf, 1622 }; 1623 1624 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom) 1625 { 1626 struct rtl8180_priv *priv = eeprom->data; 1627 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); 1628 1629 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE; 1630 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ; 1631 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK; 1632 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS; 1633 } 1634 1635 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom) 1636 { 1637 struct rtl8180_priv *priv = eeprom->data; 1638 u8 reg = 2 << 6; 1639 1640 if (eeprom->reg_data_in) 1641 reg |= RTL818X_EEPROM_CMD_WRITE; 1642 if (eeprom->reg_data_out) 1643 reg |= RTL818X_EEPROM_CMD_READ; 1644 if (eeprom->reg_data_clock) 1645 reg |= RTL818X_EEPROM_CMD_CK; 1646 if (eeprom->reg_chip_select) 1647 reg |= RTL818X_EEPROM_CMD_CS; 1648 1649 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg); 1650 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); 1651 udelay(10); 1652 } 1653 1654 static void rtl8180_eeprom_read(struct rtl8180_priv *priv) 1655 { 1656 struct eeprom_93cx6 eeprom; 1657 int eeprom_cck_table_adr; 1658 u16 eeprom_val; 1659 int i; 1660 1661 eeprom.data = priv; 1662 eeprom.register_read = rtl8180_eeprom_register_read; 1663 eeprom.register_write = rtl8180_eeprom_register_write; 1664 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6)) 1665 eeprom.width = PCI_EEPROM_WIDTH_93C66; 1666 else 1667 eeprom.width = PCI_EEPROM_WIDTH_93C46; 1668 1669 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, 1670 RTL818X_EEPROM_CMD_PROGRAM); 1671 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); 1672 udelay(10); 1673 1674 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val); 1675 eeprom_val &= 0xFF; 1676 priv->rf_type = eeprom_val; 1677 1678 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val); 1679 priv->csthreshold = eeprom_val >> 8; 1680 1681 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)priv->mac_addr, 3); 1682 1683 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) 1684 eeprom_cck_table_adr = 0x30; 1685 else 1686 eeprom_cck_table_adr = 0x10; 1687 1688 /* CCK TX power */ 1689 for (i = 0; i < 14; i += 2) { 1690 u16 txpwr; 1691 eeprom_93cx6_read(&eeprom, eeprom_cck_table_adr + (i >> 1), 1692 &txpwr); 1693 priv->channels[i].hw_value = txpwr & 0xFF; 1694 priv->channels[i + 1].hw_value = txpwr >> 8; 1695 } 1696 1697 /* OFDM TX power */ 1698 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) { 1699 for (i = 0; i < 14; i += 2) { 1700 u16 txpwr; 1701 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr); 1702 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8; 1703 priv->channels[i + 1].hw_value |= txpwr & 0xFF00; 1704 } 1705 } 1706 1707 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) { 1708 __le32 anaparam; 1709 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2); 1710 priv->anaparam = le32_to_cpu(anaparam); 1711 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam); 1712 } 1713 1714 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) { 1715 eeprom_93cx6_read(&eeprom, 0x3F, &eeprom_val); 1716 priv->antenna_diversity_en = !!(eeprom_val & 0x100); 1717 priv->antenna_diversity_default = (eeprom_val & 0xC00) == 0x400; 1718 1719 eeprom_93cx6_read(&eeprom, 0x7C, &eeprom_val); 1720 priv->xtal_out = eeprom_val & 0xF; 1721 priv->xtal_in = (eeprom_val & 0xF0) >> 4; 1722 priv->xtal_cal = !!(eeprom_val & 0x1000); 1723 priv->thermal_meter_val = (eeprom_val & 0xF00) >> 8; 1724 priv->thermal_meter_en = !!(eeprom_val & 0x2000); 1725 } 1726 1727 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, 1728 RTL818X_EEPROM_CMD_NORMAL); 1729 } 1730 1731 static int rtl8180_probe(struct pci_dev *pdev, 1732 const struct pci_device_id *id) 1733 { 1734 struct ieee80211_hw *dev; 1735 struct rtl8180_priv *priv; 1736 unsigned long mem_len; 1737 unsigned int io_len; 1738 int err; 1739 const char *chip_name, *rf_name = NULL; 1740 u32 reg; 1741 1742 err = pci_enable_device(pdev); 1743 if (err) { 1744 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n", 1745 pci_name(pdev)); 1746 return err; 1747 } 1748 1749 err = pci_request_regions(pdev, KBUILD_MODNAME); 1750 if (err) { 1751 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n", 1752 pci_name(pdev)); 1753 goto err_disable_dev; 1754 } 1755 1756 io_len = pci_resource_len(pdev, 0); 1757 mem_len = pci_resource_len(pdev, 1); 1758 1759 if (mem_len < sizeof(struct rtl818x_csr) || 1760 io_len < sizeof(struct rtl818x_csr)) { 1761 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n", 1762 pci_name(pdev)); 1763 err = -ENOMEM; 1764 goto err_free_reg; 1765 } 1766 1767 if ((err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) || 1768 (err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)))) { 1769 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n", 1770 pci_name(pdev)); 1771 goto err_free_reg; 1772 } 1773 1774 pci_set_master(pdev); 1775 1776 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops); 1777 if (!dev) { 1778 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n", 1779 pci_name(pdev)); 1780 err = -ENOMEM; 1781 goto err_free_reg; 1782 } 1783 1784 priv = dev->priv; 1785 priv->pdev = pdev; 1786 1787 dev->max_rates = 1; 1788 SET_IEEE80211_DEV(dev, &pdev->dev); 1789 pci_set_drvdata(pdev, dev); 1790 1791 priv->map_pio = false; 1792 priv->map = pci_iomap(pdev, 1, mem_len); 1793 if (!priv->map) { 1794 priv->map = pci_iomap(pdev, 0, io_len); 1795 priv->map_pio = true; 1796 } 1797 1798 if (!priv->map) { 1799 dev_err(&pdev->dev, "Cannot map device memory/PIO\n"); 1800 err = -ENOMEM; 1801 goto err_free_dev; 1802 } 1803 1804 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels)); 1805 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates)); 1806 1807 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels)); 1808 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates)); 1809 1810 priv->band.band = NL80211_BAND_2GHZ; 1811 priv->band.channels = priv->channels; 1812 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels); 1813 priv->band.bitrates = priv->rates; 1814 priv->band.n_bitrates = 4; 1815 dev->wiphy->bands[NL80211_BAND_2GHZ] = &priv->band; 1816 1817 ieee80211_hw_set(dev, HOST_BROADCAST_PS_BUFFERING); 1818 ieee80211_hw_set(dev, RX_INCLUDES_FCS); 1819 1820 dev->vif_data_size = sizeof(struct rtl8180_vif); 1821 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 1822 BIT(NL80211_IFTYPE_ADHOC); 1823 dev->max_signal = 65; 1824 1825 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); 1826 reg &= RTL818X_TX_CONF_HWVER_MASK; 1827 switch (reg) { 1828 case RTL818X_TX_CONF_R8180_ABCD: 1829 chip_name = "RTL8180"; 1830 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180; 1831 break; 1832 1833 case RTL818X_TX_CONF_R8180_F: 1834 chip_name = "RTL8180vF"; 1835 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180; 1836 break; 1837 1838 case RTL818X_TX_CONF_R8185_ABC: 1839 chip_name = "RTL8185"; 1840 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185; 1841 break; 1842 1843 case RTL818X_TX_CONF_R8185_D: 1844 chip_name = "RTL8185vD"; 1845 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185; 1846 break; 1847 1848 case RTL818X_TX_CONF_RTL8187SE: 1849 chip_name = "RTL8187SE"; 1850 if (priv->map_pio) { 1851 dev_err(&pdev->dev, 1852 "MMIO failed. PIO not supported on RTL8187SE\n"); 1853 err = -ENOMEM; 1854 goto err_iounmap; 1855 } 1856 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8187SE; 1857 break; 1858 1859 default: 1860 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n", 1861 pci_name(pdev), reg >> 25); 1862 err = -ENODEV; 1863 goto err_iounmap; 1864 } 1865 1866 /* we declare to MAC80211 all the queues except for beacon queue 1867 * that will be eventually handled by DRV. 1868 * TX rings are arranged in such a way that lower is the IDX, 1869 * higher is the priority, in order to achieve direct mapping 1870 * with mac80211, however the beacon queue is an exception and it 1871 * is mapped on the highst tx ring IDX. 1872 */ 1873 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) 1874 dev->queues = RTL8187SE_NR_TX_QUEUES - 1; 1875 else 1876 dev->queues = RTL8180_NR_TX_QUEUES - 1; 1877 1878 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) { 1879 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates); 1880 pci_try_set_mwi(pdev); 1881 } 1882 1883 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) 1884 ieee80211_hw_set(dev, SIGNAL_DBM); 1885 else 1886 ieee80211_hw_set(dev, SIGNAL_UNSPEC); 1887 1888 wiphy_ext_feature_set(dev->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 1889 1890 rtl8180_eeprom_read(priv); 1891 1892 switch (priv->rf_type) { 1893 case 1: rf_name = "Intersil"; 1894 break; 1895 case 2: rf_name = "RFMD"; 1896 break; 1897 case 3: priv->rf = &sa2400_rf_ops; 1898 break; 1899 case 4: priv->rf = &max2820_rf_ops; 1900 break; 1901 case 5: priv->rf = &grf5101_rf_ops; 1902 break; 1903 case 9: 1904 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) 1905 priv->rf = rtl8187se_detect_rf(dev); 1906 else 1907 priv->rf = rtl8180_detect_rf(dev); 1908 break; 1909 case 10: 1910 rf_name = "RTL8255"; 1911 break; 1912 default: 1913 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n", 1914 pci_name(pdev), priv->rf_type); 1915 err = -ENODEV; 1916 goto err_iounmap; 1917 } 1918 1919 if (!priv->rf) { 1920 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n", 1921 pci_name(pdev), rf_name); 1922 err = -ENODEV; 1923 goto err_iounmap; 1924 } 1925 1926 if (!is_valid_ether_addr(priv->mac_addr)) { 1927 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using" 1928 " randomly generated MAC addr\n", pci_name(pdev)); 1929 eth_random_addr(priv->mac_addr); 1930 } 1931 SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr); 1932 1933 spin_lock_init(&priv->lock); 1934 1935 err = ieee80211_register_hw(dev); 1936 if (err) { 1937 printk(KERN_ERR "%s (rtl8180): Cannot register device\n", 1938 pci_name(pdev)); 1939 goto err_iounmap; 1940 } 1941 1942 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n", 1943 priv->mac_addr, chip_name, priv->rf->name); 1944 1945 return 0; 1946 1947 err_iounmap: 1948 pci_iounmap(pdev, priv->map); 1949 1950 err_free_dev: 1951 ieee80211_free_hw(dev); 1952 1953 err_free_reg: 1954 pci_release_regions(pdev); 1955 1956 err_disable_dev: 1957 pci_disable_device(pdev); 1958 return err; 1959 } 1960 1961 static void rtl8180_remove(struct pci_dev *pdev) 1962 { 1963 struct ieee80211_hw *dev = pci_get_drvdata(pdev); 1964 struct rtl8180_priv *priv; 1965 1966 if (!dev) 1967 return; 1968 1969 ieee80211_unregister_hw(dev); 1970 1971 priv = dev->priv; 1972 1973 pci_iounmap(pdev, priv->map); 1974 pci_release_regions(pdev); 1975 pci_disable_device(pdev); 1976 ieee80211_free_hw(dev); 1977 } 1978 1979 #define rtl8180_suspend NULL 1980 #define rtl8180_resume NULL 1981 1982 static SIMPLE_DEV_PM_OPS(rtl8180_pm_ops, rtl8180_suspend, rtl8180_resume); 1983 1984 static struct pci_driver rtl8180_driver = { 1985 .name = KBUILD_MODNAME, 1986 .id_table = rtl8180_table, 1987 .probe = rtl8180_probe, 1988 .remove = rtl8180_remove, 1989 .driver.pm = &rtl8180_pm_ops, 1990 }; 1991 1992 module_pci_driver(rtl8180_driver); 1993