1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
4  *
5  * Register definitions taken from original Realtek rtl8723au driver
6  */
7 
8 #include <asm/byteorder.h>
9 
10 #define RTL8XXXU_DEBUG_REG_WRITE	0x01
11 #define RTL8XXXU_DEBUG_REG_READ		0x02
12 #define RTL8XXXU_DEBUG_RFREG_WRITE	0x04
13 #define RTL8XXXU_DEBUG_RFREG_READ	0x08
14 #define RTL8XXXU_DEBUG_CHANNEL		0x10
15 #define RTL8XXXU_DEBUG_TX		0x20
16 #define RTL8XXXU_DEBUG_TX_DUMP		0x40
17 #define RTL8XXXU_DEBUG_RX		0x80
18 #define RTL8XXXU_DEBUG_RX_DUMP		0x100
19 #define RTL8XXXU_DEBUG_USB		0x200
20 #define RTL8XXXU_DEBUG_KEY		0x400
21 #define RTL8XXXU_DEBUG_H2C		0x800
22 #define RTL8XXXU_DEBUG_ACTION		0x1000
23 #define RTL8XXXU_DEBUG_EFUSE		0x2000
24 #define RTL8XXXU_DEBUG_INTERRUPT	0x4000
25 
26 #define RTW_USB_CONTROL_MSG_TIMEOUT	500
27 #define RTL8XXXU_MAX_REG_POLL		500
28 #define	USB_INTR_CONTENT_LENGTH		56
29 
30 #define RTL8XXXU_OUT_ENDPOINTS		4
31 
32 #define REALTEK_USB_READ		0xc0
33 #define REALTEK_USB_WRITE		0x40
34 #define REALTEK_USB_CMD_REQ		0x05
35 #define REALTEK_USB_CMD_IDX		0x00
36 
37 #define TX_TOTAL_PAGE_NUM		0xf8
38 #define TX_TOTAL_PAGE_NUM_8188F		0xf7
39 #define TX_TOTAL_PAGE_NUM_8192E		0xf3
40 #define TX_TOTAL_PAGE_NUM_8723B		0xf7
41 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */
42 #define TX_PAGE_NUM_PUBQ		0xe7
43 #define TX_PAGE_NUM_HI_PQ		0x0c
44 #define TX_PAGE_NUM_LO_PQ		0x02
45 #define TX_PAGE_NUM_NORM_PQ		0x02
46 
47 #define TX_PAGE_NUM_PUBQ_8188F		0xe5
48 #define TX_PAGE_NUM_HI_PQ_8188F		0x0c
49 #define TX_PAGE_NUM_LO_PQ_8188F		0x02
50 #define TX_PAGE_NUM_NORM_PQ_8188F	0x02
51 
52 #define TX_PAGE_NUM_PUBQ_8192E		0xe7
53 #define TX_PAGE_NUM_HI_PQ_8192E		0x08
54 #define TX_PAGE_NUM_LO_PQ_8192E		0x0c
55 #define TX_PAGE_NUM_NORM_PQ_8192E	0x00
56 
57 #define TX_PAGE_NUM_PUBQ_8723B		0xe7
58 #define TX_PAGE_NUM_HI_PQ_8723B		0x0c
59 #define TX_PAGE_NUM_LO_PQ_8723B		0x02
60 #define TX_PAGE_NUM_NORM_PQ_8723B	0x02
61 
62 #define RTL_FW_PAGE_SIZE		4096
63 #define RTL8XXXU_FIRMWARE_POLL_MAX	1000
64 
65 #define RTL8723A_CHANNEL_GROUPS		3
66 #define RTL8723A_MAX_RF_PATHS		2
67 #define RTL8723B_CHANNEL_GROUPS		6
68 #define RTL8723B_TX_COUNT		4
69 #define RTL8723B_MAX_RF_PATHS		4
70 #define RTL8XXXU_MAX_CHANNEL_GROUPS	6
71 #define RF6052_MAX_TX_PWR		0x3f
72 
73 #define EFUSE_MAP_LEN			512
74 #define EFUSE_MAX_SECTION_8723A		64
75 #define EFUSE_REAL_CONTENT_LEN_8723A	512
76 #define EFUSE_BT_MAP_LEN_8723A		1024
77 #define EFUSE_MAX_WORD_UNIT		4
78 
79 enum rtl8xxxu_rtl_chip {
80 	RTL8192S = 0x81920,
81 	RTL8191S = 0x81910,
82 	RTL8192C = 0x8192c,
83 	RTL8191C = 0x8191c,
84 	RTL8188C = 0x8188c,
85 	RTL8188R = 0x81889,
86 	RTL8192D = 0x8192d,
87 	RTL8723A = 0x8723a,
88 	RTL8188E = 0x8188e,
89 	RTL8812  = 0x88120,
90 	RTL8821  = 0x88210,
91 	RTL8192E = 0x8192e,
92 	RTL8191E = 0x8191e,
93 	RTL8723B = 0x8723b,
94 	RTL8814A = 0x8814a,
95 	RTL8881A = 0x8881a,
96 	RTL8821B = 0x8821b,
97 	RTL8822B = 0x8822b,
98 	RTL8703B = 0x8703b,
99 	RTL8195A = 0x8195a,
100 	RTL8188F = 0x8188f
101 };
102 
103 enum rtl8xxxu_rx_type {
104 	RX_TYPE_DATA_PKT = 0,
105 	RX_TYPE_C2H = 1,
106 	RX_TYPE_ERROR = -1
107 };
108 
109 struct rtl8xxxu_rxdesc16 {
110 #ifdef __LITTLE_ENDIAN
111 	u32 pktlen:14;
112 	u32 crc32:1;
113 	u32 icverr:1;
114 	u32 drvinfo_sz:4;
115 	u32 security:3;
116 	u32 qos:1;
117 	u32 shift:2;
118 	u32 phy_stats:1;
119 	u32 swdec:1;
120 	u32 ls:1;
121 	u32 fs:1;
122 	u32 eor:1;
123 	u32 own:1;
124 
125 	u32 macid:5;
126 	u32 tid:4;
127 	u32 hwrsvd:4;
128 	u32 amsdu:1;
129 	u32 paggr:1;
130 	u32 faggr:1;
131 	u32 a1fit:4;
132 	u32 a2fit:4;
133 	u32 pam:1;
134 	u32 pwr:1;
135 	u32 md:1;
136 	u32 mf:1;
137 	u32 type:2;
138 	u32 mc:1;
139 	u32 bc:1;
140 
141 	u32 seq:12;
142 	u32 frag:4;
143 	u32 pkt_cnt:8;
144 	u32 reserved:6;
145 	u32 nextind:1;
146 	u32 reserved0:1;
147 
148 	u32 rxmcs:6;
149 	u32 rxht:1;
150 	u32 gf:1;
151 	u32 splcp:1;
152 	u32 bw:1;
153 	u32 htc:1;
154 	u32 eosp:1;
155 	u32 bssidfit:2;
156 	u32 reserved1:16;
157 	u32 unicastwake:1;
158 	u32 magicwake:1;
159 
160 	u32 pattern0match:1;
161 	u32 pattern1match:1;
162 	u32 pattern2match:1;
163 	u32 pattern3match:1;
164 	u32 pattern4match:1;
165 	u32 pattern5match:1;
166 	u32 pattern6match:1;
167 	u32 pattern7match:1;
168 	u32 pattern8match:1;
169 	u32 pattern9match:1;
170 	u32 patternamatch:1;
171 	u32 patternbmatch:1;
172 	u32 patterncmatch:1;
173 	u32 reserved2:19;
174 #else
175 	u32 own:1;
176 	u32 eor:1;
177 	u32 fs:1;
178 	u32 ls:1;
179 	u32 swdec:1;
180 	u32 phy_stats:1;
181 	u32 shift:2;
182 	u32 qos:1;
183 	u32 security:3;
184 	u32 drvinfo_sz:4;
185 	u32 icverr:1;
186 	u32 crc32:1;
187 	u32 pktlen:14;
188 
189 	u32 bc:1;
190 	u32 mc:1;
191 	u32 type:2;
192 	u32 mf:1;
193 	u32 md:1;
194 	u32 pwr:1;
195 	u32 pam:1;
196 	u32 a2fit:4;
197 	u32 a1fit:4;
198 	u32 faggr:1;
199 	u32 paggr:1;
200 	u32 amsdu:1;
201 	u32 hwrsvd:4;
202 	u32 tid:4;
203 	u32 macid:5;
204 
205 	u32 reserved0:1;
206 	u32 nextind:1;
207 	u32 reserved:6;
208 	u32 pkt_cnt:8;
209 	u32 frag:4;
210 	u32 seq:12;
211 
212 	u32 magicwake:1;
213 	u32 unicastwake:1;
214 	u32 reserved1:16;
215 	u32 bssidfit:2;
216 	u32 eosp:1;
217 	u32 htc:1;
218 	u32 bw:1;
219 	u32 splcp:1;
220 	u32 gf:1;
221 	u32 rxht:1;
222 	u32 rxmcs:6;
223 
224 	u32 reserved2:19;
225 	u32 patterncmatch:1;
226 	u32 patternbmatch:1;
227 	u32 patternamatch:1;
228 	u32 pattern9match:1;
229 	u32 pattern8match:1;
230 	u32 pattern7match:1;
231 	u32 pattern6match:1;
232 	u32 pattern5match:1;
233 	u32 pattern4match:1;
234 	u32 pattern3match:1;
235 	u32 pattern2match:1;
236 	u32 pattern1match:1;
237 	u32 pattern0match:1;
238 #endif
239 	u32 tsfl;
240 #if 0
241 	u32 bassn:12;
242 	u32 bavld:1;
243 	u32 reserved3:19;
244 #endif
245 };
246 
247 struct rtl8xxxu_rxdesc24 {
248 #ifdef __LITTLE_ENDIAN
249 	u32 pktlen:14;
250 	u32 crc32:1;
251 	u32 icverr:1;
252 	u32 drvinfo_sz:4;
253 	u32 security:3;
254 	u32 qos:1;
255 	u32 shift:2;
256 	u32 phy_stats:1;
257 	u32 swdec:1;
258 	u32 ls:1;
259 	u32 fs:1;
260 	u32 eor:1;
261 	u32 own:1;
262 
263 	u32 macid:7;
264 	u32 dummy1_0:1;
265 	u32 tid:4;
266 	u32 dummy1_1:1;
267 	u32 amsdu:1;
268 	u32 rxid_match:1;
269 	u32 paggr:1;
270 	u32 a1fit:4;	/* 16 */
271 	u32 chkerr:1;
272 	u32 ipver:1;
273 	u32 tcpudp:1;
274 	u32 chkvld:1;
275 	u32 pam:1;
276 	u32 pwr:1;
277 	u32 more_data:1;
278 	u32 more_frag:1;
279 	u32 type:2;
280 	u32 mc:1;
281 	u32 bc:1;
282 
283 	u32 seq:12;
284 	u32 frag:4;
285 	u32 rx_is_qos:1;	/* 16 */
286 	u32 dummy2_0:1;
287 	u32 wlanhd_iv_len:6;
288 	u32 dummy2_1:4;
289 	u32 rpt_sel:1;
290 	u32 dummy2_2:3;
291 
292 	u32 rxmcs:7;
293 	u32 dummy3_0:3;
294 	u32 htc:1;
295 	u32 eosp:1;
296 	u32 bssidfit:2;
297 	u32 dummy3_1:2;
298 	u32 usb_agg_pktnum:8;	/* 16 */
299 	u32 dummy3_2:5;
300 	u32 pattern_match:1;
301 	u32 unicast_match:1;
302 	u32 magic_match:1;
303 
304 	u32 splcp:1;
305 	u32 ldcp:1;
306 	u32 stbc:1;
307 	u32 dummy4_0:1;
308 	u32 bw:2;
309 	u32 dummy4_1:26;
310 #else
311 	u32 own:1;
312 	u32 eor:1;
313 	u32 fs:1;
314 	u32 ls:1;
315 	u32 swdec:1;
316 	u32 phy_stats:1;
317 	u32 shift:2;
318 	u32 qos:1;
319 	u32 security:3;
320 	u32 drvinfo_sz:4;
321 	u32 icverr:1;
322 	u32 crc32:1;
323 	u32 pktlen:14;
324 
325 	u32 bc:1;
326 	u32 mc:1;
327 	u32 type:2;
328 	u32 mf:1;
329 	u32 md:1;
330 	u32 pwr:1;
331 	u32 pam:1;
332 	u32 a2fit:4;
333 	u32 a1fit:4;
334 	u32 faggr:1;
335 	u32 paggr:1;
336 	u32 amsdu:1;
337 	u32 hwrsvd:4;
338 	u32 tid:4;
339 	u32 macid:5;
340 
341 	u32 dummy2_2:3;
342 	u32 rpt_sel:1;
343 	u32 dummy2_1:4;
344 	u32 wlanhd_iv_len:6;
345 	u32 dummy2_0:1;
346 	u32 rx_is_qos:1;
347 	u32 frag:4;		/* 16 */
348 	u32 seq:12;
349 
350 	u32 magic_match:1;
351 	u32 unicast_match:1;
352 	u32 pattern_match:1;
353 	u32 dummy3_2:5;
354 	u32 usb_agg_pktnum:8;
355 	u32 dummy3_1:2;		/* 16 */
356 	u32 bssidfit:2;
357 	u32 eosp:1;
358 	u32 htc:1;
359 	u32 dummy3_0:3;
360 	u32 rxmcs:7;
361 
362 	u32 dumm4_1:26;
363 	u32 bw:2;
364 	u32 dummy4_0:1;
365 	u32 stbc:1;
366 	u32 ldcp:1;
367 	u32 splcp:1;
368 #endif
369 	u32 tsfl;
370 };
371 
372 struct rtl8xxxu_txdesc32 {
373 	__le16 pkt_size;
374 	u8 pkt_offset;
375 	u8 txdw0;
376 	__le32 txdw1;
377 	__le32 txdw2;
378 	__le32 txdw3;
379 	__le32 txdw4;
380 	__le32 txdw5;
381 	__le32 txdw6;
382 	__le16 csum;
383 	__le16 txdw7;
384 };
385 
386 struct rtl8xxxu_txdesc40 {
387 	__le16 pkt_size;
388 	u8 pkt_offset;
389 	u8 txdw0;
390 	__le32 txdw1;
391 	__le32 txdw2;
392 	__le32 txdw3;
393 	__le32 txdw4;
394 	__le32 txdw5;
395 	__le32 txdw6;
396 	__le16 csum;
397 	__le16 txdw7;
398 	__le32 txdw8;
399 	__le32 txdw9;
400 };
401 
402 /*  CCK Rates, TxHT = 0 */
403 #define DESC_RATE_1M			0x00
404 #define DESC_RATE_2M			0x01
405 #define DESC_RATE_5_5M			0x02
406 #define DESC_RATE_11M			0x03
407 
408 /*  OFDM Rates, TxHT = 0 */
409 #define DESC_RATE_6M			0x04
410 #define DESC_RATE_9M			0x05
411 #define DESC_RATE_12M			0x06
412 #define DESC_RATE_18M			0x07
413 #define DESC_RATE_24M			0x08
414 #define DESC_RATE_36M			0x09
415 #define DESC_RATE_48M			0x0a
416 #define DESC_RATE_54M			0x0b
417 
418 /*  MCS Rates, TxHT = 1 */
419 #define DESC_RATE_MCS0			0x0c
420 #define DESC_RATE_MCS1			0x0d
421 #define DESC_RATE_MCS2			0x0e
422 #define DESC_RATE_MCS3			0x0f
423 #define DESC_RATE_MCS4			0x10
424 #define DESC_RATE_MCS5			0x11
425 #define DESC_RATE_MCS6			0x12
426 #define DESC_RATE_MCS7			0x13
427 #define DESC_RATE_MCS8			0x14
428 #define DESC_RATE_MCS9			0x15
429 #define DESC_RATE_MCS10			0x16
430 #define DESC_RATE_MCS11			0x17
431 #define DESC_RATE_MCS12			0x18
432 #define DESC_RATE_MCS13			0x19
433 #define DESC_RATE_MCS14			0x1a
434 #define DESC_RATE_MCS15			0x1b
435 #define DESC_RATE_MCS15_SG		0x1c
436 #define DESC_RATE_MCS32			0x20
437 
438 #define TXDESC_OFFSET_SZ		0
439 #define TXDESC_OFFSET_SHT		16
440 #if 0
441 #define TXDESC_BMC			BIT(24)
442 #define TXDESC_LSG			BIT(26)
443 #define TXDESC_FSG			BIT(27)
444 #define TXDESC_OWN			BIT(31)
445 #else
446 #define TXDESC_BROADMULTICAST		BIT(0)
447 #define TXDESC_HTC			BIT(1)
448 #define TXDESC_LAST_SEGMENT		BIT(2)
449 #define TXDESC_FIRST_SEGMENT		BIT(3)
450 #define TXDESC_LINIP			BIT(4)
451 #define TXDESC_NO_ACM			BIT(5)
452 #define TXDESC_GF			BIT(6)
453 #define TXDESC_OWN			BIT(7)
454 #endif
455 
456 /* Word 1 */
457 /*
458  * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are
459  * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid.
460  */
461 #define TXDESC_PKT_OFFSET_SZ		0
462 #define TXDESC32_AGG_ENABLE		BIT(5)
463 #define TXDESC32_AGG_BREAK		BIT(6)
464 #define TXDESC40_MACID_SHIFT		0
465 #define TXDESC40_MACID_MASK		0x00f0
466 #define TXDESC_QUEUE_SHIFT		8
467 #define TXDESC_QUEUE_MASK		0x1f00
468 #define TXDESC_QUEUE_BK			0x2
469 #define TXDESC_QUEUE_BE			0x0
470 #define TXDESC_QUEUE_VI			0x5
471 #define TXDESC_QUEUE_VO			0x7
472 #define TXDESC_QUEUE_BEACON		0x10
473 #define TXDESC_QUEUE_HIGH		0x11
474 #define TXDESC_QUEUE_MGNT		0x12
475 #define TXDESC_QUEUE_CMD		0x13
476 #define TXDESC_QUEUE_MAX		(TXDESC_QUEUE_CMD + 1)
477 #define TXDESC40_RDG_NAV_EXT		BIT(13)
478 #define TXDESC40_LSIG_TXOP_ENABLE	BIT(14)
479 #define TXDESC40_PIFS			BIT(15)
480 
481 #define DESC_RATE_ID_SHIFT		16
482 #define DESC_RATE_ID_MASK		0xf
483 #define TXDESC_NAVUSEHDR		BIT(20)
484 #define TXDESC_SEC_RC4			0x00400000
485 #define TXDESC_SEC_AES			0x00c00000
486 #define TXDESC_PKT_OFFSET_SHIFT		26
487 #define TXDESC_AGG_EN			BIT(29)
488 #define TXDESC_HWPC			BIT(31)
489 
490 /* Word 2 */
491 #define TXDESC40_PAID_SHIFT		0
492 #define TXDESC40_PAID_MASK		0x1ff
493 #define TXDESC40_CCA_RTS_SHIFT		10
494 #define TXDESC40_CCA_RTS_MASK		0xc00
495 #define TXDESC40_AGG_ENABLE		BIT(12)
496 #define TXDESC40_RDG_ENABLE		BIT(13)
497 #define TXDESC40_AGG_BREAK		BIT(16)
498 #define TXDESC40_MORE_FRAG		BIT(17)
499 #define TXDESC40_RAW			BIT(18)
500 #define TXDESC32_ACK_REPORT		BIT(19)
501 #define TXDESC40_SPE_RPT		BIT(19)
502 #define TXDESC_AMPDU_DENSITY_SHIFT	20
503 #define TXDESC40_BT_INT			BIT(23)
504 #define TXDESC40_GID_SHIFT		24
505 
506 /* Word 3 */
507 #define TXDESC40_USE_DRIVER_RATE	BIT(8)
508 #define TXDESC40_CTS_SELF_ENABLE	BIT(11)
509 #define TXDESC40_RTS_CTS_ENABLE		BIT(12)
510 #define TXDESC40_HW_RTS_ENABLE		BIT(13)
511 #define TXDESC32_SEQ_SHIFT		16
512 #define TXDESC32_SEQ_MASK		0x0fff0000
513 
514 /* Word 4 */
515 #define TXDESC32_RTS_RATE_SHIFT		0
516 #define TXDESC32_RTS_RATE_MASK		0x3f
517 #define TXDESC32_QOS			BIT(6)
518 #define TXDESC32_HW_SEQ_ENABLE		BIT(7)
519 #define TXDESC32_USE_DRIVER_RATE	BIT(8)
520 #define TXDESC_DISABLE_DATA_FB		BIT(10)
521 #define TXDESC32_CTS_SELF_ENABLE	BIT(11)
522 #define TXDESC32_RTS_CTS_ENABLE		BIT(12)
523 #define TXDESC32_HW_RTS_ENABLE		BIT(13)
524 #define TXDESC_PRIME_CH_OFF_LOWER	BIT(20)
525 #define TXDESC_PRIME_CH_OFF_UPPER	BIT(21)
526 #define TXDESC32_SHORT_PREAMBLE		BIT(24)
527 #define TXDESC_DATA_BW			BIT(25)
528 #define TXDESC_RTS_DATA_BW		BIT(27)
529 #define TXDESC_RTS_PRIME_CH_OFF_LOWER	BIT(28)
530 #define TXDESC_RTS_PRIME_CH_OFF_UPPER	BIT(29)
531 #define TXDESC40_DATA_RATE_FB_SHIFT	8
532 #define TXDESC40_DATA_RATE_FB_MASK	0x00001f00
533 #define TXDESC40_RETRY_LIMIT_ENABLE	BIT(17)
534 #define TXDESC40_RETRY_LIMIT_SHIFT	18
535 #define TXDESC40_RETRY_LIMIT_MASK	0x00fc0000
536 #define TXDESC40_RTS_RATE_SHIFT		24
537 #define TXDESC40_RTS_RATE_MASK		0x3f000000
538 
539 /* Word 5 */
540 #define TXDESC40_SHORT_PREAMBLE		BIT(4)
541 #define TXDESC32_SHORT_GI		BIT(6)
542 #define TXDESC_CCX_TAG			BIT(7)
543 #define TXDESC32_RETRY_LIMIT_ENABLE	BIT(17)
544 #define TXDESC32_RETRY_LIMIT_SHIFT	18
545 #define TXDESC32_RETRY_LIMIT_MASK	0x00fc0000
546 
547 /* Word 6 */
548 #define TXDESC_MAX_AGG_SHIFT		11
549 
550 /* Word 8 */
551 #define TXDESC40_HW_SEQ_ENABLE		BIT(15)
552 
553 /* Word 9 */
554 #define TXDESC40_SEQ_SHIFT		12
555 #define TXDESC40_SEQ_MASK		0x00fff000
556 
557 struct phy_rx_agc_info {
558 #ifdef __LITTLE_ENDIAN
559 	u8	gain:7, trsw:1;
560 #else
561 	u8	trsw:1, gain:7;
562 #endif
563 };
564 
565 struct rtl8723au_phy_stats {
566 	struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS];
567 	u8	ch_corr[RTL8723A_MAX_RF_PATHS];
568 	u8	cck_sig_qual_ofdm_pwdb_all;
569 	u8	cck_agc_rpt_ofdm_cfosho_a;
570 	u8	cck_rpt_b_ofdm_cfosho_b;
571 	u8	reserved_1;
572 	u8	noise_power_db_msb;
573 	s8	path_cfotail[RTL8723A_MAX_RF_PATHS];
574 	u8	pcts_mask[RTL8723A_MAX_RF_PATHS];
575 	s8	stream_rxevm[RTL8723A_MAX_RF_PATHS];
576 	u8	path_rxsnr[RTL8723A_MAX_RF_PATHS];
577 	u8	noise_power_db_lsb;
578 	u8	reserved_2[3];
579 	u8	stream_csi[RTL8723A_MAX_RF_PATHS];
580 	u8	stream_target_csi[RTL8723A_MAX_RF_PATHS];
581 	s8	sig_evm;
582 	u8	reserved_3;
583 
584 #ifdef __LITTLE_ENDIAN
585 	u8	antsel_rx_keep_2:1;	/* ex_intf_flg:1; */
586 	u8	sgi_en:1;
587 	u8	rxsc:2;
588 	u8	idle_long:1;
589 	u8	r_ant_train_en:1;
590 	u8	antenna_select_b:1;
591 	u8	antenna_select:1;
592 #else	/*  _BIG_ENDIAN_ */
593 	u8	antenna_select:1;
594 	u8	antenna_select_b:1;
595 	u8	r_ant_train_en:1;
596 	u8	idle_long:1;
597 	u8	rxsc:2;
598 	u8	sgi_en:1;
599 	u8	antsel_rx_keep_2:1;	/* ex_intf_flg:1; */
600 #endif
601 };
602 
603 /*
604  * Regs to backup
605  */
606 #define RTL8XXXU_ADDA_REGS		16
607 #define RTL8XXXU_MAC_REGS		4
608 #define RTL8XXXU_BB_REGS		9
609 
610 struct rtl8xxxu_firmware_header {
611 	__le16	signature;		/*  92C0: test chip; 92C,
612 					    88C0: test chip;
613 					    88C1: MP A-cut;
614 					    92C1: MP A-cut */
615 	u8	category;		/*  AP/NIC and USB/PCI */
616 	u8	function;
617 
618 	__le16	major_version;		/*  FW Version */
619 	u8	minor_version;		/*  FW Subversion, default 0x00 */
620 	u8	reserved1;
621 
622 	u8	month;			/*  Release time Month field */
623 	u8	date;			/*  Release time Date field */
624 	u8	hour;			/*  Release time Hour field */
625 	u8	minute;			/*  Release time Minute field */
626 
627 	__le16	ramcodesize;		/*  Size of RAM code */
628 	u16	reserved2;
629 
630 	__le32	svn_idx;		/*  SVN entry index */
631 	u32	reserved3;
632 
633 	u32	reserved4;
634 	u32	reserved5;
635 
636 	u8	data[];
637 };
638 
639 /*
640  * 8723au/8192cu/8188ru required base power index offset tables.
641  */
642 struct rtl8xxxu_power_base {
643 	u32 reg_0e00;
644 	u32 reg_0e04;
645 	u32 reg_0e08;
646 	u32 reg_086c;
647 
648 	u32 reg_0e10;
649 	u32 reg_0e14;
650 	u32 reg_0e18;
651 	u32 reg_0e1c;
652 
653 	u32 reg_0830;
654 	u32 reg_0834;
655 	u32 reg_0838;
656 	u32 reg_086c_2;
657 
658 	u32 reg_083c;
659 	u32 reg_0848;
660 	u32 reg_084c;
661 	u32 reg_0868;
662 };
663 
664 /*
665  * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14
666  */
667 struct rtl8723au_idx {
668 #ifdef __LITTLE_ENDIAN
669 	int	a:4;
670 	int	b:4;
671 #else
672 	int	b:4;
673 	int	a:4;
674 #endif
675 } __attribute__((packed));
676 
677 struct rtl8723au_efuse {
678 	__le16 rtl_id;
679 	u8 res0[0xe];
680 	u8 cck_tx_power_index_A[3];	/* 0x10 */
681 	u8 cck_tx_power_index_B[3];
682 	u8 ht40_1s_tx_power_index_A[3];	/* 0x16 */
683 	u8 ht40_1s_tx_power_index_B[3];
684 	/*
685 	 * The following entries are half-bytes split as:
686 	 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
687 	 */
688 	struct rtl8723au_idx ht20_tx_power_index_diff[3];
689 	struct rtl8723au_idx ofdm_tx_power_index_diff[3];
690 	struct rtl8723au_idx ht40_max_power_offset[3];
691 	struct rtl8723au_idx ht20_max_power_offset[3];
692 	u8 channel_plan;		/* 0x28 */
693 	u8 tssi_a;
694 	u8 thermal_meter;
695 	u8 rf_regulatory;
696 	u8 rf_option_2;
697 	u8 rf_option_3;
698 	u8 rf_option_4;
699 	u8 res7;
700 	u8 version			/* 0x30 */;
701 	u8 customer_id_major;
702 	u8 customer_id_minor;
703 	u8 xtal_k;
704 	u8 chipset;			/* 0x34 */
705 	u8 res8[0x82];
706 	u8 vid;				/* 0xb7 */
707 	u8 res9;
708 	u8 pid;				/* 0xb9 */
709 	u8 res10[0x0c];
710 	u8 mac_addr[ETH_ALEN];		/* 0xc6 */
711 	u8 res11[2];
712 	u8 vendor_name[7];
713 	u8 res12[2];
714 	u8 device_name[0x29];		/* 0xd7 */
715 };
716 
717 struct rtl8192cu_efuse {
718 	__le16 rtl_id;
719 	__le16 hpon;
720 	u8 res0[2];
721 	__le16 clk;
722 	__le16 testr;
723 	__le16 vid;
724 	__le16 did;
725 	__le16 svid;
726 	__le16 smid;						/* 0x10 */
727 	u8 res1[4];
728 	u8 mac_addr[ETH_ALEN];					/* 0x16 */
729 	u8 res2[2];
730 	u8 vendor_name[7];
731 	u8 res3[3];
732 	u8 device_name[0x14];					/* 0x28 */
733 	u8 res4[0x1e];						/* 0x3c */
734 	u8 cck_tx_power_index_A[3];				/* 0x5a */
735 	u8 cck_tx_power_index_B[3];
736 	u8 ht40_1s_tx_power_index_A[3];				/* 0x60 */
737 	u8 ht40_1s_tx_power_index_B[3];
738 	/*
739 	 * The following entries are half-bytes split as:
740 	 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
741 	 */
742 	struct rtl8723au_idx ht40_2s_tx_power_index_diff[3];
743 	struct rtl8723au_idx ht20_tx_power_index_diff[3];	/* 0x69 */
744 	struct rtl8723au_idx ofdm_tx_power_index_diff[3];
745 	struct rtl8723au_idx ht40_max_power_offset[3];		/* 0x6f */
746 	struct rtl8723au_idx ht20_max_power_offset[3];
747 	u8 channel_plan;					/* 0x75 */
748 	u8 tssi_a;
749 	u8 tssi_b;
750 	u8 thermal_meter;	/* xtal_k */			/* 0x78 */
751 	u8 rf_regulatory;
752 	u8 rf_option_2;
753 	u8 rf_option_3;
754 	u8 rf_option_4;
755 	u8 res5[1];						/* 0x7d */
756 	u8 version;
757 	u8 customer_id;
758 };
759 
760 struct rtl8723bu_pwr_idx {
761 #ifdef __LITTLE_ENDIAN
762 	int	ht20:4;
763 	int	ht40:4;
764 	int	ofdm:4;
765 	int	cck:4;
766 #else
767 	int	cck:4;
768 	int	ofdm:4;
769 	int	ht40:4;
770 	int	ht20:4;
771 #endif
772 } __attribute__((packed));
773 
774 struct rtl8723bu_efuse_tx_power {
775 	u8 cck_base[6];
776 	u8 ht40_base[5];
777 	struct rtl8723au_idx ht20_ofdm_1s_diff;
778 	struct rtl8723bu_pwr_idx pwr_diff[3];
779 	u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */
780 };
781 
782 struct rtl8723bu_efuse {
783 	__le16 rtl_id;
784 	u8 res0[0x0e];
785 	struct rtl8723bu_efuse_tx_power tx_power_index_A;	/* 0x10 */
786 	struct rtl8723bu_efuse_tx_power tx_power_index_B;	/* 0x3a */
787 	struct rtl8723bu_efuse_tx_power tx_power_index_C;	/* 0x64 */
788 	struct rtl8723bu_efuse_tx_power tx_power_index_D;	/* 0x8e */
789 	u8 channel_plan;		/* 0xb8 */
790 	u8 xtal_k;
791 	u8 thermal_meter;
792 	u8 iqk_lck;
793 	u8 pa_type;			/* 0xbc */
794 	u8 lna_type_2g;			/* 0xbd */
795 	u8 res2[3];
796 	u8 rf_board_option;
797 	u8 rf_feature_option;
798 	u8 rf_bt_setting;
799 	u8 eeprom_version;
800 	u8 eeprom_customer_id;
801 	u8 res3[2];
802 	u8 tx_pwr_calibrate_rate;
803 	u8 rf_antenna_option;		/* 0xc9 */
804 	u8 rfe_option;
805 	u8 res4[9];
806 	u8 usb_optional_function;
807 	u8 res5[0x1e];
808 	u8 res6[2];
809 	u8 serial[0x0b];		/* 0xf5 */
810 	u8 vid;				/* 0x100 */
811 	u8 res7;
812 	u8 pid;
813 	u8 res8[4];
814 	u8 mac_addr[ETH_ALEN];		/* 0x107 */
815 	u8 res9[2];
816 	u8 vendor_name[0x07];
817 	u8 res10[2];
818 	u8 device_name[0x14];
819 	u8 res11[0xcf];
820 	u8 package_type;		/* 0x1fb */
821 	u8 res12[0x4];
822 };
823 
824 struct rtl8192eu_efuse_tx_power {
825 	u8 cck_base[6];
826 	u8 ht40_base[5];
827 	struct rtl8723au_idx ht20_ofdm_1s_diff;
828 	struct rtl8723bu_pwr_idx pwr_diff[3];
829 	u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */
830 };
831 
832 struct rtl8192eu_efuse {
833 	__le16 rtl_id;
834 	u8 res0[0x0e];
835 	struct rtl8192eu_efuse_tx_power tx_power_index_A;	/* 0x10 */
836 	struct rtl8192eu_efuse_tx_power tx_power_index_B;	/* 0x3a */
837 	u8 res2[0x54];
838 	u8 channel_plan;		/* 0xb8 */
839 	u8 xtal_k;
840 	u8 thermal_meter;
841 	u8 iqk_lck;
842 	u8 pa_type;			/* 0xbc */
843 	u8 lna_type_2g;			/* 0xbd */
844 	u8 res3[1];
845 	u8 lna_type_5g;			/* 0xbf */
846 	u8 res4[1];
847 	u8 rf_board_option;
848 	u8 rf_feature_option;
849 	u8 rf_bt_setting;
850 	u8 eeprom_version;
851 	u8 eeprom_customer_id;
852 	u8 res5[3];
853 	u8 rf_antenna_option;		/* 0xc9 */
854 	u8 res6[6];
855 	u8 vid;				/* 0xd0 */
856 	u8 res7[1];
857 	u8 pid;				/* 0xd2 */
858 	u8 res8[1];
859 	u8 usb_optional_function;
860 	u8 res9[2];
861 	u8 mac_addr[ETH_ALEN];		/* 0xd7 */
862 	u8 device_info[80];
863 	u8 res11[3];
864 	u8 unknown[0x0d];		/* 0x130 */
865 	u8 res12[0xc3];
866 };
867 
868 struct rtl8188fu_efuse_tx_power {
869 	u8 cck_base[6];
870 	u8 ht40_base[5];
871 	/* a: ofdm; b: ht20 */
872 	struct rtl8723au_idx ht20_ofdm_1s_diff;
873 };
874 
875 struct rtl8188fu_efuse {
876 	__le16 rtl_id;
877 	u8 res0[0x0e];
878 	struct rtl8188fu_efuse_tx_power tx_power_index_A;	/* 0x10 */
879 	u8 res1[0x9c];			/* 0x1c */
880 	u8 channel_plan;		/* 0xb8 */
881 	u8 xtal_k;
882 	u8 thermal_meter;
883 	u8 iqk_lck;
884 	u8 res2[5];
885 	u8 rf_board_option;
886 	u8 rf_feature_option;
887 	u8 rf_bt_setting;
888 	u8 eeprom_version;
889 	u8 eeprom_customer_id;
890 	u8 res3[2];
891 	u8 kfree_thermal_k_on;
892 	u8 rf_antenna_option;		/* 0xc9 */
893 	u8 rfe_option;
894 	u8 country_code;
895 	u8 res4[4];
896 	u8 vid;				/* 0xd0 */
897 	u8 res5[1];
898 	u8 pid;				/* 0xd2 */
899 	u8 res6[1];
900 	u8 usb_optional_function;
901 	u8 res7[2];
902 	u8 mac_addr[ETH_ALEN];		/* 0xd7 */
903 	u8 res8[2];
904 	u8 vendor_name[7];
905 	u8 res9[2];
906 	u8 device_name[7];		/* 0xe8 */
907 	u8 res10[0x41];
908 	u8 unknown[0x0d];		/* 0x130 */
909 	u8 res11[0xc3];
910 };
911 
912 struct rtl8xxxu_reg8val {
913 	u16 reg;
914 	u8 val;
915 };
916 
917 struct rtl8xxxu_reg32val {
918 	u16 reg;
919 	u32 val;
920 };
921 
922 struct rtl8xxxu_rfregval {
923 	u8 reg;
924 	u32 val;
925 };
926 
927 enum rtl8xxxu_rfpath {
928 	RF_A = 0,
929 	RF_B = 1,
930 };
931 
932 struct rtl8xxxu_rfregs {
933 	u16 hssiparm1;
934 	u16 hssiparm2;
935 	u16 lssiparm;
936 	u16 hspiread;
937 	u16 lssiread;
938 	u16 rf_sw_ctrl;
939 };
940 
941 #define H2C_MAX_MBOX			4
942 #define H2C_EXT				BIT(7)
943 #define  H2C_JOIN_BSS_DISCONNECT	0
944 #define  H2C_JOIN_BSS_CONNECT		1
945 
946 /*
947  * H2C (firmware) commands differ between the older generation chips
948  * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu,
949  * 8192[de]u, 8192eu, and 8812.
950  */
951 enum h2c_cmd_8723a {
952 	H2C_SET_POWER_MODE = 1,
953 	H2C_JOIN_BSS_REPORT = 2,
954 	H2C_SET_RSSI = 5,
955 	H2C_SET_RATE_MASK = (6 | H2C_EXT),
956 };
957 
958 enum h2c_cmd_8723b {
959 	/*
960 	 * Common Class: 000
961 	 */
962 	H2C_8723B_RSVD_PAGE = 0x00,
963 	H2C_8723B_MEDIA_STATUS_RPT = 0x01,
964 	H2C_8723B_SCAN_ENABLE = 0x02,
965 	H2C_8723B_KEEP_ALIVE = 0x03,
966 	H2C_8723B_DISCON_DECISION = 0x04,
967 	H2C_8723B_PSD_OFFLOAD = 0x05,
968 	H2C_8723B_AP_OFFLOAD = 0x08,
969 	H2C_8723B_BCN_RSVDPAGE = 0x09,
970 	H2C_8723B_PROBERSP_RSVDPAGE = 0x0A,
971 	H2C_8723B_FCS_RSVDPAGE = 0x10,
972 	H2C_8723B_FCS_INFO = 0x11,
973 	H2C_8723B_AP_WOW_GPIO_CTRL = 0x13,
974 
975 	/*
976 	 * PoweSave Class: 001
977 	 */
978 	H2C_8723B_SET_PWR_MODE = 0x20,
979 	H2C_8723B_PS_TUNING_PARA = 0x21,
980 	H2C_8723B_PS_TUNING_PARA2 = 0x22,
981 	H2C_8723B_P2P_LPS_PARAM = 0x23,
982 	H2C_8723B_P2P_PS_OFFLOAD = 0x24,
983 	H2C_8723B_PS_SCAN_ENABLE = 0x25,
984 	H2C_8723B_SAP_PS_ = 0x26,
985 	H2C_8723B_INACTIVE_PS_ = 0x27,
986 	H2C_8723B_FWLPS_IN_IPS_ = 0x28,
987 
988 	/*
989 	 * Dynamic Mechanism Class: 010
990 	 */
991 	H2C_8723B_MACID_CFG_RAID = 0x40,
992 	H2C_8723B_TXBF = 0x41,
993 	H2C_8723B_RSSI_SETTING = 0x42,
994 	H2C_8723B_AP_REQ_TXRPT = 0x43,
995 	H2C_8723B_INIT_RATE_COLLECT = 0x44,
996 
997 	/*
998 	 * BT Class: 011
999 	 */
1000 	H2C_8723B_B_TYPE_TDMA = 0x60,
1001 	H2C_8723B_BT_INFO = 0x61,
1002 	H2C_8723B_FORCE_BT_TXPWR = 0x62,
1003 	H2C_8723B_BT_IGNORE_WLANACT = 0x63,
1004 	H2C_8723B_DAC_SWING_VALUE = 0x64,
1005 	H2C_8723B_ANT_SEL_RSV = 0x65,
1006 	H2C_8723B_WL_OPMODE = 0x66,
1007 	H2C_8723B_BT_MP_OPER = 0x67,
1008 	H2C_8723B_BT_CONTROL = 0x68,
1009 	H2C_8723B_BT_WIFI_CTRL = 0x69,
1010 	H2C_8723B_BT_FW_PATCH = 0x6a,
1011 	H2C_8723B_BT_WLAN_CALIBRATION = 0x6d,
1012 	H2C_8723B_BT_GRANT = 0x6e,
1013 
1014 	/*
1015 	 * WOWLAN Class: 100
1016 	 */
1017 	H2C_8723B_WOWLAN = 0x80,
1018 	H2C_8723B_REMOTE_WAKE_CTRL = 0x81,
1019 	H2C_8723B_AOAC_GLOBAL_INFO = 0x82,
1020 	H2C_8723B_AOAC_RSVD_PAGE = 0x83,
1021 	H2C_8723B_AOAC_RSVD_PAGE2 = 0x84,
1022 	H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85,
1023 	H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86,
1024 	H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87,
1025 
1026 	H2C_8723B_RESET_TSF = 0xC0,
1027 };
1028 
1029 
1030 struct h2c_cmd {
1031 	union {
1032 		struct {
1033 			u8 cmd;
1034 			u8 data[7];
1035 		} __packed cmd;
1036 		struct {
1037 			__le32 data;
1038 			__le16 ext;
1039 		} __packed raw;
1040 		struct {
1041 			__le32 data;
1042 			__le32 ext;
1043 		} __packed raw_wide;
1044 		struct {
1045 			u8 cmd;
1046 			u8 data;
1047 		} __packed joinbss;
1048 		struct {
1049 			u8 cmd;
1050 			__le16 mask_hi;
1051 			u8 arg;
1052 			__le16 mask_lo;
1053 		} __packed ramask;
1054 		struct {
1055 			u8 cmd;
1056 			u8 parm;
1057 			u8 macid;
1058 			u8 macid_end;
1059 		} __packed media_status_rpt;
1060 		struct {
1061 			u8 cmd;
1062 			u8 macid;
1063 			/*
1064 			 * [0:4] - RAID
1065 			 * [7]   - SGI
1066 			 */
1067 			u8 data1;
1068 			/*
1069 			 * [0:1] - Bandwidth
1070 			 * [3]   - No Update
1071 			 * [4:5] - VHT enable
1072 			 * [6]   - DISPT
1073 			 * [7]   - DISRA
1074 			 */
1075 			u8 data2;
1076 			u8 ramask0;
1077 			u8 ramask1;
1078 			u8 ramask2;
1079 			u8 ramask3;
1080 		} __packed b_macid_cfg;
1081 		struct {
1082 			u8 cmd;
1083 			u8 data1;
1084 			u8 data2;
1085 			u8 data3;
1086 			u8 data4;
1087 			u8 data5;
1088 		} __packed b_type_dma;
1089 		struct {
1090 			u8 cmd;
1091 			u8 data;
1092 		} __packed bt_info;
1093 		struct {
1094 			u8 cmd;
1095 			u8 operreq;
1096 			u8 opcode;
1097 			u8 data;
1098 			u8 addr;
1099 		} __packed bt_mp_oper;
1100 		struct {
1101 			u8 cmd;
1102 			u8 data;
1103 		} __packed bt_wlan_calibration;
1104 		struct {
1105 			u8 cmd;
1106 			u8 data;
1107 		} __packed ignore_wlan;
1108 		struct {
1109 			u8 cmd;
1110 			u8 ant_inverse;
1111 			u8 int_switch_type;
1112 		} __packed ant_sel_rsv;
1113 		struct {
1114 			u8 cmd;
1115 			u8 data;
1116 		} __packed bt_grant;
1117 	};
1118 };
1119 
1120 enum c2h_evt_8723b {
1121 	C2H_8723B_DEBUG = 0,
1122 	C2H_8723B_TSF = 1,
1123 	C2H_8723B_AP_RPT_RSP = 2,
1124 	C2H_8723B_CCX_TX_RPT = 3,
1125 	C2H_8723B_BT_RSSI = 4,
1126 	C2H_8723B_BT_OP_MODE = 5,
1127 	C2H_8723B_EXT_RA_RPT = 6,
1128 	C2H_8723B_BT_INFO = 9,
1129 	C2H_8723B_HW_INFO_EXCH = 0x0a,
1130 	C2H_8723B_BT_MP_INFO = 0x0b,
1131 	C2H_8723B_RA_REPORT = 0x0c,
1132 	C2H_8723B_FW_DEBUG = 0xff,
1133 };
1134 
1135 enum bt_info_src_8723b {
1136 	BT_INFO_SRC_8723B_WIFI_FW = 0x0,
1137         BT_INFO_SRC_8723B_BT_RSP = 0x1,
1138         BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2,
1139 };
1140 
1141 enum bt_mp_oper_opcode_8723b {
1142 	BT_MP_OP_GET_BT_VERSION	= 0x00,
1143 	BT_MP_OP_RESET = 0x01,
1144 	BT_MP_OP_TEST_CTRL = 0x02,
1145 	BT_MP_OP_SET_BT_MODE = 0x03,
1146 	BT_MP_OP_SET_CHNL_TX_GAIN = 0x04,
1147 	BT_MP_OP_SET_PKT_TYPE_LEN = 0x05,
1148 	BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06,
1149 	BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07,
1150 	BT_MP_OP_SET_PKT_HEADER = 0x08,
1151 	BT_MP_OP_SET_WHITENCOEFF = 0x09,
1152 	BT_MP_OP_SET_BD_ADDR_L = 0x0a,
1153 	BT_MP_OP_SET_BD_ADDR_H = 0x0b,
1154 	BT_MP_OP_WRITE_REG_ADDR = 0x0c,
1155 	BT_MP_OP_WRITE_REG_VALUE = 0x0d,
1156 	BT_MP_OP_GET_BT_STATUS = 0x0e,
1157 	BT_MP_OP_GET_BD_ADDR_L = 0x0f,
1158 	BT_MP_OP_GET_BD_ADDR_H = 0x10,
1159 	BT_MP_OP_READ_REG = 0x11,
1160 	BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12,
1161 	BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13,
1162 	BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14,
1163 	BT_MP_OP_GET_RX_PKT_CNT_L = 0x15,
1164 	BT_MP_OP_GET_RX_PKT_CNT_H = 0x16,
1165 	BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17,
1166 	BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18,
1167 	BT_MP_OP_GET_RSSI = 0x19,
1168 	BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a,
1169 	BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b,
1170 	BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c,
1171 	BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d,
1172 	BT_MP_OP_GET_AFH_MAP_L = 0x1e,
1173 	BT_MP_OP_GET_AFH_MAP_M = 0x1f,
1174 	BT_MP_OP_GET_AFH_MAP_H = 0x20,
1175 	BT_MP_OP_GET_AFH_STATUS = 0x21,
1176 	BT_MP_OP_SET_TRACKING_INTERVAL = 0x22,
1177 	BT_MP_OP_SET_THERMAL_METER = 0x23,
1178 	BT_MP_OP_ENABLE_CFO_TRACKING = 0x24,
1179 };
1180 
1181 enum rtl8xxxu_bw_mode {
1182 	RTL8XXXU_CHANNEL_WIDTH_20 = 0,
1183 	RTL8XXXU_CHANNEL_WIDTH_40 = 1,
1184 	RTL8XXXU_CHANNEL_WIDTH_80 = 2,
1185 	RTL8XXXU_CHANNEL_WIDTH_160 = 3,
1186 	RTL8XXXU_CHANNEL_WIDTH_80_80 = 4,
1187 	RTL8XXXU_CHANNEL_WIDTH_MAX = 5,
1188 };
1189 
1190 struct rtl8723bu_c2h {
1191 	u8 id;
1192 	u8 seq;
1193 	union {
1194 		struct {
1195 			u8 payload[0];
1196 		} __packed raw;
1197 		struct {
1198 			u8 ext_id;
1199 			u8 status:4;
1200 			u8 retlen:4;
1201 			u8 opcode_ver:4;
1202 			u8 req_num:4;
1203 			u8 payload[2];
1204 		} __packed bt_mp_info;
1205 		struct {
1206 			u8 response_source:4;
1207 			u8 dummy0_0:4;
1208 
1209 			u8 bt_info;
1210 
1211 			u8 retry_count:4;
1212 			u8 dummy2_0:1;
1213 			u8 bt_page:1;
1214 			u8 tx_rx_mask:1;
1215 			u8 dummy2_2:1;
1216 
1217 			u8 rssi;
1218 
1219 			u8 basic_rate:1;
1220 			u8 bt_has_reset:1;
1221 			u8 dummy4_1:1;
1222 			u8 ignore_wlan:1;
1223 			u8 auto_report:1;
1224 			u8 dummy4_2:3;
1225 
1226 			u8 a4;
1227 			u8 a5;
1228 		} __packed bt_info;
1229 		struct {
1230 			u8 rate:7;
1231 			u8 sgi:1;
1232 			u8 macid;
1233 			u8 ldpc:1;
1234 			u8 txbf:1;
1235 			u8 noisy_state:1;
1236 			u8 dummy2_0:5;
1237 			u8 dummy3_0;
1238 			u8 dummy4_0;
1239 			u8 dummy5_0;
1240 			u8 bw;
1241 		} __packed ra_report;
1242 	};
1243 } __packed;
1244 
1245 struct rtl8xxxu_fileops;
1246 
1247 /*mlme related.*/
1248 enum wireless_mode {
1249 	WIRELESS_MODE_UNKNOWN = 0,
1250 	/* Sub-Element */
1251 	WIRELESS_MODE_B = BIT(0),
1252 	WIRELESS_MODE_G = BIT(1),
1253 	WIRELESS_MODE_A = BIT(2),
1254 	WIRELESS_MODE_N_24G = BIT(3),
1255 	WIRELESS_MODE_N_5G = BIT(4),
1256 	WIRELESS_AUTO = BIT(5),
1257 	WIRELESS_MODE_AC = BIT(6),
1258 	WIRELESS_MODE_MAX = 0x7F,
1259 };
1260 
1261 /* from rtlwifi/wifi.h */
1262 enum ratr_table_mode_new {
1263 	RATEID_IDX_BGN_40M_2SS = 0,
1264 	RATEID_IDX_BGN_40M_1SS = 1,
1265 	RATEID_IDX_BGN_20M_2SS_BN = 2,
1266 	RATEID_IDX_BGN_20M_1SS_BN = 3,
1267 	RATEID_IDX_GN_N2SS = 4,
1268 	RATEID_IDX_GN_N1SS = 5,
1269 	RATEID_IDX_BG = 6,
1270 	RATEID_IDX_G = 7,
1271 	RATEID_IDX_B = 8,
1272 	RATEID_IDX_VHT_2SS = 9,
1273 	RATEID_IDX_VHT_1SS = 10,
1274 	RATEID_IDX_MIX1 = 11,
1275 	RATEID_IDX_MIX2 = 12,
1276 	RATEID_IDX_VHT_3SS = 13,
1277 	RATEID_IDX_BGN_3SS = 14,
1278 };
1279 
1280 #define BT_INFO_8723B_1ANT_B_FTP		BIT(7)
1281 #define BT_INFO_8723B_1ANT_B_A2DP		BIT(6)
1282 #define BT_INFO_8723B_1ANT_B_HID		BIT(5)
1283 #define BT_INFO_8723B_1ANT_B_SCO_BUSY		BIT(4)
1284 #define BT_INFO_8723B_1ANT_B_ACL_BUSY		BIT(3)
1285 #define BT_INFO_8723B_1ANT_B_INQ_PAGE		BIT(2)
1286 #define BT_INFO_8723B_1ANT_B_SCO_ESCO		BIT(1)
1287 #define BT_INFO_8723B_1ANT_B_CONNECTION	BIT(0)
1288 
1289 enum _BT_8723B_1ANT_STATUS {
1290 	BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE      = 0x0,
1291 	BT_8723B_1ANT_STATUS_CONNECTED_IDLE          = 0x1,
1292 	BT_8723B_1ANT_STATUS_INQ_PAGE                = 0x2,
1293 	BT_8723B_1ANT_STATUS_ACL_BUSY                = 0x3,
1294 	BT_8723B_1ANT_STATUS_SCO_BUSY                = 0x4,
1295 	BT_8723B_1ANT_STATUS_ACL_SCO_BUSY            = 0x5,
1296 	BT_8723B_1ANT_STATUS_MAX
1297 };
1298 
1299 struct rtl8xxxu_btcoex {
1300 	u8      bt_status;
1301 	bool	bt_busy;
1302 	bool	has_sco;
1303 	bool	has_a2dp;
1304 	bool    has_hid;
1305 	bool    has_pan;
1306 	bool	hid_only;
1307 	bool	a2dp_only;
1308 	bool    c2h_bt_inquiry;
1309 };
1310 
1311 #define RTL8XXXU_RATR_STA_INIT 0
1312 #define RTL8XXXU_RATR_STA_HIGH 1
1313 #define RTL8XXXU_RATR_STA_MID  2
1314 #define RTL8XXXU_RATR_STA_LOW  3
1315 
1316 #define RTL8XXXU_NOISE_FLOOR_MIN	-100
1317 #define RTL8XXXU_SNR_THRESH_HIGH	50
1318 #define RTL8XXXU_SNR_THRESH_LOW	20
1319 
1320 struct rtl8xxxu_ra_report {
1321 	struct rate_info txrate;
1322 	u32 bit_rate;
1323 	u8 desc_rate;
1324 };
1325 
1326 #define CFO_TH_XTAL_HIGH	20 /* kHz */
1327 #define CFO_TH_XTAL_LOW	10 /* kHz */
1328 #define CFO_TH_ATC		80 /* kHz */
1329 
1330 struct rtl8xxxu_cfo_tracking {
1331 	bool adjust;
1332 	bool atc_status;
1333 	int cfo_tail[2];
1334 	u8 crystal_cap;
1335 	u32 packet_count;
1336 	u32 packet_count_pre;
1337 };
1338 
1339 struct rtl8xxxu_priv {
1340 	struct ieee80211_hw *hw;
1341 	struct usb_device *udev;
1342 	struct rtl8xxxu_fileops *fops;
1343 
1344 	spinlock_t tx_urb_lock;
1345 	struct list_head tx_urb_free_list;
1346 	int tx_urb_free_count;
1347 	bool tx_stopped;
1348 
1349 	spinlock_t rx_urb_lock;
1350 	struct list_head rx_urb_pending_list;
1351 	int rx_urb_pending_count;
1352 	bool shutdown;
1353 	struct work_struct rx_urb_wq;
1354 
1355 	u8 mac_addr[ETH_ALEN];
1356 	char chip_name[8];
1357 	char chip_vendor[8];
1358 	u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1359 	u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1360 	u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1361 	u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1362 	/*
1363 	 * The following entries are half-bytes split as:
1364 	 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
1365 	 */
1366 	struct rtl8723au_idx ht40_2s_tx_power_index_diff[
1367 		RTL8723A_CHANNEL_GROUPS];
1368 	struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1369 	struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1370 	struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1371 	struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1372 	/*
1373 	 * Newer generation chips only keep power diffs per TX count,
1374 	 * not per channel group.
1375 	 */
1376 	struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT];
1377 	struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT];
1378 	struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT];
1379 	struct rtl8xxxu_power_base *power_base;
1380 	u32 chip_cut:4;
1381 	u32 rom_rev:4;
1382 	u32 is_multi_func:1;
1383 	u32 has_wifi:1;
1384 	u32 has_bluetooth:1;
1385 	u32 enable_bluetooth:1;
1386 	u32 has_gps:1;
1387 	u32 hi_pa:1;
1388 	u32 vendor_umc:1;
1389 	u32 vendor_smic:1;
1390 	u32 has_polarity_ctrl:1;
1391 	u32 has_eeprom:1;
1392 	u32 boot_eeprom:1;
1393 	u32 usb_interrupts:1;
1394 	u32 ep_tx_high_queue:1;
1395 	u32 ep_tx_normal_queue:1;
1396 	u32 ep_tx_low_queue:1;
1397 	u32 rx_buf_aggregation:1;
1398 	u32 cck_agc_report_type:1;
1399 	u8 default_crystal_cap;
1400 	unsigned int pipe_interrupt;
1401 	unsigned int pipe_in;
1402 	unsigned int pipe_out[TXDESC_QUEUE_MAX];
1403 	u8 out_ep[RTL8XXXU_OUT_ENDPOINTS];
1404 	u8 ep_tx_count;
1405 	u8 rf_paths;
1406 	u8 rx_paths;
1407 	u8 tx_paths;
1408 	u32 rege94;
1409 	u32 rege9c;
1410 	u32 regeb4;
1411 	u32 regebc;
1412 	int next_mbox;
1413 	int nr_out_eps;
1414 
1415 	struct mutex h2c_mutex;
1416 
1417 	struct usb_anchor rx_anchor;
1418 	struct usb_anchor tx_anchor;
1419 	struct usb_anchor int_anchor;
1420 	struct rtl8xxxu_firmware_header *fw_data;
1421 	size_t fw_size;
1422 	struct mutex usb_buf_mutex;
1423 	union {
1424 		__le32 val32;
1425 		__le16 val16;
1426 		u8 val8;
1427 	} usb_buf;
1428 	union {
1429 		u8 raw[EFUSE_MAP_LEN];
1430 		struct rtl8723au_efuse efuse8723;
1431 		struct rtl8723bu_efuse efuse8723bu;
1432 		struct rtl8192cu_efuse efuse8192;
1433 		struct rtl8192eu_efuse efuse8192eu;
1434 		struct rtl8188fu_efuse efuse8188fu;
1435 	} efuse_wifi;
1436 	u32 adda_backup[RTL8XXXU_ADDA_REGS];
1437 	u32 mac_backup[RTL8XXXU_MAC_REGS];
1438 	u32 bb_backup[RTL8XXXU_BB_REGS];
1439 	u32 bb_recovery_backup[RTL8XXXU_BB_REGS];
1440 	enum rtl8xxxu_rtl_chip rtl_chip;
1441 	u8 pi_enabled:1;
1442 	u8 no_pape:1;
1443 	u8 int_buf[USB_INTR_CONTENT_LENGTH];
1444 	u8 rssi_level;
1445 	DECLARE_BITMAP(tx_aggr_started, IEEE80211_NUM_TIDS);
1446 	DECLARE_BITMAP(tid_tx_operational, IEEE80211_NUM_TIDS);
1447 	/*
1448 	 * Only one virtual interface permitted because only STA mode
1449 	 * is supported and no iface_combinations are provided.
1450 	 */
1451 	struct ieee80211_vif *vif;
1452 	struct delayed_work ra_watchdog;
1453 	struct work_struct c2hcmd_work;
1454 	struct sk_buff_head c2hcmd_queue;
1455 	struct rtl8xxxu_btcoex bt_coex;
1456 	struct rtl8xxxu_ra_report ra_report;
1457 	struct rtl8xxxu_cfo_tracking cfo_tracking;
1458 };
1459 
1460 struct rtl8xxxu_rx_urb {
1461 	struct urb urb;
1462 	struct ieee80211_hw *hw;
1463 	struct list_head list;
1464 };
1465 
1466 struct rtl8xxxu_tx_urb {
1467 	struct urb urb;
1468 	struct ieee80211_hw *hw;
1469 	struct list_head list;
1470 };
1471 
1472 struct rtl8xxxu_fileops {
1473 	int (*identify_chip) (struct rtl8xxxu_priv *priv);
1474 	int (*parse_efuse) (struct rtl8xxxu_priv *priv);
1475 	int (*load_firmware) (struct rtl8xxxu_priv *priv);
1476 	int (*power_on) (struct rtl8xxxu_priv *priv);
1477 	void (*power_off) (struct rtl8xxxu_priv *priv);
1478 	void (*reset_8051) (struct rtl8xxxu_priv *priv);
1479 	int (*llt_init) (struct rtl8xxxu_priv *priv);
1480 	void (*init_phy_bb) (struct rtl8xxxu_priv *priv);
1481 	int (*init_phy_rf) (struct rtl8xxxu_priv *priv);
1482 	void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv);
1483 	void (*phy_lc_calibrate) (struct rtl8xxxu_priv *priv);
1484 	void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv);
1485 	void (*config_channel) (struct ieee80211_hw *hw);
1486 	int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb);
1487 	void (*init_aggregation) (struct rtl8xxxu_priv *priv);
1488 	void (*init_statistics) (struct rtl8xxxu_priv *priv);
1489 	void (*init_burst) (struct rtl8xxxu_priv *priv);
1490 	void (*enable_rf) (struct rtl8xxxu_priv *priv);
1491 	void (*disable_rf) (struct rtl8xxxu_priv *priv);
1492 	void (*usb_quirks) (struct rtl8xxxu_priv *priv);
1493 	void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel,
1494 			      bool ht40);
1495 	void (*update_rate_mask) (struct rtl8xxxu_priv *priv,
1496 				  u32 ramask, u8 rateid, int sgi, int txbw_40mhz);
1497 	void (*report_connect) (struct rtl8xxxu_priv *priv,
1498 				u8 macid, bool connect);
1499 	void (*fill_txdesc) (struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
1500 			     struct ieee80211_tx_info *tx_info,
1501 			     struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
1502 			     bool short_preamble, bool ampdu_enable,
1503 			     u32 rts_rate);
1504 	void (*set_crystal_cap) (struct rtl8xxxu_priv *priv, u8 crystal_cap);
1505 	s8 (*cck_rssi) (struct rtl8xxxu_priv *priv, u8 cck_agc_rpt);
1506 	int writeN_block_size;
1507 	int rx_agg_buf_size;
1508 	char tx_desc_size;
1509 	char rx_desc_size;
1510 	u8 has_s0s1:1;
1511 	u8 has_tx_report:1;
1512 	u8 gen2_thermal_meter:1;
1513 	u8 needs_full_init:1;
1514 	u32 adda_1t_init;
1515 	u32 adda_1t_path_on;
1516 	u32 adda_2t_path_on_a;
1517 	u32 adda_2t_path_on_b;
1518 	u16 trxff_boundary;
1519 	u8 pbp_rx;
1520 	u8 pbp_tx;
1521 	const struct rtl8xxxu_reg8val *mactable;
1522 	u8 total_page_num;
1523 	u8 page_num_hi;
1524 	u8 page_num_lo;
1525 	u8 page_num_norm;
1526 };
1527 
1528 extern int rtl8xxxu_debug;
1529 
1530 extern const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[];
1531 extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[];
1532 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr);
1533 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr);
1534 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr);
1535 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val);
1536 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val);
1537 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val);
1538 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1539 			enum rtl8xxxu_rfpath path, u8 reg);
1540 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1541 			 enum rtl8xxxu_rfpath path, u8 reg, u32 data);
1542 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
1543 			u32 *backup, int count);
1544 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
1545 			   u32 *backup, int count);
1546 void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv,
1547 			    const u32 *reg, u32 *backup);
1548 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
1549 			       const u32 *reg, u32 *backup);
1550 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
1551 			   bool path_a_on);
1552 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
1553 			      const u32 *regs, u32 *backup);
1554 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
1555 				int result[][8], int candidate, bool tx_only);
1556 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
1557 				int result[][8], int candidate, bool tx_only);
1558 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
1559 			 const struct rtl8xxxu_rfregval *table,
1560 			 enum rtl8xxxu_rfpath path);
1561 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
1562 			   const struct rtl8xxxu_reg32val *array);
1563 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name);
1564 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv);
1565 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv);
1566 void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor);
1567 void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor);
1568 void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv);
1569 int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv);
1570 int rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data);
1571 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv);
1572 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv);
1573 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start);
1574 void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv);
1575 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv);
1576 int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv,
1577 			  struct h2c_cmd *h2c, int len);
1578 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv);
1579 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv);
1580 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv);
1581 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv);
1582 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv);
1583 void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv,
1584 				int channel, bool ht40);
1585 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw);
1586 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw);
1587 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv);
1588 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv);
1589 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
1590 			       u32 ramask, u8 rateid, int sgi, int txbw_40mhz);
1591 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
1592 				    u32 ramask, u8 rateid, int sgi, int txbw_40mhz);
1593 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
1594 				  u8 macid, bool connect);
1595 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
1596 				  u8 macid, bool connect);
1597 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv);
1598 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv);
1599 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv);
1600 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv);
1601 void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv);
1602 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb);
1603 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb);
1604 int rtl8xxxu_gen2_channel_to_group(int channel);
1605 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
1606 				      int result[][8], int c1, int c2);
1607 void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
1608 			     struct ieee80211_tx_info *tx_info,
1609 			     struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
1610 			     bool short_preamble, bool ampdu_enable,
1611 			     u32 rts_rate);
1612 void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
1613 			     struct ieee80211_tx_info *tx_info,
1614 			     struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
1615 			     bool short_preamble, bool ampdu_enable,
1616 			     u32 rts_rate);
1617 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
1618 			   u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5);
1619 void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv);
1620 void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap);
1621 s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, u8 cck_agc_rpt);
1622 
1623 extern struct rtl8xxxu_fileops rtl8188fu_fops;
1624 extern struct rtl8xxxu_fileops rtl8192cu_fops;
1625 extern struct rtl8xxxu_fileops rtl8192eu_fops;
1626 extern struct rtl8xxxu_fileops rtl8723au_fops;
1627 extern struct rtl8xxxu_fileops rtl8723bu_fops;
1628