1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #include "../wifi.h" 5 #include "../efuse.h" 6 #include "../base.h" 7 #include "../cam.h" 8 #include "../ps.h" 9 #include "../usb.h" 10 #include "reg.h" 11 #include "def.h" 12 #include "phy.h" 13 #include "../rtl8192c/phy_common.h" 14 #include "mac.h" 15 #include "dm.h" 16 #include "../rtl8192c/dm_common.h" 17 #include "../rtl8192c/fw_common.h" 18 #include "hw.h" 19 #include "../rtl8192ce/hw.h" 20 #include "trx.h" 21 #include "led.h" 22 #include "table.h" 23 24 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw) 25 { 26 struct rtl_priv *rtlpriv = rtl_priv(hw); 27 struct rtl_phy *rtlphy = &(rtlpriv->phy); 28 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); 29 30 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH; 31 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY; 32 if (IS_HIGHT_PA(rtlefuse->board_type)) { 33 rtlphy->hwparam_tables[PHY_REG_PG].length = 34 RTL8192CUPHY_REG_ARRAY_PG_HPLENGTH; 35 rtlphy->hwparam_tables[PHY_REG_PG].pdata = 36 RTL8192CUPHY_REG_ARRAY_PG_HP; 37 } else { 38 rtlphy->hwparam_tables[PHY_REG_PG].length = 39 RTL8192CUPHY_REG_ARRAY_PGLENGTH; 40 rtlphy->hwparam_tables[PHY_REG_PG].pdata = 41 RTL8192CUPHY_REG_ARRAY_PG; 42 } 43 /* 2T */ 44 rtlphy->hwparam_tables[PHY_REG_2T].length = 45 RTL8192CUPHY_REG_2TARRAY_LENGTH; 46 rtlphy->hwparam_tables[PHY_REG_2T].pdata = 47 RTL8192CUPHY_REG_2TARRAY; 48 rtlphy->hwparam_tables[RADIOA_2T].length = 49 RTL8192CURADIOA_2TARRAYLENGTH; 50 rtlphy->hwparam_tables[RADIOA_2T].pdata = 51 RTL8192CURADIOA_2TARRAY; 52 rtlphy->hwparam_tables[RADIOB_2T].length = 53 RTL8192CURADIOB_2TARRAYLENGTH; 54 rtlphy->hwparam_tables[RADIOB_2T].pdata = 55 RTL8192CU_RADIOB_2TARRAY; 56 rtlphy->hwparam_tables[AGCTAB_2T].length = 57 RTL8192CUAGCTAB_2TARRAYLENGTH; 58 rtlphy->hwparam_tables[AGCTAB_2T].pdata = 59 RTL8192CUAGCTAB_2TARRAY; 60 /* 1T */ 61 if (IS_HIGHT_PA(rtlefuse->board_type)) { 62 rtlphy->hwparam_tables[PHY_REG_1T].length = 63 RTL8192CUPHY_REG_1T_HPARRAYLENGTH; 64 rtlphy->hwparam_tables[PHY_REG_1T].pdata = 65 RTL8192CUPHY_REG_1T_HPARRAY; 66 rtlphy->hwparam_tables[RADIOA_1T].length = 67 RTL8192CURADIOA_1T_HPARRAYLENGTH; 68 rtlphy->hwparam_tables[RADIOA_1T].pdata = 69 RTL8192CURADIOA_1T_HPARRAY; 70 rtlphy->hwparam_tables[RADIOB_1T].length = 71 RTL8192CURADIOB_1TARRAYLENGTH; 72 rtlphy->hwparam_tables[RADIOB_1T].pdata = 73 RTL8192CU_RADIOB_1TARRAY; 74 rtlphy->hwparam_tables[AGCTAB_1T].length = 75 RTL8192CUAGCTAB_1T_HPARRAYLENGTH; 76 rtlphy->hwparam_tables[AGCTAB_1T].pdata = 77 RTL8192CUAGCTAB_1T_HPARRAY; 78 } else { 79 rtlphy->hwparam_tables[PHY_REG_1T].length = 80 RTL8192CUPHY_REG_1TARRAY_LENGTH; 81 rtlphy->hwparam_tables[PHY_REG_1T].pdata = 82 RTL8192CUPHY_REG_1TARRAY; 83 rtlphy->hwparam_tables[RADIOA_1T].length = 84 RTL8192CURADIOA_1TARRAYLENGTH; 85 rtlphy->hwparam_tables[RADIOA_1T].pdata = 86 RTL8192CU_RADIOA_1TARRAY; 87 rtlphy->hwparam_tables[RADIOB_1T].length = 88 RTL8192CURADIOB_1TARRAYLENGTH; 89 rtlphy->hwparam_tables[RADIOB_1T].pdata = 90 RTL8192CU_RADIOB_1TARRAY; 91 rtlphy->hwparam_tables[AGCTAB_1T].length = 92 RTL8192CUAGCTAB_1TARRAYLENGTH; 93 rtlphy->hwparam_tables[AGCTAB_1T].pdata = 94 RTL8192CUAGCTAB_1TARRAY; 95 } 96 } 97 98 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 99 bool autoload_fail, 100 u8 *hwinfo) 101 { 102 struct rtl_priv *rtlpriv = rtl_priv(hw); 103 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 104 u8 rf_path, index, tempval; 105 u16 i; 106 107 for (rf_path = 0; rf_path < 2; rf_path++) { 108 for (i = 0; i < 3; i++) { 109 if (!autoload_fail) { 110 rtlefuse-> 111 eeprom_chnlarea_txpwr_cck[rf_path][i] = 112 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 113 rtlefuse-> 114 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 115 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + 116 i]; 117 } else { 118 rtlefuse-> 119 eeprom_chnlarea_txpwr_cck[rf_path][i] = 120 EEPROM_DEFAULT_TXPOWERLEVEL; 121 rtlefuse-> 122 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 123 EEPROM_DEFAULT_TXPOWERLEVEL; 124 } 125 } 126 } 127 for (i = 0; i < 3; i++) { 128 if (!autoload_fail) 129 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; 130 else 131 tempval = EEPROM_DEFAULT_HT40_2SDIFF; 132 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = 133 (tempval & 0xf); 134 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = 135 ((tempval & 0xf0) >> 4); 136 } 137 for (rf_path = 0; rf_path < 2; rf_path++) 138 for (i = 0; i < 3; i++) 139 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 140 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 141 rf_path, i, 142 rtlefuse-> 143 eeprom_chnlarea_txpwr_cck[rf_path][i]); 144 for (rf_path = 0; rf_path < 2; rf_path++) 145 for (i = 0; i < 3; i++) 146 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 147 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 148 rf_path, i, 149 rtlefuse-> 150 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]); 151 for (rf_path = 0; rf_path < 2; rf_path++) 152 for (i = 0; i < 3; i++) 153 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 154 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 155 rf_path, i, 156 rtlefuse-> 157 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]); 158 for (rf_path = 0; rf_path < 2; rf_path++) { 159 for (i = 0; i < 14; i++) { 160 index = rtl92c_get_chnl_group((u8)i); 161 rtlefuse->txpwrlevel_cck[rf_path][i] = 162 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index]; 163 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 164 rtlefuse-> 165 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index]; 166 if ((rtlefuse-> 167 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] - 168 rtlefuse-> 169 eprom_chnl_txpwr_ht40_2sdf[rf_path][index]) 170 > 0) { 171 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 172 rtlefuse-> 173 eeprom_chnlarea_txpwr_ht40_1s[rf_path] 174 [index] - rtlefuse-> 175 eprom_chnl_txpwr_ht40_2sdf[rf_path] 176 [index]; 177 } else { 178 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 179 } 180 } 181 for (i = 0; i < 14; i++) { 182 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 183 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i, 184 rtlefuse->txpwrlevel_cck[rf_path][i], 185 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 186 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 187 } 188 } 189 for (i = 0; i < 3; i++) { 190 if (!autoload_fail) { 191 rtlefuse->eeprom_pwrlimit_ht40[i] = 192 hwinfo[EEPROM_TXPWR_GROUP + i]; 193 rtlefuse->eeprom_pwrlimit_ht20[i] = 194 hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; 195 } else { 196 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; 197 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; 198 } 199 } 200 for (rf_path = 0; rf_path < 2; rf_path++) { 201 for (i = 0; i < 14; i++) { 202 index = rtl92c_get_chnl_group((u8)i); 203 if (rf_path == RF90_PATH_A) { 204 rtlefuse->pwrgroup_ht20[rf_path][i] = 205 (rtlefuse->eeprom_pwrlimit_ht20[index] 206 & 0xf); 207 rtlefuse->pwrgroup_ht40[rf_path][i] = 208 (rtlefuse->eeprom_pwrlimit_ht40[index] 209 & 0xf); 210 } else if (rf_path == RF90_PATH_B) { 211 rtlefuse->pwrgroup_ht20[rf_path][i] = 212 ((rtlefuse->eeprom_pwrlimit_ht20[index] 213 & 0xf0) >> 4); 214 rtlefuse->pwrgroup_ht40[rf_path][i] = 215 ((rtlefuse->eeprom_pwrlimit_ht40[index] 216 & 0xf0) >> 4); 217 } 218 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 219 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 220 rf_path, i, 221 rtlefuse->pwrgroup_ht20[rf_path][i]); 222 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 223 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 224 rf_path, i, 225 rtlefuse->pwrgroup_ht40[rf_path][i]); 226 } 227 } 228 for (i = 0; i < 14; i++) { 229 index = rtl92c_get_chnl_group((u8)i); 230 if (!autoload_fail) 231 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 232 else 233 tempval = EEPROM_DEFAULT_HT20_DIFF; 234 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 235 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 236 ((tempval >> 4) & 0xF); 237 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) 238 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; 239 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 240 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 241 index = rtl92c_get_chnl_group((u8)i); 242 if (!autoload_fail) 243 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 244 else 245 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 246 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); 247 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 248 ((tempval >> 4) & 0xF); 249 } 250 rtlefuse->legacy_ht_txpowerdiff = 251 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 252 for (i = 0; i < 14; i++) 253 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 254 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 255 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 256 for (i = 0; i < 14; i++) 257 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 258 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 259 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 260 for (i = 0; i < 14; i++) 261 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 262 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 263 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 264 for (i = 0; i < 14; i++) 265 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 266 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 267 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 268 if (!autoload_fail) 269 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 270 else 271 rtlefuse->eeprom_regulatory = 0; 272 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 273 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 274 if (!autoload_fail) { 275 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 276 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B]; 277 } else { 278 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 279 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; 280 } 281 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 282 "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 283 rtlefuse->eeprom_tssi[RF90_PATH_A], 284 rtlefuse->eeprom_tssi[RF90_PATH_B]); 285 if (!autoload_fail) 286 tempval = hwinfo[EEPROM_THERMAL_METER]; 287 else 288 tempval = EEPROM_DEFAULT_THERMALMETER; 289 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 290 if (rtlefuse->eeprom_thermalmeter < 0x06 || 291 rtlefuse->eeprom_thermalmeter > 0x1c) 292 rtlefuse->eeprom_thermalmeter = 0x12; 293 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 294 rtlefuse->apk_thermalmeterignore = true; 295 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 296 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 297 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 298 } 299 300 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents) 301 { 302 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 303 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 304 u8 boardtype; 305 306 if (IS_NORMAL_CHIP(rtlhal->version)) { 307 boardtype = ((contents[EEPROM_RF_OPT1]) & 308 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/ 309 } else { 310 boardtype = contents[EEPROM_RF_OPT4]; 311 boardtype &= BOARD_TYPE_TEST_MASK; 312 } 313 rtlefuse->board_type = boardtype; 314 if (IS_HIGHT_PA(rtlefuse->board_type)) 315 rtlefuse->external_pa = 1; 316 pr_info("Board Type %x\n", rtlefuse->board_type); 317 } 318 319 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw) 320 { 321 struct rtl_priv *rtlpriv = rtl_priv(hw); 322 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 323 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 324 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 325 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 326 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 327 0}; 328 u8 *hwinfo; 329 330 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 331 if (!hwinfo) 332 return; 333 334 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 335 goto exit; 336 337 _rtl92cu_read_txpower_info_from_hwpg(hw, 338 rtlefuse->autoload_failflag, hwinfo); 339 _rtl92cu_read_board_type(hw, hwinfo); 340 341 rtlefuse->txpwr_fromeprom = true; 342 if (rtlhal->oem_id == RT_CID_DEFAULT) { 343 switch (rtlefuse->eeprom_oemid) { 344 case EEPROM_CID_DEFAULT: 345 if (rtlefuse->eeprom_did == 0x8176) { 346 if ((rtlefuse->eeprom_svid == 0x103C && 347 rtlefuse->eeprom_smid == 0x1629)) 348 rtlhal->oem_id = RT_CID_819X_HP; 349 else 350 rtlhal->oem_id = RT_CID_DEFAULT; 351 } else { 352 rtlhal->oem_id = RT_CID_DEFAULT; 353 } 354 break; 355 case EEPROM_CID_TOSHIBA: 356 rtlhal->oem_id = RT_CID_TOSHIBA; 357 break; 358 case EEPROM_CID_QMI: 359 rtlhal->oem_id = RT_CID_819X_QMI; 360 break; 361 case EEPROM_CID_WHQL: 362 default: 363 rtlhal->oem_id = RT_CID_DEFAULT; 364 break; 365 } 366 } 367 exit: 368 kfree(hwinfo); 369 } 370 371 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw) 372 { 373 struct rtl_priv *rtlpriv = rtl_priv(hw); 374 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 375 376 switch (rtlhal->oem_id) { 377 case RT_CID_819X_HP: 378 rtlpriv->ledctl.led_opendrain = true; 379 break; 380 case RT_CID_819X_LENOVO: 381 case RT_CID_DEFAULT: 382 case RT_CID_TOSHIBA: 383 case RT_CID_CCX: 384 case RT_CID_819X_ACER: 385 case RT_CID_WHQL: 386 default: 387 break; 388 } 389 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n", 390 rtlhal->oem_id); 391 } 392 393 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw) 394 { 395 396 struct rtl_priv *rtlpriv = rtl_priv(hw); 397 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 398 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 399 u8 tmp_u1b; 400 401 if (!IS_NORMAL_CHIP(rtlhal->version)) 402 return; 403 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 404 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ? 405 EEPROM_93C46 : EEPROM_BOOT_EFUSE; 406 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n", 407 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE"); 408 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true; 409 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n", 410 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!"); 411 _rtl92cu_read_adapter_info(hw); 412 _rtl92cu_hal_customized_behavior(hw); 413 return; 414 } 415 416 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw) 417 { 418 struct rtl_priv *rtlpriv = rtl_priv(hw); 419 int status = 0; 420 u16 value16; 421 u8 value8; 422 /* polling autoload done. */ 423 u32 pollingcount = 0; 424 425 do { 426 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) { 427 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 428 "Autoload Done!\n"); 429 break; 430 } 431 if (pollingcount++ > 100) { 432 pr_err("Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n"); 433 return -ENODEV; 434 } 435 } while (true); 436 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */ 437 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 438 /* Power on when re-enter from IPS/Radio off/card disable */ 439 /* enable SPS into PWM mode */ 440 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 441 udelay(100); 442 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); 443 if (0 == (value8 & LDV12_EN)) { 444 value8 |= LDV12_EN; 445 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8); 446 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 447 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n", 448 value8); 449 udelay(100); 450 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL); 451 value8 &= ~ISO_MD2PP; 452 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8); 453 } 454 /* auto enable WLAN */ 455 pollingcount = 0; 456 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO); 457 value16 |= APFM_ONMAC; 458 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16); 459 do { 460 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) { 461 pr_info("MAC auto ON okay!\n"); 462 break; 463 } 464 if (pollingcount++ > 1000) { 465 pr_err("Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n"); 466 return -ENODEV; 467 } 468 } while (true); 469 /* Enable Radio ,GPIO ,and LED function */ 470 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812); 471 /* release RF digital isolation */ 472 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 473 value16 &= ~ISO_DIOR; 474 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16); 475 /* Reconsider when to do this operation after asking HWSD. */ 476 pollingcount = 0; 477 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv, 478 REG_APSD_CTRL) & ~BIT(6))); 479 do { 480 pollingcount++; 481 } while ((pollingcount < 200) && 482 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7))); 483 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ 484 value16 = rtl_read_word(rtlpriv, REG_CR); 485 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN | 486 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC); 487 rtl_write_word(rtlpriv, REG_CR, value16); 488 return status; 489 } 490 491 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw, 492 bool wmm_enable, 493 u8 out_ep_num, 494 u8 queue_sel) 495 { 496 struct rtl_priv *rtlpriv = rtl_priv(hw); 497 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 498 bool ischipn = IS_NORMAL_CHIP(rtlhal->version); 499 u32 outepnum = (u32)out_ep_num; 500 u32 numhq = 0; 501 u32 numlq = 0; 502 u32 numnq = 0; 503 u32 numpubq; 504 u32 value32; 505 u8 value8; 506 u32 txqpagenum, txqpageunit, txqremaininpage; 507 508 if (!wmm_enable) { 509 numpubq = (ischipn) ? CHIP_B_PAGE_NUM_PUBQ : 510 CHIP_A_PAGE_NUM_PUBQ; 511 txqpagenum = TX_TOTAL_PAGE_NUMBER - numpubq; 512 513 txqpageunit = txqpagenum / outepnum; 514 txqremaininpage = txqpagenum % outepnum; 515 if (queue_sel & TX_SELE_HQ) 516 numhq = txqpageunit; 517 if (queue_sel & TX_SELE_LQ) 518 numlq = txqpageunit; 519 /* HIGH priority queue always present in the configuration of 520 * 2 out-ep. Remainder pages have assigned to High queue */ 521 if (outepnum > 1 && txqremaininpage) 522 numhq += txqremaininpage; 523 /* NOTE: This step done before writting REG_RQPN. */ 524 if (ischipn) { 525 if (queue_sel & TX_SELE_NQ) 526 numnq = txqpageunit; 527 value8 = (u8)_NPQ(numnq); 528 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 529 } 530 } else { 531 /* for WMM ,number of out-ep must more than or equal to 2! */ 532 numpubq = ischipn ? WMM_CHIP_B_PAGE_NUM_PUBQ : 533 WMM_CHIP_A_PAGE_NUM_PUBQ; 534 if (queue_sel & TX_SELE_HQ) { 535 numhq = ischipn ? WMM_CHIP_B_PAGE_NUM_HPQ : 536 WMM_CHIP_A_PAGE_NUM_HPQ; 537 } 538 if (queue_sel & TX_SELE_LQ) { 539 numlq = ischipn ? WMM_CHIP_B_PAGE_NUM_LPQ : 540 WMM_CHIP_A_PAGE_NUM_LPQ; 541 } 542 /* NOTE: This step done before writting REG_RQPN. */ 543 if (ischipn) { 544 if (queue_sel & TX_SELE_NQ) 545 numnq = WMM_CHIP_B_PAGE_NUM_NPQ; 546 value8 = (u8)_NPQ(numnq); 547 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 548 } 549 } 550 /* TX DMA */ 551 value32 = _HPQ(numhq) | _LPQ(numlq) | _PUBQ(numpubq) | LD_RQPN; 552 rtl_write_dword(rtlpriv, REG_RQPN, value32); 553 } 554 555 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable) 556 { 557 struct rtl_priv *rtlpriv = rtl_priv(hw); 558 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 559 u8 txpktbuf_bndy; 560 u8 value8; 561 562 if (!wmm_enable) 563 txpktbuf_bndy = TX_PAGE_BOUNDARY; 564 else /* for WMM */ 565 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version)) 566 ? WMM_CHIP_B_TX_PAGE_BOUNDARY 567 : WMM_CHIP_A_TX_PAGE_BOUNDARY; 568 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 569 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 570 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); 571 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); 572 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy); 573 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); 574 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128); 575 rtl_write_byte(rtlpriv, REG_PBP, value8); 576 } 577 578 static void _rtl92c_init_chipn_reg_priority(struct ieee80211_hw *hw, u16 beq, 579 u16 bkq, u16 viq, u16 voq, 580 u16 mgtq, u16 hiq) 581 { 582 struct rtl_priv *rtlpriv = rtl_priv(hw); 583 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7); 584 585 value16 |= _TXDMA_BEQ_MAP(beq) | _TXDMA_BKQ_MAP(bkq) | 586 _TXDMA_VIQ_MAP(viq) | _TXDMA_VOQ_MAP(voq) | 587 _TXDMA_MGQ_MAP(mgtq) | _TXDMA_HIQ_MAP(hiq); 588 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16); 589 } 590 591 static void _rtl92cu_init_chipn_one_out_ep_priority(struct ieee80211_hw *hw, 592 bool wmm_enable, 593 u8 queue_sel) 594 { 595 u16 uninitialized_var(value); 596 597 switch (queue_sel) { 598 case TX_SELE_HQ: 599 value = QUEUE_HIGH; 600 break; 601 case TX_SELE_LQ: 602 value = QUEUE_LOW; 603 break; 604 case TX_SELE_NQ: 605 value = QUEUE_NORMAL; 606 break; 607 default: 608 WARN_ON(1); /* Shall not reach here! */ 609 break; 610 } 611 _rtl92c_init_chipn_reg_priority(hw, value, value, value, value, 612 value, value); 613 pr_info("Tx queue select: 0x%02x\n", queue_sel); 614 } 615 616 static void _rtl92cu_init_chipn_two_out_ep_priority(struct ieee80211_hw *hw, 617 bool wmm_enable, 618 u8 queue_sel) 619 { 620 u16 beq, bkq, viq, voq, mgtq, hiq; 621 u16 uninitialized_var(valuehi); 622 u16 uninitialized_var(valuelow); 623 624 switch (queue_sel) { 625 case (TX_SELE_HQ | TX_SELE_LQ): 626 valuehi = QUEUE_HIGH; 627 valuelow = QUEUE_LOW; 628 break; 629 case (TX_SELE_NQ | TX_SELE_LQ): 630 valuehi = QUEUE_NORMAL; 631 valuelow = QUEUE_LOW; 632 break; 633 case (TX_SELE_HQ | TX_SELE_NQ): 634 valuehi = QUEUE_HIGH; 635 valuelow = QUEUE_NORMAL; 636 break; 637 default: 638 WARN_ON(1); 639 break; 640 } 641 if (!wmm_enable) { 642 beq = valuelow; 643 bkq = valuelow; 644 viq = valuehi; 645 voq = valuehi; 646 mgtq = valuehi; 647 hiq = valuehi; 648 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */ 649 beq = valuehi; 650 bkq = valuelow; 651 viq = valuelow; 652 voq = valuehi; 653 mgtq = valuehi; 654 hiq = valuehi; 655 } 656 _rtl92c_init_chipn_reg_priority(hw, beq, bkq, viq, voq, mgtq, hiq); 657 pr_info("Tx queue select: 0x%02x\n", queue_sel); 658 } 659 660 static void _rtl92cu_init_chipn_three_out_ep_priority(struct ieee80211_hw *hw, 661 bool wmm_enable, 662 u8 queue_sel) 663 { 664 u16 beq, bkq, viq, voq, mgtq, hiq; 665 666 if (!wmm_enable) { /* typical setting */ 667 beq = QUEUE_LOW; 668 bkq = QUEUE_LOW; 669 viq = QUEUE_NORMAL; 670 voq = QUEUE_HIGH; 671 mgtq = QUEUE_HIGH; 672 hiq = QUEUE_HIGH; 673 } else { /* for WMM */ 674 beq = QUEUE_LOW; 675 bkq = QUEUE_NORMAL; 676 viq = QUEUE_NORMAL; 677 voq = QUEUE_HIGH; 678 mgtq = QUEUE_HIGH; 679 hiq = QUEUE_HIGH; 680 } 681 _rtl92c_init_chipn_reg_priority(hw, beq, bkq, viq, voq, mgtq, hiq); 682 pr_info("Tx queue select :0x%02x..\n", queue_sel); 683 } 684 685 static void _rtl92cu_init_chipn_queue_priority(struct ieee80211_hw *hw, 686 bool wmm_enable, 687 u8 out_ep_num, 688 u8 queue_sel) 689 { 690 switch (out_ep_num) { 691 case 1: 692 _rtl92cu_init_chipn_one_out_ep_priority(hw, wmm_enable, 693 queue_sel); 694 break; 695 case 2: 696 _rtl92cu_init_chipn_two_out_ep_priority(hw, wmm_enable, 697 queue_sel); 698 break; 699 case 3: 700 _rtl92cu_init_chipn_three_out_ep_priority(hw, wmm_enable, 701 queue_sel); 702 break; 703 default: 704 WARN_ON(1); /* Shall not reach here! */ 705 break; 706 } 707 } 708 709 static void _rtl92cu_init_chipt_queue_priority(struct ieee80211_hw *hw, 710 bool wmm_enable, 711 u8 out_ep_num, 712 u8 queue_sel) 713 { 714 u8 hq_sele = 0; 715 struct rtl_priv *rtlpriv = rtl_priv(hw); 716 717 switch (out_ep_num) { 718 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */ 719 if (!wmm_enable) /* typical setting */ 720 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ | 721 HQSEL_HIQ; 722 else /* for WMM */ 723 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ | 724 HQSEL_HIQ; 725 break; 726 case 1: 727 if (TX_SELE_LQ == queue_sel) { 728 /* map all endpoint to Low queue */ 729 hq_sele = 0; 730 } else if (TX_SELE_HQ == queue_sel) { 731 /* map all endpoint to High queue */ 732 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ | 733 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ; 734 } 735 break; 736 default: 737 WARN_ON(1); /* Shall not reach here! */ 738 break; 739 } 740 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele); 741 pr_info("Tx queue select :0x%02x..\n", hq_sele); 742 } 743 744 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw, 745 bool wmm_enable, 746 u8 out_ep_num, 747 u8 queue_sel) 748 { 749 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 750 751 if (IS_NORMAL_CHIP(rtlhal->version)) 752 _rtl92cu_init_chipn_queue_priority(hw, wmm_enable, out_ep_num, 753 queue_sel); 754 else 755 _rtl92cu_init_chipt_queue_priority(hw, wmm_enable, out_ep_num, 756 queue_sel); 757 } 758 759 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw) 760 { 761 u16 value16; 762 u32 value32; 763 struct rtl_priv *rtlpriv = rtl_priv(hw); 764 765 value32 = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS | 766 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | 767 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32); 768 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&value32)); 769 /* Accept all multicast address */ 770 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF); 771 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF); 772 /* Accept all management frames */ 773 value16 = 0xFFFF; 774 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MGT_FILTER, 775 (u8 *)(&value16)); 776 /* Reject all control frame - default value is 0 */ 777 value16 = 0x0; 778 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CTRL_FILTER, 779 (u8 *)(&value16)); 780 /* Accept all data frames */ 781 value16 = 0xFFFF; 782 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DATA_FILTER, 783 (u8 *)(&value16)); 784 } 785 786 static void _rtl92cu_init_beacon_parameters(struct ieee80211_hw *hw) 787 { 788 struct rtl_priv *rtlpriv = rtl_priv(hw); 789 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 790 791 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010); 792 793 /* TODO: Remove these magic number */ 794 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404); 795 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME); 796 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); 797 /* Change beacon AIFS to the largest number 798 * beacause test chip does not contension before sending beacon. 799 */ 800 if (IS_NORMAL_CHIP(rtlhal->version)) 801 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F); 802 else 803 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF); 804 } 805 806 static int _rtl92cu_init_mac(struct ieee80211_hw *hw) 807 { 808 struct rtl_priv *rtlpriv = rtl_priv(hw); 809 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 810 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); 811 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv); 812 int err = 0; 813 u32 boundary = 0; 814 u8 wmm_enable = false; /* TODO */ 815 u8 out_ep_nums = rtlusb->out_ep_nums; 816 u8 queue_sel = rtlusb->out_queue_sel; 817 818 err = _rtl92cu_init_power_on(hw); 819 820 if (err) { 821 pr_err("Failed to init power on!\n"); 822 return err; 823 } 824 if (!wmm_enable) { 825 boundary = TX_PAGE_BOUNDARY; 826 } else { /* for WMM */ 827 boundary = (IS_NORMAL_CHIP(rtlhal->version)) 828 ? WMM_CHIP_B_TX_PAGE_BOUNDARY 829 : WMM_CHIP_A_TX_PAGE_BOUNDARY; 830 } 831 if (false == rtl92c_init_llt_table(hw, boundary)) { 832 pr_err("Failed to init LLT Table!\n"); 833 return -EINVAL; 834 } 835 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums, 836 queue_sel); 837 _rtl92c_init_trx_buffer(hw, wmm_enable); 838 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums, 839 queue_sel); 840 /* Get Rx PHY status in order to report RSSI and others. */ 841 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE); 842 rtl92c_init_interrupt(hw); 843 rtl92c_init_network_type(hw); 844 _rtl92cu_init_wmac_setting(hw); 845 rtl92c_init_adaptive_ctrl(hw); 846 rtl92c_init_edca(hw); 847 rtl92c_init_rate_fallback(hw); 848 rtl92c_init_retry_function(hw); 849 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20); 850 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version)); 851 _rtl92cu_init_beacon_parameters(hw); 852 rtl92c_init_ampdu_aggregation(hw); 853 rtl92c_init_beacon_max_error(hw); 854 return err; 855 } 856 857 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw) 858 { 859 struct rtl_priv *rtlpriv = rtl_priv(hw); 860 u8 sec_reg_value = 0x0; 861 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 862 863 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 864 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 865 rtlpriv->sec.pairwise_enc_algorithm, 866 rtlpriv->sec.group_enc_algorithm); 867 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 868 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 869 "not open sw encryption\n"); 870 return; 871 } 872 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 873 if (rtlpriv->sec.use_defaultkey) { 874 sec_reg_value |= SCR_TXUSEDK; 875 sec_reg_value |= SCR_RXUSEDK; 876 } 877 if (IS_NORMAL_CHIP(rtlhal->version)) 878 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 879 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 880 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n", 881 sec_reg_value); 882 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 883 } 884 885 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw) 886 { 887 struct rtl_priv *rtlpriv = rtl_priv(hw); 888 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 889 890 /* To Fix MAC loopback mode fail. */ 891 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f); 892 rtl_write_byte(rtlpriv, 0x15, 0xe9); 893 /* HW SEQ CTRL */ 894 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ 895 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 896 /* fixed USB interface interference issue */ 897 rtl_write_byte(rtlpriv, 0xfe40, 0xe0); 898 rtl_write_byte(rtlpriv, 0xfe41, 0x8d); 899 rtl_write_byte(rtlpriv, 0xfe42, 0x80); 900 rtlusb->reg_bcn_ctrl_val = 0x18; 901 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); 902 } 903 904 static void _initpabias(struct ieee80211_hw *hw) 905 { 906 struct rtl_priv *rtlpriv = rtl_priv(hw); 907 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 908 u8 pa_setting; 909 910 /* FIXED PA current issue */ 911 pa_setting = efuse_read_1byte(hw, 0x1FA); 912 if (!(pa_setting & BIT(0))) { 913 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406); 914 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406); 915 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406); 916 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406); 917 } 918 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) && 919 IS_92C_SERIAL(rtlhal->version)) { 920 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406); 921 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406); 922 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406); 923 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406); 924 } 925 if (!(pa_setting & BIT(4))) { 926 pa_setting = rtl_read_byte(rtlpriv, 0x16); 927 pa_setting &= 0x0F; 928 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90); 929 } 930 } 931 932 int rtl92cu_hw_init(struct ieee80211_hw *hw) 933 { 934 struct rtl_priv *rtlpriv = rtl_priv(hw); 935 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 936 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 937 struct rtl_phy *rtlphy = &(rtlpriv->phy); 938 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 939 int err = 0; 940 unsigned long flags; 941 942 /* As this function can take a very long time (up to 350 ms) 943 * and can be called with irqs disabled, reenable the irqs 944 * to let the other devices continue being serviced. 945 * 946 * It is safe doing so since our own interrupts will only be enabled 947 * in a subsequent step. 948 */ 949 local_save_flags(flags); 950 local_irq_enable(); 951 952 rtlhal->fw_ready = false; 953 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU; 954 err = _rtl92cu_init_mac(hw); 955 if (err) { 956 pr_err("init mac failed!\n"); 957 goto exit; 958 } 959 err = rtl92c_download_fw(hw); 960 if (err) { 961 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 962 "Failed to download FW. Init HW without FW now..\n"); 963 err = 1; 964 goto exit; 965 } 966 967 rtlhal->fw_ready = true; 968 rtlhal->last_hmeboxnum = 0; /* h2c */ 969 _rtl92cu_phy_param_tab_init(hw); 970 rtl92cu_phy_mac_config(hw); 971 rtl92cu_phy_bb_config(hw); 972 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 973 rtl92c_phy_rf_config(hw); 974 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && 975 !IS_92C_SERIAL(rtlhal->version)) { 976 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 977 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 978 } 979 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 980 RF_CHNLBW, RFREG_OFFSET_MASK); 981 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 982 RF_CHNLBW, RFREG_OFFSET_MASK); 983 rtl92cu_bb_block_on(hw); 984 rtl_cam_reset_all_entry(hw); 985 rtl92cu_enable_hw_security_config(hw); 986 ppsc->rfpwr_state = ERFON; 987 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 988 if (ppsc->rfpwr_state == ERFON) { 989 rtl92c_phy_set_rfpath_switch(hw, 1); 990 if (rtlphy->iqk_initialized) { 991 rtl92c_phy_iq_calibrate(hw, true); 992 } else { 993 rtl92c_phy_iq_calibrate(hw, false); 994 rtlphy->iqk_initialized = true; 995 } 996 rtl92c_dm_check_txpower_tracking(hw); 997 rtl92c_phy_lc_calibrate(hw); 998 } 999 _rtl92cu_hw_configure(hw); 1000 _initpabias(hw); 1001 rtl92c_dm_init(hw); 1002 exit: 1003 local_irq_restore(flags); 1004 return err; 1005 } 1006 1007 static void disable_rfafeandresetbb(struct ieee80211_hw *hw) 1008 { 1009 struct rtl_priv *rtlpriv = rtl_priv(hw); 1010 /************************************** 1011 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue 1012 b. RF path 0 offset 0x00 = 0x00 disable RF 1013 c. APSD_CTRL 0x600[7:0] = 0x40 1014 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine 1015 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine 1016 ***************************************/ 1017 u8 erfpath = 0, value8 = 0; 1018 1019 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1020 rtl_set_rfreg(hw, (enum radio_path)erfpath, 0x0, MASKBYTE0, 0x0); 1021 1022 value8 |= APSDOFF; 1023 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/ 1024 value8 = 0; 1025 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTN); 1026 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/ 1027 value8 &= (~FEN_BB_GLB_RSTN); 1028 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/ 1029 } 1030 1031 static void _resetdigitalprocedure1(struct ieee80211_hw *hw, bool withouthwsm) 1032 { 1033 struct rtl_priv *rtlpriv = rtl_priv(hw); 1034 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1035 1036 if (rtlhal->fw_version <= 0x20) { 1037 /***************************** 1038 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status 1039 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset) 1040 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE 1041 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable) 1042 ******************************/ 1043 u16 valu16 = 0; 1044 1045 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1046 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1047 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 & 1048 (~FEN_CPUEN))); /* reset MCU ,8051 */ 1049 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF; 1050 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 | 1051 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */ 1052 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1053 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 | 1054 FEN_CPUEN)); /* enable MCU ,8051 */ 1055 } else { 1056 u8 retry_cnts = 0; 1057 1058 /* IF fw in RAM code, do reset */ 1059 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) { 1060 /* reset MCU ready status */ 1061 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1062 /* 8051 reset by self */ 1063 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20); 1064 while ((retry_cnts++ < 100) && 1065 (FEN_CPUEN & rtl_read_word(rtlpriv, 1066 REG_SYS_FUNC_EN))) { 1067 udelay(50); 1068 } 1069 if (retry_cnts >= 100) { 1070 pr_err("8051 reset failed!.........................\n"); 1071 /* if 8051 reset fail, reset MAC. */ 1072 rtl_write_byte(rtlpriv, 1073 REG_SYS_FUNC_EN + 1, 1074 0x50); 1075 udelay(100); 1076 } 1077 } 1078 /* Reset MAC and Enable 8051 */ 1079 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54); 1080 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1081 } 1082 if (withouthwsm) { 1083 /***************************** 1084 Without HW auto state machine 1085 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock 1086 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL 1087 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK 1088 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON 1089 ******************************/ 1090 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); 1091 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); 1092 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F); 1093 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9); 1094 } 1095 } 1096 1097 static void _resetdigitalprocedure2(struct ieee80211_hw *hw) 1098 { 1099 struct rtl_priv *rtlpriv = rtl_priv(hw); 1100 /***************************** 1101 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction 1102 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock 1103 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON 1104 ******************************/ 1105 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); 1106 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82); 1107 } 1108 1109 static void _disablegpio(struct ieee80211_hw *hw) 1110 { 1111 struct rtl_priv *rtlpriv = rtl_priv(hw); 1112 /*************************************** 1113 j. GPIO_PIN_CTRL 0x44[31:0]=0x000 1114 k. Value = GPIO_PIN_CTRL[7:0] 1115 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level 1116 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780 1117 n. LEDCFG 0x4C[15:0] = 0x8080 1118 ***************************************/ 1119 u8 value8; 1120 u16 value16; 1121 u32 value32; 1122 1123 /* 1. Disable GPIO[7:0] */ 1124 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000); 1125 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF; 1126 value8 = (u8)(value32&0x000000FF); 1127 value32 |= ((value8<<8) | 0x00FF0000); 1128 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32); 1129 /* 2. Disable GPIO[10:8] */ 1130 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00); 1131 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F; 1132 value8 = (u8)(value16&0x000F); 1133 value16 |= ((value8<<4) | 0x0780); 1134 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16); 1135 /* 3. Disable LED0 & 1 */ 1136 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); 1137 } 1138 1139 static void disable_analog(struct ieee80211_hw *hw, bool withouthwsm) 1140 { 1141 struct rtl_priv *rtlpriv = rtl_priv(hw); 1142 u16 value16 = 0; 1143 u8 value8 = 0; 1144 1145 if (withouthwsm) { 1146 /***************************** 1147 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power 1148 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power 1149 r. When driver call disable, the ASIC will turn off remaining 1150 clock automatically 1151 ******************************/ 1152 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); 1153 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); 1154 value8 &= (~LDV12_EN); 1155 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8); 1156 } 1157 1158 /***************************** 1159 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode 1160 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend 1161 ******************************/ 1162 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); 1163 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN); 1164 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16); 1165 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E); 1166 } 1167 1168 static void carddisable_hwsm(struct ieee80211_hw *hw) 1169 { 1170 /* ==== RF Off Sequence ==== */ 1171 disable_rfafeandresetbb(hw); 1172 /* ==== Reset digital sequence ====== */ 1173 _resetdigitalprocedure1(hw, false); 1174 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1175 _disablegpio(hw); 1176 /* ==== Disable analog sequence === */ 1177 disable_analog(hw, false); 1178 } 1179 1180 static void carddisablewithout_hwsm(struct ieee80211_hw *hw) 1181 { 1182 /*==== RF Off Sequence ==== */ 1183 disable_rfafeandresetbb(hw); 1184 /* ==== Reset digital sequence ====== */ 1185 _resetdigitalprocedure1(hw, true); 1186 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1187 _disablegpio(hw); 1188 /* ==== Reset digital sequence ====== */ 1189 _resetdigitalprocedure2(hw); 1190 /* ==== Disable analog sequence === */ 1191 disable_analog(hw, true); 1192 } 1193 1194 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 1195 u8 set_bits, u8 clear_bits) 1196 { 1197 struct rtl_priv *rtlpriv = rtl_priv(hw); 1198 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 1199 1200 rtlusb->reg_bcn_ctrl_val |= set_bits; 1201 rtlusb->reg_bcn_ctrl_val &= ~clear_bits; 1202 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); 1203 } 1204 1205 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw) 1206 { 1207 struct rtl_priv *rtlpriv = rtl_priv(hw); 1208 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1209 u8 tmp1byte = 0; 1210 1211 if (IS_NORMAL_CHIP(rtlhal->version)) { 1212 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 1213 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1214 tmp1byte & (~BIT(6))); 1215 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 1216 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 1217 tmp1byte &= ~(BIT(0)); 1218 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 1219 } else { 1220 rtl_write_byte(rtlpriv, REG_TXPAUSE, 1221 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6)); 1222 } 1223 } 1224 1225 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw) 1226 { 1227 struct rtl_priv *rtlpriv = rtl_priv(hw); 1228 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1229 u8 tmp1byte = 0; 1230 1231 if (IS_NORMAL_CHIP(rtlhal->version)) { 1232 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 1233 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1234 tmp1byte | BIT(6)); 1235 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 1236 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 1237 tmp1byte |= BIT(0); 1238 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 1239 } else { 1240 rtl_write_byte(rtlpriv, REG_TXPAUSE, 1241 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6))); 1242 } 1243 } 1244 1245 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw) 1246 { 1247 struct rtl_priv *rtlpriv = rtl_priv(hw); 1248 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1249 1250 if (IS_NORMAL_CHIP(rtlhal->version)) 1251 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1)); 1252 else 1253 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1254 } 1255 1256 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw) 1257 { 1258 struct rtl_priv *rtlpriv = rtl_priv(hw); 1259 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1260 1261 if (IS_NORMAL_CHIP(rtlhal->version)) 1262 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0); 1263 else 1264 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); 1265 } 1266 1267 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw, 1268 enum nl80211_iftype type) 1269 { 1270 struct rtl_priv *rtlpriv = rtl_priv(hw); 1271 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1272 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1273 1274 bt_msr &= 0xfc; 1275 if (type == NL80211_IFTYPE_UNSPECIFIED || type == 1276 NL80211_IFTYPE_STATION) { 1277 _rtl92cu_stop_tx_beacon(hw); 1278 _rtl92cu_enable_bcn_sub_func(hw); 1279 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) { 1280 _rtl92cu_resume_tx_beacon(hw); 1281 _rtl92cu_disable_bcn_sub_func(hw); 1282 } else { 1283 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1284 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n", 1285 type); 1286 } 1287 switch (type) { 1288 case NL80211_IFTYPE_UNSPECIFIED: 1289 bt_msr |= MSR_NOLINK; 1290 ledaction = LED_CTL_LINK; 1291 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1292 "Set Network type to NO LINK!\n"); 1293 break; 1294 case NL80211_IFTYPE_ADHOC: 1295 bt_msr |= MSR_ADHOC; 1296 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1297 "Set Network type to Ad Hoc!\n"); 1298 break; 1299 case NL80211_IFTYPE_STATION: 1300 bt_msr |= MSR_INFRA; 1301 ledaction = LED_CTL_LINK; 1302 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1303 "Set Network type to STA!\n"); 1304 break; 1305 case NL80211_IFTYPE_AP: 1306 bt_msr |= MSR_AP; 1307 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1308 "Set Network type to AP!\n"); 1309 break; 1310 default: 1311 pr_err("Network type %d not supported!\n", type); 1312 goto error_out; 1313 } 1314 rtl_write_byte(rtlpriv, MSR, bt_msr); 1315 rtlpriv->cfg->ops->led_control(hw, ledaction); 1316 if ((bt_msr & MSR_MASK) == MSR_AP) 1317 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1318 else 1319 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1320 return 0; 1321 error_out: 1322 return 1; 1323 } 1324 1325 void rtl92cu_card_disable(struct ieee80211_hw *hw) 1326 { 1327 struct rtl_priv *rtlpriv = rtl_priv(hw); 1328 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1329 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 1330 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1331 enum nl80211_iftype opmode; 1332 1333 mac->link_state = MAC80211_NOLINK; 1334 opmode = NL80211_IFTYPE_UNSPECIFIED; 1335 _rtl92cu_set_media_status(hw, opmode); 1336 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1337 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1338 if (rtlusb->disablehwsm) 1339 carddisable_hwsm(hw); 1340 else 1341 carddisablewithout_hwsm(hw); 1342 1343 /* after power off we should do iqk again */ 1344 rtlpriv->phy.iqk_initialized = false; 1345 } 1346 1347 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1348 { 1349 struct rtl_priv *rtlpriv = rtl_priv(hw); 1350 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1351 u32 reg_rcr; 1352 1353 if (rtlpriv->psc.rfpwr_state != ERFON) 1354 return; 1355 1356 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1357 1358 if (check_bssid) { 1359 u8 tmp; 1360 1361 if (IS_NORMAL_CHIP(rtlhal->version)) { 1362 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1363 tmp = BIT(4); 1364 } else { 1365 reg_rcr |= RCR_CBSSID; 1366 tmp = BIT(4) | BIT(5); 1367 } 1368 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1369 (u8 *) (®_rcr)); 1370 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp); 1371 } else { 1372 u8 tmp; 1373 1374 if (IS_NORMAL_CHIP(rtlhal->version)) { 1375 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1376 tmp = BIT(4); 1377 } else { 1378 reg_rcr &= ~RCR_CBSSID; 1379 tmp = BIT(4) | BIT(5); 1380 } 1381 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1382 rtlpriv->cfg->ops->set_hw_reg(hw, 1383 HW_VAR_RCR, (u8 *) (®_rcr)); 1384 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0); 1385 } 1386 } 1387 1388 /*========================================================================== */ 1389 1390 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1391 { 1392 struct rtl_priv *rtlpriv = rtl_priv(hw); 1393 1394 if (_rtl92cu_set_media_status(hw, type)) 1395 return -EOPNOTSUPP; 1396 1397 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1398 if (type != NL80211_IFTYPE_AP) 1399 rtl92cu_set_check_bssid(hw, true); 1400 } else { 1401 rtl92cu_set_check_bssid(hw, false); 1402 } 1403 1404 return 0; 1405 } 1406 1407 static void _beacon_function_enable(struct ieee80211_hw *hw) 1408 { 1409 struct rtl_priv *rtlpriv = rtl_priv(hw); 1410 1411 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00); 1412 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F); 1413 } 1414 1415 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw) 1416 { 1417 1418 struct rtl_priv *rtlpriv = rtl_priv(hw); 1419 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1420 u16 bcn_interval, atim_window; 1421 u32 value32; 1422 1423 bcn_interval = mac->beacon_interval; 1424 atim_window = 2; /*FIX MERGE */ 1425 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1426 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1427 _rtl92cu_init_beacon_parameters(hw); 1428 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 1429 /* 1430 * Force beacon frame transmission even after receiving beacon frame 1431 * from other ad hoc STA 1432 * 1433 * 1434 * Reset TSF Timer to zero, added by Roger. 2008.06.24 1435 */ 1436 value32 = rtl_read_dword(rtlpriv, REG_TCR); 1437 value32 &= ~TSFRST; 1438 rtl_write_dword(rtlpriv, REG_TCR, value32); 1439 value32 |= TSFRST; 1440 rtl_write_dword(rtlpriv, REG_TCR, value32); 1441 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD, 1442 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n", 1443 value32); 1444 /* TODO: Modify later (Find the right parameters) 1445 * NOTE: Fix test chip's bug (about contention windows's randomness) */ 1446 if ((mac->opmode == NL80211_IFTYPE_ADHOC) || 1447 (mac->opmode == NL80211_IFTYPE_MESH_POINT) || 1448 (mac->opmode == NL80211_IFTYPE_AP)) { 1449 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50); 1450 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50); 1451 } 1452 _beacon_function_enable(hw); 1453 } 1454 1455 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw) 1456 { 1457 struct rtl_priv *rtlpriv = rtl_priv(hw); 1458 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1459 u16 bcn_interval = mac->beacon_interval; 1460 1461 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n", 1462 bcn_interval); 1463 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1464 } 1465 1466 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw, 1467 u32 add_msr, u32 rm_msr) 1468 { 1469 } 1470 1471 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 1472 { 1473 struct rtl_priv *rtlpriv = rtl_priv(hw); 1474 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1475 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1476 1477 switch (variable) { 1478 case HW_VAR_RCR: 1479 *((u32 *)(val)) = mac->rx_conf; 1480 break; 1481 case HW_VAR_RF_STATE: 1482 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 1483 break; 1484 case HW_VAR_FWLPS_RF_ON:{ 1485 enum rf_pwrstate rfstate; 1486 u32 val_rcr; 1487 1488 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, 1489 (u8 *)(&rfstate)); 1490 if (rfstate == ERFOFF) { 1491 *((bool *) (val)) = true; 1492 } else { 1493 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 1494 val_rcr &= 0x00070000; 1495 if (val_rcr) 1496 *((bool *) (val)) = false; 1497 else 1498 *((bool *) (val)) = true; 1499 } 1500 break; 1501 } 1502 case HW_VAR_FW_PSMODE_STATUS: 1503 *((bool *) (val)) = ppsc->fw_current_inpsmode; 1504 break; 1505 case HW_VAR_CORRECT_TSF:{ 1506 u64 tsf; 1507 u32 *ptsf_low = (u32 *)&tsf; 1508 u32 *ptsf_high = ((u32 *)&tsf) + 1; 1509 1510 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 1511 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 1512 *((u64 *)(val)) = tsf; 1513 break; 1514 } 1515 case HW_VAR_MGT_FILTER: 1516 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0); 1517 break; 1518 case HW_VAR_CTRL_FILTER: 1519 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1); 1520 break; 1521 case HW_VAR_DATA_FILTER: 1522 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2); 1523 break; 1524 case HAL_DEF_WOWLAN: 1525 break; 1526 default: 1527 pr_err("switch case %#x not processed\n", variable); 1528 break; 1529 } 1530 } 1531 1532 static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb) 1533 { 1534 /* Currently nothing happens here. 1535 * Traffic stops after some seconds in WPA2 802.11n mode. 1536 * Maybe because rtl8192cu chip should be set from here? 1537 * If I understand correctly, the realtek vendor driver sends some urbs 1538 * if its "here". 1539 * 1540 * This is maybe necessary: 1541 * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, 1, 1, skb); 1542 */ 1543 return true; 1544 } 1545 1546 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 1547 { 1548 struct rtl_priv *rtlpriv = rtl_priv(hw); 1549 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1550 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1551 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1552 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1553 enum wireless_mode wirelessmode = mac->mode; 1554 u8 idx = 0; 1555 1556 switch (variable) { 1557 case HW_VAR_ETHER_ADDR:{ 1558 for (idx = 0; idx < ETH_ALEN; idx++) { 1559 rtl_write_byte(rtlpriv, (REG_MACID + idx), 1560 val[idx]); 1561 } 1562 break; 1563 } 1564 case HW_VAR_BASIC_RATE:{ 1565 u16 rate_cfg = ((u16 *) val)[0]; 1566 u8 rate_index = 0; 1567 1568 rate_cfg &= 0x15f; 1569 /* TODO */ 1570 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO 1571 * && ((rate_cfg & 0x150) == 0)) { 1572 * rate_cfg |= 0x010; 1573 * } */ 1574 rate_cfg |= 0x01; 1575 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 1576 rtl_write_byte(rtlpriv, REG_RRSR + 1, 1577 (rate_cfg >> 8) & 0xff); 1578 while (rate_cfg > 0x1) { 1579 rate_cfg >>= 1; 1580 rate_index++; 1581 } 1582 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 1583 rate_index); 1584 break; 1585 } 1586 case HW_VAR_BSSID:{ 1587 for (idx = 0; idx < ETH_ALEN; idx++) { 1588 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 1589 val[idx]); 1590 } 1591 break; 1592 } 1593 case HW_VAR_SIFS:{ 1594 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]); 1595 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]); 1596 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 1597 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 1598 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]); 1599 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]); 1600 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n"); 1601 break; 1602 } 1603 case HW_VAR_SLOT_TIME:{ 1604 u8 e_aci; 1605 u8 QOS_MODE = 1; 1606 1607 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 1608 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1609 "HW_VAR_SLOT_TIME %x\n", val[0]); 1610 if (QOS_MODE) { 1611 for (e_aci = 0; e_aci < AC_MAX; e_aci++) 1612 rtlpriv->cfg->ops->set_hw_reg(hw, 1613 HW_VAR_AC_PARAM, 1614 &e_aci); 1615 } else { 1616 u8 sifstime = 0; 1617 u8 u1baifs; 1618 1619 if (IS_WIRELESS_MODE_A(wirelessmode) || 1620 IS_WIRELESS_MODE_N_24G(wirelessmode) || 1621 IS_WIRELESS_MODE_N_5G(wirelessmode)) 1622 sifstime = 16; 1623 else 1624 sifstime = 10; 1625 u1baifs = sifstime + (2 * val[0]); 1626 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM, 1627 u1baifs); 1628 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM, 1629 u1baifs); 1630 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM, 1631 u1baifs); 1632 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM, 1633 u1baifs); 1634 } 1635 break; 1636 } 1637 case HW_VAR_ACK_PREAMBLE:{ 1638 u8 reg_tmp; 1639 u8 short_preamble = (bool)*val; 1640 1641 reg_tmp = 0; 1642 if (short_preamble) 1643 reg_tmp |= 0x80; 1644 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 1645 break; 1646 } 1647 case HW_VAR_AMPDU_MIN_SPACE:{ 1648 u8 min_spacing_to_set; 1649 u8 sec_min_space; 1650 1651 min_spacing_to_set = *val; 1652 if (min_spacing_to_set <= 7) { 1653 switch (rtlpriv->sec.pairwise_enc_algorithm) { 1654 case NO_ENCRYPTION: 1655 case AESCCMP_ENCRYPTION: 1656 sec_min_space = 0; 1657 break; 1658 case WEP40_ENCRYPTION: 1659 case WEP104_ENCRYPTION: 1660 case TKIP_ENCRYPTION: 1661 sec_min_space = 6; 1662 break; 1663 default: 1664 sec_min_space = 7; 1665 break; 1666 } 1667 if (min_spacing_to_set < sec_min_space) 1668 min_spacing_to_set = sec_min_space; 1669 mac->min_space_cfg = ((mac->min_space_cfg & 1670 0xf8) | 1671 min_spacing_to_set); 1672 *val = min_spacing_to_set; 1673 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1674 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 1675 mac->min_space_cfg); 1676 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 1677 mac->min_space_cfg); 1678 } 1679 break; 1680 } 1681 case HW_VAR_SHORTGI_DENSITY:{ 1682 u8 density_to_set; 1683 1684 density_to_set = *val; 1685 density_to_set &= 0x1f; 1686 mac->min_space_cfg &= 0x07; 1687 mac->min_space_cfg |= (density_to_set << 3); 1688 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1689 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 1690 mac->min_space_cfg); 1691 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 1692 mac->min_space_cfg); 1693 break; 1694 } 1695 case HW_VAR_AMPDU_FACTOR:{ 1696 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; 1697 u8 factor_toset; 1698 u8 *p_regtoset = NULL; 1699 u8 index = 0; 1700 1701 p_regtoset = regtoset_normal; 1702 factor_toset = *val; 1703 if (factor_toset <= 3) { 1704 factor_toset = (1 << (factor_toset + 2)); 1705 if (factor_toset > 0xf) 1706 factor_toset = 0xf; 1707 for (index = 0; index < 4; index++) { 1708 if ((p_regtoset[index] & 0xf0) > 1709 (factor_toset << 4)) 1710 p_regtoset[index] = 1711 (p_regtoset[index] & 0x0f) 1712 | (factor_toset << 4); 1713 if ((p_regtoset[index] & 0x0f) > 1714 factor_toset) 1715 p_regtoset[index] = 1716 (p_regtoset[index] & 0xf0) 1717 | (factor_toset); 1718 rtl_write_byte(rtlpriv, 1719 (REG_AGGLEN_LMT + index), 1720 p_regtoset[index]); 1721 } 1722 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1723 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 1724 factor_toset); 1725 } 1726 break; 1727 } 1728 case HW_VAR_AC_PARAM:{ 1729 u8 e_aci = *val; 1730 u32 u4b_ac_param; 1731 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min); 1732 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max); 1733 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op); 1734 1735 u4b_ac_param = (u32) mac->ac[e_aci].aifs; 1736 u4b_ac_param |= (u32) ((cw_min & 0xF) << 1737 AC_PARAM_ECW_MIN_OFFSET); 1738 u4b_ac_param |= (u32) ((cw_max & 0xF) << 1739 AC_PARAM_ECW_MAX_OFFSET); 1740 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET; 1741 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1742 "queue:%x, ac_param:%x\n", 1743 e_aci, u4b_ac_param); 1744 switch (e_aci) { 1745 case AC1_BK: 1746 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 1747 u4b_ac_param); 1748 break; 1749 case AC0_BE: 1750 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 1751 u4b_ac_param); 1752 break; 1753 case AC2_VI: 1754 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 1755 u4b_ac_param); 1756 break; 1757 case AC3_VO: 1758 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 1759 u4b_ac_param); 1760 break; 1761 default: 1762 WARN_ONCE(true, "rtl8192cu: invalid aci: %d !\n", 1763 e_aci); 1764 break; 1765 } 1766 break; 1767 } 1768 case HW_VAR_RCR:{ 1769 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); 1770 mac->rx_conf = ((u32 *) (val))[0]; 1771 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG, 1772 "### Set RCR(0x%08x) ###\n", mac->rx_conf); 1773 break; 1774 } 1775 case HW_VAR_RETRY_LIMIT:{ 1776 u8 retry_limit = val[0]; 1777 1778 rtl_write_word(rtlpriv, REG_RL, 1779 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 1780 retry_limit << RETRY_LIMIT_LONG_SHIFT); 1781 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, 1782 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n", 1783 retry_limit); 1784 break; 1785 } 1786 case HW_VAR_DUAL_TSF_RST: 1787 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 1788 break; 1789 case HW_VAR_EFUSE_BYTES: 1790 rtlefuse->efuse_usedbytes = *((u16 *) val); 1791 break; 1792 case HW_VAR_EFUSE_USAGE: 1793 rtlefuse->efuse_usedpercentage = *val; 1794 break; 1795 case HW_VAR_IO_CMD: 1796 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); 1797 break; 1798 case HW_VAR_WPA_CONFIG: 1799 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 1800 break; 1801 case HW_VAR_SET_RPWM:{ 1802 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM); 1803 1804 if (rpwm_val & BIT(7)) 1805 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val); 1806 else 1807 rtl_write_byte(rtlpriv, REG_USB_HRPWM, 1808 *val | BIT(7)); 1809 break; 1810 } 1811 case HW_VAR_H2C_FW_PWRMODE:{ 1812 u8 psmode = *val; 1813 1814 if ((psmode != FW_PS_ACTIVE_MODE) && 1815 (!IS_92C_SERIAL(rtlhal->version))) 1816 rtl92c_dm_rf_saving(hw, true); 1817 rtl92c_set_fw_pwrmode_cmd(hw, (*val)); 1818 break; 1819 } 1820 case HW_VAR_FW_PSMODE_STATUS: 1821 ppsc->fw_current_inpsmode = *((bool *) val); 1822 break; 1823 case HW_VAR_H2C_FW_JOINBSSRPT:{ 1824 u8 mstatus = *val; 1825 u8 tmp_reg422; 1826 bool recover = false; 1827 1828 if (mstatus == RT_MEDIA_CONNECT) { 1829 rtlpriv->cfg->ops->set_hw_reg(hw, 1830 HW_VAR_AID, NULL); 1831 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03); 1832 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); 1833 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); 1834 tmp_reg422 = rtl_read_byte(rtlpriv, 1835 REG_FWHW_TXQ_CTRL + 2); 1836 if (tmp_reg422 & BIT(6)) 1837 recover = true; 1838 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1839 tmp_reg422 & (~BIT(6))); 1840 rtl92c_set_fw_rsvdpagepkt(hw, 1841 &usb_cmd_send_packet); 1842 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); 1843 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1844 if (recover) 1845 rtl_write_byte(rtlpriv, 1846 REG_FWHW_TXQ_CTRL + 2, 1847 tmp_reg422 | BIT(6)); 1848 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 1849 } 1850 rtl92c_set_fw_joinbss_report_cmd(hw, (*val)); 1851 break; 1852 } 1853 case HW_VAR_AID:{ 1854 u16 u2btmp; 1855 1856 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 1857 u2btmp &= 0xC000; 1858 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, 1859 (u2btmp | mac->assoc_id)); 1860 break; 1861 } 1862 case HW_VAR_CORRECT_TSF:{ 1863 u8 btype_ibss = val[0]; 1864 1865 if (btype_ibss) 1866 _rtl92cu_stop_tx_beacon(hw); 1867 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); 1868 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf & 1869 0xffffffff)); 1870 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 1871 (u32)((mac->tsf >> 32) & 0xffffffff)); 1872 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); 1873 if (btype_ibss) 1874 _rtl92cu_resume_tx_beacon(hw); 1875 break; 1876 } 1877 case HW_VAR_MGT_FILTER: 1878 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val); 1879 mac->rx_mgt_filter = *(u16 *)val; 1880 break; 1881 case HW_VAR_CTRL_FILTER: 1882 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val); 1883 mac->rx_ctrl_filter = *(u16 *)val; 1884 break; 1885 case HW_VAR_DATA_FILTER: 1886 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val); 1887 mac->rx_data_filter = *(u16 *)val; 1888 break; 1889 case HW_VAR_KEEP_ALIVE:{ 1890 u8 array[2]; 1891 1892 array[0] = 0xff; 1893 array[1] = *((u8 *)val); 1894 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, 1895 array); 1896 break; 1897 } 1898 default: 1899 pr_err("switch case %#x not processed\n", variable); 1900 break; 1901 } 1902 } 1903 1904 static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw, 1905 struct ieee80211_sta *sta) 1906 { 1907 struct rtl_priv *rtlpriv = rtl_priv(hw); 1908 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1909 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1910 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1911 u32 ratr_value; 1912 u8 ratr_index = 0; 1913 u8 nmode = mac->ht_enable; 1914 u8 mimo_ps = IEEE80211_SMPS_OFF; 1915 u16 shortgi_rate; 1916 u32 tmp_ratr_value; 1917 u8 curtxbw_40mhz = mac->bw_40; 1918 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1919 1 : 0; 1920 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1921 1 : 0; 1922 enum wireless_mode wirelessmode = mac->mode; 1923 1924 if (rtlhal->current_bandtype == BAND_ON_5G) 1925 ratr_value = sta->supp_rates[1] << 4; 1926 else 1927 ratr_value = sta->supp_rates[0]; 1928 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1929 ratr_value = 0xfff; 1930 1931 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1932 sta->ht_cap.mcs.rx_mask[0] << 12); 1933 switch (wirelessmode) { 1934 case WIRELESS_MODE_B: 1935 if (ratr_value & 0x0000000c) 1936 ratr_value &= 0x0000000d; 1937 else 1938 ratr_value &= 0x0000000f; 1939 break; 1940 case WIRELESS_MODE_G: 1941 ratr_value &= 0x00000FF5; 1942 break; 1943 case WIRELESS_MODE_N_24G: 1944 case WIRELESS_MODE_N_5G: 1945 nmode = 1; 1946 if (mimo_ps == IEEE80211_SMPS_STATIC) { 1947 ratr_value &= 0x0007F005; 1948 } else { 1949 u32 ratr_mask; 1950 1951 if (get_rf_type(rtlphy) == RF_1T2R || 1952 get_rf_type(rtlphy) == RF_1T1R) 1953 ratr_mask = 0x000ff005; 1954 else 1955 ratr_mask = 0x0f0ff005; 1956 1957 ratr_value &= ratr_mask; 1958 } 1959 break; 1960 default: 1961 if (rtlphy->rf_type == RF_1T2R) 1962 ratr_value &= 0x000ff0ff; 1963 else 1964 ratr_value &= 0x0f0ff0ff; 1965 1966 break; 1967 } 1968 1969 ratr_value &= 0x0FFFFFFF; 1970 1971 if (nmode && ((curtxbw_40mhz && 1972 curshortgi_40mhz) || (!curtxbw_40mhz && 1973 curshortgi_20mhz))) { 1974 ratr_value |= 0x10000000; 1975 tmp_ratr_value = (ratr_value >> 12); 1976 1977 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 1978 if ((1 << shortgi_rate) & tmp_ratr_value) 1979 break; 1980 } 1981 1982 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 1983 (shortgi_rate << 4) | (shortgi_rate); 1984 } 1985 1986 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 1987 1988 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 1989 rtl_read_dword(rtlpriv, REG_ARFR0)); 1990 } 1991 1992 static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, 1993 struct ieee80211_sta *sta, 1994 u8 rssi_level, bool update_bw) 1995 { 1996 struct rtl_priv *rtlpriv = rtl_priv(hw); 1997 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1998 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1999 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2000 struct rtl_sta_info *sta_entry = NULL; 2001 u32 ratr_bitmap; 2002 u8 ratr_index; 2003 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; 2004 u8 curshortgi_40mhz = curtxbw_40mhz && 2005 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2006 1 : 0; 2007 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2008 1 : 0; 2009 enum wireless_mode wirelessmode = 0; 2010 bool shortgi = false; 2011 u8 rate_mask[5]; 2012 u8 macid = 0; 2013 u8 mimo_ps = IEEE80211_SMPS_OFF; 2014 2015 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 2016 wirelessmode = sta_entry->wireless_mode; 2017 if (mac->opmode == NL80211_IFTYPE_STATION || 2018 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2019 curtxbw_40mhz = mac->bw_40; 2020 else if (mac->opmode == NL80211_IFTYPE_AP || 2021 mac->opmode == NL80211_IFTYPE_ADHOC) 2022 macid = sta->aid + 1; 2023 2024 if (rtlhal->current_bandtype == BAND_ON_5G) 2025 ratr_bitmap = sta->supp_rates[1] << 4; 2026 else 2027 ratr_bitmap = sta->supp_rates[0]; 2028 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2029 ratr_bitmap = 0xfff; 2030 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2031 sta->ht_cap.mcs.rx_mask[0] << 12); 2032 switch (wirelessmode) { 2033 case WIRELESS_MODE_B: 2034 ratr_index = RATR_INX_WIRELESS_B; 2035 if (ratr_bitmap & 0x0000000c) 2036 ratr_bitmap &= 0x0000000d; 2037 else 2038 ratr_bitmap &= 0x0000000f; 2039 break; 2040 case WIRELESS_MODE_G: 2041 ratr_index = RATR_INX_WIRELESS_GB; 2042 2043 if (rssi_level == 1) 2044 ratr_bitmap &= 0x00000f00; 2045 else if (rssi_level == 2) 2046 ratr_bitmap &= 0x00000ff0; 2047 else 2048 ratr_bitmap &= 0x00000ff5; 2049 break; 2050 case WIRELESS_MODE_A: 2051 ratr_index = RATR_INX_WIRELESS_A; 2052 ratr_bitmap &= 0x00000ff0; 2053 break; 2054 case WIRELESS_MODE_N_24G: 2055 case WIRELESS_MODE_N_5G: 2056 ratr_index = RATR_INX_WIRELESS_NGB; 2057 2058 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2059 if (rssi_level == 1) 2060 ratr_bitmap &= 0x00070000; 2061 else if (rssi_level == 2) 2062 ratr_bitmap &= 0x0007f000; 2063 else 2064 ratr_bitmap &= 0x0007f005; 2065 } else { 2066 if (rtlphy->rf_type == RF_1T2R || 2067 rtlphy->rf_type == RF_1T1R) { 2068 if (curtxbw_40mhz) { 2069 if (rssi_level == 1) 2070 ratr_bitmap &= 0x000f0000; 2071 else if (rssi_level == 2) 2072 ratr_bitmap &= 0x000ff000; 2073 else 2074 ratr_bitmap &= 0x000ff015; 2075 } else { 2076 if (rssi_level == 1) 2077 ratr_bitmap &= 0x000f0000; 2078 else if (rssi_level == 2) 2079 ratr_bitmap &= 0x000ff000; 2080 else 2081 ratr_bitmap &= 0x000ff005; 2082 } 2083 } else { 2084 if (curtxbw_40mhz) { 2085 if (rssi_level == 1) 2086 ratr_bitmap &= 0x0f0f0000; 2087 else if (rssi_level == 2) 2088 ratr_bitmap &= 0x0f0ff000; 2089 else 2090 ratr_bitmap &= 0x0f0ff015; 2091 } else { 2092 if (rssi_level == 1) 2093 ratr_bitmap &= 0x0f0f0000; 2094 else if (rssi_level == 2) 2095 ratr_bitmap &= 0x0f0ff000; 2096 else 2097 ratr_bitmap &= 0x0f0ff005; 2098 } 2099 } 2100 } 2101 2102 if ((curtxbw_40mhz && curshortgi_40mhz) || 2103 (!curtxbw_40mhz && curshortgi_20mhz)) { 2104 2105 if (macid == 0) 2106 shortgi = true; 2107 else if (macid == 1) 2108 shortgi = false; 2109 } 2110 break; 2111 default: 2112 ratr_index = RATR_INX_WIRELESS_NGB; 2113 2114 if (rtlphy->rf_type == RF_1T2R) 2115 ratr_bitmap &= 0x000ff0ff; 2116 else 2117 ratr_bitmap &= 0x0f0ff0ff; 2118 break; 2119 } 2120 sta_entry->ratr_index = ratr_index; 2121 2122 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2123 "ratr_bitmap :%x\n", ratr_bitmap); 2124 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2125 (ratr_index << 28); 2126 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 2127 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2128 "Rate_index:%x, ratr_val:%x, %5phC\n", 2129 ratr_index, ratr_bitmap, rate_mask); 2130 memcpy(rtlpriv->rate_mask, rate_mask, 5); 2131 /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a 2132 * "scheduled while atomic" if called directly */ 2133 schedule_work(&rtlpriv->works.fill_h2c_cmd); 2134 2135 if (macid != 0) 2136 sta_entry->ratr_index = ratr_index; 2137 } 2138 2139 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw, 2140 struct ieee80211_sta *sta, 2141 u8 rssi_level, bool update_bw) 2142 { 2143 struct rtl_priv *rtlpriv = rtl_priv(hw); 2144 2145 if (rtlpriv->dm.useramask) 2146 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 2147 else 2148 rtl92cu_update_hal_rate_table(hw, sta); 2149 } 2150 2151 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw) 2152 { 2153 struct rtl_priv *rtlpriv = rtl_priv(hw); 2154 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2155 u16 sifs_timer; 2156 2157 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2158 &mac->slot_time); 2159 if (!mac->ht_enable) 2160 sifs_timer = 0x0a0a; 2161 else 2162 sifs_timer = 0x0e0e; 2163 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2164 } 2165 2166 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid) 2167 { 2168 struct rtl_priv *rtlpriv = rtl_priv(hw); 2169 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2170 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate; 2171 u8 u1tmp = 0; 2172 bool actuallyset = false; 2173 unsigned long flag = 0; 2174 /* to do - usb autosuspend */ 2175 u8 usb_autosuspend = 0; 2176 2177 if (ppsc->swrf_processing) 2178 return false; 2179 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2180 if (ppsc->rfchange_inprogress) { 2181 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2182 return false; 2183 } else { 2184 ppsc->rfchange_inprogress = true; 2185 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2186 } 2187 cur_rfstate = ppsc->rfpwr_state; 2188 if (usb_autosuspend) { 2189 /* to do................... */ 2190 } else { 2191 if (ppsc->pwrdown_mode) { 2192 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR); 2193 e_rfpowerstate_toset = (u1tmp & BIT(7)) ? 2194 ERFOFF : ERFON; 2195 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 2196 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp); 2197 } else { 2198 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, 2199 rtl_read_byte(rtlpriv, 2200 REG_MAC_PINMUX_CFG) & ~(BIT(3))); 2201 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 2202 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? 2203 ERFON : ERFOFF; 2204 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 2205 "GPIO_IN=%02x\n", u1tmp); 2206 } 2207 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n", 2208 e_rfpowerstate_toset); 2209 } 2210 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 2211 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2212 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2213 ppsc->hwradiooff = false; 2214 actuallyset = true; 2215 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset == 2216 ERFOFF)) { 2217 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2218 "GPIOChangeRF - HW Radio OFF\n"); 2219 ppsc->hwradiooff = true; 2220 actuallyset = true; 2221 } else { 2222 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2223 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n", 2224 ppsc->hwradiooff, e_rfpowerstate_toset); 2225 } 2226 if (actuallyset) { 2227 ppsc->hwradiooff = true; 2228 if (e_rfpowerstate_toset == ERFON) { 2229 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) && 2230 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) 2231 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2232 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2233 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3)) 2234 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2235 } 2236 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2237 ppsc->rfchange_inprogress = false; 2238 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2239 /* For power down module, we need to enable register block 2240 * contrl reg at 0x1c. Then enable power down control bit 2241 * of register 0x04 BIT4 and BIT15 as 1. 2242 */ 2243 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) { 2244 /* Enable register area 0x0-0xc. */ 2245 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 2246 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812); 2247 } 2248 if (e_rfpowerstate_toset == ERFOFF) { 2249 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) 2250 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2251 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2252 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2253 } 2254 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) { 2255 /* Enter D3 or ASPM after GPIO had been done. */ 2256 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) 2257 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2258 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2259 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2260 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2261 ppsc->rfchange_inprogress = false; 2262 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2263 } else { 2264 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2265 ppsc->rfchange_inprogress = false; 2266 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2267 } 2268 *valid = 1; 2269 return !ppsc->hwradiooff; 2270 } 2271