1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #ifndef __RTL92CU_TRX_H__ 5 #define __RTL92CU_TRX_H__ 6 7 #define RTL92C_USB_BULK_IN_NUM 1 8 #define RTL92C_NUM_RX_URBS 8 9 #define RTL92C_NUM_TX_URBS 32 10 11 #define RTL92C_SIZE_MAX_RX_BUFFER 15360 /* 8192 */ 12 #define RX_DRV_INFO_SIZE_UNIT 8 13 14 #define RTL_AGG_ON 1 15 16 enum usb_rx_agg_mode { 17 USB_RX_AGG_DISABLE, 18 USB_RX_AGG_DMA, 19 USB_RX_AGG_USB, 20 USB_RX_AGG_DMA_USB 21 }; 22 23 #define TX_SELE_HQ BIT(0) /* High Queue */ 24 #define TX_SELE_LQ BIT(1) /* Low Queue */ 25 #define TX_SELE_NQ BIT(2) /* Normal Queue */ 26 27 #define RTL_USB_TX_AGG_NUM_DESC 5 28 29 #define RTL_USB_RX_AGG_PAGE_NUM 4 30 #define RTL_USB_RX_AGG_PAGE_TIMEOUT 3 31 32 #define RTL_USB_RX_AGG_BLOCK_NUM 5 33 #define RTL_USB_RX_AGG_BLOCK_TIMEOUT 3 34 35 /*======================== rx status =========================================*/ 36 37 struct rx_drv_info_92c { 38 /* 39 * Driver info contain PHY status and other variabel size info 40 * PHY Status content as below 41 */ 42 43 /* DWORD 0 */ 44 u8 gain_trsw[4]; 45 46 /* DWORD 1 */ 47 u8 pwdb_all; 48 u8 cfosho[4]; 49 50 /* DWORD 2 */ 51 u8 cfotail[4]; 52 53 /* DWORD 3 */ 54 s8 rxevm[2]; 55 s8 rxsnr[4]; 56 57 /* DWORD 4 */ 58 u8 pdsnr[2]; 59 60 /* DWORD 5 */ 61 u8 csi_current[2]; 62 u8 csi_target[2]; 63 64 /* DWORD 6 */ 65 u8 sigevm; 66 u8 max_ex_pwr; 67 u8 ex_intf_flag:1; 68 u8 sgi_en:1; 69 u8 rxsc:2; 70 u8 reserve:4; 71 } __packed; 72 73 /* macros to read various fields in RX descriptor */ 74 75 /* DWORD 0 */ 76 static inline u32 get_rx_desc_pkt_len(__le32 *__rxdesc) 77 { 78 return le32_get_bits(*__rxdesc, GENMASK(13, 0)); 79 } 80 81 static inline u32 get_rx_desc_crc32(__le32 *__rxdesc) 82 { 83 return le32_get_bits(*__rxdesc, BIT(14)); 84 } 85 86 static inline u32 get_rx_desc_icv(__le32 *__rxdesc) 87 { 88 return le32_get_bits(*__rxdesc, BIT(15)); 89 } 90 91 static inline u32 get_rx_desc_drvinfo_size(__le32 *__rxdesc) 92 { 93 return le32_get_bits(*__rxdesc, GENMASK(19, 16)); 94 } 95 96 static inline u32 get_rx_desc_shift(__le32 *__rxdesc) 97 { 98 return le32_get_bits(*__rxdesc, GENMASK(25, 24)); 99 } 100 101 static inline u32 get_rx_desc_phy_status(__le32 *__rxdesc) 102 { 103 return le32_get_bits(*__rxdesc, BIT(26)); 104 } 105 106 static inline u32 get_rx_desc_swdec(__le32 *__rxdesc) 107 { 108 return le32_get_bits(*__rxdesc, BIT(27)); 109 } 110 111 112 /* DWORD 1 */ 113 static inline u32 get_rx_desc_paggr(__le32 *__rxdesc) 114 { 115 return le32_get_bits(*(__rxdesc + 1), BIT(14)); 116 } 117 118 static inline u32 get_rx_desc_faggr(__le32 *__rxdesc) 119 { 120 return le32_get_bits(*(__rxdesc + 1), BIT(15)); 121 } 122 123 124 /* DWORD 3 */ 125 static inline u32 get_rx_desc_rx_mcs(__le32 *__rxdesc) 126 { 127 return le32_get_bits(*(__rxdesc + 3), GENMASK(5, 0)); 128 } 129 130 static inline u32 get_rx_desc_rx_ht(__le32 *__rxdesc) 131 { 132 return le32_get_bits(*(__rxdesc + 3), BIT(6)); 133 } 134 135 static inline u32 get_rx_desc_splcp(__le32 *__rxdesc) 136 { 137 return le32_get_bits(*(__rxdesc + 3), BIT(8)); 138 } 139 140 static inline u32 get_rx_desc_bw(__le32 *__rxdesc) 141 { 142 return le32_get_bits(*(__rxdesc + 3), BIT(9)); 143 } 144 145 146 /* DWORD 5 */ 147 static inline u32 get_rx_desc_tsfl(__le32 *__rxdesc) 148 { 149 return le32_to_cpu(*((__rxdesc + 5))); 150 } 151 152 153 /*======================= tx desc ============================================*/ 154 155 /* macros to set various fields in TX descriptor */ 156 157 /* Dword 0 */ 158 static inline void set_tx_desc_pkt_size(__le32 *__txdesc, u32 __value) 159 { 160 le32p_replace_bits(__txdesc, __value, GENMASK(15, 0)); 161 } 162 163 static inline void set_tx_desc_offset(__le32 *__txdesc, u32 __value) 164 { 165 le32p_replace_bits(__txdesc, __value, GENMASK(23, 16)); 166 } 167 168 static inline void set_tx_desc_bmc(__le32 *__txdesc, u32 __value) 169 { 170 le32p_replace_bits(__txdesc, __value, BIT(24)); 171 } 172 173 static inline void set_tx_desc_htc(__le32 *__txdesc, u32 __value) 174 { 175 le32p_replace_bits(__txdesc, __value, BIT(25)); 176 } 177 178 static inline void set_tx_desc_last_seg(__le32 *__txdesc, u32 __value) 179 { 180 le32p_replace_bits(__txdesc, __value, BIT(26)); 181 } 182 183 static inline void set_tx_desc_first_seg(__le32 *__txdesc, u32 __value) 184 { 185 le32p_replace_bits(__txdesc, __value, BIT(27)); 186 } 187 188 static inline void set_tx_desc_linip(__le32 *__txdesc, u32 __value) 189 { 190 le32p_replace_bits(__txdesc, __value, BIT(28)); 191 } 192 193 static inline void set_tx_desc_own(__le32 *__txdesc, u32 __value) 194 { 195 le32p_replace_bits(__txdesc, __value, BIT(31)); 196 } 197 198 199 /* Dword 1 */ 200 static inline void set_tx_desc_macid(__le32 *__txdesc, u32 __value) 201 { 202 le32p_replace_bits((__txdesc + 1), __value, GENMASK(4, 0)); 203 } 204 205 static inline void set_tx_desc_agg_enable(__le32 *__txdesc, u32 __value) 206 { 207 le32p_replace_bits((__txdesc + 1), __value, BIT(5)); 208 } 209 210 static inline void set_tx_desc_agg_break(__le32 *__txdesc, u32 __value) 211 { 212 le32p_replace_bits((__txdesc + 1), __value, BIT(6)); 213 } 214 215 static inline void set_tx_desc_rdg_enable(__le32 *__txdesc, u32 __value) 216 { 217 le32p_replace_bits((__txdesc + 1), __value, BIT(7)); 218 } 219 220 static inline void set_tx_desc_queue_sel(__le32 *__txdesc, u32 __value) 221 { 222 le32p_replace_bits((__txdesc + 1), __value, GENMASK(12, 8)); 223 } 224 225 static inline void set_tx_desc_rate_id(__le32 *__txdesc, u32 __value) 226 { 227 le32p_replace_bits((__txdesc + 1), __value, GENMASK(19, 16)); 228 } 229 230 static inline void set_tx_desc_nav_use_hdr(__le32 *__txdesc, u32 __value) 231 { 232 le32p_replace_bits((__txdesc + 1), __value, BIT(20)); 233 } 234 235 static inline void set_tx_desc_sec_type(__le32 *__txdesc, u32 __value) 236 { 237 le32p_replace_bits((__txdesc + 1), __value, GENMASK(23, 22)); 238 } 239 240 static inline void set_tx_desc_pkt_offset(__le32 *__txdesc, u32 __value) 241 { 242 le32p_replace_bits((__txdesc + 1), __value, GENMASK(30, 26)); 243 } 244 245 246 /* Dword 2 */ 247 static inline void set_tx_desc_more_frag(__le32 *__txdesc, u32 __value) 248 { 249 le32p_replace_bits((__txdesc + 2), __value, BIT(17)); 250 } 251 252 static inline void set_tx_desc_ampdu_density(__le32 *__txdesc, u32 __value) 253 { 254 le32p_replace_bits((__txdesc + 2), __value, GENMASK(22, 20)); 255 } 256 257 258 /* Dword 3 */ 259 static inline void set_tx_desc_seq(__le32 *__txdesc, u32 __value) 260 { 261 le32p_replace_bits((__txdesc + 3), __value, GENMASK(27, 16)); 262 } 263 264 static inline void set_tx_desc_pkt_id(__le32 *__txdesc, u32 __value) 265 { 266 le32p_replace_bits((__txdesc + 3), __value, GENMASK(31, 28)); 267 } 268 269 270 /* Dword 4 */ 271 static inline void set_tx_desc_rts_rate(__le32 *__txdesc, u32 __value) 272 { 273 le32p_replace_bits((__txdesc + 4), __value, GENMASK(4, 0)); 274 } 275 276 static inline void set_tx_desc_qos(__le32 *__txdesc, u32 __value) 277 { 278 le32p_replace_bits((__txdesc + 4), __value, BIT(6)); 279 } 280 281 static inline void set_tx_desc_hwseq_en(__le32 *__txdesc, u32 __value) 282 { 283 le32p_replace_bits((__txdesc + 4), __value, BIT(7)); 284 } 285 286 static inline void set_tx_desc_use_rate(__le32 *__txdesc, u32 __value) 287 { 288 le32p_replace_bits((__txdesc + 4), __value, BIT(8)); 289 } 290 291 static inline void set_tx_desc_disable_fb(__le32 *__txdesc, u32 __value) 292 { 293 le32p_replace_bits((__txdesc + 4), __value, BIT(10)); 294 } 295 296 static inline void set_tx_desc_cts2self(__le32 *__txdesc, u32 __value) 297 { 298 le32p_replace_bits((__txdesc + 4), __value, BIT(11)); 299 } 300 301 static inline void set_tx_desc_rts_enable(__le32 *__txdesc, u32 __value) 302 { 303 le32p_replace_bits((__txdesc + 4), __value, BIT(12)); 304 } 305 306 static inline void set_tx_desc_hw_rts_enable(__le32 *__txdesc, u32 __value) 307 { 308 le32p_replace_bits((__txdesc + 4), __value, BIT(13)); 309 } 310 311 static inline void set_tx_desc_data_sc(__le32 *__txdesc, u32 __value) 312 { 313 le32p_replace_bits((__txdesc + 4), __value, GENMASK(21, 20)); 314 } 315 316 static inline void set_tx_desc_data_bw(__le32 *__txdesc, u32 __value) 317 { 318 le32p_replace_bits((__txdesc + 4), __value, BIT(25)); 319 } 320 321 static inline void set_tx_desc_rts_short(__le32 *__txdesc, u32 __value) 322 { 323 le32p_replace_bits((__txdesc + 4), __value, BIT(26)); 324 } 325 326 static inline void set_tx_desc_rts_bw(__le32 *__txdesc, u32 __value) 327 { 328 le32p_replace_bits((__txdesc + 4), __value, BIT(27)); 329 } 330 331 static inline void set_tx_desc_rts_sc(__le32 *__txdesc, u32 __value) 332 { 333 le32p_replace_bits((__txdesc + 4), __value, GENMASK(29, 28)); 334 } 335 336 static inline void set_tx_desc_rts_stbc(__le32 *__txdesc, u32 __value) 337 { 338 le32p_replace_bits((__txdesc + 4), __value, GENMASK(31, 30)); 339 } 340 341 342 /* Dword 5 */ 343 static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val) 344 { 345 le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0)); 346 } 347 348 static inline void set_tx_desc_data_shortgi(__le32 *__pdesc, u32 __val) 349 { 350 le32p_replace_bits((__pdesc + 5), __val, BIT(6)); 351 } 352 353 static inline void set_tx_desc_data_rate_fb_limit(__le32 *__txdesc, u32 __value) 354 { 355 le32p_replace_bits((__txdesc + 5), __value, GENMASK(12, 8)); 356 } 357 358 static inline void set_tx_desc_rts_rate_fb_limit(__le32 *__txdesc, u32 __value) 359 { 360 le32p_replace_bits((__txdesc + 5), __value, GENMASK(16, 13)); 361 } 362 363 364 /* Dword 6 */ 365 static inline void set_tx_desc_max_agg_num(__le32 *__txdesc, u32 __value) 366 { 367 le32p_replace_bits((__txdesc + 6), __value, GENMASK(15, 11)); 368 } 369 370 371 /* Dword 7 */ 372 static inline void set_tx_desc_tx_desc_checksum(__le32 *__txdesc, u32 __value) 373 { 374 le32p_replace_bits((__txdesc + 7), __value, GENMASK(15, 0)); 375 } 376 377 378 int rtl8192cu_endpoint_mapping(struct ieee80211_hw *hw); 379 u16 rtl8192cu_mq_to_hwq(__le16 fc, u16 mac80211_queue_index); 380 bool rtl92cu_rx_query_desc(struct ieee80211_hw *hw, 381 struct rtl_stats *stats, 382 struct ieee80211_rx_status *rx_status, 383 u8 *p_desc, struct sk_buff *skb); 384 void rtl8192cu_rx_hdl(struct ieee80211_hw *hw, struct sk_buff * skb); 385 void rtl8192c_tx_cleanup(struct ieee80211_hw *hw, struct sk_buff *skb); 386 int rtl8192c_tx_post_hdl(struct ieee80211_hw *hw, struct urb *urb, 387 struct sk_buff *skb); 388 struct sk_buff *rtl8192c_tx_aggregate_hdl(struct ieee80211_hw *, 389 struct sk_buff_head *); 390 void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw, 391 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 392 u8 *pbd_desc_tx, struct ieee80211_tx_info *info, 393 struct ieee80211_sta *sta, 394 struct sk_buff *skb, 395 u8 queue_index, 396 struct rtl_tcb_desc *tcb_desc); 397 void rtl92cu_fill_fake_txdesc(struct ieee80211_hw *hw, u8 *pdesc, 398 u32 buffer_len, bool ispspoll); 399 void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw, 400 u8 *pdesc, bool b_firstseg, 401 bool b_lastseg, struct sk_buff *skb); 402 403 #endif 404