1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../core.h" 28 #include "../pci.h" 29 #include "../base.h" 30 #include "reg.h" 31 #include "def.h" 32 #include "phy.h" 33 #include "dm.h" 34 #include "hw.h" 35 #include "sw.h" 36 #include "trx.h" 37 #include "led.h" 38 39 #include <linux/module.h> 40 41 static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw) 42 { 43 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 44 45 /*close ASPM for AMD defaultly */ 46 rtlpci->const_amdpci_aspm = 0; 47 48 /* 49 * ASPM PS mode. 50 * 0 - Disable ASPM, 51 * 1 - Enable ASPM without Clock Req, 52 * 2 - Enable ASPM with Clock Req, 53 * 3 - Alwyas Enable ASPM with Clock Req, 54 * 4 - Always Enable ASPM without Clock Req. 55 * set defult to RTL8192CE:3 RTL8192E:2 56 * */ 57 rtlpci->const_pci_aspm = 3; 58 59 /*Setting for PCI-E device */ 60 rtlpci->const_devicepci_aspm_setting = 0x03; 61 62 /*Setting for PCI-E bridge */ 63 rtlpci->const_hostpci_aspm_setting = 0x02; 64 65 /* 66 * In Hw/Sw Radio Off situation. 67 * 0 - Default, 68 * 1 - From ASPM setting without low Mac Pwr, 69 * 2 - From ASPM setting with low Mac Pwr, 70 * 3 - Bus D3 71 * set default to RTL8192CE:0 RTL8192SE:2 72 */ 73 rtlpci->const_hwsw_rfoff_d3 = 0; 74 75 /* 76 * This setting works for those device with 77 * backdoor ASPM setting such as EPHY setting. 78 * 0 - Not support ASPM, 79 * 1 - Support ASPM, 80 * 2 - According to chipset. 81 */ 82 rtlpci->const_support_pciaspm = 1; 83 } 84 85 static int rtl92d_init_sw_vars(struct ieee80211_hw *hw) 86 { 87 int err; 88 u8 tid; 89 struct rtl_priv *rtlpriv = rtl_priv(hw); 90 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 91 92 rtlpriv->dm.dm_initialgain_enable = true; 93 rtlpriv->dm.dm_flag = 0; 94 rtlpriv->dm.disable_framebursting = false; 95 rtlpriv->dm.thermalvalue = 0; 96 rtlpriv->dm.useramask = true; 97 98 /* dual mac */ 99 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) 100 rtlpriv->phy.current_channel = 36; 101 else 102 rtlpriv->phy.current_channel = 1; 103 104 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { 105 rtlpriv->rtlhal.disable_amsdu_8k = true; 106 /* No long RX - reduce fragmentation */ 107 rtlpci->rxbuffersize = 4096; 108 } 109 110 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); 111 112 rtlpci->receive_config = ( 113 RCR_APPFCS 114 | RCR_AMF 115 | RCR_ADF 116 | RCR_APP_MIC 117 | RCR_APP_ICV 118 | RCR_AICV 119 | RCR_ACRC32 120 | RCR_AB 121 | RCR_AM 122 | RCR_APM 123 | RCR_APP_PHYST_RXFF 124 | RCR_HTC_LOC_CTRL 125 ); 126 127 rtlpci->irq_mask[0] = (u32) ( 128 IMR_ROK 129 | IMR_VODOK 130 | IMR_VIDOK 131 | IMR_BEDOK 132 | IMR_BKDOK 133 | IMR_MGNTDOK 134 | IMR_HIGHDOK 135 | IMR_BDOK 136 | IMR_RDU 137 | IMR_RXFOVW 138 ); 139 140 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD); 141 142 /* for debug level */ 143 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug; 144 /* for LPS & IPS */ 145 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 146 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 147 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 148 if (!rtlpriv->psc.inactiveps) 149 pr_info("Power Save off (module option)\n"); 150 if (!rtlpriv->psc.fwctrl_lps) 151 pr_info("FW Power Save off (module option)\n"); 152 rtlpriv->psc.reg_fwctrl_lps = 3; 153 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 154 /* for ASPM, you can close aspm through 155 * set const_support_pciaspm = 0 */ 156 rtl92d_init_aspm_vars(hw); 157 158 if (rtlpriv->psc.reg_fwctrl_lps == 1) 159 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; 160 else if (rtlpriv->psc.reg_fwctrl_lps == 2) 161 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; 162 else if (rtlpriv->psc.reg_fwctrl_lps == 3) 163 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; 164 165 /* for early mode */ 166 rtlpriv->rtlhal.earlymode_enable = false; 167 for (tid = 0; tid < 8; tid++) 168 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]); 169 170 /* for firmware buf */ 171 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000); 172 if (!rtlpriv->rtlhal.pfirmware) { 173 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 174 "Can't alloc buffer for fw\n"); 175 return 1; 176 } 177 178 rtlpriv->max_fw_size = 0x8000; 179 pr_info("Driver for Realtek RTL8192DE WLAN interface\n"); 180 pr_info("Loading firmware file %s\n", rtlpriv->cfg->fw_name); 181 182 /* request fw */ 183 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name, 184 rtlpriv->io.dev, GFP_KERNEL, hw, 185 rtl_fw_cb); 186 if (err) { 187 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 188 "Failed to request firmware!\n"); 189 return 1; 190 } 191 192 return 0; 193 } 194 195 static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw) 196 { 197 struct rtl_priv *rtlpriv = rtl_priv(hw); 198 u8 tid; 199 200 if (rtlpriv->rtlhal.pfirmware) { 201 vfree(rtlpriv->rtlhal.pfirmware); 202 rtlpriv->rtlhal.pfirmware = NULL; 203 } 204 for (tid = 0; tid < 8; tid++) 205 skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]); 206 } 207 208 static struct rtl_hal_ops rtl8192de_hal_ops = { 209 .init_sw_vars = rtl92d_init_sw_vars, 210 .deinit_sw_vars = rtl92d_deinit_sw_vars, 211 .read_eeprom_info = rtl92de_read_eeprom_info, 212 .interrupt_recognized = rtl92de_interrupt_recognized, 213 .hw_init = rtl92de_hw_init, 214 .hw_disable = rtl92de_card_disable, 215 .hw_suspend = rtl92de_suspend, 216 .hw_resume = rtl92de_resume, 217 .enable_interrupt = rtl92de_enable_interrupt, 218 .disable_interrupt = rtl92de_disable_interrupt, 219 .set_network_type = rtl92de_set_network_type, 220 .set_chk_bssid = rtl92de_set_check_bssid, 221 .set_qos = rtl92de_set_qos, 222 .set_bcn_reg = rtl92de_set_beacon_related_registers, 223 .set_bcn_intv = rtl92de_set_beacon_interval, 224 .update_interrupt_mask = rtl92de_update_interrupt_mask, 225 .get_hw_reg = rtl92de_get_hw_reg, 226 .set_hw_reg = rtl92de_set_hw_reg, 227 .update_rate_tbl = rtl92de_update_hal_rate_tbl, 228 .fill_tx_desc = rtl92de_tx_fill_desc, 229 .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc, 230 .query_rx_desc = rtl92de_rx_query_desc, 231 .set_channel_access = rtl92de_update_channel_access_setting, 232 .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking, 233 .set_bw_mode = rtl92d_phy_set_bw_mode, 234 .switch_channel = rtl92d_phy_sw_chnl, 235 .dm_watchdog = rtl92d_dm_watchdog, 236 .scan_operation_backup = rtl_phy_scan_operation_backup, 237 .set_rf_power_state = rtl92d_phy_set_rf_power_state, 238 .led_control = rtl92de_led_control, 239 .set_desc = rtl92de_set_desc, 240 .get_desc = rtl92de_get_desc, 241 .tx_polling = rtl92de_tx_polling, 242 .enable_hw_sec = rtl92de_enable_hw_security_config, 243 .set_key = rtl92de_set_key, 244 .init_sw_leds = rtl92de_init_sw_leds, 245 .get_bbreg = rtl92d_phy_query_bb_reg, 246 .set_bbreg = rtl92d_phy_set_bb_reg, 247 .get_rfreg = rtl92d_phy_query_rf_reg, 248 .set_rfreg = rtl92d_phy_set_rf_reg, 249 .linked_set_reg = rtl92d_linked_set_reg, 250 .get_btc_status = rtl_btc_status_false, 251 }; 252 253 static struct rtl_mod_params rtl92de_mod_params = { 254 .sw_crypto = false, 255 .inactiveps = true, 256 .swctrl_lps = true, 257 .fwctrl_lps = false, 258 .debug = DBG_EMERG, 259 }; 260 261 static const struct rtl_hal_cfg rtl92de_hal_cfg = { 262 .bar_id = 2, 263 .write_readback = true, 264 .name = "rtl8192de", 265 .fw_name = "rtlwifi/rtl8192defw.bin", 266 .ops = &rtl8192de_hal_ops, 267 .mod_params = &rtl92de_mod_params, 268 269 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, 270 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, 271 .maps[SYS_CLK] = REG_SYS_CLKR, 272 .maps[MAC_RCR_AM] = RCR_AM, 273 .maps[MAC_RCR_AB] = RCR_AB, 274 .maps[MAC_RCR_ACRC32] = RCR_ACRC32, 275 .maps[MAC_RCR_ACF] = RCR_ACF, 276 .maps[MAC_RCR_AAP] = RCR_AAP, 277 278 .maps[EFUSE_TEST] = REG_EFUSE_TEST, 279 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, 280 .maps[EFUSE_CLK] = 0, /* just for 92se */ 281 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, 282 .maps[EFUSE_PWC_EV12V] = PWC_EV12V, 283 .maps[EFUSE_FEN_ELDR] = FEN_ELDR, 284 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, 285 .maps[EFUSE_ANA8M] = 0, /* just for 92se */ 286 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, 287 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, 288 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, 289 290 .maps[RWCAM] = REG_CAMCMD, 291 .maps[WCAMI] = REG_CAMWRITE, 292 .maps[RCAMO] = REG_CAMREAD, 293 .maps[CAMDBG] = REG_CAMDBG, 294 .maps[SECR] = REG_SECCFG, 295 .maps[SEC_CAM_NONE] = CAM_NONE, 296 .maps[SEC_CAM_WEP40] = CAM_WEP40, 297 .maps[SEC_CAM_TKIP] = CAM_TKIP, 298 .maps[SEC_CAM_AES] = CAM_AES, 299 .maps[SEC_CAM_WEP104] = CAM_WEP104, 300 301 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, 302 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, 303 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, 304 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, 305 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, 306 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, 307 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, 308 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, 309 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, 310 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, 311 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, 312 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, 313 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, 314 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, 315 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, 316 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, 317 318 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, 319 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, 320 .maps[RTL_IMR_BCNINT] = IMR_BCNINT, 321 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, 322 .maps[RTL_IMR_RDU] = IMR_RDU, 323 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, 324 .maps[RTL_IMR_BDOK] = IMR_BDOK, 325 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, 326 .maps[RTL_IMR_TBDER] = IMR_TBDER, 327 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, 328 .maps[RTL_IMR_TBDOK] = IMR_TBDOK, 329 .maps[RTL_IMR_BKDOK] = IMR_BKDOK, 330 .maps[RTL_IMR_BEDOK] = IMR_BEDOK, 331 .maps[RTL_IMR_VIDOK] = IMR_VIDOK, 332 .maps[RTL_IMR_VODOK] = IMR_VODOK, 333 .maps[RTL_IMR_ROK] = IMR_ROK, 334 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER), 335 336 .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M, 337 .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M, 338 .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M, 339 .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M, 340 .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M, 341 .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M, 342 .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M, 343 .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M, 344 .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M, 345 .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M, 346 .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M, 347 .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M, 348 349 .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7, 350 .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15, 351 }; 352 353 static struct pci_device_id rtl92de_pci_ids[] = { 354 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)}, 355 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)}, 356 {}, 357 }; 358 359 MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids); 360 361 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 362 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 363 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); 364 MODULE_LICENSE("GPL"); 365 MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless"); 366 MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin"); 367 368 module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444); 369 module_param_named(debug, rtl92de_mod_params.debug, int, 0444); 370 module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444); 371 module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444); 372 module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444); 373 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); 374 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); 375 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n"); 376 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n"); 377 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)"); 378 379 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume); 380 381 static struct pci_driver rtl92de_driver = { 382 .name = KBUILD_MODNAME, 383 .id_table = rtl92de_pci_ids, 384 .probe = rtl_pci_probe, 385 .remove = rtl_pci_disconnect, 386 .driver.pm = &rtlwifi_pm_ops, 387 }; 388 389 /* add global spin lock to solve the problem that 390 * Dul mac register operation on the same time */ 391 spinlock_t globalmutex_power; 392 spinlock_t globalmutex_for_fwdownload; 393 spinlock_t globalmutex_for_power_and_efuse; 394 395 static int __init rtl92de_module_init(void) 396 { 397 int ret = 0; 398 399 spin_lock_init(&globalmutex_power); 400 spin_lock_init(&globalmutex_for_fwdownload); 401 spin_lock_init(&globalmutex_for_power_and_efuse); 402 403 ret = pci_register_driver(&rtl92de_driver); 404 if (ret) 405 RT_ASSERT(false, "No device found\n"); 406 return ret; 407 } 408 409 static void __exit rtl92de_module_exit(void) 410 { 411 pci_unregister_driver(&rtl92de_driver); 412 } 413 414 module_init(rtl92de_module_init); 415 module_exit(rtl92de_module_exit); 416