1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
3 
4 #ifndef __RTL92E_PWRSEQ_H__
5 #define __RTL92E_PWRSEQ_H__
6 
7 #include "../pwrseqcmd.h"
8 /**
9  *	Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd
10  *	There are 6 HW Power States:
11  *	0: POFF--Power Off
12  *	1: PDN--Power Down
13  *	2: CARDEMU--Card Emulation
14  *	3: ACT--Active Mode
15  *	4: LPS--Low Power State
16  *	5: SUS--Suspend
17  *
18  *	The transision from different states are defined below
19  *	TRANS_CARDEMU_TO_ACT
20  *	TRANS_ACT_TO_CARDEMU
21  *	TRANS_CARDEMU_TO_SUS
22  *	TRANS_SUS_TO_CARDEMU
23  *	TRANS_CARDEMU_TO_PDN
24  *	TRANS_ACT_TO_LPS
25  *	TRANS_LPS_TO_ACT
26  *
27  *	TRANS_END
28  *	PWR SEQ Version: rtl8192E_PwrSeq_V09.h
29  */
30 
31 #define	RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS	18
32 #define	RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS	18
33 #define	RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS	18
34 #define	RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS	18
35 #define	RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS	18
36 #define	RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS	18
37 #define	RTL8192E_TRANS_ACT_TO_LPS_STEPS		23
38 #define	RTL8192E_TRANS_LPS_TO_ACT_STEPS		23
39 #define	RTL8192E_TRANS_END_STEPS		1
40 
41 #define RTL8192E_TRANS_CARDEMU_TO_ACT					\
42 	/* format */							\
43 	/* comments here */						\
44 	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
45 	/* disable HWPDN 0x04[15]=0*/					\
46 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
47 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},			\
48 	/* disable SW LPS 0x04[10]=0*/					\
49 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
50 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0},			\
51 	/* disable WL suspend*/						\
52 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
53 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},		\
54 	/* wait till 0x04[17] = 1    power ready*/			\
55 	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
56 	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)},		\
57 	/* release WLON reset  0x04[16]=1*/				\
58 	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
59 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
60 	/* polling until return 0*/					\
61 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
62 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
63 	/**/								\
64 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
65 	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0},
66 
67 #define RTL8192E_TRANS_ACT_TO_CARDEMU					\
68 	/* format */							\
69 	/* comments here */						\
70 	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
71 	/*0x1F[7:0] = 0 turn off RF*/					\
72 	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
73 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0},			\
74 	/*0x4C[23]=0x4E[7]=0, switch DPDT_SEL_P output from register 0x65[2] */\
75 	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
76 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},			\
77 	/*0x04[9] = 1 turn off MAC by HW state machine*/		\
78 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
79 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)},		\
80 	/*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
81 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
82 	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), 0},
83 
84 #define RTL8192E_TRANS_CARDEMU_TO_SUS					\
85 	/* format */							\
86 	/* comments here */						\
87 	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
88 	/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/		\
89 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
90 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\
91 	/*0x04[12:11] = 2b'01 enable WL suspend*/			\
92 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
93 	 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,	\
94 	 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},				\
95 	/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/		\
96 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
97 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
98 	/*Set SDIO suspend local register*/				\
99 	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
100 	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
101 	 /*wait power state to suspend*/				\
102 	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
103 	 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
104 
105 #define RTL8192E_TRANS_SUS_TO_CARDEMU					\
106 	/* format */							\
107 	/* comments here */						\
108 	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
109 	/*Set SDIO suspend local register*/				\
110 	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
111 	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0},			\
112 	/*wait power state to suspend*/					\
113 	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
114 	 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)},		\
115 	/*0x04[12:11] = 2b'00 disable WL suspend*/			\
116 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
117 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
118 
119 #define RTL8192E_TRANS_CARDEMU_TO_CARDDIS				\
120 	/* format */							\
121 	/* comments here */						\
122 	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
123 	/*0x07=0x20 , SOP option to disable BG/MB*/			\
124 	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
125 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x20},			\
126 	/*Unlock small LDO Register*/					\
127 	{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
128 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)},		\
129 	/*Disable small LDO*/						\
130 	{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
131 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0},			\
132 	/*0x04[12:11] = 2b'01 enable WL suspend*/			\
133 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
134 	 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,		\
135 	 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},				\
136 	/*0x04[10] = 1, enable SW LPS*/					\
137 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
138 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)},		\
139 	/*Set SDIO suspend local register*/				\
140 	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
141 	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
142 	/*wait power state to suspend*/					\
143 	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
144 	 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
145 
146 #define RTL8192E_TRANS_CARDDIS_TO_CARDEMU				\
147 	/* format */							\
148 	/* comments here */						\
149 	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
150 	/*Set SDIO suspend local register*/				\
151 	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
152 	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0},			\
153 	/*wait power state to suspend*/					\
154 	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
155 	 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)},		\
156 	/*Enable small LDO*/						\
157 	{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
158 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
159 	/*Lock small LDO Register*/					\
160 	{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
161 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0},			\
162 	/*0x04[12:11] = 2b'00 disable WL suspend*/			\
163 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
164 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
165 
166 #define RTL8192E_TRANS_CARDEMU_TO_PDN					\
167 	/* format */							\
168 	/* comments here */						\
169 	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
170 	/* 0x04[16] = 0*/						\
171 	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
172 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0},			\
173 	/* 0x04[15] = 1*/						\
174 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
175 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), BIT(7)},
176 
177 #define RTL8192E_TRANS_PDN_TO_CARDEMU					\
178 	/* format */							\
179 	/* comments here */						\
180 	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
181 	/* 0x04[15] = 0*/						\
182 	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
183 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},
184 
185 #define RTL8192E_TRANS_ACT_TO_LPS					\
186 	/* format */							\
187 	/* comments here */						\
188 	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
189 	/*PCIe DMA stop*/						\
190 	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
191 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},			\
192 	/*Tx Pause*/							\
193 	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
194 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},			\
195 	/*Should be zero if no packet is transmitting*/			\
196 	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
197 	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},			\
198 	/*Should be zero if no packet is transmitting*/			\
199 	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
200 	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},			\
201 	/*Should be zero if no packet is transmitting*/			\
202 	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
203 	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},			\
204 	/*Should be zero if no packet is transmitting*/			\
205 	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
206 	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},			\
207 	/*CCK and OFDM are disabled,and clock are gated*/		\
208 	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
209 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0},			\
210 	/*Delay 1us*/							\
211 	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
212 	 PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},		\
213 	/*Whole BB is reset*/						\
214 	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
215 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0},			\
216 	/*Reset MAC TRX*/						\
217 	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
218 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x03},			\
219 	/*check if removed later*/					\
220 	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
221 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0},			\
222 	/*When driver enter Sus/ Disable, enable LOP for BT*/		\
223 	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
224 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x00},			\
225 	/*Respond TxOK to scheduler*/					\
226 	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
227 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(5), BIT(5)},
228 
229 #define RTL8192E_TRANS_LPS_TO_ACT					\
230 	/* format */							\
231 	/* comments here */						\
232 	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
233 	/*SDIO RPWM, For Repeatly In and out, Taggle bit should be changed*/\
234 	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
235 	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, 0xFF, 0x84},		\
236 	/*USB RPWM*/							\
237 	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,	\
238 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84},			\
239 	/*PCIe RPWM*/							\
240 	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
241 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84},			\
242 	/*Delay*/							\
243 	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
244 	 PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS},		\
245 	/*0x08[4] = 0 switch TSF to 40M*/				\
246 	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
247 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4), 0},			\
248 	/*Polling 0x109[7]=0  TSF in 40M*/				\
249 	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
250 	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(7), 0},		\
251 	/*0x101[1] = 1*/						\
252 	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
253 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)},		\
254 	/*0x100[7:0] = 0xFF  enable WMAC TRX*/				\
255 	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
256 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},			\
257 	/* 0x02[1:0] = 2b'11 enable BB macro*/				\
258 	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
259 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\
260 	/*0x522 = 0*/							\
261 	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
262 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0},			\
263 	/*Clear ISR*/							\
264 	{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
265 	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},
266 
267 #define RTL8192E_TRANS_END						\
268 	/* format */							\
269 	/* comments here */						\
270 	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
271 	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
272 	 0, PWR_CMD_END, 0, 0},
273 
274 extern struct wlan_pwr_cfg rtl8192E_power_on_flow
275 					[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS +
276 					 RTL8192E_TRANS_END_STEPS];
277 extern struct wlan_pwr_cfg rtl8192E_radio_off_flow
278 					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
279 					 RTL8192E_TRANS_END_STEPS];
280 extern struct wlan_pwr_cfg rtl8192E_card_disable_flow
281 					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
282 					 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
283 					 RTL8192E_TRANS_END_STEPS];
284 extern struct wlan_pwr_cfg rtl8192E_card_enable_flow
285 					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
286 					 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
287 					 RTL8192E_TRANS_END_STEPS];
288 extern struct wlan_pwr_cfg rtl8192E_suspend_flow
289 					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
290 					 RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
291 					 RTL8192E_TRANS_END_STEPS];
292 extern struct wlan_pwr_cfg rtl8192E_resume_flow
293 					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
294 					 RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
295 					 RTL8192E_TRANS_END_STEPS];
296 extern struct wlan_pwr_cfg rtl8192E_hwpdn_flow
297 					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
298 					 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
299 					 RTL8192E_TRANS_END_STEPS];
300 extern struct wlan_pwr_cfg rtl8192E_enter_lps_flow
301 					[RTL8192E_TRANS_ACT_TO_LPS_STEPS +
302 					 RTL8192E_TRANS_END_STEPS];
303 extern struct wlan_pwr_cfg rtl8192E_leave_lps_flow
304 					[RTL8192E_TRANS_LPS_TO_ACT_STEPS +
305 					 RTL8192E_TRANS_END_STEPS];
306 
307 /* RTL8192EE Power Configuration CMDs for PCIe interface */
308 #define RTL8192E_NIC_PWR_ON_FLOW	rtl8192E_power_on_flow
309 #define RTL8192E_NIC_RF_OFF_FLOW	rtl8192E_radio_off_flow
310 #define RTL8192E_NIC_DISABLE_FLOW	rtl8192E_card_disable_flow
311 #define RTL8192E_NIC_ENABLE_FLOW	rtl8192E_card_enable_flow
312 #define RTL8192E_NIC_SUSPEND_FLOW	rtl8192E_suspend_flow
313 #define RTL8192E_NIC_RESUME_FLOW	rtl8192E_resume_flow
314 #define RTL8192E_NIC_PDN_FLOW		rtl8192E_hwpdn_flow
315 #define RTL8192E_NIC_LPS_ENTER_FLOW	rtl8192E_enter_lps_flow
316 #define RTL8192E_NIC_LPS_LEAVE_FLOW	rtl8192E_leave_lps_flow
317 
318 #endif
319