1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8821c.h" 12 #include "rtw8821c_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 #include "bf.h" 17 #include "regd.h" 18 19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52}; 20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17, 21 -20, -24, -28, -31, -34, -37, -40, -44}; 22 23 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse, 24 struct rtw8821c_efuse *map) 25 { 26 ether_addr_copy(efuse->addr, map->e.mac_addr); 27 } 28 29 static void rtw8821cu_efuse_parsing(struct rtw_efuse *efuse, 30 struct rtw8821c_efuse *map) 31 { 32 ether_addr_copy(efuse->addr, map->u.mac_addr); 33 } 34 35 enum rtw8821ce_rf_set { 36 SWITCH_TO_BTG, 37 SWITCH_TO_WLG, 38 SWITCH_TO_WLA, 39 SWITCH_TO_BT, 40 }; 41 42 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 43 { 44 struct rtw_efuse *efuse = &rtwdev->efuse; 45 struct rtw8821c_efuse *map; 46 int i; 47 48 map = (struct rtw8821c_efuse *)log_map; 49 50 efuse->rfe_option = map->rfe_option; 51 efuse->rf_board_option = map->rf_board_option; 52 efuse->crystal_cap = map->xtal_k; 53 efuse->pa_type_2g = map->pa_type; 54 efuse->pa_type_5g = map->pa_type; 55 efuse->lna_type_2g = map->lna_type_2g[0]; 56 efuse->lna_type_5g = map->lna_type_5g[0]; 57 efuse->channel_plan = map->channel_plan; 58 efuse->country_code[0] = map->country_code[0]; 59 efuse->country_code[1] = map->country_code[1]; 60 efuse->bt_setting = map->rf_bt_setting; 61 efuse->regd = map->rf_board_option & 0x7; 62 efuse->thermal_meter[0] = map->thermal_meter; 63 efuse->thermal_meter_k = map->thermal_meter; 64 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; 65 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; 66 67 for (i = 0; i < 4; i++) 68 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 69 70 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4) 71 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g; 72 73 switch (rtw_hci_type(rtwdev)) { 74 case RTW_HCI_TYPE_PCIE: 75 rtw8821ce_efuse_parsing(efuse, map); 76 break; 77 case RTW_HCI_TYPE_USB: 78 rtw8821cu_efuse_parsing(efuse, map); 79 break; 80 default: 81 /* unsupported now */ 82 return -ENOTSUPP; 83 } 84 85 return 0; 86 } 87 88 static const u32 rtw8821c_txscale_tbl[] = { 89 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 90 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 91 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 92 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 93 }; 94 95 static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev) 96 { 97 u8 i = 0; 98 u32 swing, table_value; 99 100 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000); 101 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) { 102 table_value = rtw8821c_txscale_tbl[i]; 103 if (swing == table_value) 104 break; 105 } 106 107 return i; 108 } 109 110 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev) 111 { 112 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 113 u8 swing_idx = rtw8821c_get_swing_index(rtwdev); 114 115 if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl)) 116 dm_info->default_ofdm_index = 24; 117 else 118 dm_info->default_ofdm_index = swing_idx; 119 120 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); 121 dm_info->delta_power_index[RF_PATH_A] = 0; 122 dm_info->delta_power_index_last[RF_PATH_A] = 0; 123 dm_info->pwr_trk_triggered = false; 124 dm_info->pwr_trk_init_trigger = true; 125 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 126 } 127 128 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev) 129 { 130 rtw_bf_phy_init(rtwdev); 131 /* Grouping bitmap parameters */ 132 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); 133 } 134 135 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev) 136 { 137 struct rtw_hal *hal = &rtwdev->hal; 138 u8 crystal_cap, val; 139 140 /* power on BB/RF domain */ 141 val = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 142 val |= BIT_FEN_PCIEA; 143 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 144 145 /* toggle BB reset */ 146 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 147 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 148 val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 149 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 150 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST; 151 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val); 152 153 rtw_write8(rtwdev, REG_RF_CTRL, 154 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 155 usleep_range(10, 11); 156 rtw_write8(rtwdev, REG_WLRF1 + 3, 157 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 158 usleep_range(10, 11); 159 160 /* pre init before header files config */ 161 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 162 163 rtw_phy_load_tables(rtwdev); 164 165 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 166 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); 167 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); 168 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); 169 170 /* post init after header files config */ 171 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 172 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); 173 hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); 174 hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); 175 176 rtw_phy_init(rtwdev); 177 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; 178 179 rtw8821c_pwrtrack_init(rtwdev); 180 181 rtw8821c_phy_bf_init(rtwdev); 182 } 183 184 static int rtw8821c_mac_init(struct rtw_dev *rtwdev) 185 { 186 u32 value32; 187 u16 pre_txcnt; 188 189 /* protocol configuration */ 190 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 191 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 192 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 193 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 194 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 195 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 196 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 197 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 198 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 199 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 200 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 201 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 202 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 203 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 204 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 205 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); 206 207 /* EDCA configuration */ 208 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 209 rtw_write16(rtwdev, REG_TXPAUSE, 0); 210 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 211 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 212 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 213 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 214 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 215 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 216 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 217 218 /* Set beacon cotnrol - enable TSF and other related functions */ 219 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 220 221 /* Set send beacon related registers */ 222 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 223 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 224 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 225 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 226 227 /* WMAC configuration */ 228 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 229 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 230 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 231 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 232 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 233 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 234 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40); 235 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); 236 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, 237 BIT_DIS_CHK_VHTSIGB_CRC); 238 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 239 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 240 241 return 0; 242 } 243 244 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 245 { 246 u8 ldo_pwr; 247 248 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 249 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); 250 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 251 } 252 253 static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set) 254 { 255 u32 reg; 256 257 rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST); 258 rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN); 259 260 reg = rtw_read32(rtwdev, REG_RFECTL); 261 switch (rf_set) { 262 case SWITCH_TO_BTG: 263 reg |= B_BTG_SWITCH; 264 reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH | 265 B_WLA_SWITCH); 266 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA); 267 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA); 268 break; 269 case SWITCH_TO_WLG: 270 reg |= B_WL_SWITCH | B_WLG_SWITCH; 271 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH); 272 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA); 273 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA); 274 break; 275 case SWITCH_TO_WLA: 276 reg |= B_WL_SWITCH | B_WLA_SWITCH; 277 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH); 278 break; 279 case SWITCH_TO_BT: 280 default: 281 break; 282 } 283 284 rtw_write32(rtwdev, REG_RFECTL, reg); 285 } 286 287 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 288 { 289 u32 rf_reg18; 290 291 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 292 293 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 294 RF18_BW_MASK); 295 296 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G); 297 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 298 299 if (channel >= 100 && channel <= 140) 300 rf_reg18 |= RF18_RFSI_GE; 301 else if (channel > 140) 302 rf_reg18 |= RF18_RFSI_GT; 303 304 switch (bw) { 305 case RTW_CHANNEL_WIDTH_5: 306 case RTW_CHANNEL_WIDTH_10: 307 case RTW_CHANNEL_WIDTH_20: 308 default: 309 rf_reg18 |= RF18_BW_20M; 310 break; 311 case RTW_CHANNEL_WIDTH_40: 312 rf_reg18 |= RF18_BW_40M; 313 break; 314 case RTW_CHANNEL_WIDTH_80: 315 rf_reg18 |= RF18_BW_80M; 316 break; 317 } 318 319 if (channel <= 14) { 320 if (rtwdev->efuse.rfe_option == 0) 321 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG); 322 else if (rtwdev->efuse.rfe_option == 2 || 323 rtwdev->efuse.rfe_option == 4) 324 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG); 325 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); 326 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf); 327 } else { 328 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA); 329 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); 330 } 331 332 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 333 334 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 335 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 336 } 337 338 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 339 { 340 if (bw == RTW_CHANNEL_WIDTH_40) { 341 /* RX DFIR for BW40 */ 342 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 343 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 344 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 345 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 346 } else if (bw == RTW_CHANNEL_WIDTH_80) { 347 /* RX DFIR for BW80 */ 348 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 349 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 350 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 351 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); 352 } else { 353 /* RX DFIR for BW20, BW10 and BW5 */ 354 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 355 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 356 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 357 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); 358 } 359 } 360 361 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 362 u8 primary_ch_idx) 363 { 364 struct rtw_hal *hal = &rtwdev->hal; 365 u32 val32; 366 367 if (channel <= 14) { 368 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 369 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 370 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 371 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 372 373 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); 374 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 375 if (channel == 14) { 376 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); 377 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 378 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); 379 } else { 380 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 381 hal->ch_param[0]); 382 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 383 hal->ch_param[1] & MASKLWORD); 384 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 385 hal->ch_param[2]); 386 } 387 } else if (channel > 35) { 388 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 389 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 390 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 391 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 392 393 if (channel >= 36 && channel <= 64) 394 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1); 395 else if (channel >= 100 && channel <= 144) 396 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2); 397 else if (channel >= 149) 398 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3); 399 400 if (channel >= 36 && channel <= 48) 401 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 402 else if (channel >= 52 && channel <= 64) 403 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 404 else if (channel >= 100 && channel <= 116) 405 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 406 else if (channel >= 118 && channel <= 177) 407 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 408 } 409 410 switch (bw) { 411 case RTW_CHANNEL_WIDTH_20: 412 default: 413 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 414 val32 &= 0xffcffc00; 415 val32 |= 0x10010000; 416 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 417 418 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 419 break; 420 case RTW_CHANNEL_WIDTH_40: 421 if (primary_ch_idx == 1) 422 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 423 else 424 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 425 426 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 427 val32 &= 0xff3ff300; 428 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | 429 RTW_CHANNEL_WIDTH_40; 430 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 431 432 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 433 break; 434 case RTW_CHANNEL_WIDTH_80: 435 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 436 val32 &= 0xfcffcf00; 437 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | 438 RTW_CHANNEL_WIDTH_80; 439 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 440 441 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 442 break; 443 case RTW_CHANNEL_WIDTH_5: 444 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 445 val32 &= 0xefcefc00; 446 val32 |= 0x200240; 447 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 448 449 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 450 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 451 break; 452 case RTW_CHANNEL_WIDTH_10: 453 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 454 val32 &= 0xefcefc00; 455 val32 |= 0x300380; 456 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 457 458 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 459 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 460 break; 461 } 462 } 463 464 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel) 465 { 466 struct rtw_efuse efuse = rtwdev->efuse; 467 u8 tx_bb_swing; 468 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; 469 470 tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g : 471 efuse.tx_bb_swing_setting_5g; 472 if (tx_bb_swing > 9) 473 tx_bb_swing = 0; 474 475 return swing2setting[(tx_bb_swing / 3)]; 476 } 477 478 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel, 479 u8 bw, u8 primary_ch_idx) 480 { 481 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 482 rtw8821c_get_bb_swing(rtwdev, channel)); 483 rtw8821c_pwrtrack_init(rtwdev); 484 } 485 486 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 487 u8 primary_chan_idx) 488 { 489 rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 490 rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx); 491 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 492 rtw8821c_set_channel_rf(rtwdev, channel, bw); 493 rtw8821c_set_channel_rxdfir(rtwdev, bw); 494 } 495 496 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx) 497 { 498 struct rtw_efuse *efuse = &rtwdev->efuse; 499 const s8 *lna_gain_table; 500 int lna_gain_table_size; 501 s8 rx_pwr_all = 0; 502 s8 lna_gain = 0; 503 504 if (efuse->rfe_option == 0) { 505 lna_gain_table = lna_gain_table_0; 506 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0); 507 } else { 508 lna_gain_table = lna_gain_table_1; 509 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1); 510 } 511 512 if (lna_idx >= lna_gain_table_size) { 513 rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx); 514 return -120; 515 } 516 517 lna_gain = lna_gain_table[lna_idx]; 518 rx_pwr_all = lna_gain - 2 * vga_idx; 519 520 return rx_pwr_all; 521 } 522 523 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 524 struct rtw_rx_pkt_stat *pkt_stat) 525 { 526 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 527 s8 rx_power; 528 u8 lna_idx = 0; 529 u8 vga_idx = 0; 530 531 vga_idx = GET_PHY_STAT_P0_VGA(phy_status); 532 lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) | 533 FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status)); 534 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx); 535 536 pkt_stat->rx_power[RF_PATH_A] = rx_power; 537 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 538 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 539 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 540 pkt_stat->signal_power = rx_power; 541 } 542 543 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 544 struct rtw_rx_pkt_stat *pkt_stat) 545 { 546 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 547 u8 rxsc, bw; 548 s8 min_rx_power = -120; 549 550 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 551 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 552 else 553 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 554 555 if (rxsc >= 1 && rxsc <= 8) 556 bw = RTW_CHANNEL_WIDTH_20; 557 else if (rxsc >= 9 && rxsc <= 12) 558 bw = RTW_CHANNEL_WIDTH_40; 559 else if (rxsc >= 13) 560 bw = RTW_CHANNEL_WIDTH_80; 561 else 562 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 563 564 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 565 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 566 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 567 pkt_stat->bw = bw; 568 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 569 min_rx_power); 570 } 571 572 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 573 struct rtw_rx_pkt_stat *pkt_stat) 574 { 575 u8 page; 576 577 page = *phy_status & 0xf; 578 579 switch (page) { 580 case 0: 581 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 582 break; 583 case 1: 584 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 585 break; 586 default: 587 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 588 return; 589 } 590 } 591 592 static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 593 struct rtw_rx_pkt_stat *pkt_stat, 594 struct ieee80211_rx_status *rx_status) 595 { 596 struct ieee80211_hdr *hdr; 597 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 598 u8 *phy_status = NULL; 599 600 memset(pkt_stat, 0, sizeof(*pkt_stat)); 601 602 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 603 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 604 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 605 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 606 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 607 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 608 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 609 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 610 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 611 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 612 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 613 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 614 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 615 616 /* drv_info_sz is in unit of 8-bytes */ 617 pkt_stat->drv_info_sz *= 8; 618 619 /* c2h cmd pkt's rx/phy status is not interested */ 620 if (pkt_stat->is_c2h) 621 return; 622 623 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 624 pkt_stat->drv_info_sz); 625 if (pkt_stat->phy_status) { 626 phy_status = rx_desc + desc_sz + pkt_stat->shift; 627 query_phy_status(rtwdev, phy_status, pkt_stat); 628 } 629 630 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 631 } 632 633 static void 634 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 635 { 636 struct rtw_hal *hal = &rtwdev->hal; 637 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 638 static u32 phy_pwr_idx; 639 u8 rate, rate_idx, pwr_index, shift; 640 int j; 641 642 for (j = 0; j < rtw_rate_size[rs]; j++) { 643 rate = rtw_rate_section[rs][j]; 644 pwr_index = hal->tx_pwr_tbl[path][rate]; 645 shift = rate & 0x3; 646 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 647 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) { 648 rate_idx = rate & 0xfc; 649 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 650 phy_pwr_idx); 651 phy_pwr_idx = 0; 652 } 653 } 654 } 655 656 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev) 657 { 658 struct rtw_hal *hal = &rtwdev->hal; 659 int rs, path; 660 661 for (path = 0; path < hal->rf_path_num; path++) { 662 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 663 if (rs == RTW_RATE_SECTION_HT_2S || 664 rs == RTW_RATE_SECTION_VHT_2S) 665 continue; 666 rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs); 667 } 668 } 669 } 670 671 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev) 672 { 673 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 674 u32 cck_enable; 675 u32 cck_fa_cnt; 676 u32 ofdm_fa_cnt; 677 u32 crc32_cnt; 678 u32 cca32_cnt; 679 680 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); 681 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK); 682 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM); 683 684 dm_info->cck_fa_cnt = cck_fa_cnt; 685 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 686 if (cck_enable) 687 dm_info->total_fa_cnt += cck_fa_cnt; 688 dm_info->total_fa_cnt = ofdm_fa_cnt; 689 690 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK); 691 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 692 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 693 694 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM); 695 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 696 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 697 698 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT); 699 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 700 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 701 702 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT); 703 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); 704 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); 705 706 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM); 707 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); 708 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 709 if (cck_enable) { 710 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK); 711 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); 712 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 713 } 714 715 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); 716 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); 717 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); 718 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); 719 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); 720 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); 721 } 722 723 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev) 724 { 725 static int do_iqk_cnt; 726 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 727 u32 rf_reg, iqk_fail_mask; 728 int counter; 729 bool reload; 730 731 if (rtw_is_assoc(rtwdev)) 732 para.segment_iqk = 1; 733 734 rtw_fw_do_iqk(rtwdev, ¶); 735 736 for (counter = 0; counter < 300; counter++) { 737 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 738 if (rf_reg == 0xabcde) 739 break; 740 msleep(20); 741 } 742 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 743 744 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 745 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 746 rtw_dbg(rtwdev, RTW_DBG_PHY, 747 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 748 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 749 } 750 751 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev) 752 { 753 rtw8821c_do_iqk(rtwdev); 754 } 755 756 /* for coex */ 757 static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev) 758 { 759 /* enable TBTT nterrupt */ 760 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 761 762 /* BT report packet sample rate */ 763 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 764 765 /* enable BT counter statistics */ 766 rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE); 767 768 /* enable PTA (3-wire function form BT side) */ 769 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 770 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 771 772 /* enable PTA (tx/rx signal form WiFi side) */ 773 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 774 /* wl tx signal to PTA not case EDCCA */ 775 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 776 /* GNT_BT=1 while select both */ 777 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 778 779 /* beacon queue always hi-pri */ 780 rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE, 781 BCN_PRI_EN); 782 } 783 784 static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, 785 u8 pos_type) 786 { 787 struct rtw_coex *coex = &rtwdev->coex; 788 struct rtw_coex_dm *coex_dm = &coex->dm; 789 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 790 u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type; 791 bool polarity_inverse; 792 u8 regval = 0; 793 794 if (switch_status == coex_dm->cur_switch_status) 795 return; 796 797 if (coex_rfe->wlg_at_btg) { 798 ctrl_type = COEX_SWITCH_CTRL_BY_BBSW; 799 800 if (coex_rfe->ant_switch_polarity) 801 pos_type = COEX_SWITCH_TO_WLA; 802 else 803 pos_type = COEX_SWITCH_TO_WLG_BT; 804 } 805 806 coex_dm->cur_switch_status = switch_status; 807 808 if (coex_rfe->ant_switch_diversity && 809 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) 810 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; 811 812 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); 813 814 switch (ctrl_type) { 815 default: 816 case COEX_SWITCH_CTRL_BY_BBSW: 817 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 818 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 819 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 820 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 821 DPDT_CTRL_PIN); 822 823 if (pos_type == COEX_SWITCH_TO_WLG_BT) { 824 if (coex_rfe->rfe_module_type != 0x4 && 825 coex_rfe->rfe_module_type != 0x2) 826 regval = 0x3; 827 else 828 regval = (!polarity_inverse ? 0x2 : 0x1); 829 } else if (pos_type == COEX_SWITCH_TO_WLG) { 830 regval = (!polarity_inverse ? 0x2 : 0x1); 831 } else { 832 regval = (!polarity_inverse ? 0x1 : 0x2); 833 } 834 835 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 836 regval); 837 break; 838 case COEX_SWITCH_CTRL_BY_PTA: 839 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 840 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 841 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 842 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 843 PTA_CTRL_PIN); 844 845 regval = (!polarity_inverse ? 0x2 : 0x1); 846 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15, 847 regval); 848 break; 849 case COEX_SWITCH_CTRL_BY_ANTDIV: 850 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 851 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 852 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 853 ANTDIC_CTRL_PIN); 854 break; 855 case COEX_SWITCH_CTRL_BY_MAC: 856 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 857 858 regval = (!polarity_inverse ? 0x0 : 0x1); 859 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, 860 regval); 861 break; 862 case COEX_SWITCH_CTRL_BY_FW: 863 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 864 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 865 break; 866 case COEX_SWITCH_CTRL_BY_BT: 867 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN); 868 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); 869 break; 870 } 871 872 if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) { 873 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 874 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 875 } else { 876 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1); 877 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2); 878 } 879 } 880 881 static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 882 {} 883 884 static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 885 { 886 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN); 887 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN); 888 rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN); 889 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS); 890 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT); 891 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT); 892 } 893 894 static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 895 { 896 struct rtw_coex *coex = &rtwdev->coex; 897 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 898 struct rtw_efuse *efuse = &rtwdev->efuse; 899 900 coex_rfe->rfe_module_type = efuse->rfe_option; 901 coex_rfe->ant_switch_polarity = 0; 902 coex_rfe->ant_switch_exist = true; 903 coex_rfe->wlg_at_btg = false; 904 905 switch (coex_rfe->rfe_module_type) { 906 case 0: 907 case 8: 908 case 1: 909 case 9: /* 1-Ant, Main, WLG */ 910 default: /* 2-Ant, DPDT, WLG */ 911 break; 912 case 2: 913 case 10: /* 1-Ant, Main, BTG */ 914 case 7: 915 case 15: /* 2-Ant, DPDT, BTG */ 916 coex_rfe->wlg_at_btg = true; 917 break; 918 case 3: 919 case 11: /* 1-Ant, Aux, WLG */ 920 coex_rfe->ant_switch_polarity = 1; 921 break; 922 case 4: 923 case 12: /* 1-Ant, Aux, BTG */ 924 coex_rfe->wlg_at_btg = true; 925 coex_rfe->ant_switch_polarity = 1; 926 break; 927 case 5: 928 case 13: /* 2-Ant, no switch, WLG */ 929 case 6: 930 case 14: /* 2-Ant, no antenna switch, WLG */ 931 coex_rfe->ant_switch_exist = false; 932 break; 933 } 934 } 935 936 static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 937 { 938 struct rtw_coex *coex = &rtwdev->coex; 939 struct rtw_coex_dm *coex_dm = &coex->dm; 940 struct rtw_efuse *efuse = &rtwdev->efuse; 941 bool share_ant = efuse->share_ant; 942 943 if (share_ant) 944 return; 945 946 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 947 return; 948 949 coex_dm->cur_wl_pwr_lvl = wl_pwr; 950 } 951 952 static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 953 {} 954 955 static void 956 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 957 s8 pwr_idx_offset_lower, 958 s8 *txagc_idx, u8 *swing_idx) 959 { 960 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 961 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; 962 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 963 u8 swing_lower_bound = 0; 964 u8 max_pwr_idx_offset = 0xf; 965 s8 agc_index = 0; 966 u8 swing_index = dm_info->default_ofdm_index; 967 968 pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset); 969 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); 970 971 if (delta_pwr_idx >= 0) { 972 if (delta_pwr_idx <= pwr_idx_offset) { 973 agc_index = delta_pwr_idx; 974 swing_index = dm_info->default_ofdm_index; 975 } else if (delta_pwr_idx > pwr_idx_offset) { 976 agc_index = pwr_idx_offset; 977 swing_index = dm_info->default_ofdm_index + 978 delta_pwr_idx - pwr_idx_offset; 979 swing_index = min_t(u8, swing_index, swing_upper_bound); 980 } 981 } else if (delta_pwr_idx < 0) { 982 if (delta_pwr_idx >= pwr_idx_offset_lower) { 983 agc_index = delta_pwr_idx; 984 swing_index = dm_info->default_ofdm_index; 985 } else if (delta_pwr_idx < pwr_idx_offset_lower) { 986 if (dm_info->default_ofdm_index > 987 (pwr_idx_offset_lower - delta_pwr_idx)) 988 swing_index = dm_info->default_ofdm_index + 989 delta_pwr_idx - pwr_idx_offset_lower; 990 else 991 swing_index = swing_lower_bound; 992 993 agc_index = pwr_idx_offset_lower; 994 } 995 } 996 997 if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) { 998 rtw_warn(rtwdev, "swing index overflow\n"); 999 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; 1000 } 1001 1002 *txagc_idx = agc_index; 1003 *swing_idx = swing_index; 1004 } 1005 1006 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset, 1007 s8 pwr_idx_offset_lower) 1008 { 1009 s8 txagc_idx; 1010 u8 swing_idx; 1011 1012 rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower, 1013 &txagc_idx, &swing_idx); 1014 rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx); 1015 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21), 1016 rtw8821c_txscale_tbl[swing_idx]); 1017 } 1018 1019 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev) 1020 { 1021 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1022 u8 pwr_idx_offset, tx_pwr_idx; 1023 s8 pwr_idx_offset_lower; 1024 u8 channel = rtwdev->hal.current_channel; 1025 u8 band_width = rtwdev->hal.current_band_width; 1026 u8 regd = rtw_regd_get(rtwdev); 1027 u8 tx_rate = dm_info->tx_rate; 1028 u8 max_pwr_idx = rtwdev->chip->max_power_index; 1029 1030 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate, 1031 band_width, channel, regd); 1032 1033 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 1034 1035 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 1036 pwr_idx_offset_lower = 0 - tx_pwr_idx; 1037 1038 rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower); 1039 } 1040 1041 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev) 1042 { 1043 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1044 struct rtw_swing_table swing_table; 1045 u8 thermal_value, delta; 1046 1047 rtw_phy_config_swing_table(rtwdev, &swing_table); 1048 1049 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1050 return; 1051 1052 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1053 1054 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1055 1056 if (dm_info->pwr_trk_init_trigger) 1057 dm_info->pwr_trk_init_trigger = false; 1058 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1059 RF_PATH_A)) 1060 goto iqk; 1061 1062 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1063 1064 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1065 1066 dm_info->delta_power_index[RF_PATH_A] = 1067 rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A, 1068 RF_PATH_A, delta); 1069 if (dm_info->delta_power_index[RF_PATH_A] == 1070 dm_info->delta_power_index_last[RF_PATH_A]) 1071 goto iqk; 1072 else 1073 dm_info->delta_power_index_last[RF_PATH_A] = 1074 dm_info->delta_power_index[RF_PATH_A]; 1075 rtw8821c_pwrtrack_set(rtwdev); 1076 1077 iqk: 1078 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 1079 rtw8821c_do_iqk(rtwdev); 1080 } 1081 1082 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev) 1083 { 1084 struct rtw_efuse *efuse = &rtwdev->efuse; 1085 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1086 1087 if (efuse->power_track_type != 0) 1088 return; 1089 1090 if (!dm_info->pwr_trk_triggered) { 1091 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1092 GENMASK(17, 16), 0x03); 1093 dm_info->pwr_trk_triggered = true; 1094 return; 1095 } 1096 1097 rtw8821c_phy_pwrtrack(rtwdev); 1098 dm_info->pwr_trk_triggered = false; 1099 } 1100 1101 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev, 1102 struct rtw_vif *vif, 1103 struct rtw_bfee *bfee, bool enable) 1104 { 1105 if (enable) 1106 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 1107 else 1108 rtw_bf_remove_bfee_su(rtwdev, bfee); 1109 } 1110 1111 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 1112 struct rtw_vif *vif, 1113 struct rtw_bfee *bfee, bool enable) 1114 { 1115 if (enable) 1116 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 1117 else 1118 rtw_bf_remove_bfee_mu(rtwdev, bfee); 1119 } 1120 1121 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 1122 struct rtw_bfee *bfee, bool enable) 1123 { 1124 if (bfee->role == RTW_BFEE_SU) 1125 rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 1126 else if (bfee->role == RTW_BFEE_MU) 1127 rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 1128 else 1129 rtw_warn(rtwdev, "wrong bfee role\n"); 1130 } 1131 1132 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 1133 { 1134 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1135 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13}; 1136 u8 cck_n_rx; 1137 1138 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", 1139 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); 1140 1141 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 1142 return; 1143 1144 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) && 1145 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1; 1146 rtw_dbg(rtwdev, RTW_DBG_PHY, 1147 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", 1148 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx, 1149 dm_info->cck_pd_default + new_lvl * 2, 1150 pd[new_lvl], dm_info->cck_fa_avg); 1151 1152 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 1153 1154 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 1155 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); 1156 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, 1157 dm_info->cck_pd_default + new_lvl * 2); 1158 } 1159 1160 static void rtw8821c_fill_txdesc_checksum(struct rtw_dev *rtwdev, 1161 struct rtw_tx_pkt_info *pkt_info, 1162 u8 *txdesc) 1163 { 1164 fill_txdesc_checksum_common(txdesc, 16); 1165 } 1166 1167 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = { 1168 {0x0086, 1169 RTW_PWR_CUT_ALL_MSK, 1170 RTW_PWR_INTF_SDIO_MSK, 1171 RTW_PWR_ADDR_SDIO, 1172 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1173 {0x0086, 1174 RTW_PWR_CUT_ALL_MSK, 1175 RTW_PWR_INTF_SDIO_MSK, 1176 RTW_PWR_ADDR_SDIO, 1177 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1178 {0x004A, 1179 RTW_PWR_CUT_ALL_MSK, 1180 RTW_PWR_INTF_USB_MSK, 1181 RTW_PWR_ADDR_MAC, 1182 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1183 {0x0005, 1184 RTW_PWR_CUT_ALL_MSK, 1185 RTW_PWR_INTF_ALL_MSK, 1186 RTW_PWR_ADDR_MAC, 1187 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1188 {0x0300, 1189 RTW_PWR_CUT_ALL_MSK, 1190 RTW_PWR_INTF_PCI_MSK, 1191 RTW_PWR_ADDR_MAC, 1192 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1193 {0x0301, 1194 RTW_PWR_CUT_ALL_MSK, 1195 RTW_PWR_INTF_PCI_MSK, 1196 RTW_PWR_ADDR_MAC, 1197 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1198 {0xFFFF, 1199 RTW_PWR_CUT_ALL_MSK, 1200 RTW_PWR_INTF_ALL_MSK, 1201 0, 1202 RTW_PWR_CMD_END, 0, 0}, 1203 }; 1204 1205 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = { 1206 {0x0020, 1207 RTW_PWR_CUT_ALL_MSK, 1208 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1209 RTW_PWR_ADDR_MAC, 1210 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1211 {0x0001, 1212 RTW_PWR_CUT_ALL_MSK, 1213 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1214 RTW_PWR_ADDR_MAC, 1215 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1216 {0x0000, 1217 RTW_PWR_CUT_ALL_MSK, 1218 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1219 RTW_PWR_ADDR_MAC, 1220 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1221 {0x0005, 1222 RTW_PWR_CUT_ALL_MSK, 1223 RTW_PWR_INTF_ALL_MSK, 1224 RTW_PWR_ADDR_MAC, 1225 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1226 {0x0075, 1227 RTW_PWR_CUT_ALL_MSK, 1228 RTW_PWR_INTF_PCI_MSK, 1229 RTW_PWR_ADDR_MAC, 1230 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1231 {0x0006, 1232 RTW_PWR_CUT_ALL_MSK, 1233 RTW_PWR_INTF_ALL_MSK, 1234 RTW_PWR_ADDR_MAC, 1235 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1236 {0x0075, 1237 RTW_PWR_CUT_ALL_MSK, 1238 RTW_PWR_INTF_PCI_MSK, 1239 RTW_PWR_ADDR_MAC, 1240 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1241 {0x0006, 1242 RTW_PWR_CUT_ALL_MSK, 1243 RTW_PWR_INTF_ALL_MSK, 1244 RTW_PWR_ADDR_MAC, 1245 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1246 {0x0005, 1247 RTW_PWR_CUT_ALL_MSK, 1248 RTW_PWR_INTF_ALL_MSK, 1249 RTW_PWR_ADDR_MAC, 1250 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1251 {0x0005, 1252 RTW_PWR_CUT_ALL_MSK, 1253 RTW_PWR_INTF_ALL_MSK, 1254 RTW_PWR_ADDR_MAC, 1255 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1256 {0x10C3, 1257 RTW_PWR_CUT_ALL_MSK, 1258 RTW_PWR_INTF_USB_MSK, 1259 RTW_PWR_ADDR_MAC, 1260 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1261 {0x0005, 1262 RTW_PWR_CUT_ALL_MSK, 1263 RTW_PWR_INTF_ALL_MSK, 1264 RTW_PWR_ADDR_MAC, 1265 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1266 {0x0005, 1267 RTW_PWR_CUT_ALL_MSK, 1268 RTW_PWR_INTF_ALL_MSK, 1269 RTW_PWR_ADDR_MAC, 1270 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1271 {0x0020, 1272 RTW_PWR_CUT_ALL_MSK, 1273 RTW_PWR_INTF_ALL_MSK, 1274 RTW_PWR_ADDR_MAC, 1275 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1276 {0x0074, 1277 RTW_PWR_CUT_ALL_MSK, 1278 RTW_PWR_INTF_PCI_MSK, 1279 RTW_PWR_ADDR_MAC, 1280 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1281 {0x0022, 1282 RTW_PWR_CUT_ALL_MSK, 1283 RTW_PWR_INTF_PCI_MSK, 1284 RTW_PWR_ADDR_MAC, 1285 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1286 {0x0062, 1287 RTW_PWR_CUT_ALL_MSK, 1288 RTW_PWR_INTF_PCI_MSK, 1289 RTW_PWR_ADDR_MAC, 1290 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 1291 (BIT(7) | BIT(6) | BIT(5))}, 1292 {0x0061, 1293 RTW_PWR_CUT_ALL_MSK, 1294 RTW_PWR_INTF_PCI_MSK, 1295 RTW_PWR_ADDR_MAC, 1296 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 1297 {0x007C, 1298 RTW_PWR_CUT_ALL_MSK, 1299 RTW_PWR_INTF_ALL_MSK, 1300 RTW_PWR_ADDR_MAC, 1301 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1302 {0xFFFF, 1303 RTW_PWR_CUT_ALL_MSK, 1304 RTW_PWR_INTF_ALL_MSK, 1305 0, 1306 RTW_PWR_CMD_END, 0, 0}, 1307 }; 1308 1309 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = { 1310 {0x0093, 1311 RTW_PWR_CUT_ALL_MSK, 1312 RTW_PWR_INTF_ALL_MSK, 1313 RTW_PWR_ADDR_MAC, 1314 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1315 {0x001F, 1316 RTW_PWR_CUT_ALL_MSK, 1317 RTW_PWR_INTF_ALL_MSK, 1318 RTW_PWR_ADDR_MAC, 1319 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1320 {0x0049, 1321 RTW_PWR_CUT_ALL_MSK, 1322 RTW_PWR_INTF_ALL_MSK, 1323 RTW_PWR_ADDR_MAC, 1324 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1325 {0x0006, 1326 RTW_PWR_CUT_ALL_MSK, 1327 RTW_PWR_INTF_ALL_MSK, 1328 RTW_PWR_ADDR_MAC, 1329 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1330 {0x0002, 1331 RTW_PWR_CUT_ALL_MSK, 1332 RTW_PWR_INTF_ALL_MSK, 1333 RTW_PWR_ADDR_MAC, 1334 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1335 {0x10C3, 1336 RTW_PWR_CUT_ALL_MSK, 1337 RTW_PWR_INTF_USB_MSK, 1338 RTW_PWR_ADDR_MAC, 1339 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1340 {0x0005, 1341 RTW_PWR_CUT_ALL_MSK, 1342 RTW_PWR_INTF_ALL_MSK, 1343 RTW_PWR_ADDR_MAC, 1344 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1345 {0x0005, 1346 RTW_PWR_CUT_ALL_MSK, 1347 RTW_PWR_INTF_ALL_MSK, 1348 RTW_PWR_ADDR_MAC, 1349 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1350 {0x0020, 1351 RTW_PWR_CUT_ALL_MSK, 1352 RTW_PWR_INTF_ALL_MSK, 1353 RTW_PWR_ADDR_MAC, 1354 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1355 {0x0000, 1356 RTW_PWR_CUT_ALL_MSK, 1357 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1358 RTW_PWR_ADDR_MAC, 1359 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1360 {0xFFFF, 1361 RTW_PWR_CUT_ALL_MSK, 1362 RTW_PWR_INTF_ALL_MSK, 1363 0, 1364 RTW_PWR_CMD_END, 0, 0}, 1365 }; 1366 1367 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = { 1368 {0x0007, 1369 RTW_PWR_CUT_ALL_MSK, 1370 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1371 RTW_PWR_ADDR_MAC, 1372 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1373 {0x0067, 1374 RTW_PWR_CUT_ALL_MSK, 1375 RTW_PWR_INTF_ALL_MSK, 1376 RTW_PWR_ADDR_MAC, 1377 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1378 {0x0005, 1379 RTW_PWR_CUT_ALL_MSK, 1380 RTW_PWR_INTF_PCI_MSK, 1381 RTW_PWR_ADDR_MAC, 1382 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1383 {0x004A, 1384 RTW_PWR_CUT_ALL_MSK, 1385 RTW_PWR_INTF_USB_MSK, 1386 RTW_PWR_ADDR_MAC, 1387 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1388 {0x0067, 1389 RTW_PWR_CUT_ALL_MSK, 1390 RTW_PWR_INTF_SDIO_MSK, 1391 RTW_PWR_ADDR_MAC, 1392 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1393 {0x0067, 1394 RTW_PWR_CUT_ALL_MSK, 1395 RTW_PWR_INTF_SDIO_MSK, 1396 RTW_PWR_ADDR_MAC, 1397 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1398 {0x004F, 1399 RTW_PWR_CUT_ALL_MSK, 1400 RTW_PWR_INTF_SDIO_MSK, 1401 RTW_PWR_ADDR_MAC, 1402 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1403 {0x0067, 1404 RTW_PWR_CUT_ALL_MSK, 1405 RTW_PWR_INTF_SDIO_MSK, 1406 RTW_PWR_ADDR_MAC, 1407 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1408 {0x0046, 1409 RTW_PWR_CUT_ALL_MSK, 1410 RTW_PWR_INTF_SDIO_MSK, 1411 RTW_PWR_ADDR_MAC, 1412 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1413 {0x0067, 1414 RTW_PWR_CUT_ALL_MSK, 1415 RTW_PWR_INTF_SDIO_MSK, 1416 RTW_PWR_ADDR_MAC, 1417 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1418 {0x0046, 1419 RTW_PWR_CUT_ALL_MSK, 1420 RTW_PWR_INTF_SDIO_MSK, 1421 RTW_PWR_ADDR_MAC, 1422 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1423 {0x0062, 1424 RTW_PWR_CUT_ALL_MSK, 1425 RTW_PWR_INTF_SDIO_MSK, 1426 RTW_PWR_ADDR_MAC, 1427 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1428 {0x0081, 1429 RTW_PWR_CUT_ALL_MSK, 1430 RTW_PWR_INTF_ALL_MSK, 1431 RTW_PWR_ADDR_MAC, 1432 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1433 {0x0005, 1434 RTW_PWR_CUT_ALL_MSK, 1435 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1436 RTW_PWR_ADDR_MAC, 1437 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1438 {0x0086, 1439 RTW_PWR_CUT_ALL_MSK, 1440 RTW_PWR_INTF_SDIO_MSK, 1441 RTW_PWR_ADDR_SDIO, 1442 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1443 {0x0086, 1444 RTW_PWR_CUT_ALL_MSK, 1445 RTW_PWR_INTF_SDIO_MSK, 1446 RTW_PWR_ADDR_SDIO, 1447 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1448 {0x0090, 1449 RTW_PWR_CUT_ALL_MSK, 1450 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1451 RTW_PWR_ADDR_MAC, 1452 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1453 {0x0044, 1454 RTW_PWR_CUT_ALL_MSK, 1455 RTW_PWR_INTF_SDIO_MSK, 1456 RTW_PWR_ADDR_SDIO, 1457 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1458 {0x0040, 1459 RTW_PWR_CUT_ALL_MSK, 1460 RTW_PWR_INTF_SDIO_MSK, 1461 RTW_PWR_ADDR_SDIO, 1462 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1463 {0x0041, 1464 RTW_PWR_CUT_ALL_MSK, 1465 RTW_PWR_INTF_SDIO_MSK, 1466 RTW_PWR_ADDR_SDIO, 1467 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1468 {0x0042, 1469 RTW_PWR_CUT_ALL_MSK, 1470 RTW_PWR_INTF_SDIO_MSK, 1471 RTW_PWR_ADDR_SDIO, 1472 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1473 {0xFFFF, 1474 RTW_PWR_CUT_ALL_MSK, 1475 RTW_PWR_INTF_ALL_MSK, 1476 0, 1477 RTW_PWR_CMD_END, 0, 0}, 1478 }; 1479 1480 static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = { 1481 trans_carddis_to_cardemu_8821c, 1482 trans_cardemu_to_act_8821c, 1483 NULL 1484 }; 1485 1486 static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = { 1487 trans_act_to_cardemu_8821c, 1488 trans_cardemu_to_carddis_8821c, 1489 NULL 1490 }; 1491 1492 static const struct rtw_intf_phy_para usb2_param_8821c[] = { 1493 {0xFFFF, 0x00, 1494 RTW_IP_SEL_PHY, 1495 RTW_INTF_PHY_CUT_ALL, 1496 RTW_INTF_PHY_PLATFORM_ALL}, 1497 }; 1498 1499 static const struct rtw_intf_phy_para usb3_param_8821c[] = { 1500 {0xFFFF, 0x0000, 1501 RTW_IP_SEL_PHY, 1502 RTW_INTF_PHY_CUT_ALL, 1503 RTW_INTF_PHY_PLATFORM_ALL}, 1504 }; 1505 1506 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = { 1507 {0x0009, 0x6380, 1508 RTW_IP_SEL_PHY, 1509 RTW_INTF_PHY_CUT_ALL, 1510 RTW_INTF_PHY_PLATFORM_ALL}, 1511 {0xFFFF, 0x0000, 1512 RTW_IP_SEL_PHY, 1513 RTW_INTF_PHY_CUT_ALL, 1514 RTW_INTF_PHY_PLATFORM_ALL}, 1515 }; 1516 1517 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = { 1518 {0xFFFF, 0x0000, 1519 RTW_IP_SEL_PHY, 1520 RTW_INTF_PHY_CUT_ALL, 1521 RTW_INTF_PHY_PLATFORM_ALL}, 1522 }; 1523 1524 static const struct rtw_intf_phy_para_table phy_para_table_8821c = { 1525 .usb2_para = usb2_param_8821c, 1526 .usb3_para = usb3_param_8821c, 1527 .gen1_para = pcie_gen1_param_8821c, 1528 .gen2_para = pcie_gen2_param_8821c, 1529 .n_usb2_para = ARRAY_SIZE(usb2_param_8821c), 1530 .n_usb3_para = ARRAY_SIZE(usb2_param_8821c), 1531 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8821c), 1532 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c), 1533 }; 1534 1535 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = { 1536 [0] = RTW_DEF_RFE(8821c, 0, 0), 1537 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2), 1538 [4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2), 1539 [6] = RTW_DEF_RFE(8821c, 0, 0), 1540 [34] = RTW_DEF_RFE(8821c, 0, 0), 1541 }; 1542 1543 static struct rtw_hw_reg rtw8821c_dig[] = { 1544 [0] = { .addr = 0xc50, .mask = 0x7f }, 1545 }; 1546 1547 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = { 1548 .ctrl = LTECOEX_ACCESS_CTRL, 1549 .wdata = LTECOEX_WRITE_DATA, 1550 .rdata = LTECOEX_READ_DATA, 1551 }; 1552 1553 static struct rtw_page_table page_table_8821c[] = { 1554 /* not sure what [0] stands for */ 1555 {16, 16, 16, 14, 1}, 1556 {16, 16, 16, 14, 1}, 1557 {16, 16, 0, 0, 1}, 1558 {16, 16, 16, 0, 1}, 1559 {16, 16, 16, 14, 1}, 1560 }; 1561 1562 static struct rtw_rqpn rqpn_table_8821c[] = { 1563 /* not sure what [0] stands for */ 1564 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1565 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1566 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1567 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1568 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1569 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1570 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1571 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 1572 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1573 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1574 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1575 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 1576 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 1577 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 1578 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 1579 }; 1580 1581 static struct rtw_prioq_addrs prioq_addrs_8821c = { 1582 .prio[RTW_DMA_MAPPING_EXTRA] = { 1583 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 1584 }, 1585 .prio[RTW_DMA_MAPPING_LOW] = { 1586 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 1587 }, 1588 .prio[RTW_DMA_MAPPING_NORMAL] = { 1589 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 1590 }, 1591 .prio[RTW_DMA_MAPPING_HIGH] = { 1592 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 1593 }, 1594 .wsize = true, 1595 }; 1596 1597 static struct rtw_chip_ops rtw8821c_ops = { 1598 .phy_set_param = rtw8821c_phy_set_param, 1599 .read_efuse = rtw8821c_read_efuse, 1600 .query_rx_desc = rtw8821c_query_rx_desc, 1601 .set_channel = rtw8821c_set_channel, 1602 .mac_init = rtw8821c_mac_init, 1603 .read_rf = rtw_phy_read_rf, 1604 .write_rf = rtw_phy_write_rf_reg_sipi, 1605 .set_antenna = NULL, 1606 .set_tx_power_index = rtw8821c_set_tx_power_index, 1607 .cfg_ldo25 = rtw8821c_cfg_ldo25, 1608 .false_alarm_statistics = rtw8821c_false_alarm_statistics, 1609 .phy_calibration = rtw8821c_phy_calibration, 1610 .cck_pd_set = rtw8821c_phy_cck_pd_set, 1611 .pwr_track = rtw8821c_pwr_track, 1612 .config_bfee = rtw8821c_bf_config_bfee, 1613 .set_gid_table = rtw_bf_set_gid_table, 1614 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 1615 .fill_txdesc_checksum = rtw8821c_fill_txdesc_checksum, 1616 1617 .coex_set_init = rtw8821c_coex_cfg_init, 1618 .coex_set_ant_switch = rtw8821c_coex_cfg_ant_switch, 1619 .coex_set_gnt_fix = rtw8821c_coex_cfg_gnt_fix, 1620 .coex_set_gnt_debug = rtw8821c_coex_cfg_gnt_debug, 1621 .coex_set_rfe_type = rtw8821c_coex_cfg_rfe_type, 1622 .coex_set_wl_tx_power = rtw8821c_coex_cfg_wl_tx_power, 1623 .coex_set_wl_rx_gain = rtw8821c_coex_cfg_wl_rx_gain, 1624 }; 1625 1626 /* rssi in percentage % (dbm = % - 100) */ 1627 static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40}; 1628 static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101}; 1629 1630 /* Shared-Antenna Coex Table */ 1631 static const struct coex_table_para table_sant_8821c[] = { 1632 {0x55555555, 0x55555555}, /* case-0 */ 1633 {0x55555555, 0x55555555}, 1634 {0x66555555, 0x66555555}, 1635 {0xaaaaaaaa, 0xaaaaaaaa}, 1636 {0x5a5a5a5a, 0x5a5a5a5a}, 1637 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1638 {0x6a5a5555, 0xaaaaaaaa}, 1639 {0x6a5a56aa, 0x6a5a56aa}, 1640 {0x6a5a5a5a, 0x6a5a5a5a}, 1641 {0x66555555, 0x5a5a5a5a}, 1642 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1643 {0x66555555, 0xaaaaaaaa}, 1644 {0x66555555, 0x6a5a5aaa}, 1645 {0x66555555, 0x6aaa6aaa}, 1646 {0x66555555, 0x6a5a5aaa}, 1647 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1648 {0xffff55ff, 0xfafafafa}, 1649 {0xffff55ff, 0x6afa5afa}, 1650 {0xaaffffaa, 0xfafafafa}, 1651 {0xaa5555aa, 0x5a5a5a5a}, 1652 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1653 {0xaa5555aa, 0xaaaaaaaa}, 1654 {0xffffffff, 0x55555555}, 1655 {0xffffffff, 0x5a5a5a5a}, 1656 {0xffffffff, 0x5a5a5a5a}, 1657 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 1658 {0x55555555, 0x5a5a5a5a}, 1659 {0x55555555, 0xaaaaaaaa}, 1660 {0x66555555, 0x6a5a6a5a}, 1661 {0x66556655, 0x66556655}, 1662 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 1663 {0xffffffff, 0x5aaa5aaa}, 1664 {0x56555555, 0x5a5a5aaa} 1665 }; 1666 1667 /* Non-Shared-Antenna Coex Table */ 1668 static const struct coex_table_para table_nsant_8821c[] = { 1669 {0xffffffff, 0xffffffff}, /* case-100 */ 1670 {0xffff55ff, 0xfafafafa}, 1671 {0x66555555, 0x66555555}, 1672 {0xaaaaaaaa, 0xaaaaaaaa}, 1673 {0x5a5a5a5a, 0x5a5a5a5a}, 1674 {0xffffffff, 0xffffffff}, /* case-105 */ 1675 {0x5afa5afa, 0x5afa5afa}, 1676 {0x55555555, 0xfafafafa}, 1677 {0x66555555, 0xfafafafa}, 1678 {0x66555555, 0x5a5a5a5a}, 1679 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 1680 {0x66555555, 0xaaaaaaaa}, 1681 {0xffff55ff, 0xfafafafa}, 1682 {0xffff55ff, 0x5afa5afa}, 1683 {0xffff55ff, 0xaaaaaaaa}, 1684 {0xffff55ff, 0xffff55ff}, /* case-115 */ 1685 {0xaaffffaa, 0x5afa5afa}, 1686 {0xaaffffaa, 0xaaaaaaaa}, 1687 {0xffffffff, 0xfafafafa}, 1688 {0xffff55ff, 0xfafafafa}, 1689 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 1690 {0xffff55ff, 0x5afa5afa}, 1691 {0xffff55ff, 0x5afa5afa}, 1692 {0x55ff55ff, 0x55ff55ff} 1693 }; 1694 1695 /* Shared-Antenna TDMA */ 1696 static const struct coex_tdma_para tdma_sant_8821c[] = { 1697 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1698 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1699 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1700 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1701 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1702 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */ 1703 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1704 { {0x61, 0x35, 0x03, 0x11, 0x10} }, 1705 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1706 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1707 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1708 { {0x61, 0x08, 0x03, 0x11, 0x15} }, 1709 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1710 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1711 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1712 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1713 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1714 { {0x51, 0x3a, 0x03, 0x11, 0x50} }, 1715 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1716 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1717 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1718 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1719 { {0x51, 0x08, 0x03, 0x30, 0x54} }, 1720 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1721 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1722 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1723 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1724 { {0x61, 0x08, 0x03, 0x11, 0x11} } 1725 }; 1726 1727 /* Non-Shared-Antenna TDMA */ 1728 static const struct coex_tdma_para tdma_nsant_8821c[] = { 1729 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */ 1730 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 1731 { {0x61, 0x25, 0x03, 0x11, 0x11} }, 1732 { {0x61, 0x35, 0x03, 0x11, 0x11} }, 1733 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1734 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 1735 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1736 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1737 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1738 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1739 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 1740 { {0x61, 0x10, 0x03, 0x11, 0x11} }, 1741 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1742 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1743 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1744 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 1745 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1746 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1747 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1748 { {0x51, 0x21, 0x03, 0x10, 0x50} }, 1749 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */ 1750 { {0x51, 0x10, 0x03, 0x10, 0x50} } 1751 }; 1752 1753 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} }; 1754 1755 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 1756 static const struct coex_rf_para rf_para_tx_8821c[] = { 1757 {0, 0, false, 7}, /* for normal */ 1758 {0, 20, false, 7}, /* for WL-CPT */ 1759 {8, 17, true, 4}, 1760 {7, 18, true, 4}, 1761 {6, 19, true, 4}, 1762 {5, 20, true, 4} 1763 }; 1764 1765 static const struct coex_rf_para rf_para_rx_8821c[] = { 1766 {0, 0, false, 7}, /* for normal */ 1767 {0, 20, false, 7}, /* for WL-CPT */ 1768 {3, 24, true, 5}, 1769 {2, 26, true, 5}, 1770 {1, 27, true, 5}, 1771 {0, 28, true, 5} 1772 }; 1773 1774 static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c)); 1775 1776 static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = { 1777 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1778 11, 11, 12, 12, 12, 12, 12}, 1779 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1780 11, 12, 12, 12, 12, 12, 12, 12}, 1781 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1782 11, 12, 12, 12, 12, 12, 12}, 1783 }; 1784 1785 static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = { 1786 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1787 12, 12, 12, 12, 12, 12, 12}, 1788 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1789 12, 12, 12, 12, 12, 12, 12, 12}, 1790 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1791 11, 12, 12, 12, 12, 12, 12, 12}, 1792 }; 1793 1794 static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = { 1795 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 1796 11, 11, 12, 12, 12, 12, 12}, 1797 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 1798 11, 12, 12, 12, 12, 12, 12, 12}, 1799 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 1800 11, 12, 12, 12, 12, 12, 12}, 1801 }; 1802 1803 static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = { 1804 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 1805 12, 12, 12, 12, 12, 12, 12}, 1806 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 1807 12, 12, 12, 12, 12, 12, 12, 12}, 1808 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 1809 11, 12, 12, 12, 12, 12, 12, 12}, 1810 }; 1811 1812 static const u8 rtw8821c_pwrtrk_2gb_n[] = { 1813 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1814 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1815 }; 1816 1817 static const u8 rtw8821c_pwrtrk_2gb_p[] = { 1818 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1819 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1820 }; 1821 1822 static const u8 rtw8821c_pwrtrk_2ga_n[] = { 1823 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 1824 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9 1825 }; 1826 1827 static const u8 rtw8821c_pwrtrk_2ga_p[] = { 1828 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 1829 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9 1830 }; 1831 1832 static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = { 1833 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1834 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1835 }; 1836 1837 static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = { 1838 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1839 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1840 }; 1841 1842 static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = { 1843 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 1844 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9 1845 }; 1846 1847 static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = { 1848 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 1849 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9 1850 }; 1851 1852 static const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = { 1853 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0], 1854 .pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1], 1855 .pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2], 1856 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0], 1857 .pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1], 1858 .pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2], 1859 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0], 1860 .pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1], 1861 .pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2], 1862 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0], 1863 .pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1], 1864 .pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2], 1865 .pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n, 1866 .pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p, 1867 .pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n, 1868 .pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p, 1869 .pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n, 1870 .pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p, 1871 .pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n, 1872 .pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p, 1873 }; 1874 1875 static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = { 1876 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1877 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1878 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1879 {0, 0, RTW_REG_DOMAIN_NL}, 1880 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1881 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1882 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1883 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1884 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 1885 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 1886 {0, 0, RTW_REG_DOMAIN_NL}, 1887 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 1888 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 1889 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 1890 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 1891 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A}, 1892 {0, 0, RTW_REG_DOMAIN_NL}, 1893 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 1894 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1895 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 1896 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1897 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 1898 }; 1899 1900 const struct rtw_chip_info rtw8821c_hw_spec = { 1901 .ops = &rtw8821c_ops, 1902 .id = RTW_CHIP_TYPE_8821C, 1903 .fw_name = "rtw88/rtw8821c_fw.bin", 1904 .wlan_cpu = RTW_WCPU_11AC, 1905 .tx_pkt_desc_sz = 48, 1906 .tx_buf_desc_sz = 16, 1907 .rx_pkt_desc_sz = 24, 1908 .rx_buf_desc_sz = 8, 1909 .phy_efuse_size = 512, 1910 .log_efuse_size = 512, 1911 .ptct_efuse_size = 96, 1912 .txff_size = 65536, 1913 .rxff_size = 16384, 1914 .txgi_factor = 1, 1915 .is_pwr_by_rate_dec = true, 1916 .max_power_index = 0x3f, 1917 .csi_buf_pg_num = 0, 1918 .band = RTW_BAND_2G | RTW_BAND_5G, 1919 .page_size = TX_PAGE_SIZE, 1920 .dig_min = 0x1c, 1921 .ht_supported = true, 1922 .vht_supported = true, 1923 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 1924 .sys_func_en = 0xD8, 1925 .pwr_on_seq = card_enable_flow_8821c, 1926 .pwr_off_seq = card_disable_flow_8821c, 1927 .page_table = page_table_8821c, 1928 .rqpn_table = rqpn_table_8821c, 1929 .prioq_addrs = &prioq_addrs_8821c, 1930 .intf_table = &phy_para_table_8821c, 1931 .dig = rtw8821c_dig, 1932 .rf_base_addr = {0x2800, 0x2c00}, 1933 .rf_sipi_addr = {0xc90, 0xe90}, 1934 .ltecoex_addr = &rtw8821c_ltecoex_addr, 1935 .mac_tbl = &rtw8821c_mac_tbl, 1936 .agc_tbl = &rtw8821c_agc_tbl, 1937 .bb_tbl = &rtw8821c_bb_tbl, 1938 .rf_tbl = {&rtw8821c_rf_a_tbl}, 1939 .rfe_defs = rtw8821c_rfe_defs, 1940 .rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs), 1941 .rx_ldpc = false, 1942 .pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl, 1943 .iqk_threshold = 8, 1944 .bfer_su_max_num = 2, 1945 .bfer_mu_max_num = 1, 1946 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2, 1947 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 1948 1949 .coex_para_ver = 0x19092746, 1950 .bt_desired_ver = 0x46, 1951 .scbd_support = true, 1952 .new_scbd10_def = false, 1953 .ble_hid_profile_support = false, 1954 .wl_mimo_ps_support = false, 1955 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 1956 .bt_rssi_type = COEX_BTRSSI_RATIO, 1957 .ant_isolation = 15, 1958 .rssi_tolerance = 2, 1959 .wl_rssi_step = wl_rssi_step_8821c, 1960 .bt_rssi_step = bt_rssi_step_8821c, 1961 .table_sant_num = ARRAY_SIZE(table_sant_8821c), 1962 .table_sant = table_sant_8821c, 1963 .table_nsant_num = ARRAY_SIZE(table_nsant_8821c), 1964 .table_nsant = table_nsant_8821c, 1965 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c), 1966 .tdma_sant = tdma_sant_8821c, 1967 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c), 1968 .tdma_nsant = tdma_nsant_8821c, 1969 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c), 1970 .wl_rf_para_tx = rf_para_tx_8821c, 1971 .wl_rf_para_rx = rf_para_rx_8821c, 1972 .bt_afh_span_bw20 = 0x24, 1973 .bt_afh_span_bw40 = 0x36, 1974 .afh_5g_num = ARRAY_SIZE(afh_5g_8821c), 1975 .afh_5g = afh_5g_8821c, 1976 1977 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c), 1978 .coex_info_hw_regs = coex_info_hw_regs_8821c, 1979 }; 1980 EXPORT_SYMBOL(rtw8821c_hw_spec); 1981 1982 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin"); 1983 1984 MODULE_AUTHOR("Realtek Corporation"); 1985 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver"); 1986 MODULE_LICENSE("Dual BSD/GPL"); 1987