1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_TX_H_ 6 #define __RTW_TX_H_ 7 8 #define RTK_TX_MAX_AGG_NUM_MASK 0x1f 9 10 #define RTW_TX_PROBE_TIMEOUT msecs_to_jiffies(500) 11 12 #define SET_TX_DESC_TXPKTSIZE(txdesc, value) \ 13 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(15, 0)) 14 #define SET_TX_DESC_OFFSET(txdesc, value) \ 15 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(23, 16)) 16 #define SET_TX_DESC_PKT_OFFSET(txdesc, value) \ 17 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(28, 24)) 18 #define SET_TX_DESC_QSEL(txdesc, value) \ 19 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(12, 8)) 20 #define SET_TX_DESC_BMC(txdesc, value) \ 21 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(24)) 22 #define SET_TX_DESC_RATE_ID(txdesc, value) \ 23 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(20, 16)) 24 #define SET_TX_DESC_DATARATE(txdesc, value) \ 25 le32p_replace_bits((__le32 *)(txdesc) + 0x04, value, GENMASK(6, 0)) 26 #define SET_TX_DESC_DISDATAFB(txdesc, value) \ 27 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(10)) 28 #define SET_TX_DESC_USE_RATE(txdesc, value) \ 29 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(8)) 30 #define SET_TX_DESC_SEC_TYPE(txdesc, value) \ 31 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(23, 22)) 32 #define SET_TX_DESC_DATA_BW(txdesc, value) \ 33 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, GENMASK(6, 5)) 34 #define SET_TX_DESC_SW_SEQ(txdesc, value) \ 35 le32p_replace_bits((__le32 *)(txdesc) + 0x09, value, GENMASK(23, 12)) 36 #define SET_TX_DESC_MAX_AGG_NUM(txdesc, value) \ 37 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, GENMASK(21, 17)) 38 #define SET_TX_DESC_USE_RTS(tx_desc, value) \ 39 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(12)) 40 #define SET_TX_DESC_RTSRATE(txdesc, value) \ 41 le32p_replace_bits((__le32 *)(txdesc) + 0x04, value, GENMASK(28, 24)) 42 #define SET_TX_DESC_DATA_RTS_SHORT(txdesc, value) \ 43 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(12)) 44 #define SET_TX_DESC_AMPDU_DENSITY(txdesc, value) \ 45 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, GENMASK(22, 20)) 46 #define SET_TX_DESC_DATA_STBC(txdesc, value) \ 47 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, GENMASK(9, 8)) 48 #define SET_TX_DESC_DATA_LDPC(txdesc, value) \ 49 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(7)) 50 #define SET_TX_DESC_AGG_EN(txdesc, value) \ 51 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(12)) 52 #define SET_TX_DESC_LS(txdesc, value) \ 53 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(26)) 54 #define SET_TX_DESC_DATA_SHORT(txdesc, value) \ 55 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(4)) 56 #define SET_TX_DESC_SPE_RPT(tx_desc, value) \ 57 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(19)) 58 #define SET_TX_DESC_SW_DEFINE(tx_desc, value) \ 59 le32p_replace_bits((__le32 *)(txdesc) + 0x06, value, GENMASK(11, 0)) 60 #define SET_TX_DESC_DISQSELSEQ(txdesc, value) \ 61 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(31)) 62 #define SET_TX_DESC_EN_HWSEQ(txdesc, value) \ 63 le32p_replace_bits((__le32 *)(txdesc) + 0x08, value, BIT(15)) 64 #define SET_TX_DESC_HW_SSN_SEL(txdesc, value) \ 65 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, GENMASK(7, 6)) 66 #define SET_TX_DESC_NAVUSEHDR(txdesc, value) \ 67 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(15)) 68 #define SET_TX_DESC_BT_NULL(txdesc, value) \ 69 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(23)) 70 71 enum rtw_tx_desc_queue_select { 72 TX_DESC_QSEL_TID0 = 0, 73 TX_DESC_QSEL_TID1 = 1, 74 TX_DESC_QSEL_TID2 = 2, 75 TX_DESC_QSEL_TID3 = 3, 76 TX_DESC_QSEL_TID4 = 4, 77 TX_DESC_QSEL_TID5 = 5, 78 TX_DESC_QSEL_TID6 = 6, 79 TX_DESC_QSEL_TID7 = 7, 80 TX_DESC_QSEL_TID8 = 8, 81 TX_DESC_QSEL_TID9 = 9, 82 TX_DESC_QSEL_TID10 = 10, 83 TX_DESC_QSEL_TID11 = 11, 84 TX_DESC_QSEL_TID12 = 12, 85 TX_DESC_QSEL_TID13 = 13, 86 TX_DESC_QSEL_TID14 = 14, 87 TX_DESC_QSEL_TID15 = 15, 88 TX_DESC_QSEL_BEACON = 16, 89 TX_DESC_QSEL_HIGH = 17, 90 TX_DESC_QSEL_MGMT = 18, 91 TX_DESC_QSEL_H2C = 19, 92 }; 93 94 enum rtw_rsvd_packet_type; 95 96 void rtw_tx(struct rtw_dev *rtwdev, 97 struct ieee80211_tx_control *control, 98 struct sk_buff *skb); 99 void rtw_txq_init(struct rtw_dev *rtwdev, struct ieee80211_txq *txq); 100 void rtw_txq_cleanup(struct rtw_dev *rtwdev, struct ieee80211_txq *txq); 101 void rtw_tx_work(struct work_struct *w); 102 void rtw_tx_pkt_info_update(struct rtw_dev *rtwdev, 103 struct rtw_tx_pkt_info *pkt_info, 104 struct ieee80211_sta *sta, 105 struct sk_buff *skb); 106 void rtw_tx_fill_tx_desc(struct rtw_tx_pkt_info *pkt_info, struct sk_buff *skb); 107 void rtw_tx_report_enqueue(struct rtw_dev *rtwdev, struct sk_buff *skb, u8 sn); 108 void rtw_tx_report_handle(struct rtw_dev *rtwdev, struct sk_buff *skb, int src); 109 void rtw_tx_rsvd_page_pkt_info_update(struct rtw_dev *rtwdev, 110 struct rtw_tx_pkt_info *pkt_info, 111 struct sk_buff *skb, 112 enum rtw_rsvd_packet_type type); 113 struct sk_buff * 114 rtw_tx_write_data_rsvd_page_get(struct rtw_dev *rtwdev, 115 struct rtw_tx_pkt_info *pkt_info, 116 u8 *buf, u32 size); 117 struct sk_buff * 118 rtw_tx_write_data_h2c_get(struct rtw_dev *rtwdev, 119 struct rtw_tx_pkt_info *pkt_info, 120 u8 *buf, u32 size); 121 122 #endif 123