1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 struct rtw89_mac_gen_def; 18 struct rtw89_phy_gen_def; 19 struct rtw89_efuse_block_cfg; 20 struct rtw89_h2c_rf_tssi; 21 struct rtw89_fw_txpwr_track_cfg; 22 struct rtw89_phy_rfk_log_fmt; 23 24 extern const struct ieee80211_ops rtw89_ops; 25 26 #define MASKBYTE0 0xff 27 #define MASKBYTE1 0xff00 28 #define MASKBYTE2 0xff0000 29 #define MASKBYTE3 0xff000000 30 #define MASKBYTE4 0xff00000000ULL 31 #define MASKHWORD 0xffff0000 32 #define MASKLWORD 0x0000ffff 33 #define MASKDWORD 0xffffffff 34 #define RFREG_MASK 0xfffff 35 #define INV_RF_DATA 0xffffffff 36 #define BYPASS_CR_DATA 0xbabecafe 37 38 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 39 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 40 #define CFO_TRACK_MAX_USER 64 41 #define MAX_RSSI 110 42 #define RSSI_FACTOR 1 43 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 44 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 45 #define DELTA_SWINGIDX_SIZE 30 46 47 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 48 #define RTW89_RADIOTAP_ROOM_EHT \ 49 (sizeof(struct ieee80211_radiotap_tlv) + \ 50 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 51 sizeof(struct ieee80211_radiotap_tlv) + \ 52 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 53 #define RTW89_RADIOTAP_ROOM \ 54 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 55 56 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 57 #define RTW89_HTC_VARIANT_HE 3 58 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 59 #define RTW89_HTC_VARIANT_HE_CID_OM 1 60 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 61 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 62 63 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 64 enum htc_om_channel_width { 65 HTC_OM_CHANNEL_WIDTH_20 = 0, 66 HTC_OM_CHANNEL_WIDTH_40 = 1, 67 HTC_OM_CHANNEL_WIDTH_80 = 2, 68 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 69 }; 70 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 71 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 72 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 73 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 74 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 75 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 76 77 #define RTW89_TF_PAD GENMASK(11, 0) 78 #define RTW89_TF_BASIC_USER_INFO_SZ 6 79 80 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 81 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 82 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 83 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 84 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 85 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 86 87 enum rtw89_subband { 88 RTW89_CH_2G = 0, 89 RTW89_CH_5G_BAND_1 = 1, 90 /* RTW89_CH_5G_BAND_2 = 2, unused */ 91 RTW89_CH_5G_BAND_3 = 3, 92 RTW89_CH_5G_BAND_4 = 4, 93 94 RTW89_CH_6G_BAND_IDX0, /* Low */ 95 RTW89_CH_6G_BAND_IDX1, /* Low */ 96 RTW89_CH_6G_BAND_IDX2, /* Mid */ 97 RTW89_CH_6G_BAND_IDX3, /* Mid */ 98 RTW89_CH_6G_BAND_IDX4, /* High */ 99 RTW89_CH_6G_BAND_IDX5, /* High */ 100 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 101 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 102 103 RTW89_SUBBAND_NR, 104 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 105 }; 106 107 enum rtw89_gain_offset { 108 RTW89_GAIN_OFFSET_2G_CCK, 109 RTW89_GAIN_OFFSET_2G_OFDM, 110 RTW89_GAIN_OFFSET_5G_LOW, 111 RTW89_GAIN_OFFSET_5G_MID, 112 RTW89_GAIN_OFFSET_5G_HIGH, 113 RTW89_GAIN_OFFSET_6G_L0, 114 RTW89_GAIN_OFFSET_6G_L1, 115 RTW89_GAIN_OFFSET_6G_M0, 116 RTW89_GAIN_OFFSET_6G_M1, 117 RTW89_GAIN_OFFSET_6G_H0, 118 RTW89_GAIN_OFFSET_6G_H1, 119 RTW89_GAIN_OFFSET_6G_UH0, 120 RTW89_GAIN_OFFSET_6G_UH1, 121 122 RTW89_GAIN_OFFSET_NR, 123 }; 124 125 enum rtw89_hci_type { 126 RTW89_HCI_TYPE_PCIE, 127 RTW89_HCI_TYPE_USB, 128 RTW89_HCI_TYPE_SDIO, 129 }; 130 131 enum rtw89_core_chip_id { 132 RTL8852A, 133 RTL8852B, 134 RTL8852C, 135 RTL8851B, 136 RTL8922A, 137 }; 138 139 enum rtw89_chip_gen { 140 RTW89_CHIP_AX, 141 RTW89_CHIP_BE, 142 143 RTW89_CHIP_GEN_NUM, 144 }; 145 146 enum rtw89_cv { 147 CHIP_CAV, 148 CHIP_CBV, 149 CHIP_CCV, 150 CHIP_CDV, 151 CHIP_CEV, 152 CHIP_CFV, 153 CHIP_CV_MAX, 154 CHIP_CV_INVALID = CHIP_CV_MAX, 155 }; 156 157 enum rtw89_bacam_ver { 158 RTW89_BACAM_V0, 159 RTW89_BACAM_V1, 160 161 RTW89_BACAM_V0_EXT = 99, 162 }; 163 164 enum rtw89_core_tx_type { 165 RTW89_CORE_TX_TYPE_DATA, 166 RTW89_CORE_TX_TYPE_MGMT, 167 RTW89_CORE_TX_TYPE_FWCMD, 168 }; 169 170 enum rtw89_core_rx_type { 171 RTW89_CORE_RX_TYPE_WIFI = 0, 172 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 173 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 174 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 175 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 176 RTW89_CORE_RX_TYPE_SS2FW = 5, 177 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 178 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 179 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 180 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 181 RTW89_CORE_RX_TYPE_C2H = 10, 182 RTW89_CORE_RX_TYPE_CSI = 11, 183 RTW89_CORE_RX_TYPE_CQI = 12, 184 RTW89_CORE_RX_TYPE_H2C = 13, 185 RTW89_CORE_RX_TYPE_FWDL = 14, 186 }; 187 188 enum rtw89_txq_flags { 189 RTW89_TXQ_F_AMPDU = 0, 190 RTW89_TXQ_F_BLOCK_BA = 1, 191 RTW89_TXQ_F_FORBID_BA = 2, 192 }; 193 194 enum rtw89_net_type { 195 RTW89_NET_TYPE_NO_LINK = 0, 196 RTW89_NET_TYPE_AD_HOC = 1, 197 RTW89_NET_TYPE_INFRA = 2, 198 RTW89_NET_TYPE_AP_MODE = 3, 199 }; 200 201 enum rtw89_wifi_role { 202 RTW89_WIFI_ROLE_NONE, 203 RTW89_WIFI_ROLE_STATION, 204 RTW89_WIFI_ROLE_AP, 205 RTW89_WIFI_ROLE_AP_VLAN, 206 RTW89_WIFI_ROLE_ADHOC, 207 RTW89_WIFI_ROLE_ADHOC_MASTER, 208 RTW89_WIFI_ROLE_MESH_POINT, 209 RTW89_WIFI_ROLE_MONITOR, 210 RTW89_WIFI_ROLE_P2P_DEVICE, 211 RTW89_WIFI_ROLE_P2P_CLIENT, 212 RTW89_WIFI_ROLE_P2P_GO, 213 RTW89_WIFI_ROLE_NAN, 214 RTW89_WIFI_ROLE_MLME_MAX 215 }; 216 217 enum rtw89_upd_mode { 218 RTW89_ROLE_CREATE, 219 RTW89_ROLE_REMOVE, 220 RTW89_ROLE_TYPE_CHANGE, 221 RTW89_ROLE_INFO_CHANGE, 222 RTW89_ROLE_CON_DISCONN, 223 RTW89_ROLE_BAND_SW, 224 RTW89_ROLE_FW_RESTORE, 225 }; 226 227 enum rtw89_self_role { 228 RTW89_SELF_ROLE_CLIENT, 229 RTW89_SELF_ROLE_AP, 230 RTW89_SELF_ROLE_AP_CLIENT 231 }; 232 233 enum rtw89_msk_sO_el { 234 RTW89_NO_MSK, 235 RTW89_SMA, 236 RTW89_TMA, 237 RTW89_BSSID 238 }; 239 240 enum rtw89_sch_tx_sel { 241 RTW89_SCH_TX_SEL_ALL, 242 RTW89_SCH_TX_SEL_HIQ, 243 RTW89_SCH_TX_SEL_MG0, 244 RTW89_SCH_TX_SEL_MACID, 245 }; 246 247 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 248 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 249 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 250 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 251 */ 252 enum rtw89_add_cam_sec_mode { 253 RTW89_ADDR_CAM_SEC_NONE = 0, 254 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 255 RTW89_ADDR_CAM_SEC_NORMAL = 2, 256 RTW89_ADDR_CAM_SEC_4GROUP = 3, 257 }; 258 259 enum rtw89_sec_key_type { 260 RTW89_SEC_KEY_TYPE_NONE = 0, 261 RTW89_SEC_KEY_TYPE_WEP40 = 1, 262 RTW89_SEC_KEY_TYPE_WEP104 = 2, 263 RTW89_SEC_KEY_TYPE_TKIP = 3, 264 RTW89_SEC_KEY_TYPE_WAPI = 4, 265 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 266 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 267 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 268 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 269 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 270 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 271 }; 272 273 enum rtw89_port { 274 RTW89_PORT_0 = 0, 275 RTW89_PORT_1 = 1, 276 RTW89_PORT_2 = 2, 277 RTW89_PORT_3 = 3, 278 RTW89_PORT_4 = 4, 279 RTW89_PORT_NUM 280 }; 281 282 enum rtw89_band { 283 RTW89_BAND_2G = 0, 284 RTW89_BAND_5G = 1, 285 RTW89_BAND_6G = 2, 286 RTW89_BAND_NUM, 287 }; 288 289 enum rtw89_hw_rate { 290 RTW89_HW_RATE_CCK1 = 0x0, 291 RTW89_HW_RATE_CCK2 = 0x1, 292 RTW89_HW_RATE_CCK5_5 = 0x2, 293 RTW89_HW_RATE_CCK11 = 0x3, 294 RTW89_HW_RATE_OFDM6 = 0x4, 295 RTW89_HW_RATE_OFDM9 = 0x5, 296 RTW89_HW_RATE_OFDM12 = 0x6, 297 RTW89_HW_RATE_OFDM18 = 0x7, 298 RTW89_HW_RATE_OFDM24 = 0x8, 299 RTW89_HW_RATE_OFDM36 = 0x9, 300 RTW89_HW_RATE_OFDM48 = 0xA, 301 RTW89_HW_RATE_OFDM54 = 0xB, 302 RTW89_HW_RATE_MCS0 = 0x80, 303 RTW89_HW_RATE_MCS1 = 0x81, 304 RTW89_HW_RATE_MCS2 = 0x82, 305 RTW89_HW_RATE_MCS3 = 0x83, 306 RTW89_HW_RATE_MCS4 = 0x84, 307 RTW89_HW_RATE_MCS5 = 0x85, 308 RTW89_HW_RATE_MCS6 = 0x86, 309 RTW89_HW_RATE_MCS7 = 0x87, 310 RTW89_HW_RATE_MCS8 = 0x88, 311 RTW89_HW_RATE_MCS9 = 0x89, 312 RTW89_HW_RATE_MCS10 = 0x8A, 313 RTW89_HW_RATE_MCS11 = 0x8B, 314 RTW89_HW_RATE_MCS12 = 0x8C, 315 RTW89_HW_RATE_MCS13 = 0x8D, 316 RTW89_HW_RATE_MCS14 = 0x8E, 317 RTW89_HW_RATE_MCS15 = 0x8F, 318 RTW89_HW_RATE_MCS16 = 0x90, 319 RTW89_HW_RATE_MCS17 = 0x91, 320 RTW89_HW_RATE_MCS18 = 0x92, 321 RTW89_HW_RATE_MCS19 = 0x93, 322 RTW89_HW_RATE_MCS20 = 0x94, 323 RTW89_HW_RATE_MCS21 = 0x95, 324 RTW89_HW_RATE_MCS22 = 0x96, 325 RTW89_HW_RATE_MCS23 = 0x97, 326 RTW89_HW_RATE_MCS24 = 0x98, 327 RTW89_HW_RATE_MCS25 = 0x99, 328 RTW89_HW_RATE_MCS26 = 0x9A, 329 RTW89_HW_RATE_MCS27 = 0x9B, 330 RTW89_HW_RATE_MCS28 = 0x9C, 331 RTW89_HW_RATE_MCS29 = 0x9D, 332 RTW89_HW_RATE_MCS30 = 0x9E, 333 RTW89_HW_RATE_MCS31 = 0x9F, 334 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 335 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 336 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 337 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 338 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 339 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 340 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 341 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 342 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 343 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 344 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 345 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 346 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 347 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 348 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 349 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 350 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 351 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 352 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 353 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 354 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 355 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 356 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 357 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 358 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 359 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 360 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 361 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 362 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 363 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 364 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 365 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 366 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 367 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 368 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 369 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 370 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 371 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 372 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 373 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 374 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 375 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 376 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 377 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 378 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 379 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 380 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 381 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 382 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 383 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 384 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 385 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 386 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 387 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 388 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 389 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 390 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 391 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 392 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 393 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 394 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 395 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 396 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 397 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 398 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 399 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 400 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 401 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 402 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 403 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 404 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 405 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 406 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 407 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 408 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 409 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 410 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 411 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 412 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 413 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 414 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 415 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 416 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 417 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 418 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 419 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 420 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 421 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 422 423 RTW89_HW_RATE_V1_MCS0 = 0x100, 424 RTW89_HW_RATE_V1_MCS1 = 0x101, 425 RTW89_HW_RATE_V1_MCS2 = 0x102, 426 RTW89_HW_RATE_V1_MCS3 = 0x103, 427 RTW89_HW_RATE_V1_MCS4 = 0x104, 428 RTW89_HW_RATE_V1_MCS5 = 0x105, 429 RTW89_HW_RATE_V1_MCS6 = 0x106, 430 RTW89_HW_RATE_V1_MCS7 = 0x107, 431 RTW89_HW_RATE_V1_MCS8 = 0x108, 432 RTW89_HW_RATE_V1_MCS9 = 0x109, 433 RTW89_HW_RATE_V1_MCS10 = 0x10A, 434 RTW89_HW_RATE_V1_MCS11 = 0x10B, 435 RTW89_HW_RATE_V1_MCS12 = 0x10C, 436 RTW89_HW_RATE_V1_MCS13 = 0x10D, 437 RTW89_HW_RATE_V1_MCS14 = 0x10E, 438 RTW89_HW_RATE_V1_MCS15 = 0x10F, 439 RTW89_HW_RATE_V1_MCS16 = 0x110, 440 RTW89_HW_RATE_V1_MCS17 = 0x111, 441 RTW89_HW_RATE_V1_MCS18 = 0x112, 442 RTW89_HW_RATE_V1_MCS19 = 0x113, 443 RTW89_HW_RATE_V1_MCS20 = 0x114, 444 RTW89_HW_RATE_V1_MCS21 = 0x115, 445 RTW89_HW_RATE_V1_MCS22 = 0x116, 446 RTW89_HW_RATE_V1_MCS23 = 0x117, 447 RTW89_HW_RATE_V1_MCS24 = 0x118, 448 RTW89_HW_RATE_V1_MCS25 = 0x119, 449 RTW89_HW_RATE_V1_MCS26 = 0x11A, 450 RTW89_HW_RATE_V1_MCS27 = 0x11B, 451 RTW89_HW_RATE_V1_MCS28 = 0x11C, 452 RTW89_HW_RATE_V1_MCS29 = 0x11D, 453 RTW89_HW_RATE_V1_MCS30 = 0x11E, 454 RTW89_HW_RATE_V1_MCS31 = 0x11F, 455 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 456 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 457 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 467 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 468 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 469 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 479 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 480 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 481 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 491 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 492 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 493 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 503 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 504 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 505 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 515 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 516 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 517 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 527 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 528 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 529 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 539 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 540 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 541 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 551 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 552 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 553 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 567 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 568 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 569 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 581 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 582 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 583 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 595 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 596 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 597 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 609 610 RTW89_HW_RATE_NR, 611 RTW89_HW_RATE_INVAL, 612 613 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 614 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 615 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 616 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 617 }; 618 619 /* 2G channels, 620 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 621 */ 622 #define RTW89_2G_CH_NUM 14 623 624 /* 5G channels, 625 * 36, 38, 40, 42, 44, 46, 48, 50, 626 * 52, 54, 56, 58, 60, 62, 64, 627 * 100, 102, 104, 106, 108, 110, 112, 114, 628 * 116, 118, 120, 122, 124, 126, 128, 130, 629 * 132, 134, 136, 138, 140, 142, 144, 630 * 149, 151, 153, 155, 157, 159, 161, 163, 631 * 165, 167, 169, 171, 173, 175, 177 632 */ 633 #define RTW89_5G_CH_NUM 53 634 635 /* 6G channels, 636 * 1, 3, 5, 7, 9, 11, 13, 15, 637 * 17, 19, 21, 23, 25, 27, 29, 33, 638 * 35, 37, 39, 41, 43, 45, 47, 49, 639 * 51, 53, 55, 57, 59, 61, 65, 67, 640 * 69, 71, 73, 75, 77, 79, 81, 83, 641 * 85, 87, 89, 91, 93, 97, 99, 101, 642 * 103, 105, 107, 109, 111, 113, 115, 117, 643 * 119, 121, 123, 125, 129, 131, 133, 135, 644 * 137, 139, 141, 143, 145, 147, 149, 151, 645 * 153, 155, 157, 161, 163, 165, 167, 169, 646 * 171, 173, 175, 177, 179, 181, 183, 185, 647 * 187, 189, 193, 195, 197, 199, 201, 203, 648 * 205, 207, 209, 211, 213, 215, 217, 219, 649 * 221, 225, 227, 229, 231, 233, 235, 237, 650 * 239, 241, 243, 245, 247, 249, 251, 253, 651 */ 652 #define RTW89_6G_CH_NUM 120 653 654 enum rtw89_rate_section { 655 RTW89_RS_CCK, 656 RTW89_RS_OFDM, 657 RTW89_RS_MCS, /* for HT/VHT/HE */ 658 RTW89_RS_HEDCM, 659 RTW89_RS_OFFSET, 660 RTW89_RS_NUM, 661 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 662 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 663 }; 664 665 enum rtw89_rate_offset_indexes { 666 RTW89_RATE_OFFSET_HE, 667 RTW89_RATE_OFFSET_VHT, 668 RTW89_RATE_OFFSET_HT, 669 RTW89_RATE_OFFSET_OFDM, 670 RTW89_RATE_OFFSET_CCK, 671 RTW89_RATE_OFFSET_DLRU_EHT, 672 RTW89_RATE_OFFSET_DLRU_HE, 673 RTW89_RATE_OFFSET_EHT, 674 __RTW89_RATE_OFFSET_NUM, 675 676 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 677 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 678 }; 679 680 enum rtw89_rate_num { 681 RTW89_RATE_CCK_NUM = 4, 682 RTW89_RATE_OFDM_NUM = 8, 683 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 684 685 RTW89_RATE_MCS_NUM_AX = 12, 686 RTW89_RATE_MCS_NUM_BE = 16, 687 __RTW89_RATE_MCS_NUM = 16, 688 }; 689 690 enum rtw89_nss { 691 RTW89_NSS_1 = 0, 692 RTW89_NSS_2 = 1, 693 /* HE DCM only support 1ss and 2ss */ 694 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 695 RTW89_NSS_3 = 2, 696 RTW89_NSS_4 = 3, 697 RTW89_NSS_NUM, 698 }; 699 700 enum rtw89_ntx { 701 RTW89_1TX = 0, 702 RTW89_2TX = 1, 703 RTW89_NTX_NUM, 704 }; 705 706 enum rtw89_beamforming_type { 707 RTW89_NONBF = 0, 708 RTW89_BF = 1, 709 RTW89_BF_NUM, 710 }; 711 712 enum rtw89_ofdma_type { 713 RTW89_NON_OFDMA = 0, 714 RTW89_OFDMA = 1, 715 RTW89_OFDMA_NUM, 716 }; 717 718 enum rtw89_regulation_type { 719 RTW89_WW = 0, 720 RTW89_ETSI = 1, 721 RTW89_FCC = 2, 722 RTW89_MKK = 3, 723 RTW89_NA = 4, 724 RTW89_IC = 5, 725 RTW89_KCC = 6, 726 RTW89_ACMA = 7, 727 RTW89_NCC = 8, 728 RTW89_MEXICO = 9, 729 RTW89_CHILE = 10, 730 RTW89_UKRAINE = 11, 731 RTW89_CN = 12, 732 RTW89_QATAR = 13, 733 RTW89_UK = 14, 734 RTW89_THAILAND = 15, 735 RTW89_REGD_NUM, 736 }; 737 738 enum rtw89_reg_6ghz_power { 739 RTW89_REG_6GHZ_POWER_VLP = 0, 740 RTW89_REG_6GHZ_POWER_LPI = 1, 741 RTW89_REG_6GHZ_POWER_STD = 2, 742 743 NUM_OF_RTW89_REG_6GHZ_POWER, 744 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 745 }; 746 747 enum rtw89_fw_pkt_ofld_type { 748 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 749 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 750 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 751 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 752 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 753 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 754 RTW89_PKT_OFLD_TYPE_NDP = 6, 755 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 756 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 757 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 758 RTW89_PKT_OFLD_TYPE_NUM, 759 }; 760 761 struct rtw89_txpwr_byrate { 762 s8 cck[RTW89_RATE_CCK_NUM]; 763 s8 ofdm[RTW89_RATE_OFDM_NUM]; 764 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 765 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 766 s8 offset[__RTW89_RATE_OFFSET_NUM]; 767 s8 trap; 768 }; 769 770 struct rtw89_rate_desc { 771 enum rtw89_nss nss; 772 enum rtw89_rate_section rs; 773 enum rtw89_ofdma_type ofdma; 774 u8 idx; 775 }; 776 777 #define PHY_STS_HDR_LEN 8 778 #define RF_PATH_MAX 4 779 #define RTW89_MAX_PPDU_CNT 8 780 struct rtw89_rx_phy_ppdu { 781 void *buf; 782 u32 len; 783 u8 rssi_avg; 784 u8 rssi[RF_PATH_MAX]; 785 u8 mac_id; 786 u8 chan_idx; 787 u8 ie; 788 u16 rate; 789 struct { 790 bool has; 791 u8 avg_snr; 792 u8 evm_max; 793 u8 evm_min; 794 } ofdm; 795 bool to_self; 796 bool valid; 797 }; 798 799 enum rtw89_mac_idx { 800 RTW89_MAC_0 = 0, 801 RTW89_MAC_1 = 1, 802 }; 803 804 enum rtw89_phy_idx { 805 RTW89_PHY_0 = 0, 806 RTW89_PHY_1 = 1, 807 RTW89_PHY_MAX 808 }; 809 810 enum rtw89_sub_entity_idx { 811 RTW89_SUB_ENTITY_0 = 0, 812 RTW89_SUB_ENTITY_1 = 1, 813 814 NUM_OF_RTW89_SUB_ENTITY, 815 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 816 }; 817 818 enum rtw89_rf_path { 819 RF_PATH_A = 0, 820 RF_PATH_B = 1, 821 RF_PATH_C = 2, 822 RF_PATH_D = 3, 823 RF_PATH_AB, 824 RF_PATH_AC, 825 RF_PATH_AD, 826 RF_PATH_BC, 827 RF_PATH_BD, 828 RF_PATH_CD, 829 RF_PATH_ABC, 830 RF_PATH_ABD, 831 RF_PATH_ACD, 832 RF_PATH_BCD, 833 RF_PATH_ABCD, 834 }; 835 836 enum rtw89_rf_path_bit { 837 RF_A = BIT(0), 838 RF_B = BIT(1), 839 RF_C = BIT(2), 840 RF_D = BIT(3), 841 842 RF_AB = (RF_A | RF_B), 843 RF_AC = (RF_A | RF_C), 844 RF_AD = (RF_A | RF_D), 845 RF_BC = (RF_B | RF_C), 846 RF_BD = (RF_B | RF_D), 847 RF_CD = (RF_C | RF_D), 848 849 RF_ABC = (RF_A | RF_B | RF_C), 850 RF_ABD = (RF_A | RF_B | RF_D), 851 RF_ACD = (RF_A | RF_C | RF_D), 852 RF_BCD = (RF_B | RF_C | RF_D), 853 854 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 855 }; 856 857 enum rtw89_bandwidth { 858 RTW89_CHANNEL_WIDTH_20 = 0, 859 RTW89_CHANNEL_WIDTH_40 = 1, 860 RTW89_CHANNEL_WIDTH_80 = 2, 861 RTW89_CHANNEL_WIDTH_160 = 3, 862 RTW89_CHANNEL_WIDTH_320 = 4, 863 864 /* keep index order above */ 865 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 866 867 RTW89_CHANNEL_WIDTH_80_80 = 5, 868 RTW89_CHANNEL_WIDTH_5 = 6, 869 RTW89_CHANNEL_WIDTH_10 = 7, 870 }; 871 872 enum rtw89_ps_mode { 873 RTW89_PS_MODE_NONE = 0, 874 RTW89_PS_MODE_RFOFF = 1, 875 RTW89_PS_MODE_CLK_GATED = 2, 876 RTW89_PS_MODE_PWR_GATED = 3, 877 }; 878 879 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 880 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 881 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 882 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 883 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 884 885 enum rtw89_ru_bandwidth { 886 RTW89_RU26 = 0, 887 RTW89_RU52 = 1, 888 RTW89_RU106 = 2, 889 RTW89_RU52_26 = 3, 890 RTW89_RU106_26 = 4, 891 RTW89_RU_NUM, 892 }; 893 894 enum rtw89_sc_offset { 895 RTW89_SC_DONT_CARE = 0, 896 RTW89_SC_20_UPPER = 1, 897 RTW89_SC_20_LOWER = 2, 898 RTW89_SC_20_UPMOST = 3, 899 RTW89_SC_20_LOWEST = 4, 900 RTW89_SC_20_UP2X = 5, 901 RTW89_SC_20_LOW2X = 6, 902 RTW89_SC_20_UP3X = 7, 903 RTW89_SC_20_LOW3X = 8, 904 RTW89_SC_40_UPPER = 9, 905 RTW89_SC_40_LOWER = 10, 906 }; 907 908 enum rtw89_wow_flags { 909 RTW89_WOW_FLAG_EN_MAGIC_PKT, 910 RTW89_WOW_FLAG_EN_REKEY_PKT, 911 RTW89_WOW_FLAG_EN_DISCONNECT, 912 RTW89_WOW_FLAG_NUM, 913 }; 914 915 struct rtw89_chan { 916 u8 channel; 917 u8 primary_channel; 918 enum rtw89_band band_type; 919 enum rtw89_bandwidth band_width; 920 921 /* The follow-up are derived from the above. We must ensure that it 922 * is assigned correctly in rtw89_chan_create() if new one is added. 923 */ 924 u32 freq; 925 enum rtw89_subband subband_type; 926 enum rtw89_sc_offset pri_ch_idx; 927 u8 pri_sb_idx; 928 }; 929 930 struct rtw89_chan_rcd { 931 u8 prev_primary_channel; 932 enum rtw89_band prev_band_type; 933 bool band_changed; 934 }; 935 936 struct rtw89_channel_help_params { 937 u32 tx_en; 938 }; 939 940 struct rtw89_port_reg { 941 u32 port_cfg; 942 u32 tbtt_prohib; 943 u32 bcn_area; 944 u32 bcn_early; 945 u32 tbtt_early; 946 u32 tbtt_agg; 947 u32 bcn_space; 948 u32 bcn_forcetx; 949 u32 bcn_err_cnt; 950 u32 bcn_err_flag; 951 u32 dtim_ctrl; 952 u32 tbtt_shift; 953 u32 bcn_cnt_tmr; 954 u32 tsftr_l; 955 u32 tsftr_h; 956 u32 md_tsft; 957 u32 bss_color; 958 u32 mbssid; 959 u32 mbssid_drop; 960 u32 tsf_sync; 961 u32 ptcl_dbg; 962 u32 ptcl_dbg_info; 963 u32 bcn_drop_all; 964 u32 hiq_win[RTW89_PORT_NUM]; 965 }; 966 967 struct rtw89_txwd_body { 968 __le32 dword0; 969 __le32 dword1; 970 __le32 dword2; 971 __le32 dword3; 972 __le32 dword4; 973 __le32 dword5; 974 } __packed; 975 976 struct rtw89_txwd_body_v1 { 977 __le32 dword0; 978 __le32 dword1; 979 __le32 dword2; 980 __le32 dword3; 981 __le32 dword4; 982 __le32 dword5; 983 __le32 dword6; 984 __le32 dword7; 985 } __packed; 986 987 struct rtw89_txwd_body_v2 { 988 __le32 dword0; 989 __le32 dword1; 990 __le32 dword2; 991 __le32 dword3; 992 __le32 dword4; 993 __le32 dword5; 994 __le32 dword6; 995 __le32 dword7; 996 } __packed; 997 998 struct rtw89_txwd_info { 999 __le32 dword0; 1000 __le32 dword1; 1001 __le32 dword2; 1002 __le32 dword3; 1003 __le32 dword4; 1004 __le32 dword5; 1005 } __packed; 1006 1007 struct rtw89_txwd_info_v2 { 1008 __le32 dword0; 1009 __le32 dword1; 1010 __le32 dword2; 1011 __le32 dword3; 1012 __le32 dword4; 1013 __le32 dword5; 1014 __le32 dword6; 1015 __le32 dword7; 1016 } __packed; 1017 1018 struct rtw89_rx_desc_info { 1019 u16 pkt_size; 1020 u8 pkt_type; 1021 u8 drv_info_size; 1022 u8 phy_rpt_size; 1023 u8 hdr_cnv_size; 1024 u8 shift; 1025 u8 wl_hd_iv_len; 1026 bool long_rxdesc; 1027 bool bb_sel; 1028 bool mac_info_valid; 1029 u16 data_rate; 1030 u8 gi_ltf; 1031 u8 bw; 1032 u32 free_run_cnt; 1033 u8 user_id; 1034 bool sr_en; 1035 u8 ppdu_cnt; 1036 u8 ppdu_type; 1037 bool icv_err; 1038 bool crc32_err; 1039 bool hw_dec; 1040 bool sw_dec; 1041 bool addr1_match; 1042 u8 frag; 1043 u16 seq; 1044 u8 frame_type; 1045 u8 rx_pl_id; 1046 bool addr_cam_valid; 1047 u8 addr_cam_id; 1048 u8 sec_cam_id; 1049 u8 mac_id; 1050 u16 offset; 1051 u16 rxd_len; 1052 bool ready; 1053 }; 1054 1055 struct rtw89_rxdesc_short { 1056 __le32 dword0; 1057 __le32 dword1; 1058 __le32 dword2; 1059 __le32 dword3; 1060 } __packed; 1061 1062 struct rtw89_rxdesc_short_v2 { 1063 __le32 dword0; 1064 __le32 dword1; 1065 __le32 dword2; 1066 __le32 dword3; 1067 __le32 dword4; 1068 __le32 dword5; 1069 } __packed; 1070 1071 struct rtw89_rxdesc_long { 1072 __le32 dword0; 1073 __le32 dword1; 1074 __le32 dword2; 1075 __le32 dword3; 1076 __le32 dword4; 1077 __le32 dword5; 1078 __le32 dword6; 1079 __le32 dword7; 1080 } __packed; 1081 1082 struct rtw89_rxdesc_long_v2 { 1083 __le32 dword0; 1084 __le32 dword1; 1085 __le32 dword2; 1086 __le32 dword3; 1087 __le32 dword4; 1088 __le32 dword5; 1089 __le32 dword6; 1090 __le32 dword7; 1091 __le32 dword8; 1092 __le32 dword9; 1093 } __packed; 1094 1095 struct rtw89_tx_desc_info { 1096 u16 pkt_size; 1097 u8 wp_offset; 1098 u8 mac_id; 1099 u8 qsel; 1100 u8 ch_dma; 1101 u8 hdr_llc_len; 1102 bool is_bmc; 1103 bool en_wd_info; 1104 bool wd_page; 1105 bool use_rate; 1106 bool dis_data_fb; 1107 bool tid_indicate; 1108 bool agg_en; 1109 bool bk; 1110 u8 ampdu_density; 1111 u8 ampdu_num; 1112 bool sec_en; 1113 u8 addr_info_nr; 1114 u8 sec_keyid; 1115 u8 sec_type; 1116 u8 sec_cam_idx; 1117 u8 sec_seq[6]; 1118 u16 data_rate; 1119 u16 data_retry_lowest_rate; 1120 bool fw_dl; 1121 u16 seq; 1122 bool a_ctrl_bsr; 1123 u8 hw_ssn_sel; 1124 #define RTW89_MGMT_HW_SSN_SEL 1 1125 u8 hw_seq_mode; 1126 #define RTW89_MGMT_HW_SEQ_MODE 1 1127 bool hiq; 1128 u8 port; 1129 bool er_cap; 1130 }; 1131 1132 struct rtw89_core_tx_request { 1133 enum rtw89_core_tx_type tx_type; 1134 1135 struct sk_buff *skb; 1136 struct ieee80211_vif *vif; 1137 struct ieee80211_sta *sta; 1138 struct rtw89_tx_desc_info desc_info; 1139 }; 1140 1141 struct rtw89_txq { 1142 struct list_head list; 1143 unsigned long flags; 1144 int wait_cnt; 1145 }; 1146 1147 struct rtw89_mac_ax_gnt { 1148 u8 gnt_bt_sw_en; 1149 u8 gnt_bt; 1150 u8 gnt_wl_sw_en; 1151 u8 gnt_wl; 1152 } __packed; 1153 1154 struct rtw89_mac_ax_wl_act { 1155 u8 wlan_act_en; 1156 u8 wlan_act; 1157 }; 1158 1159 #define RTW89_MAC_AX_COEX_GNT_NR 2 1160 struct rtw89_mac_ax_coex_gnt { 1161 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1162 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1163 }; 1164 1165 enum rtw89_btc_ncnt { 1166 BTC_NCNT_POWER_ON = 0x0, 1167 BTC_NCNT_POWER_OFF, 1168 BTC_NCNT_INIT_COEX, 1169 BTC_NCNT_SCAN_START, 1170 BTC_NCNT_SCAN_FINISH, 1171 BTC_NCNT_SPECIAL_PACKET, 1172 BTC_NCNT_SWITCH_BAND, 1173 BTC_NCNT_RFK_TIMEOUT, 1174 BTC_NCNT_SHOW_COEX_INFO, 1175 BTC_NCNT_ROLE_INFO, 1176 BTC_NCNT_CONTROL, 1177 BTC_NCNT_RADIO_STATE, 1178 BTC_NCNT_CUSTOMERIZE, 1179 BTC_NCNT_WL_RFK, 1180 BTC_NCNT_WL_STA, 1181 BTC_NCNT_FWINFO, 1182 BTC_NCNT_TIMER, 1183 BTC_NCNT_NUM 1184 }; 1185 1186 enum rtw89_btc_btinfo { 1187 BTC_BTINFO_L0 = 0, 1188 BTC_BTINFO_L1, 1189 BTC_BTINFO_L2, 1190 BTC_BTINFO_L3, 1191 BTC_BTINFO_H0, 1192 BTC_BTINFO_H1, 1193 BTC_BTINFO_H2, 1194 BTC_BTINFO_H3, 1195 BTC_BTINFO_MAX 1196 }; 1197 1198 enum rtw89_btc_dcnt { 1199 BTC_DCNT_RUN = 0x0, 1200 BTC_DCNT_CX_RUNINFO, 1201 BTC_DCNT_RPT, 1202 BTC_DCNT_RPT_HANG, 1203 BTC_DCNT_CYCLE, 1204 BTC_DCNT_CYCLE_HANG, 1205 BTC_DCNT_W1, 1206 BTC_DCNT_W1_HANG, 1207 BTC_DCNT_B1, 1208 BTC_DCNT_B1_HANG, 1209 BTC_DCNT_TDMA_NONSYNC, 1210 BTC_DCNT_SLOT_NONSYNC, 1211 BTC_DCNT_BTCNT_HANG, 1212 BTC_DCNT_WL_SLOT_DRIFT, 1213 BTC_DCNT_WL_STA_LAST, 1214 BTC_DCNT_BT_SLOT_DRIFT, 1215 BTC_DCNT_BT_SLOT_FLOOD, 1216 BTC_DCNT_FDDT_TRIG, 1217 BTC_DCNT_E2G, 1218 BTC_DCNT_E2G_HANG, 1219 BTC_DCNT_NUM 1220 }; 1221 1222 enum rtw89_btc_wl_state_cnt { 1223 BTC_WCNT_SCANAP = 0x0, 1224 BTC_WCNT_DHCP, 1225 BTC_WCNT_EAPOL, 1226 BTC_WCNT_ARP, 1227 BTC_WCNT_SCBDUPDATE, 1228 BTC_WCNT_RFK_REQ, 1229 BTC_WCNT_RFK_GO, 1230 BTC_WCNT_RFK_REJECT, 1231 BTC_WCNT_RFK_TIMEOUT, 1232 BTC_WCNT_CH_UPDATE, 1233 BTC_WCNT_NUM 1234 }; 1235 1236 enum rtw89_btc_bt_state_cnt { 1237 BTC_BCNT_RETRY = 0x0, 1238 BTC_BCNT_REINIT, 1239 BTC_BCNT_REENABLE, 1240 BTC_BCNT_SCBDREAD, 1241 BTC_BCNT_RELINK, 1242 BTC_BCNT_IGNOWL, 1243 BTC_BCNT_INQPAG, 1244 BTC_BCNT_INQ, 1245 BTC_BCNT_PAGE, 1246 BTC_BCNT_ROLESW, 1247 BTC_BCNT_AFH, 1248 BTC_BCNT_INFOUPDATE, 1249 BTC_BCNT_INFOSAME, 1250 BTC_BCNT_SCBDUPDATE, 1251 BTC_BCNT_HIPRI_TX, 1252 BTC_BCNT_HIPRI_RX, 1253 BTC_BCNT_LOPRI_TX, 1254 BTC_BCNT_LOPRI_RX, 1255 BTC_BCNT_POLUT, 1256 BTC_BCNT_RATECHG, 1257 BTC_BCNT_NUM 1258 }; 1259 1260 enum rtw89_btc_bt_profile { 1261 BTC_BT_NOPROFILE = 0, 1262 BTC_BT_HFP = BIT(0), 1263 BTC_BT_HID = BIT(1), 1264 BTC_BT_A2DP = BIT(2), 1265 BTC_BT_PAN = BIT(3), 1266 BTC_PROFILE_MAX = 4, 1267 }; 1268 1269 struct rtw89_btc_ant_info { 1270 u8 type; /* shared, dedicated */ 1271 u8 num; 1272 u8 isolation; 1273 1274 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1275 u8 diversity: 1; 1276 u8 btg_pos: 2; 1277 u8 stream_cnt: 4; 1278 }; 1279 1280 struct rtw89_btc_ant_info_v7 { 1281 u8 type; /* shared, dedicated(non-shared) */ 1282 u8 num; /* antenna count */ 1283 u8 isolation; 1284 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1285 1286 u8 diversity; /* only for wifi use 1-antenna */ 1287 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1288 u8 stream_cnt; /* spatial_stream count */ 1289 u8 rsvd; 1290 } __packed; 1291 1292 enum rtw89_tfc_dir { 1293 RTW89_TFC_UL, 1294 RTW89_TFC_DL, 1295 }; 1296 1297 struct rtw89_btc_wl_smap { 1298 u32 busy: 1; 1299 u32 scan: 1; 1300 u32 connecting: 1; 1301 u32 roaming: 1; 1302 u32 _4way: 1; 1303 u32 rf_off: 1; 1304 u32 lps: 2; 1305 u32 ips: 1; 1306 u32 init_ok: 1; 1307 u32 traffic_dir : 2; 1308 u32 rf_off_pre: 1; 1309 u32 lps_pre: 2; 1310 }; 1311 1312 enum rtw89_tfc_lv { 1313 RTW89_TFC_IDLE, 1314 RTW89_TFC_ULTRA_LOW, 1315 RTW89_TFC_LOW, 1316 RTW89_TFC_MID, 1317 RTW89_TFC_HIGH, 1318 }; 1319 1320 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1321 DECLARE_EWMA(tp, 10, 2); 1322 1323 struct rtw89_traffic_stats { 1324 /* units in bytes */ 1325 u64 tx_unicast; 1326 u64 rx_unicast; 1327 u32 tx_avg_len; 1328 u32 rx_avg_len; 1329 1330 /* count for packets */ 1331 u64 tx_cnt; 1332 u64 rx_cnt; 1333 1334 /* units in Mbps */ 1335 u32 tx_throughput; 1336 u32 rx_throughput; 1337 u32 tx_throughput_raw; 1338 u32 rx_throughput_raw; 1339 1340 u32 rx_tf_acc; 1341 u32 rx_tf_periodic; 1342 1343 enum rtw89_tfc_lv tx_tfc_lv; 1344 enum rtw89_tfc_lv rx_tfc_lv; 1345 struct ewma_tp tx_ewma_tp; 1346 struct ewma_tp rx_ewma_tp; 1347 1348 u16 tx_rate; 1349 u16 rx_rate; 1350 }; 1351 1352 struct rtw89_btc_statistic { 1353 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1354 struct rtw89_traffic_stats traffic; 1355 }; 1356 1357 #define BTC_WL_RSSI_THMAX 4 1358 1359 struct rtw89_btc_wl_link_info { 1360 struct rtw89_btc_statistic stat; 1361 enum rtw89_tfc_dir dir; 1362 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1363 u8 mac_addr[ETH_ALEN]; 1364 u8 busy; 1365 u8 ch; 1366 u8 bw; 1367 u8 band; 1368 u8 role; 1369 u8 pid; 1370 u8 phy; 1371 u8 dtim_period; 1372 u8 mode; 1373 1374 u8 mac_id; 1375 u8 tx_retry; 1376 1377 u32 bcn_period; 1378 u32 busy_t; 1379 u32 tx_time; 1380 u32 client_cnt; 1381 u32 rx_rate_drop_cnt; 1382 1383 u32 active: 1; 1384 u32 noa: 1; 1385 u32 client_ps: 1; 1386 u32 connected: 2; 1387 }; 1388 1389 union rtw89_btc_wl_state_map { 1390 u32 val; 1391 struct rtw89_btc_wl_smap map; 1392 }; 1393 1394 struct rtw89_btc_bt_hfp_desc { 1395 u32 exist: 1; 1396 u32 type: 2; 1397 u32 rsvd: 29; 1398 }; 1399 1400 struct rtw89_btc_bt_hid_desc { 1401 u32 exist: 1; 1402 u32 slot_info: 2; 1403 u32 pair_cnt: 2; 1404 u32 type: 8; 1405 u32 rsvd: 19; 1406 }; 1407 1408 struct rtw89_btc_bt_a2dp_desc { 1409 u8 exist: 1; 1410 u8 exist_last: 1; 1411 u8 play_latency: 1; 1412 u8 type: 3; 1413 u8 active: 1; 1414 u8 sink: 1; 1415 1416 u8 bitpool; 1417 u16 vendor_id; 1418 u32 device_name; 1419 u32 flush_time; 1420 }; 1421 1422 struct rtw89_btc_bt_pan_desc { 1423 u32 exist: 1; 1424 u32 type: 1; 1425 u32 active: 1; 1426 u32 rsvd: 29; 1427 }; 1428 1429 struct rtw89_btc_bt_rfk_info { 1430 u32 run: 1; 1431 u32 req: 1; 1432 u32 timeout: 1; 1433 u32 rsvd: 29; 1434 }; 1435 1436 union rtw89_btc_bt_rfk_info_map { 1437 u32 val; 1438 struct rtw89_btc_bt_rfk_info map; 1439 }; 1440 1441 struct rtw89_btc_bt_ver_info { 1442 u32 fw_coex; /* match with which coex_ver */ 1443 u32 fw; 1444 }; 1445 1446 struct rtw89_btc_bool_sta_chg { 1447 u32 now: 1; 1448 u32 last: 1; 1449 u32 remain: 1; 1450 u32 srvd: 29; 1451 }; 1452 1453 struct rtw89_btc_u8_sta_chg { 1454 u8 now; 1455 u8 last; 1456 u8 remain; 1457 u8 rsvd; 1458 }; 1459 1460 struct rtw89_btc_wl_scan_info { 1461 u8 band[RTW89_PHY_MAX]; 1462 u8 phy_map; 1463 u8 rsvd; 1464 }; 1465 1466 struct rtw89_btc_wl_dbcc_info { 1467 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1468 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1469 u8 real_band[RTW89_PHY_MAX]; 1470 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1471 }; 1472 1473 struct rtw89_btc_wl_active_role { 1474 u8 connected: 1; 1475 u8 pid: 3; 1476 u8 phy: 1; 1477 u8 noa: 1; 1478 u8 band: 2; 1479 1480 u8 client_ps: 1; 1481 u8 bw: 7; 1482 1483 u8 role; 1484 u8 ch; 1485 1486 u16 tx_lvl; 1487 u16 rx_lvl; 1488 u16 tx_rate; 1489 u16 rx_rate; 1490 }; 1491 1492 struct rtw89_btc_wl_active_role_v1 { 1493 u8 connected: 1; 1494 u8 pid: 3; 1495 u8 phy: 1; 1496 u8 noa: 1; 1497 u8 band: 2; 1498 1499 u8 client_ps: 1; 1500 u8 bw: 7; 1501 1502 u8 role; 1503 u8 ch; 1504 1505 u16 tx_lvl; 1506 u16 rx_lvl; 1507 u16 tx_rate; 1508 u16 rx_rate; 1509 1510 u32 noa_duration; /* ms */ 1511 }; 1512 1513 struct rtw89_btc_wl_active_role_v2 { 1514 u8 connected: 1; 1515 u8 pid: 3; 1516 u8 phy: 1; 1517 u8 noa: 1; 1518 u8 band: 2; 1519 1520 u8 client_ps: 1; 1521 u8 bw: 7; 1522 1523 u8 role; 1524 u8 ch; 1525 1526 u32 noa_duration; /* ms */ 1527 }; 1528 1529 struct rtw89_btc_wl_role_info_bpos { 1530 u16 none: 1; 1531 u16 station: 1; 1532 u16 ap: 1; 1533 u16 vap: 1; 1534 u16 adhoc: 1; 1535 u16 adhoc_master: 1; 1536 u16 mesh: 1; 1537 u16 moniter: 1; 1538 u16 p2p_device: 1; 1539 u16 p2p_gc: 1; 1540 u16 p2p_go: 1; 1541 u16 nan: 1; 1542 }; 1543 1544 struct rtw89_btc_wl_scc_ctrl { 1545 u8 null_role1; 1546 u8 null_role2; 1547 u8 ebt_null; /* if tx null at EBT slot */ 1548 }; 1549 1550 union rtw89_btc_wl_role_info_map { 1551 u16 val; 1552 struct rtw89_btc_wl_role_info_bpos role; 1553 }; 1554 1555 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1556 u8 connect_cnt; 1557 u8 link_mode; 1558 union rtw89_btc_wl_role_info_map role_map; 1559 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1560 }; 1561 1562 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1563 u8 connect_cnt; 1564 u8 link_mode; 1565 union rtw89_btc_wl_role_info_map role_map; 1566 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1567 u32 mrole_type; /* btc_wl_mrole_type */ 1568 u32 mrole_noa_duration; /* ms */ 1569 1570 u32 dbcc_en: 1; 1571 u32 dbcc_chg: 1; 1572 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1573 u32 link_mode_chg: 1; 1574 u32 rsvd: 27; 1575 }; 1576 1577 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1578 u8 connect_cnt; 1579 u8 link_mode; 1580 union rtw89_btc_wl_role_info_map role_map; 1581 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1582 u32 mrole_type; /* btc_wl_mrole_type */ 1583 u32 mrole_noa_duration; /* ms */ 1584 1585 u32 dbcc_en: 1; 1586 u32 dbcc_chg: 1; 1587 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1588 u32 link_mode_chg: 1; 1589 u32 rsvd: 27; 1590 }; 1591 1592 struct rtw89_btc_wl_ver_info { 1593 u32 fw_coex; /* match with which coex_ver */ 1594 u32 fw; 1595 u32 mac; 1596 u32 bb; 1597 u32 rf; 1598 }; 1599 1600 struct rtw89_btc_wl_afh_info { 1601 u8 en; 1602 u8 ch; 1603 u8 bw; 1604 u8 rsvd; 1605 } __packed; 1606 1607 struct rtw89_btc_wl_rfk_info { 1608 u32 state: 2; 1609 u32 path_map: 4; 1610 u32 phy_map: 2; 1611 u32 band: 2; 1612 u32 type: 8; 1613 u32 rsvd: 14; 1614 }; 1615 1616 struct rtw89_btc_bt_smap { 1617 u32 connect: 1; 1618 u32 ble_connect: 1; 1619 u32 acl_busy: 1; 1620 u32 sco_busy: 1; 1621 u32 mesh_busy: 1; 1622 u32 inq_pag: 1; 1623 }; 1624 1625 union rtw89_btc_bt_state_map { 1626 u32 val; 1627 struct rtw89_btc_bt_smap map; 1628 }; 1629 1630 #define BTC_BT_RSSI_THMAX 4 1631 #define BTC_BT_AFH_GROUP 12 1632 #define BTC_BT_AFH_LE_GROUP 5 1633 1634 struct rtw89_btc_bt_link_info { 1635 struct rtw89_btc_u8_sta_chg profile_cnt; 1636 struct rtw89_btc_bool_sta_chg multi_link; 1637 struct rtw89_btc_bool_sta_chg relink; 1638 struct rtw89_btc_bt_hfp_desc hfp_desc; 1639 struct rtw89_btc_bt_hid_desc hid_desc; 1640 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1641 struct rtw89_btc_bt_pan_desc pan_desc; 1642 union rtw89_btc_bt_state_map status; 1643 1644 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1645 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1646 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1647 u8 afh_map[BTC_BT_AFH_GROUP]; 1648 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1649 1650 u32 role_sw: 1; 1651 u32 slave_role: 1; 1652 u32 afh_update: 1; 1653 u32 cqddr: 1; 1654 u32 rssi: 8; 1655 u32 tx_3m: 1; 1656 u32 rsvd: 19; 1657 }; 1658 1659 struct rtw89_btc_3rdcx_info { 1660 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1661 u8 hw_coex; 1662 u16 rsvd; 1663 }; 1664 1665 struct rtw89_btc_dm_emap { 1666 u32 init: 1; 1667 u32 pta_owner: 1; 1668 u32 wl_rfk_timeout: 1; 1669 u32 bt_rfk_timeout: 1; 1670 u32 wl_fw_hang: 1; 1671 u32 cycle_hang: 1; 1672 u32 w1_hang: 1; 1673 u32 b1_hang: 1; 1674 u32 tdma_no_sync: 1; 1675 u32 slot_no_sync: 1; 1676 u32 wl_slot_drift: 1; 1677 u32 bt_slot_drift: 1; 1678 u32 role_num_mismatch: 1; 1679 u32 null1_tx_late: 1; 1680 u32 bt_afh_conflict: 1; 1681 u32 bt_leafh_conflict: 1; 1682 u32 bt_slot_flood: 1; 1683 u32 wl_e2g_hang: 1; 1684 u32 wl_ver_mismatch: 1; 1685 u32 bt_ver_mismatch: 1; 1686 u32 rfe_type0: 1; 1687 u32 h2c_buffer_over: 1; 1688 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1689 u32 wl_no_sta_ntfy: 1; 1690 1691 u32 h2c_bmap_mismatch: 1; 1692 u32 c2h_bmap_mismatch: 1; 1693 u32 h2c_struct_invalid: 1; 1694 u32 c2h_struct_invalid: 1; 1695 u32 h2c_c2h_buffer_mismatch: 1; 1696 }; 1697 1698 union rtw89_btc_dm_error_map { 1699 u32 val; 1700 struct rtw89_btc_dm_emap map; 1701 }; 1702 1703 struct rtw89_btc_rf_para { 1704 u32 tx_pwr_freerun; 1705 u32 rx_gain_freerun; 1706 u32 tx_pwr_perpkt; 1707 u32 rx_gain_perpkt; 1708 }; 1709 1710 struct rtw89_btc_wl_nhm { 1711 u8 instant_wl_nhm_dbm; 1712 u8 instant_wl_nhm_per_mhz; 1713 u16 valid_record_times; 1714 s8 record_pwr[16]; 1715 u8 record_ratio[16]; 1716 s8 pwr; /* dbm_per_MHz */ 1717 u8 ratio; 1718 u8 current_status; 1719 u8 refresh; 1720 bool start_flag; 1721 s8 pwr_max; 1722 s8 pwr_min; 1723 }; 1724 1725 struct rtw89_btc_wl_info { 1726 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1727 struct rtw89_btc_wl_rfk_info rfk_info; 1728 struct rtw89_btc_wl_ver_info ver_info; 1729 struct rtw89_btc_wl_afh_info afh_info; 1730 struct rtw89_btc_wl_role_info role_info; 1731 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1732 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1733 struct rtw89_btc_wl_scan_info scan_info; 1734 struct rtw89_btc_wl_dbcc_info dbcc_info; 1735 struct rtw89_btc_rf_para rf_para; 1736 struct rtw89_btc_wl_nhm nhm; 1737 union rtw89_btc_wl_state_map status; 1738 1739 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1740 u8 rssi_level; 1741 u8 cn_report; 1742 u8 coex_mode; 1743 1744 bool bg_mode; 1745 bool scbd_change; 1746 u32 scbd; 1747 }; 1748 1749 struct rtw89_btc_module { 1750 struct rtw89_btc_ant_info ant; 1751 u8 rfe_type; 1752 u8 cv; 1753 1754 u8 bt_solo: 1; 1755 u8 bt_pos: 1; 1756 u8 switch_type: 1; 1757 u8 wa_type: 3; 1758 1759 u8 kt_ver_adie; 1760 }; 1761 1762 struct rtw89_btc_module_v7 { 1763 u8 rfe_type; 1764 u8 kt_ver; 1765 u8 bt_solo; 1766 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1767 1768 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1769 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1770 u8 kt_ver_adie; 1771 u8 rsvd; 1772 1773 struct rtw89_btc_ant_info_v7 ant; 1774 } __packed; 1775 1776 union rtw89_btc_module_info { 1777 struct rtw89_btc_module md; 1778 struct rtw89_btc_module_v7 md_v7; 1779 }; 1780 1781 #define RTW89_BTC_DM_MAXSTEP 30 1782 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1783 1784 struct rtw89_btc_dm_step { 1785 u16 step[RTW89_BTC_DM_MAXSTEP]; 1786 u8 step_pos; 1787 bool step_ov; 1788 }; 1789 1790 struct rtw89_btc_init_info { 1791 struct rtw89_btc_module module; 1792 u8 wl_guard_ch; 1793 1794 u8 wl_only: 1; 1795 u8 wl_init_ok: 1; 1796 u8 dbcc_en: 1; 1797 u8 cx_other: 1; 1798 u8 bt_only: 1; 1799 1800 u16 rsvd; 1801 }; 1802 1803 struct rtw89_btc_init_info_v7 { 1804 u8 wl_guard_ch; 1805 u8 wl_only; 1806 u8 wl_init_ok; 1807 u8 rsvd3; 1808 1809 u8 cx_other; 1810 u8 bt_only; 1811 u8 pta_mode; 1812 u8 pta_direction; 1813 1814 struct rtw89_btc_module_v7 module; 1815 } __packed; 1816 1817 union rtw89_btc_init_info_u { 1818 struct rtw89_btc_init_info init; 1819 struct rtw89_btc_init_info_v7 init_v7; 1820 }; 1821 1822 struct rtw89_btc_wl_tx_limit_para { 1823 u16 enable; 1824 u32 tx_time; /* unit: us */ 1825 u16 tx_retry; 1826 }; 1827 1828 enum rtw89_btc_bt_scan_type { 1829 BTC_SCAN_INQ = 0, 1830 BTC_SCAN_PAGE, 1831 BTC_SCAN_BLE, 1832 BTC_SCAN_INIT, 1833 BTC_SCAN_TV, 1834 BTC_SCAN_ADV, 1835 BTC_SCAN_MAX1, 1836 }; 1837 1838 enum rtw89_btc_ble_scan_type { 1839 CXSCAN_BG = 0, 1840 CXSCAN_INIT, 1841 CXSCAN_LE, 1842 CXSCAN_MAX 1843 }; 1844 1845 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1846 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1847 1848 struct rtw89_btc_bt_scan_info_v1 { 1849 __le16 win; 1850 __le16 intvl; 1851 __le32 flags; 1852 } __packed; 1853 1854 struct rtw89_btc_bt_scan_info_v2 { 1855 __le16 win; 1856 __le16 intvl; 1857 } __packed; 1858 1859 struct rtw89_btc_fbtc_btscan_v1 { 1860 u8 fver; /* btc_ver::fcxbtscan */ 1861 u8 rsvd; 1862 __le16 rsvd2; 1863 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1864 } __packed; 1865 1866 struct rtw89_btc_fbtc_btscan_v2 { 1867 u8 fver; /* btc_ver::fcxbtscan */ 1868 u8 type; 1869 __le16 rsvd2; 1870 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1871 } __packed; 1872 1873 union rtw89_btc_fbtc_btscan { 1874 struct rtw89_btc_fbtc_btscan_v1 v1; 1875 struct rtw89_btc_fbtc_btscan_v2 v2; 1876 }; 1877 1878 struct rtw89_btc_bt_info { 1879 struct rtw89_btc_bt_link_info link_info; 1880 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1881 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1882 struct rtw89_btc_bt_ver_info ver_info; 1883 struct rtw89_btc_bool_sta_chg enable; 1884 struct rtw89_btc_bool_sta_chg inq_pag; 1885 struct rtw89_btc_rf_para rf_para; 1886 union rtw89_btc_bt_rfk_info_map rfk_info; 1887 1888 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1889 u8 rssi_level; 1890 1891 u32 scbd; 1892 u32 feature; 1893 1894 u32 mbx_avl: 1; 1895 u32 whql_test: 1; 1896 u32 igno_wl: 1; 1897 u32 reinit: 1; 1898 u32 ble_scan_en: 1; 1899 u32 btg_type: 1; 1900 u32 inq: 1; 1901 u32 pag: 1; 1902 u32 run_patch_code: 1; 1903 u32 hi_lna_rx: 1; 1904 u32 scan_rx_low_pri: 1; 1905 u32 scan_info_update: 1; 1906 u32 lna_constrain: 3; 1907 u32 rsvd: 17; 1908 }; 1909 1910 struct rtw89_btc_cx { 1911 struct rtw89_btc_wl_info wl; 1912 struct rtw89_btc_bt_info bt; 1913 struct rtw89_btc_3rdcx_info other; 1914 u32 state_map; 1915 u32 cnt_bt[BTC_BCNT_NUM]; 1916 u32 cnt_wl[BTC_WCNT_NUM]; 1917 }; 1918 1919 struct rtw89_btc_fbtc_tdma { 1920 u8 type; /* btc_ver::fcxtdma */ 1921 u8 rxflctrl; 1922 u8 txpause; 1923 u8 wtgle_n; 1924 u8 leak_n; 1925 u8 ext_ctrl; 1926 u8 rxflctrl_role; 1927 u8 option_ctrl; 1928 } __packed; 1929 1930 struct rtw89_btc_fbtc_tdma_v3 { 1931 u8 fver; /* btc_ver::fcxtdma */ 1932 u8 rsvd; 1933 __le16 rsvd1; 1934 struct rtw89_btc_fbtc_tdma tdma; 1935 } __packed; 1936 1937 union rtw89_btc_fbtc_tdma_le32 { 1938 struct rtw89_btc_fbtc_tdma v1; 1939 struct rtw89_btc_fbtc_tdma_v3 v3; 1940 }; 1941 1942 #define CXMREG_MAX 30 1943 #define CXMREG_MAX_V2 20 1944 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1945 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1946 1947 enum rtw89_btc_bt_sta_counter { 1948 BTC_BCNT_RFK_REQ = 0, 1949 BTC_BCNT_RFK_GO = 1, 1950 BTC_BCNT_RFK_REJECT = 2, 1951 BTC_BCNT_RFK_FAIL = 3, 1952 BTC_BCNT_RFK_TIMEOUT = 4, 1953 BTC_BCNT_HI_TX = 5, 1954 BTC_BCNT_HI_RX = 6, 1955 BTC_BCNT_LO_TX = 7, 1956 BTC_BCNT_LO_RX = 8, 1957 BTC_BCNT_POLLUTED = 9, 1958 BTC_BCNT_STA_MAX 1959 }; 1960 1961 enum rtw89_btc_bt_sta_counter_v105 { 1962 BTC_BCNT_RFK_REQ_V105 = 0, 1963 BTC_BCNT_HI_TX_V105 = 1, 1964 BTC_BCNT_HI_RX_V105 = 2, 1965 BTC_BCNT_LO_TX_V105 = 3, 1966 BTC_BCNT_LO_RX_V105 = 4, 1967 BTC_BCNT_POLLUTED_V105 = 5, 1968 BTC_BCNT_STA_MAX_V105 1969 }; 1970 1971 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1972 u16 fver; /* btc_ver::fcxbtcrpt */ 1973 u16 rpt_cnt; /* tmr counters */ 1974 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1975 u32 wl_fw_cx_offload; 1976 u32 wl_fw_ver; 1977 u32 rpt_enable; 1978 u32 rpt_para; /* ms */ 1979 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1980 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1981 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1982 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1983 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1984 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1985 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1986 u32 c2h_cnt; /* fw send c2h counter */ 1987 u32 h2c_cnt; /* fw recv h2c counter */ 1988 } __packed; 1989 1990 struct rtw89_btc_fbtc_rpt_ctrl_info { 1991 __le32 cnt; /* fw report counter */ 1992 __le32 en; /* report map */ 1993 __le32 para; /* not used */ 1994 1995 __le32 cnt_c2h; /* fw send c2h counter */ 1996 __le32 cnt_h2c; /* fw recv h2c counter */ 1997 __le32 len_c2h; /* The total length of the last C2H */ 1998 1999 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2000 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2001 } __packed; 2002 2003 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2004 __le32 cx_ver; /* match which driver's coex version */ 2005 __le32 fw_ver; 2006 __le32 en; /* report map */ 2007 2008 __le16 cnt; /* fw report counter */ 2009 __le16 cnt_c2h; /* fw send c2h counter */ 2010 __le16 cnt_h2c; /* fw recv h2c counter */ 2011 __le16 len_c2h; /* The total length of the last C2H */ 2012 2013 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2014 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2015 } __packed; 2016 2017 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2018 __le32 cx_ver; /* match which driver's coex version */ 2019 __le32 cx_offload; 2020 __le32 fw_ver; 2021 } __packed; 2022 2023 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2024 __le32 cnt_empty; /* a2dp empty count */ 2025 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2026 __le32 cnt_tx; 2027 __le32 cnt_ack; 2028 __le32 cnt_nack; 2029 } __packed; 2030 2031 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2032 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2033 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2034 __le32 cnt_recv; /* fw recv mailbox counter */ 2035 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2036 } __packed; 2037 2038 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2039 u8 fver; 2040 u8 rsvd; 2041 __le16 rsvd1; 2042 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2043 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2044 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2045 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2046 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 2047 } __packed; 2048 2049 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2050 u8 fver; 2051 u8 rsvd; 2052 __le16 rsvd1; 2053 2054 u8 gnt_val[RTW89_PHY_MAX][4]; 2055 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2056 2057 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2058 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2059 } __packed; 2060 2061 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2062 u8 fver; 2063 u8 rsvd; 2064 __le16 rsvd1; 2065 2066 u8 gnt_val[RTW89_PHY_MAX][4]; 2067 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2068 2069 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2070 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2071 } __packed; 2072 2073 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2074 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2075 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2076 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2077 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2078 }; 2079 2080 enum rtw89_fbtc_ext_ctrl_type { 2081 CXECTL_OFF = 0x0, /* tdma off */ 2082 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2083 CXECTL_EXT = 0x2, 2084 CXECTL_MAX 2085 }; 2086 2087 union rtw89_btc_fbtc_rxflct { 2088 u8 val; 2089 u8 type: 3; 2090 u8 tgln_n: 5; 2091 }; 2092 2093 enum rtw89_btc_cxst_state { 2094 CXST_OFF = 0x0, 2095 CXST_B2W = 0x1, 2096 CXST_W1 = 0x2, 2097 CXST_W2 = 0x3, 2098 CXST_W2B = 0x4, 2099 CXST_B1 = 0x5, 2100 CXST_B2 = 0x6, 2101 CXST_B3 = 0x7, 2102 CXST_B4 = 0x8, 2103 CXST_LK = 0x9, 2104 CXST_BLK = 0xa, 2105 CXST_E2G = 0xb, 2106 CXST_E5G = 0xc, 2107 CXST_EBT = 0xd, 2108 CXST_ENULL = 0xe, 2109 CXST_WLK = 0xf, 2110 CXST_W1FDD = 0x10, 2111 CXST_B1FDD = 0x11, 2112 CXST_MAX = 0x12, 2113 }; 2114 2115 enum rtw89_btc_cxevnt { 2116 CXEVNT_TDMA_ENTRY = 0x0, 2117 CXEVNT_WL_TMR, 2118 CXEVNT_B1_TMR, 2119 CXEVNT_B2_TMR, 2120 CXEVNT_B3_TMR, 2121 CXEVNT_B4_TMR, 2122 CXEVNT_W2B_TMR, 2123 CXEVNT_B2W_TMR, 2124 CXEVNT_BCN_EARLY, 2125 CXEVNT_A2DP_EMPTY, 2126 CXEVNT_LK_END, 2127 CXEVNT_RX_ISR, 2128 CXEVNT_RX_FC0, 2129 CXEVNT_RX_FC1, 2130 CXEVNT_BT_RELINK, 2131 CXEVNT_BT_RETRY, 2132 CXEVNT_E2G, 2133 CXEVNT_E5G, 2134 CXEVNT_EBT, 2135 CXEVNT_ENULL, 2136 CXEVNT_DRV_WLK, 2137 CXEVNT_BCN_OK, 2138 CXEVNT_BT_CHANGE, 2139 CXEVNT_EBT_EXTEND, 2140 CXEVNT_E2G_NULL1, 2141 CXEVNT_B1FDD_TMR, 2142 CXEVNT_MAX 2143 }; 2144 2145 enum { 2146 CXBCN_ALL = 0x0, 2147 CXBCN_ALL_OK, 2148 CXBCN_BT_SLOT, 2149 CXBCN_BT_OK, 2150 CXBCN_MAX 2151 }; 2152 2153 enum btc_slot_type { 2154 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2155 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2156 CXSTYPE_NUM, 2157 }; 2158 2159 enum { /* TIME */ 2160 CXT_BT = 0x0, 2161 CXT_WL = 0x1, 2162 CXT_MAX 2163 }; 2164 2165 enum { /* TIME-A2DP */ 2166 CXT_FLCTRL_OFF = 0x0, 2167 CXT_FLCTRL_ON = 0x1, 2168 CXT_FLCTRL_MAX 2169 }; 2170 2171 enum { /* STEP TYPE */ 2172 CXSTEP_NONE = 0x0, 2173 CXSTEP_EVNT = 0x1, 2174 CXSTEP_SLOT = 0x2, 2175 CXSTEP_MAX, 2176 }; 2177 2178 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2179 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2180 RPT_BT_AFH_SEQ_LE = 0x20 2181 }; 2182 2183 #define BTC_DBG_MAX1 32 2184 struct rtw89_btc_fbtc_gpio_dbg { 2185 u8 fver; /* btc_ver::fcxgpiodbg */ 2186 u8 rsvd; 2187 u16 rsvd2; 2188 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2189 u32 pre_state; /* the debug signal is 1 or 0 */ 2190 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2191 } __packed; 2192 2193 struct rtw89_btc_fbtc_mreg_val_v1 { 2194 u8 fver; /* btc_ver::fcxmreg */ 2195 u8 reg_num; 2196 __le16 rsvd; 2197 __le32 mreg_val[CXMREG_MAX]; 2198 } __packed; 2199 2200 struct rtw89_btc_fbtc_mreg_val_v2 { 2201 u8 fver; /* btc_ver::fcxmreg */ 2202 u8 reg_num; 2203 __le16 rsvd; 2204 __le32 mreg_val[CXMREG_MAX_V2]; 2205 } __packed; 2206 2207 union rtw89_btc_fbtc_mreg_val { 2208 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2209 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2210 }; 2211 2212 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2213 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2214 .offset = cpu_to_le32(__offset), } 2215 2216 struct rtw89_btc_fbtc_mreg { 2217 __le16 type; 2218 __le16 bytes; 2219 __le32 offset; 2220 } __packed; 2221 2222 struct rtw89_btc_fbtc_slot { 2223 __le16 dur; 2224 __le32 cxtbl; 2225 __le16 cxtype; 2226 } __packed; 2227 2228 struct rtw89_btc_fbtc_slots { 2229 u8 fver; /* btc_ver::fcxslots */ 2230 u8 tbl_num; 2231 __le16 rsvd; 2232 __le32 update_map; 2233 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2234 } __packed; 2235 2236 struct rtw89_btc_fbtc_step { 2237 u8 type; 2238 u8 val; 2239 __le16 difft; 2240 } __packed; 2241 2242 struct rtw89_btc_fbtc_steps_v2 { 2243 u8 fver; /* btc_ver::fcxstep */ 2244 u8 rsvd; 2245 __le16 cnt; 2246 __le16 pos_old; 2247 __le16 pos_new; 2248 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2249 } __packed; 2250 2251 struct rtw89_btc_fbtc_steps_v3 { 2252 u8 fver; 2253 u8 en; 2254 __le16 rsvd; 2255 __le32 cnt; 2256 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2257 } __packed; 2258 2259 union rtw89_btc_fbtc_steps_info { 2260 struct rtw89_btc_fbtc_steps_v2 v2; 2261 struct rtw89_btc_fbtc_steps_v3 v3; 2262 }; 2263 2264 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2265 u8 fver; /* btc_ver::fcxcysta */ 2266 u8 rsvd; 2267 __le16 cycles; /* total cycle number */ 2268 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2269 __le16 a2dpept; /* a2dp empty cnt */ 2270 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2271 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2272 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2273 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2274 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2275 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2276 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2277 __le16 tmax_a2dpept; /* max a2dp empty time */ 2278 __le16 tavg_lk; /* avg leak-slot time */ 2279 __le16 tmax_lk; /* max leak-slot time */ 2280 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2281 __le32 bcn_cnt[CXBCN_MAX]; 2282 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2283 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2284 __le32 skip_cnt; 2285 __le32 exception; 2286 __le32 except_cnt; 2287 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2288 } __packed; 2289 2290 struct rtw89_btc_fbtc_fdd_try_info { 2291 __le16 cycles[CXT_FLCTRL_MAX]; 2292 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2293 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2294 } __packed; 2295 2296 struct rtw89_btc_fbtc_cycle_time_info { 2297 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2298 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2299 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2300 } __packed; 2301 2302 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2303 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2304 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2305 } __packed; 2306 2307 struct rtw89_btc_fbtc_a2dp_trx_stat { 2308 u8 empty_cnt; 2309 u8 retry_cnt; 2310 u8 tx_rate; 2311 u8 tx_cnt; 2312 u8 ack_cnt; 2313 u8 nack_cnt; 2314 u8 rsvd1; 2315 u8 rsvd2; 2316 } __packed; 2317 2318 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2319 u8 empty_cnt; 2320 u8 retry_cnt; 2321 u8 tx_rate; 2322 u8 tx_cnt; 2323 u8 ack_cnt; 2324 u8 nack_cnt; 2325 u8 no_empty_cnt; 2326 u8 rsvd; 2327 } __packed; 2328 2329 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2330 __le16 cnt; /* a2dp empty cnt */ 2331 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2332 __le16 tavg; /* avg a2dp empty time */ 2333 __le16 tmax; /* max a2dp empty time */ 2334 } __packed; 2335 2336 struct rtw89_btc_fbtc_cycle_leak_info { 2337 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2338 __le16 tavg; /* avg leak-slot time */ 2339 __le16 tmax; /* max leak-slot time */ 2340 } __packed; 2341 2342 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2343 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2344 2345 struct rtw89_btc_fbtc_cycle_fddt_info { 2346 __le16 train_cycle; 2347 __le16 tp; 2348 2349 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2350 s8 bt_tx_power; /* decrease Tx power (dB) */ 2351 s8 bt_rx_gain; /* LNA constrain level */ 2352 u8 no_empty_cnt; 2353 2354 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2355 u8 cn; /* condition_num */ 2356 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2357 u8 train_result; /* refer to enum btc_fddt_check_map */ 2358 } __packed; 2359 2360 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2361 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2362 2363 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2364 __le16 train_cycle; 2365 __le16 tp; 2366 2367 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2368 s8 bt_tx_power; /* decrease Tx power (dB) */ 2369 s8 bt_rx_gain; /* LNA constrain level */ 2370 u8 no_empty_cnt; 2371 2372 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2373 u8 cn; /* condition_num */ 2374 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2375 u8 train_result; /* refer to enum btc_fddt_check_map */ 2376 } __packed; 2377 2378 struct rtw89_btc_fbtc_fddt_cell_status { 2379 s8 wl_tx_pwr; 2380 s8 bt_tx_pwr; 2381 s8 bt_rx_gain; 2382 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2383 } __packed; 2384 2385 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2386 u8 fver; 2387 u8 rsvd; 2388 __le16 cycles; /* total cycle number */ 2389 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2390 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2391 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2392 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2393 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2394 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2395 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2396 __le32 bcn_cnt[CXBCN_MAX]; 2397 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2398 __le32 skip_cnt; 2399 __le32 except_cnt; 2400 __le32 except_map; 2401 } __packed; 2402 2403 #define FDD_TRAIN_WL_DIRECTION 2 2404 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2405 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2406 2407 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2408 u8 fver; 2409 u8 rsvd; 2410 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2411 u8 except_cnt; 2412 2413 __le16 skip_cnt; 2414 __le16 cycles; /* total cycle number */ 2415 2416 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2417 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2418 __le16 bcn_cnt[CXBCN_MAX]; 2419 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2420 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2421 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2422 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2423 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2424 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2425 [FDD_TRAIN_WL_RSSI_LEVEL] 2426 [FDD_TRAIN_BT_RSSI_LEVEL]; 2427 __le32 except_map; 2428 } __packed; 2429 2430 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2431 u8 fver; 2432 u8 rsvd; 2433 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2434 u8 except_cnt; 2435 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2436 2437 __le16 skip_cnt; 2438 __le16 cycles; /* total cycle number */ 2439 2440 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2441 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2442 __le16 bcn_cnt[CXBCN_MAX]; 2443 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2444 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2445 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2446 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2447 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2448 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2449 [FDD_TRAIN_WL_RSSI_LEVEL] 2450 [FDD_TRAIN_BT_RSSI_LEVEL]; 2451 __le32 except_map; 2452 } __packed; 2453 2454 union rtw89_btc_fbtc_cysta_info { 2455 struct rtw89_btc_fbtc_cysta_v2 v2; 2456 struct rtw89_btc_fbtc_cysta_v3 v3; 2457 struct rtw89_btc_fbtc_cysta_v4 v4; 2458 struct rtw89_btc_fbtc_cysta_v5 v5; 2459 }; 2460 2461 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2462 u8 fver; /* btc_ver::fcxnullsta */ 2463 u8 rsvd; 2464 __le16 rsvd2; 2465 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2466 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2467 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2468 } __packed; 2469 2470 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2471 u8 fver; /* btc_ver::fcxnullsta */ 2472 u8 rsvd; 2473 __le16 rsvd2; 2474 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2475 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2476 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2477 } __packed; 2478 2479 union rtw89_btc_fbtc_cynullsta_info { 2480 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2481 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2482 }; 2483 2484 struct rtw89_btc_fbtc_btver { 2485 u8 fver; /* btc_ver::fcxbtver */ 2486 u8 rsvd; 2487 __le16 rsvd2; 2488 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2489 __le32 fw_ver; 2490 __le32 feature; 2491 } __packed; 2492 2493 struct rtw89_btc_fbtc_btafh { 2494 u8 fver; /* btc_ver::fcxbtafh */ 2495 u8 rsvd; 2496 __le16 rsvd2; 2497 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2498 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2499 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2500 } __packed; 2501 2502 struct rtw89_btc_fbtc_btafh_v2 { 2503 u8 fver; /* btc_ver::fcxbtafh */ 2504 u8 rsvd; 2505 u8 rsvd2; 2506 u8 map_type; 2507 u8 afh_l[4]; 2508 u8 afh_m[4]; 2509 u8 afh_h[4]; 2510 u8 afh_le_a[4]; 2511 u8 afh_le_b[4]; 2512 } __packed; 2513 2514 struct rtw89_btc_fbtc_btdevinfo { 2515 u8 fver; /* btc_ver::fcxbtdevinfo */ 2516 u8 rsvd; 2517 __le16 vendor_id; 2518 __le32 dev_name; /* only 24 bits valid */ 2519 __le32 flush_time; 2520 } __packed; 2521 2522 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2523 struct rtw89_btc_rf_trx_para { 2524 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2525 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2526 u8 bt_tx_power; /* decrease Tx power (dB) */ 2527 u8 bt_rx_gain; /* LNA constrain level */ 2528 }; 2529 2530 struct rtw89_btc_trx_info { 2531 u8 tx_lvl; 2532 u8 rx_lvl; 2533 u8 wl_rssi; 2534 u8 bt_rssi; 2535 2536 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2537 s8 rx_gain; /* rx gain table index (TBD.) */ 2538 s8 bt_tx_power; /* decrease Tx power (dB) */ 2539 s8 bt_rx_gain; /* LNA constrain level */ 2540 2541 u8 cn; /* condition_num */ 2542 s8 nhm; 2543 u8 bt_profile; 2544 u8 rsvd2; 2545 2546 u16 tx_rate; 2547 u16 rx_rate; 2548 2549 u32 tx_tp; 2550 u32 rx_tp; 2551 u32 rx_err_ratio; 2552 }; 2553 2554 struct rtw89_btc_dm { 2555 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2556 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 2557 struct rtw89_btc_fbtc_tdma tdma; 2558 struct rtw89_btc_fbtc_tdma tdma_now; 2559 struct rtw89_mac_ax_coex_gnt gnt; 2560 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2561 struct rtw89_btc_rf_trx_para rf_trx_para; 2562 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2563 struct rtw89_btc_dm_step dm_step; 2564 struct rtw89_btc_wl_scc_ctrl wl_scc; 2565 struct rtw89_btc_trx_info trx_info; 2566 union rtw89_btc_dm_error_map error; 2567 u32 cnt_dm[BTC_DCNT_NUM]; 2568 u32 cnt_notify[BTC_NCNT_NUM]; 2569 2570 u32 update_slot_map; 2571 u32 set_ant_path; 2572 2573 u32 wl_only: 1; 2574 u32 wl_fw_cx_offload: 1; 2575 u32 freerun: 1; 2576 u32 fddt_train: 1; 2577 u32 wl_ps_ctrl: 2; 2578 u32 wl_mimo_ps: 1; 2579 u32 leak_ap: 1; 2580 u32 noisy_level: 3; 2581 u32 coex_info_map: 8; 2582 u32 bt_only: 1; 2583 u32 wl_btg_rx: 2; 2584 u32 trx_para_level: 8; 2585 u32 wl_stb_chg: 1; 2586 u32 pta_owner: 1; 2587 2588 u32 tdma_instant_excute: 1; 2589 u32 wl_btg_rx_rb: 2; 2590 2591 u16 slot_dur[CXST_MAX]; 2592 2593 u8 run_reason; 2594 u8 run_action; 2595 2596 u8 wl_pre_agc: 2; 2597 u8 wl_lna2: 1; 2598 u8 wl_pre_agc_rb: 2; 2599 }; 2600 2601 struct rtw89_btc_ctrl { 2602 u32 manual: 1; 2603 u32 igno_bt: 1; 2604 u32 always_freerun: 1; 2605 u32 trace_step: 16; 2606 u32 rsvd: 12; 2607 }; 2608 2609 struct rtw89_btc_ctrl_v7 { 2610 u8 manual; 2611 u8 igno_bt; 2612 u8 always_freerun; 2613 u8 rsvd; 2614 } __packed; 2615 2616 union rtw89_btc_ctrl_list { 2617 struct rtw89_btc_ctrl ctrl; 2618 struct rtw89_btc_ctrl_v7 ctrl_v7; 2619 }; 2620 2621 struct rtw89_btc_dbg { 2622 /* cmd "rb" */ 2623 bool rb_done; 2624 u32 rb_val; 2625 }; 2626 2627 enum rtw89_btc_btf_fw_event { 2628 BTF_EVNT_RPT = 0, 2629 BTF_EVNT_BT_INFO = 1, 2630 BTF_EVNT_BT_SCBD = 2, 2631 BTF_EVNT_BT_REG = 3, 2632 BTF_EVNT_CX_RUNINFO = 4, 2633 BTF_EVNT_BT_PSD = 5, 2634 BTF_EVNT_BUF_OVERFLOW, 2635 BTF_EVNT_C2H_LOOPBACK, 2636 BTF_EVNT_MAX, 2637 }; 2638 2639 enum btf_fw_event_report { 2640 BTC_RPT_TYPE_CTRL = 0x0, 2641 BTC_RPT_TYPE_TDMA, 2642 BTC_RPT_TYPE_SLOT, 2643 BTC_RPT_TYPE_CYSTA, 2644 BTC_RPT_TYPE_STEP, 2645 BTC_RPT_TYPE_NULLSTA, 2646 BTC_RPT_TYPE_MREG, 2647 BTC_RPT_TYPE_GPIO_DBG, 2648 BTC_RPT_TYPE_BT_VER, 2649 BTC_RPT_TYPE_BT_SCAN, 2650 BTC_RPT_TYPE_BT_AFH, 2651 BTC_RPT_TYPE_BT_DEVICE, 2652 BTC_RPT_TYPE_TEST, 2653 BTC_RPT_TYPE_MAX = 31 2654 }; 2655 2656 enum rtw_btc_btf_reg_type { 2657 REG_MAC = 0x0, 2658 REG_BB = 0x1, 2659 REG_RF = 0x2, 2660 REG_BT_RF = 0x3, 2661 REG_BT_MODEM = 0x4, 2662 REG_BT_BLUEWIZE = 0x5, 2663 REG_BT_VENDOR = 0x6, 2664 REG_BT_LE = 0x7, 2665 REG_MAX_TYPE, 2666 }; 2667 2668 struct rtw89_btc_rpt_cmn_info { 2669 u32 rx_cnt; 2670 u32 rx_len; 2671 u32 req_len; /* expected rsp len */ 2672 u8 req_fver; /* expected rsp fver */ 2673 u8 rsp_fver; /* fver from fw */ 2674 u8 valid; 2675 } __packed; 2676 2677 union rtw89_btc_fbtc_btafh_info { 2678 struct rtw89_btc_fbtc_btafh v1; 2679 struct rtw89_btc_fbtc_btafh_v2 v2; 2680 }; 2681 2682 struct rtw89_btc_report_ctrl_state { 2683 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2684 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2685 }; 2686 2687 struct rtw89_btc_rpt_fbtc_tdma { 2688 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2689 union rtw89_btc_fbtc_tdma_le32 finfo; 2690 }; 2691 2692 struct rtw89_btc_rpt_fbtc_slots { 2693 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2694 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 2695 }; 2696 2697 struct rtw89_btc_rpt_fbtc_cysta { 2698 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2699 union rtw89_btc_fbtc_cysta_info finfo; 2700 }; 2701 2702 struct rtw89_btc_rpt_fbtc_step { 2703 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2704 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2705 }; 2706 2707 struct rtw89_btc_rpt_fbtc_nullsta { 2708 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2709 union rtw89_btc_fbtc_cynullsta_info finfo; 2710 }; 2711 2712 struct rtw89_btc_rpt_fbtc_mreg { 2713 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2714 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2715 }; 2716 2717 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2718 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2719 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2720 }; 2721 2722 struct rtw89_btc_rpt_fbtc_btver { 2723 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2724 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2725 }; 2726 2727 struct rtw89_btc_rpt_fbtc_btscan { 2728 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2729 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2730 }; 2731 2732 struct rtw89_btc_rpt_fbtc_btafh { 2733 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2734 union rtw89_btc_fbtc_btafh_info finfo; 2735 }; 2736 2737 struct rtw89_btc_rpt_fbtc_btdev { 2738 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2739 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2740 }; 2741 2742 enum rtw89_btc_btfre_type { 2743 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2744 BTFRE_UNDEF_TYPE, 2745 BTFRE_EXCEPTION, 2746 BTFRE_MAX, 2747 }; 2748 2749 struct rtw89_btc_btf_fwinfo { 2750 u32 cnt_c2h; 2751 u32 cnt_h2c; 2752 u32 cnt_h2c_fail; 2753 u32 event[BTF_EVNT_MAX]; 2754 2755 u32 err[BTFRE_MAX]; 2756 u32 len_mismch; 2757 u32 fver_mismch; 2758 u32 rpt_en_map; 2759 2760 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2761 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2762 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2763 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2764 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2765 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2766 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2767 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2768 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2769 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2770 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2771 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2772 }; 2773 2774 struct rtw89_btc_ver { 2775 enum rtw89_core_chip_id chip_id; 2776 u32 fw_ver_code; 2777 2778 u8 fcxbtcrpt; 2779 u8 fcxtdma; 2780 u8 fcxslots; 2781 u8 fcxcysta; 2782 u8 fcxstep; 2783 u8 fcxnullsta; 2784 u8 fcxmreg; 2785 u8 fcxgpiodbg; 2786 u8 fcxbtver; 2787 u8 fcxbtscan; 2788 u8 fcxbtafh; 2789 u8 fcxbtdevinfo; 2790 u8 fwlrole; 2791 u8 frptmap; 2792 u8 fcxctrl; 2793 u8 fcxinit; 2794 2795 u8 drvinfo_type; 2796 u16 info_buf; 2797 u8 max_role_num; 2798 }; 2799 2800 #define RTW89_BTC_POLICY_MAXLEN 512 2801 2802 struct rtw89_btc { 2803 const struct rtw89_btc_ver *ver; 2804 2805 struct rtw89_btc_cx cx; 2806 struct rtw89_btc_dm dm; 2807 union rtw89_btc_ctrl_list ctrl; 2808 union rtw89_btc_module_info mdinfo; 2809 struct rtw89_btc_btf_fwinfo fwinfo; 2810 struct rtw89_btc_dbg dbg; 2811 2812 struct work_struct eapol_notify_work; 2813 struct work_struct arp_notify_work; 2814 struct work_struct dhcp_notify_work; 2815 struct work_struct icmp_notify_work; 2816 2817 u32 bt_req_len; 2818 2819 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2820 u8 ant_type; 2821 u8 btg_pos; 2822 u16 policy_len; 2823 u16 policy_type; 2824 bool bt_req_en; 2825 bool update_policy_force; 2826 bool lps; 2827 bool manual_ctrl; 2828 }; 2829 2830 enum rtw89_btc_hmsg { 2831 RTW89_BTC_HMSG_TMR_EN = 0x0, 2832 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 2833 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 2834 RTW89_BTC_HMSG_FW_EV = 0x3, 2835 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 2836 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 2837 2838 NUM_OF_RTW89_BTC_HMSG, 2839 }; 2840 2841 enum rtw89_ra_mode { 2842 RTW89_RA_MODE_CCK = BIT(0), 2843 RTW89_RA_MODE_OFDM = BIT(1), 2844 RTW89_RA_MODE_HT = BIT(2), 2845 RTW89_RA_MODE_VHT = BIT(3), 2846 RTW89_RA_MODE_HE = BIT(4), 2847 RTW89_RA_MODE_EHT = BIT(5), 2848 }; 2849 2850 enum rtw89_ra_report_mode { 2851 RTW89_RA_RPT_MODE_LEGACY, 2852 RTW89_RA_RPT_MODE_HT, 2853 RTW89_RA_RPT_MODE_VHT, 2854 RTW89_RA_RPT_MODE_HE, 2855 RTW89_RA_RPT_MODE_EHT, 2856 }; 2857 2858 enum rtw89_dig_noisy_level { 2859 RTW89_DIG_NOISY_LEVEL0 = -1, 2860 RTW89_DIG_NOISY_LEVEL1 = 0, 2861 RTW89_DIG_NOISY_LEVEL2 = 1, 2862 RTW89_DIG_NOISY_LEVEL3 = 2, 2863 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2864 }; 2865 2866 enum rtw89_gi_ltf { 2867 RTW89_GILTF_LGI_4XHE32 = 0, 2868 RTW89_GILTF_SGI_4XHE08 = 1, 2869 RTW89_GILTF_2XHE16 = 2, 2870 RTW89_GILTF_2XHE08 = 3, 2871 RTW89_GILTF_1XHE16 = 4, 2872 RTW89_GILTF_1XHE08 = 5, 2873 RTW89_GILTF_MAX 2874 }; 2875 2876 enum rtw89_rx_frame_type { 2877 RTW89_RX_TYPE_MGNT = 0, 2878 RTW89_RX_TYPE_CTRL = 1, 2879 RTW89_RX_TYPE_DATA = 2, 2880 RTW89_RX_TYPE_RSVD = 3, 2881 }; 2882 2883 enum rtw89_efuse_block { 2884 RTW89_EFUSE_BLOCK_SYS = 0, 2885 RTW89_EFUSE_BLOCK_RF = 1, 2886 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 2887 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 2888 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 2889 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 2890 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 2891 RTW89_EFUSE_BLOCK_ADIE = 7, 2892 2893 RTW89_EFUSE_BLOCK_NUM, 2894 RTW89_EFUSE_BLOCK_IGNORE, 2895 }; 2896 2897 struct rtw89_ra_info { 2898 u8 is_dis_ra:1; 2899 /* Bit0 : CCK 2900 * Bit1 : OFDM 2901 * Bit2 : HT 2902 * Bit3 : VHT 2903 * Bit4 : HE 2904 * Bit5 : EHT 2905 */ 2906 u8 mode_ctrl:6; 2907 u8 bw_cap:3; /* enum rtw89_bandwidth */ 2908 u8 macid; 2909 u8 dcm_cap:1; 2910 u8 er_cap:1; 2911 u8 init_rate_lv:2; 2912 u8 upd_all:1; 2913 u8 en_sgi:1; 2914 u8 ldpc_cap:1; 2915 u8 stbc_cap:1; 2916 u8 ss_num:3; 2917 u8 giltf:3; 2918 u8 upd_bw_nss_mask:1; 2919 u8 upd_mask:1; 2920 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2921 /* BFee CSI */ 2922 u8 band_num; 2923 u8 ra_csi_rate_en:1; 2924 u8 fixed_csi_rate_en:1; 2925 u8 cr_tbl_sel:1; 2926 u8 fix_giltf_en:1; 2927 u8 fix_giltf:3; 2928 u8 rsvd2:1; 2929 u8 csi_mcs_ss_idx; 2930 u8 csi_mode:2; 2931 u8 csi_gi_ltf:3; 2932 u8 csi_bw:3; 2933 }; 2934 2935 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2936 #define RTW89_PPDU_MAC_INFO_SIZE 8 2937 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2938 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 2939 2940 #define RTW89_MAX_RX_AGG_NUM 64 2941 #define RTW89_MAX_TX_AGG_NUM 128 2942 2943 struct rtw89_ampdu_params { 2944 u16 agg_num; 2945 bool amsdu; 2946 }; 2947 2948 struct rtw89_ra_report { 2949 struct rate_info txrate; 2950 u32 bit_rate; 2951 u16 hw_rate; 2952 bool might_fallback_legacy; 2953 }; 2954 2955 DECLARE_EWMA(rssi, 10, 16); 2956 DECLARE_EWMA(evm, 10, 16); 2957 DECLARE_EWMA(snr, 10, 16); 2958 2959 struct rtw89_ba_cam_entry { 2960 struct list_head list; 2961 u8 tid; 2962 }; 2963 2964 #define RTW89_MAX_ADDR_CAM_NUM 128 2965 #define RTW89_MAX_BSSID_CAM_NUM 20 2966 #define RTW89_MAX_SEC_CAM_NUM 128 2967 #define RTW89_MAX_BA_CAM_NUM 24 2968 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2969 2970 struct rtw89_addr_cam_entry { 2971 u8 addr_cam_idx; 2972 u8 offset; 2973 u8 len; 2974 u8 valid : 1; 2975 u8 addr_mask : 6; 2976 u8 wapi : 1; 2977 u8 mask_sel : 2; 2978 u8 bssid_cam_idx: 6; 2979 2980 u8 sec_ent_mode; 2981 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2982 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2983 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2984 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2985 }; 2986 2987 struct rtw89_bssid_cam_entry { 2988 u8 bssid[ETH_ALEN]; 2989 u8 phy_idx; 2990 u8 bssid_cam_idx; 2991 u8 offset; 2992 u8 len; 2993 u8 valid : 1; 2994 u8 num; 2995 }; 2996 2997 struct rtw89_sec_cam_entry { 2998 u8 sec_cam_idx; 2999 u8 offset; 3000 u8 len; 3001 u8 type : 4; 3002 u8 ext_key : 1; 3003 u8 spp_mode : 1; 3004 /* 256 bits */ 3005 u8 key[32]; 3006 }; 3007 3008 struct rtw89_sta { 3009 u8 mac_id; 3010 bool disassoc; 3011 bool er_cap; 3012 struct rtw89_dev *rtwdev; 3013 struct rtw89_vif *rtwvif; 3014 struct rtw89_ra_info ra; 3015 struct rtw89_ra_report ra_report; 3016 int max_agg_wait; 3017 u8 prev_rssi; 3018 struct ewma_rssi avg_rssi; 3019 struct ewma_rssi rssi[RF_PATH_MAX]; 3020 struct ewma_snr avg_snr; 3021 struct ewma_evm evm_min[RF_PATH_MAX]; 3022 struct ewma_evm evm_max[RF_PATH_MAX]; 3023 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 3024 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 3025 struct ieee80211_rx_status rx_status; 3026 u16 rx_hw_rate; 3027 __le32 htc_template; 3028 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3029 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3030 struct list_head ba_cam_list; 3031 struct sk_buff_head roc_queue; 3032 3033 bool use_cfg_mask; 3034 struct cfg80211_bitrate_mask mask; 3035 3036 bool cctl_tx_time; 3037 u32 ampdu_max_time:4; 3038 bool cctl_tx_retry_limit; 3039 u32 data_tx_cnt_lmt:6; 3040 }; 3041 3042 struct rtw89_efuse { 3043 bool valid; 3044 bool power_k_valid; 3045 u8 xtal_cap; 3046 u8 addr[ETH_ALEN]; 3047 u8 rfe_type; 3048 char country_code[2]; 3049 }; 3050 3051 struct rtw89_phy_rate_pattern { 3052 u64 ra_mask; 3053 u16 rate; 3054 u8 ra_mode; 3055 bool enable; 3056 }; 3057 3058 struct rtw89_tx_wait_info { 3059 struct rcu_head rcu_head; 3060 struct completion completion; 3061 bool tx_done; 3062 }; 3063 3064 struct rtw89_tx_skb_data { 3065 struct rtw89_tx_wait_info __rcu *wait; 3066 u8 hci_priv[]; 3067 }; 3068 3069 #define RTW89_ROC_IDLE_TIMEOUT 500 3070 #define RTW89_ROC_TX_TIMEOUT 30 3071 enum rtw89_roc_state { 3072 RTW89_ROC_IDLE, 3073 RTW89_ROC_NORMAL, 3074 RTW89_ROC_MGMT, 3075 }; 3076 3077 struct rtw89_roc { 3078 struct ieee80211_channel chan; 3079 struct delayed_work roc_work; 3080 enum ieee80211_roc_type type; 3081 enum rtw89_roc_state state; 3082 int duration; 3083 }; 3084 3085 #define RTW89_P2P_MAX_NOA_NUM 2 3086 3087 struct rtw89_p2p_ie_head { 3088 u8 eid; 3089 u8 ie_len; 3090 u8 oui[3]; 3091 u8 oui_type; 3092 } __packed; 3093 3094 struct rtw89_noa_attr_head { 3095 u8 attr_type; 3096 __le16 attr_len; 3097 u8 index; 3098 u8 oppps_ctwindow; 3099 } __packed; 3100 3101 struct rtw89_p2p_noa_ie { 3102 struct rtw89_p2p_ie_head p2p_head; 3103 struct rtw89_noa_attr_head noa_head; 3104 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3105 } __packed; 3106 3107 struct rtw89_p2p_noa_setter { 3108 struct rtw89_p2p_noa_ie ie; 3109 u8 noa_count; 3110 u8 noa_index; 3111 }; 3112 3113 struct rtw89_vif { 3114 struct list_head list; 3115 struct rtw89_dev *rtwdev; 3116 struct rtw89_roc roc; 3117 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3118 enum rtw89_sub_entity_idx sub_entity_idx; 3119 enum rtw89_reg_6ghz_power reg_6ghz_power; 3120 3121 u8 mac_id; 3122 u8 port; 3123 u8 mac_addr[ETH_ALEN]; 3124 u8 bssid[ETH_ALEN]; 3125 u8 phy_idx; 3126 u8 mac_idx; 3127 u8 net_type; 3128 u8 wifi_role; 3129 u8 self_role; 3130 u8 wmm; 3131 u8 bcn_hit_cond; 3132 u8 hit_rule; 3133 u8 last_noa_nr; 3134 u64 sync_bcn_tsf; 3135 bool offchan; 3136 bool trigger; 3137 bool lsig_txop; 3138 u8 tgt_ind; 3139 u8 frm_tgt_ind; 3140 bool wowlan_pattern; 3141 bool wowlan_uc; 3142 bool wowlan_magic; 3143 bool is_hesta; 3144 bool last_a_ctrl; 3145 bool dyn_tb_bedge_en; 3146 bool pre_pwr_diff_en; 3147 bool pwr_diff_en; 3148 u8 def_tri_idx; 3149 u32 tdls_peer; 3150 struct work_struct update_beacon_work; 3151 struct rtw89_addr_cam_entry addr_cam; 3152 struct rtw89_bssid_cam_entry bssid_cam; 3153 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3154 struct rtw89_traffic_stats stats; 3155 struct rtw89_phy_rate_pattern rate_pattern; 3156 struct cfg80211_scan_request *scan_req; 3157 struct ieee80211_scan_ies *scan_ies; 3158 struct list_head general_pkt_list; 3159 struct rtw89_p2p_noa_setter p2p_noa; 3160 }; 3161 3162 enum rtw89_lv1_rcvy_step { 3163 RTW89_LV1_RCVY_STEP_1, 3164 RTW89_LV1_RCVY_STEP_2, 3165 }; 3166 3167 struct rtw89_hci_ops { 3168 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3169 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3170 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3171 void (*reset)(struct rtw89_dev *rtwdev); 3172 int (*start)(struct rtw89_dev *rtwdev); 3173 void (*stop)(struct rtw89_dev *rtwdev); 3174 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3175 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3176 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3177 3178 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3179 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3180 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3181 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3182 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3183 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3184 3185 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3186 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3187 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3188 int (*deinit)(struct rtw89_dev *rtwdev); 3189 3190 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3191 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3192 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3193 int (*napi_poll)(struct napi_struct *napi, int budget); 3194 3195 /* Deal with locks inside recovery_start and recovery_complete callbacks 3196 * by hci instance, and handle things which need to consider under SER. 3197 * e.g. turn on/off interrupts except for the one for halt notification. 3198 */ 3199 void (*recovery_start)(struct rtw89_dev *rtwdev); 3200 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3201 3202 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3203 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3204 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3205 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3206 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3207 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3208 void (*disable_intr)(struct rtw89_dev *rtwdev); 3209 void (*enable_intr)(struct rtw89_dev *rtwdev); 3210 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3211 }; 3212 3213 struct rtw89_hci_info { 3214 const struct rtw89_hci_ops *ops; 3215 enum rtw89_hci_type type; 3216 u32 rpwm_addr; 3217 u32 cpwm_addr; 3218 bool paused; 3219 }; 3220 3221 struct rtw89_chip_ops { 3222 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3223 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3224 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3225 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3226 void (*bb_reset)(struct rtw89_dev *rtwdev, 3227 enum rtw89_phy_idx phy_idx); 3228 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3229 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3230 u32 addr, u32 mask); 3231 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3232 u32 addr, u32 mask, u32 data); 3233 void (*set_channel)(struct rtw89_dev *rtwdev, 3234 const struct rtw89_chan *chan, 3235 enum rtw89_mac_idx mac_idx, 3236 enum rtw89_phy_idx phy_idx); 3237 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3238 struct rtw89_channel_help_params *p, 3239 const struct rtw89_chan *chan, 3240 enum rtw89_mac_idx mac_idx, 3241 enum rtw89_phy_idx phy_idx); 3242 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3243 enum rtw89_efuse_block block); 3244 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3245 void (*fem_setup)(struct rtw89_dev *rtwdev); 3246 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3247 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3248 void (*rfk_init)(struct rtw89_dev *rtwdev); 3249 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3250 void (*rfk_channel)(struct rtw89_dev *rtwdev); 3251 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3252 enum rtw89_phy_idx phy_idx); 3253 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 3254 void (*rfk_track)(struct rtw89_dev *rtwdev); 3255 void (*power_trim)(struct rtw89_dev *rtwdev); 3256 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3257 const struct rtw89_chan *chan, 3258 enum rtw89_phy_idx phy_idx); 3259 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3260 enum rtw89_phy_idx phy_idx); 3261 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3262 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3263 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3264 enum rtw89_phy_idx phy_idx); 3265 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3266 struct rtw89_rx_phy_ppdu *phy_ppdu, 3267 struct ieee80211_rx_status *status); 3268 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3269 enum rtw89_phy_idx phy_idx); 3270 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3271 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3272 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3273 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3274 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3275 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3276 struct rtw89_rx_desc_info *desc_info, 3277 u8 *data, u32 data_offset); 3278 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3279 struct rtw89_tx_desc_info *desc_info, 3280 void *txdesc); 3281 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3282 struct rtw89_tx_desc_info *desc_info, 3283 void *txdesc); 3284 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3285 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3286 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3287 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3288 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3289 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3290 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3291 struct rtw89_vif *rtwvif, 3292 struct rtw89_sta *rtwsta); 3293 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3294 struct rtw89_vif *rtwvif, 3295 struct rtw89_sta *rtwsta); 3296 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3297 struct ieee80211_vif *vif, 3298 struct ieee80211_sta *sta); 3299 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3300 struct ieee80211_vif *vif, 3301 struct ieee80211_sta *sta); 3302 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3303 struct rtw89_vif *rtwvif, 3304 struct rtw89_sta *rtwsta); 3305 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3306 struct rtw89_vif *rtwvif); 3307 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3308 bool valid, struct ieee80211_ampdu_params *params); 3309 3310 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3311 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3312 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3313 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3314 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3315 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3316 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3317 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3318 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3319 }; 3320 3321 enum rtw89_dma_ch { 3322 RTW89_DMA_ACH0 = 0, 3323 RTW89_DMA_ACH1 = 1, 3324 RTW89_DMA_ACH2 = 2, 3325 RTW89_DMA_ACH3 = 3, 3326 RTW89_DMA_ACH4 = 4, 3327 RTW89_DMA_ACH5 = 5, 3328 RTW89_DMA_ACH6 = 6, 3329 RTW89_DMA_ACH7 = 7, 3330 RTW89_DMA_B0MG = 8, 3331 RTW89_DMA_B0HI = 9, 3332 RTW89_DMA_B1MG = 10, 3333 RTW89_DMA_B1HI = 11, 3334 RTW89_DMA_H2C = 12, 3335 RTW89_DMA_CH_NUM = 13 3336 }; 3337 3338 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3339 3340 enum rtw89_mlo_dbcc_mode { 3341 MLO_DBCC_NOT_SUPPORT = 1, 3342 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3343 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3344 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3345 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3346 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3347 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3348 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3349 DBCC_LEGACY = 0xffffffff, 3350 }; 3351 3352 enum rtw89_scan_be_operation { 3353 RTW89_SCAN_OP_STOP, 3354 RTW89_SCAN_OP_START, 3355 RTW89_SCAN_OP_SETPARM, 3356 RTW89_SCAN_OP_GETRPT, 3357 RTW89_SCAN_OP_NUM 3358 }; 3359 3360 enum rtw89_scan_be_mode { 3361 RTW89_SCAN_MODE_SA, 3362 RTW89_SCAN_MODE_MACC, 3363 RTW89_SCAN_MODE_NUM 3364 }; 3365 3366 enum rtw89_scan_be_opmode { 3367 RTW89_SCAN_OPMODE_NONE, 3368 RTW89_SCAN_OPMODE_TBTT, 3369 RTW89_SCAN_OPMODE_INTV, 3370 RTW89_SCAN_OPMODE_CNT, 3371 RTW89_SCAN_OPMODE_NUM, 3372 }; 3373 3374 struct rtw89_scan_option { 3375 bool enable; 3376 bool target_ch_mode; 3377 u8 num_macc_role; 3378 u8 num_opch; 3379 u8 repeat; 3380 u16 norm_pd; 3381 u16 slow_pd; 3382 u16 norm_cy; 3383 u8 opch_end; 3384 u64 prohib_chan; 3385 enum rtw89_phy_idx band; 3386 enum rtw89_scan_be_operation operation; 3387 enum rtw89_scan_be_mode scan_mode; 3388 enum rtw89_mlo_dbcc_mode mlo_mode; 3389 }; 3390 3391 enum rtw89_qta_mode { 3392 RTW89_QTA_SCC, 3393 RTW89_QTA_DBCC, 3394 RTW89_QTA_DLFW, 3395 RTW89_QTA_WOW, 3396 3397 /* keep last */ 3398 RTW89_QTA_INVALID, 3399 }; 3400 3401 struct rtw89_hfc_ch_cfg { 3402 u16 min; 3403 u16 max; 3404 #define grp_0 0 3405 #define grp_1 1 3406 #define grp_num 2 3407 u8 grp; 3408 }; 3409 3410 struct rtw89_hfc_ch_info { 3411 u16 aval; 3412 u16 used; 3413 }; 3414 3415 struct rtw89_hfc_pub_cfg { 3416 u16 grp0; 3417 u16 grp1; 3418 u16 pub_max; 3419 u16 wp_thrd; 3420 }; 3421 3422 struct rtw89_hfc_pub_info { 3423 u16 g0_used; 3424 u16 g1_used; 3425 u16 g0_aval; 3426 u16 g1_aval; 3427 u16 pub_aval; 3428 u16 wp_aval; 3429 }; 3430 3431 struct rtw89_hfc_prec_cfg { 3432 u16 ch011_prec; 3433 u16 h2c_prec; 3434 u16 wp_ch07_prec; 3435 u16 wp_ch811_prec; 3436 u8 ch011_full_cond; 3437 u8 h2c_full_cond; 3438 u8 wp_ch07_full_cond; 3439 u8 wp_ch811_full_cond; 3440 }; 3441 3442 struct rtw89_hfc_param { 3443 bool en; 3444 bool h2c_en; 3445 u8 mode; 3446 const struct rtw89_hfc_ch_cfg *ch_cfg; 3447 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3448 struct rtw89_hfc_pub_cfg pub_cfg; 3449 struct rtw89_hfc_pub_info pub_info; 3450 struct rtw89_hfc_prec_cfg prec_cfg; 3451 }; 3452 3453 struct rtw89_hfc_param_ini { 3454 const struct rtw89_hfc_ch_cfg *ch_cfg; 3455 const struct rtw89_hfc_pub_cfg *pub_cfg; 3456 const struct rtw89_hfc_prec_cfg *prec_cfg; 3457 u8 mode; 3458 }; 3459 3460 struct rtw89_dle_size { 3461 u16 pge_size; 3462 u16 lnk_pge_num; 3463 u16 unlnk_pge_num; 3464 /* for WiFi 7 chips below */ 3465 u32 srt_ofst; 3466 }; 3467 3468 struct rtw89_wde_quota { 3469 u16 hif; 3470 u16 wcpu; 3471 u16 pkt_in; 3472 u16 cpu_io; 3473 }; 3474 3475 struct rtw89_ple_quota { 3476 u16 cma0_tx; 3477 u16 cma1_tx; 3478 u16 c2h; 3479 u16 h2c; 3480 u16 wcpu; 3481 u16 mpdu_proc; 3482 u16 cma0_dma; 3483 u16 cma1_dma; 3484 u16 bb_rpt; 3485 u16 wd_rel; 3486 u16 cpu_io; 3487 u16 tx_rpt; 3488 /* for WiFi 7 chips below */ 3489 u16 h2d; 3490 }; 3491 3492 struct rtw89_rsvd_quota { 3493 u16 mpdu_info_tbl; 3494 u16 b0_csi; 3495 u16 b1_csi; 3496 u16 b0_lmr; 3497 u16 b1_lmr; 3498 u16 b0_ftm; 3499 u16 b1_ftm; 3500 u16 b0_smr; 3501 u16 b1_smr; 3502 u16 others; 3503 }; 3504 3505 struct rtw89_dle_rsvd_size { 3506 u32 srt_ofst; 3507 u32 size; 3508 }; 3509 3510 struct rtw89_dle_mem { 3511 enum rtw89_qta_mode mode; 3512 const struct rtw89_dle_size *wde_size; 3513 const struct rtw89_dle_size *ple_size; 3514 const struct rtw89_wde_quota *wde_min_qt; 3515 const struct rtw89_wde_quota *wde_max_qt; 3516 const struct rtw89_ple_quota *ple_min_qt; 3517 const struct rtw89_ple_quota *ple_max_qt; 3518 /* for WiFi 7 chips below */ 3519 const struct rtw89_rsvd_quota *rsvd_qt; 3520 const struct rtw89_dle_rsvd_size *rsvd0_size; 3521 const struct rtw89_dle_rsvd_size *rsvd1_size; 3522 }; 3523 3524 struct rtw89_reg_def { 3525 u32 addr; 3526 u32 mask; 3527 }; 3528 3529 struct rtw89_reg2_def { 3530 u32 addr; 3531 u32 data; 3532 }; 3533 3534 struct rtw89_reg3_def { 3535 u32 addr; 3536 u32 mask; 3537 u32 data; 3538 }; 3539 3540 struct rtw89_reg5_def { 3541 u8 flag; /* recognized by parsers */ 3542 u8 path; 3543 u32 addr; 3544 u32 mask; 3545 u32 data; 3546 }; 3547 3548 struct rtw89_reg_imr { 3549 u32 addr; 3550 u32 clr; 3551 u32 set; 3552 }; 3553 3554 struct rtw89_phy_table { 3555 const struct rtw89_reg2_def *regs; 3556 u32 n_regs; 3557 enum rtw89_rf_path rf_path; 3558 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3559 enum rtw89_rf_path rf_path, void *data); 3560 }; 3561 3562 struct rtw89_txpwr_table { 3563 const void *data; 3564 u32 size; 3565 void (*load)(struct rtw89_dev *rtwdev, 3566 const struct rtw89_txpwr_table *tbl); 3567 }; 3568 3569 struct rtw89_txpwr_rule_2ghz { 3570 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3571 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3572 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3573 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3574 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3575 }; 3576 3577 struct rtw89_txpwr_rule_5ghz { 3578 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3579 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3580 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3581 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3582 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3583 }; 3584 3585 struct rtw89_txpwr_rule_6ghz { 3586 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3587 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3588 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3589 [RTW89_6G_CH_NUM]; 3590 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3591 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3592 [RTW89_6G_CH_NUM]; 3593 }; 3594 3595 struct rtw89_tx_shape { 3596 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3597 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3598 }; 3599 3600 struct rtw89_rfe_parms { 3601 const struct rtw89_txpwr_table *byr_tbl; 3602 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3603 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3604 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3605 struct rtw89_tx_shape tx_shape; 3606 }; 3607 3608 struct rtw89_rfe_parms_conf { 3609 const struct rtw89_rfe_parms *rfe_parms; 3610 u8 rfe_type; 3611 }; 3612 3613 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3614 3615 struct rtw89_txpwr_conf { 3616 u8 rfe_type; 3617 u8 ent_sz; 3618 u32 num_ents; 3619 const void *data; 3620 }; 3621 3622 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3623 3624 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3625 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \ 3626 memcpy(&(entry), cursor, \ 3627 min_t(u8, sizeof(entry), (conf)->ent_sz)); \ 3628 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3629 (cursor) += (conf)->ent_sz, \ 3630 memcpy(&(entry), cursor, \ 3631 min_t(u8, sizeof(entry), (conf)->ent_sz))) 3632 3633 struct rtw89_txpwr_byrate_data { 3634 struct rtw89_txpwr_conf conf; 3635 struct rtw89_txpwr_table tbl; 3636 }; 3637 3638 struct rtw89_txpwr_lmt_2ghz_data { 3639 struct rtw89_txpwr_conf conf; 3640 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3641 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3642 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3643 }; 3644 3645 struct rtw89_txpwr_lmt_5ghz_data { 3646 struct rtw89_txpwr_conf conf; 3647 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3648 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3649 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3650 }; 3651 3652 struct rtw89_txpwr_lmt_6ghz_data { 3653 struct rtw89_txpwr_conf conf; 3654 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3655 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3656 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3657 [RTW89_6G_CH_NUM]; 3658 }; 3659 3660 struct rtw89_txpwr_lmt_ru_2ghz_data { 3661 struct rtw89_txpwr_conf conf; 3662 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3663 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3664 }; 3665 3666 struct rtw89_txpwr_lmt_ru_5ghz_data { 3667 struct rtw89_txpwr_conf conf; 3668 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3669 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3670 }; 3671 3672 struct rtw89_txpwr_lmt_ru_6ghz_data { 3673 struct rtw89_txpwr_conf conf; 3674 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3675 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3676 [RTW89_6G_CH_NUM]; 3677 }; 3678 3679 struct rtw89_tx_shape_lmt_data { 3680 struct rtw89_txpwr_conf conf; 3681 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3682 }; 3683 3684 struct rtw89_tx_shape_lmt_ru_data { 3685 struct rtw89_txpwr_conf conf; 3686 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3687 }; 3688 3689 struct rtw89_rfe_data { 3690 struct rtw89_txpwr_byrate_data byrate; 3691 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 3692 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 3693 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 3694 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 3695 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 3696 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 3697 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 3698 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 3699 struct rtw89_rfe_parms rfe_parms; 3700 }; 3701 3702 struct rtw89_page_regs { 3703 u32 hci_fc_ctrl; 3704 u32 ch_page_ctrl; 3705 u32 ach_page_ctrl; 3706 u32 ach_page_info; 3707 u32 pub_page_info3; 3708 u32 pub_page_ctrl1; 3709 u32 pub_page_ctrl2; 3710 u32 pub_page_info1; 3711 u32 pub_page_info2; 3712 u32 wp_page_ctrl1; 3713 u32 wp_page_ctrl2; 3714 u32 wp_page_info1; 3715 }; 3716 3717 struct rtw89_imr_info { 3718 u32 wdrls_imr_set; 3719 u32 wsec_imr_reg; 3720 u32 wsec_imr_set; 3721 u32 mpdu_tx_imr_set; 3722 u32 mpdu_rx_imr_set; 3723 u32 sta_sch_imr_set; 3724 u32 txpktctl_imr_b0_reg; 3725 u32 txpktctl_imr_b0_clr; 3726 u32 txpktctl_imr_b0_set; 3727 u32 txpktctl_imr_b1_reg; 3728 u32 txpktctl_imr_b1_clr; 3729 u32 txpktctl_imr_b1_set; 3730 u32 wde_imr_clr; 3731 u32 wde_imr_set; 3732 u32 ple_imr_clr; 3733 u32 ple_imr_set; 3734 u32 host_disp_imr_clr; 3735 u32 host_disp_imr_set; 3736 u32 cpu_disp_imr_clr; 3737 u32 cpu_disp_imr_set; 3738 u32 other_disp_imr_clr; 3739 u32 other_disp_imr_set; 3740 u32 bbrpt_com_err_imr_reg; 3741 u32 bbrpt_chinfo_err_imr_reg; 3742 u32 bbrpt_err_imr_set; 3743 u32 bbrpt_dfs_err_imr_reg; 3744 u32 ptcl_imr_clr; 3745 u32 ptcl_imr_set; 3746 u32 cdma_imr_0_reg; 3747 u32 cdma_imr_0_clr; 3748 u32 cdma_imr_0_set; 3749 u32 cdma_imr_1_reg; 3750 u32 cdma_imr_1_clr; 3751 u32 cdma_imr_1_set; 3752 u32 phy_intf_imr_reg; 3753 u32 phy_intf_imr_clr; 3754 u32 phy_intf_imr_set; 3755 u32 rmac_imr_reg; 3756 u32 rmac_imr_clr; 3757 u32 rmac_imr_set; 3758 u32 tmac_imr_reg; 3759 u32 tmac_imr_clr; 3760 u32 tmac_imr_set; 3761 }; 3762 3763 struct rtw89_imr_table { 3764 const struct rtw89_reg_imr *regs; 3765 u32 n_regs; 3766 }; 3767 3768 struct rtw89_xtal_info { 3769 u32 xcap_reg; 3770 u32 sc_xo_mask; 3771 u32 sc_xi_mask; 3772 }; 3773 3774 struct rtw89_rrsr_cfgs { 3775 struct rtw89_reg3_def ref_rate; 3776 struct rtw89_reg3_def rsc; 3777 }; 3778 3779 struct rtw89_dig_regs { 3780 u32 seg0_pd_reg; 3781 u32 pd_lower_bound_mask; 3782 u32 pd_spatial_reuse_en; 3783 u32 bmode_pd_reg; 3784 u32 bmode_cca_rssi_limit_en; 3785 u32 bmode_pd_lower_bound_reg; 3786 u32 bmode_rssi_nocca_low_th_mask; 3787 struct rtw89_reg_def p0_lna_init; 3788 struct rtw89_reg_def p1_lna_init; 3789 struct rtw89_reg_def p0_tia_init; 3790 struct rtw89_reg_def p1_tia_init; 3791 struct rtw89_reg_def p0_rxb_init; 3792 struct rtw89_reg_def p1_rxb_init; 3793 struct rtw89_reg_def p0_p20_pagcugc_en; 3794 struct rtw89_reg_def p0_s20_pagcugc_en; 3795 struct rtw89_reg_def p1_p20_pagcugc_en; 3796 struct rtw89_reg_def p1_s20_pagcugc_en; 3797 }; 3798 3799 struct rtw89_edcca_regs { 3800 u32 edcca_level; 3801 u32 edcca_mask; 3802 u32 edcca_p_mask; 3803 u32 ppdu_level; 3804 u32 ppdu_mask; 3805 u32 rpt_a; 3806 u32 rpt_b; 3807 u32 rpt_sel; 3808 u32 rpt_sel_mask; 3809 u32 rpt_sel_be; 3810 u32 rpt_sel_be_mask; 3811 u32 tx_collision_t2r_st; 3812 u32 tx_collision_t2r_st_mask; 3813 }; 3814 3815 struct rtw89_phy_ul_tb_info { 3816 bool dyn_tb_tri_en; 3817 u8 def_if_bandedge; 3818 }; 3819 3820 struct rtw89_antdiv_stats { 3821 struct ewma_rssi cck_rssi_avg; 3822 struct ewma_rssi ofdm_rssi_avg; 3823 struct ewma_rssi non_legacy_rssi_avg; 3824 u16 pkt_cnt_cck; 3825 u16 pkt_cnt_ofdm; 3826 u16 pkt_cnt_non_legacy; 3827 u32 evm; 3828 }; 3829 3830 struct rtw89_antdiv_info { 3831 struct rtw89_antdiv_stats target_stats; 3832 struct rtw89_antdiv_stats main_stats; 3833 struct rtw89_antdiv_stats aux_stats; 3834 u8 training_count; 3835 u8 rssi_pre; 3836 bool get_stats; 3837 }; 3838 3839 enum rtw89_chanctx_state { 3840 RTW89_CHANCTX_STATE_MCC_START, 3841 RTW89_CHANCTX_STATE_MCC_STOP, 3842 }; 3843 3844 enum rtw89_chanctx_callbacks { 3845 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 3846 RTW89_CHANCTX_CALLBACK_RFK, 3847 3848 NUM_OF_RTW89_CHANCTX_CALLBACKS, 3849 }; 3850 3851 struct rtw89_chanctx_listener { 3852 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 3853 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 3854 }; 3855 3856 struct rtw89_chip_info { 3857 enum rtw89_core_chip_id chip_id; 3858 enum rtw89_chip_gen chip_gen; 3859 const struct rtw89_chip_ops *ops; 3860 const struct rtw89_mac_gen_def *mac_def; 3861 const struct rtw89_phy_gen_def *phy_def; 3862 const char *fw_basename; 3863 u8 fw_format_max; 3864 bool try_ce_fw; 3865 u8 bbmcu_nr; 3866 u32 needed_fw_elms; 3867 u32 fifo_size; 3868 bool small_fifo_size; 3869 u32 dle_scc_rsvd_size; 3870 u16 max_amsdu_limit; 3871 bool dis_2g_40m_ul_ofdma; 3872 u32 rsvd_ple_ofst; 3873 const struct rtw89_hfc_param_ini *hfc_param_ini; 3874 const struct rtw89_dle_mem *dle_mem; 3875 u8 wde_qempty_acq_grpnum; 3876 u8 wde_qempty_mgq_grpsel; 3877 u32 rf_base_addr[2]; 3878 u8 support_chanctx_num; 3879 u8 support_bands; 3880 u16 support_bandwidths; 3881 bool support_unii4; 3882 bool ul_tb_waveform_ctrl; 3883 bool ul_tb_pwr_diff; 3884 bool hw_sec_hdr; 3885 u8 rf_path_num; 3886 u8 tx_nss; 3887 u8 rx_nss; 3888 u8 acam_num; 3889 u8 bcam_num; 3890 u8 scam_num; 3891 u8 bacam_num; 3892 u8 bacam_dynamic_num; 3893 enum rtw89_bacam_ver bacam_ver; 3894 u8 ppdu_max_usr; 3895 3896 u8 sec_ctrl_efuse_size; 3897 u32 physical_efuse_size; 3898 u32 logical_efuse_size; 3899 u32 limit_efuse_size; 3900 u32 dav_phy_efuse_size; 3901 u32 dav_log_efuse_size; 3902 u32 phycap_addr; 3903 u32 phycap_size; 3904 const struct rtw89_efuse_block_cfg *efuse_blocks; 3905 3906 const struct rtw89_pwr_cfg * const *pwr_on_seq; 3907 const struct rtw89_pwr_cfg * const *pwr_off_seq; 3908 const struct rtw89_phy_table *bb_table; 3909 const struct rtw89_phy_table *bb_gain_table; 3910 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 3911 const struct rtw89_phy_table *nctl_table; 3912 const struct rtw89_rfk_tbl *nctl_post_table; 3913 const struct rtw89_phy_dig_gain_table *dig_table; 3914 const struct rtw89_dig_regs *dig_regs; 3915 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 3916 3917 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 3918 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 3919 const struct rtw89_rfe_parms *dflt_parms; 3920 const struct rtw89_chanctx_listener *chanctx_listener; 3921 3922 u8 txpwr_factor_rf; 3923 u8 txpwr_factor_mac; 3924 3925 u32 para_ver; 3926 u32 wlcx_desired; 3927 u8 btcx_desired; 3928 u8 scbd; 3929 u8 mailbox; 3930 3931 u8 afh_guard_ch; 3932 const u8 *wl_rssi_thres; 3933 const u8 *bt_rssi_thres; 3934 u8 rssi_tol; 3935 3936 u8 mon_reg_num; 3937 const struct rtw89_btc_fbtc_mreg *mon_reg; 3938 u8 rf_para_ulink_num; 3939 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 3940 u8 rf_para_dlink_num; 3941 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 3942 u8 ps_mode_supported; 3943 u8 low_power_hci_modes; 3944 3945 u32 h2c_cctl_func_id; 3946 u32 hci_func_en_addr; 3947 u32 h2c_desc_size; 3948 u32 txwd_body_size; 3949 u32 txwd_info_size; 3950 u32 h2c_ctrl_reg; 3951 const u32 *h2c_regs; 3952 struct rtw89_reg_def h2c_counter_reg; 3953 u32 c2h_ctrl_reg; 3954 const u32 *c2h_regs; 3955 struct rtw89_reg_def c2h_counter_reg; 3956 const struct rtw89_page_regs *page_regs; 3957 u32 wow_reason_reg; 3958 bool cfo_src_fd; 3959 bool cfo_hw_comp; 3960 const struct rtw89_reg_def *dcfo_comp; 3961 u8 dcfo_comp_sft; 3962 const struct rtw89_imr_info *imr_info; 3963 const struct rtw89_imr_table *imr_dmac_table; 3964 const struct rtw89_imr_table *imr_cmac_table; 3965 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 3966 struct rtw89_reg_def bss_clr_vld; 3967 u32 bss_clr_map_reg; 3968 u32 dma_ch_mask; 3969 const struct rtw89_edcca_regs *edcca_regs; 3970 const struct wiphy_wowlan_support *wowlan_stub; 3971 const struct rtw89_xtal_info *xtal_info; 3972 }; 3973 3974 union rtw89_bus_info { 3975 const struct rtw89_pci_info *pci; 3976 }; 3977 3978 struct rtw89_driver_info { 3979 const struct rtw89_chip_info *chip; 3980 union rtw89_bus_info bus; 3981 }; 3982 3983 enum rtw89_hcifc_mode { 3984 RTW89_HCIFC_POH = 0, 3985 RTW89_HCIFC_STF = 1, 3986 RTW89_HCIFC_SDIO = 2, 3987 3988 /* keep last */ 3989 RTW89_HCIFC_MODE_INVALID, 3990 }; 3991 3992 struct rtw89_dle_info { 3993 const struct rtw89_rsvd_quota *rsvd_qt; 3994 enum rtw89_qta_mode qta_mode; 3995 u16 ple_pg_size; 3996 u16 ple_free_pg; 3997 u16 c0_rx_qta; 3998 u16 c1_rx_qta; 3999 }; 4000 4001 enum rtw89_host_rpr_mode { 4002 RTW89_RPR_MODE_POH = 0, 4003 RTW89_RPR_MODE_STF 4004 }; 4005 4006 #define RTW89_COMPLETION_BUF_SIZE 40 4007 #define RTW89_WAIT_COND_IDLE UINT_MAX 4008 4009 struct rtw89_completion_data { 4010 bool err; 4011 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4012 }; 4013 4014 struct rtw89_wait_info { 4015 atomic_t cond; 4016 struct completion completion; 4017 struct rtw89_completion_data data; 4018 }; 4019 4020 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4021 4022 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4023 { 4024 init_completion(&wait->completion); 4025 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4026 } 4027 4028 struct rtw89_mac_info { 4029 struct rtw89_dle_info dle_info; 4030 struct rtw89_hfc_param hfc_param; 4031 enum rtw89_qta_mode qta_mode; 4032 u8 rpwm_seq_num; 4033 u8 cpwm_seq_num; 4034 4035 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4036 struct rtw89_wait_info fw_ofld_wait; 4037 }; 4038 4039 enum rtw89_fwdl_check_type { 4040 RTW89_FWDL_CHECK_FREERTOS_DONE, 4041 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4042 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4043 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4044 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4045 }; 4046 4047 enum rtw89_fw_type { 4048 RTW89_FW_NORMAL = 1, 4049 RTW89_FW_WOWLAN = 3, 4050 RTW89_FW_NORMAL_CE = 5, 4051 RTW89_FW_BBMCU0 = 64, 4052 RTW89_FW_BBMCU1 = 65, 4053 RTW89_FW_LOGFMT = 255, 4054 }; 4055 4056 enum rtw89_fw_feature { 4057 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4058 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4059 RTW89_FW_FEATURE_TX_WAKE, 4060 RTW89_FW_FEATURE_CRASH_TRIGGER, 4061 RTW89_FW_FEATURE_NO_PACKET_DROP, 4062 RTW89_FW_FEATURE_NO_DEEP_PS, 4063 RTW89_FW_FEATURE_NO_LPS_PG, 4064 RTW89_FW_FEATURE_BEACON_FILTER, 4065 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4066 }; 4067 4068 struct rtw89_fw_suit { 4069 enum rtw89_fw_type type; 4070 const u8 *data; 4071 u32 size; 4072 u8 major_ver; 4073 u8 minor_ver; 4074 u8 sub_ver; 4075 u8 sub_idex; 4076 u16 build_year; 4077 u16 build_mon; 4078 u16 build_date; 4079 u16 build_hour; 4080 u16 build_min; 4081 u8 cmd_ver; 4082 u8 hdr_ver; 4083 u32 commitid; 4084 }; 4085 4086 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4087 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4088 #define RTW89_FW_SUIT_VER_CODE(s) \ 4089 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4090 4091 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4092 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4093 (mfw_hdr)->ver.minor, \ 4094 (mfw_hdr)->ver.sub, \ 4095 (mfw_hdr)->ver.idx) 4096 4097 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4098 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4099 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4100 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4101 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4102 4103 struct rtw89_fw_req_info { 4104 const struct firmware *firmware; 4105 struct completion completion; 4106 }; 4107 4108 struct rtw89_fw_log { 4109 struct rtw89_fw_suit suit; 4110 bool enable; 4111 u32 last_fmt_id; 4112 u32 fmt_count; 4113 const __le32 *fmt_ids; 4114 const char *(*fmts)[]; 4115 }; 4116 4117 struct rtw89_fw_elm_info { 4118 struct rtw89_phy_table *bb_tbl; 4119 struct rtw89_phy_table *bb_gain; 4120 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4121 struct rtw89_phy_table *rf_nctl; 4122 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4123 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4124 }; 4125 4126 enum rtw89_fw_mss_dev_type { 4127 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4128 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4129 }; 4130 4131 struct rtw89_fw_secure { 4132 bool secure_boot; 4133 u32 sb_sel_mgn; 4134 u8 mss_dev_type; 4135 u8 mss_cust_idx; 4136 u8 mss_key_num; 4137 }; 4138 4139 struct rtw89_fw_info { 4140 struct rtw89_fw_req_info req; 4141 int fw_format; 4142 u8 h2c_seq; 4143 u8 rec_seq; 4144 u8 h2c_counter; 4145 u8 c2h_counter; 4146 struct rtw89_fw_suit normal; 4147 struct rtw89_fw_suit wowlan; 4148 struct rtw89_fw_suit bbmcu0; 4149 struct rtw89_fw_suit bbmcu1; 4150 struct rtw89_fw_log log; 4151 u32 feature_map; 4152 struct rtw89_fw_elm_info elm_info; 4153 struct rtw89_fw_secure sec; 4154 }; 4155 4156 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4157 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4158 4159 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4160 ((_fw)->feature_map |= BIT(_fw_feature)) 4161 4162 struct rtw89_cam_info { 4163 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4164 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4165 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4166 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4167 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4168 }; 4169 4170 enum rtw89_sar_sources { 4171 RTW89_SAR_SOURCE_NONE, 4172 RTW89_SAR_SOURCE_COMMON, 4173 4174 RTW89_SAR_SOURCE_NR, 4175 }; 4176 4177 enum rtw89_sar_subband { 4178 RTW89_SAR_2GHZ_SUBBAND, 4179 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4180 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4181 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 4182 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4183 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4184 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4185 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4186 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4187 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4188 4189 RTW89_SAR_SUBBAND_NR, 4190 }; 4191 4192 struct rtw89_sar_cfg_common { 4193 bool set[RTW89_SAR_SUBBAND_NR]; 4194 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4195 }; 4196 4197 struct rtw89_sar_info { 4198 /* used to decide how to acces SAR cfg union */ 4199 enum rtw89_sar_sources src; 4200 4201 /* reserved for different knids of SAR cfg struct. 4202 * supposed that a single cfg struct cannot handle various SAR sources. 4203 */ 4204 union { 4205 struct rtw89_sar_cfg_common cfg_common; 4206 }; 4207 }; 4208 4209 enum rtw89_tas_state { 4210 RTW89_TAS_STATE_DPR_OFF, 4211 RTW89_TAS_STATE_DPR_ON, 4212 RTW89_TAS_STATE_DPR_FORBID, 4213 }; 4214 4215 #define RTW89_TAS_MAX_WINDOW 50 4216 struct rtw89_tas_info { 4217 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4218 s32 total_txpwr; 4219 u8 cur_idx; 4220 s8 dpr_gap; 4221 s8 delta; 4222 enum rtw89_tas_state state; 4223 bool enable; 4224 }; 4225 4226 struct rtw89_chanctx_cfg { 4227 enum rtw89_sub_entity_idx idx; 4228 int ref_count; 4229 }; 4230 4231 enum rtw89_chanctx_changes { 4232 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4233 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4234 RTW89_CHANCTX_P2P_PS_CHANGE, 4235 RTW89_CHANCTX_BT_SLOT_CHANGE, 4236 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4237 4238 NUM_OF_RTW89_CHANCTX_CHANGES, 4239 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4240 }; 4241 4242 enum rtw89_entity_mode { 4243 RTW89_ENTITY_MODE_SCC, 4244 RTW89_ENTITY_MODE_MCC_PREPARE, 4245 RTW89_ENTITY_MODE_MCC, 4246 4247 NUM_OF_RTW89_ENTITY_MODE, 4248 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4249 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4250 }; 4251 4252 struct rtw89_sub_entity { 4253 struct cfg80211_chan_def chandef; 4254 struct rtw89_chan chan; 4255 struct rtw89_chan_rcd rcd; 4256 4257 /* only assigned when running with chanctx_ops */ 4258 struct rtw89_chanctx_cfg *cfg; 4259 }; 4260 4261 struct rtw89_edcca_bak { 4262 u8 a; 4263 u8 p; 4264 u8 ppdu; 4265 u8 th_old; 4266 }; 4267 4268 enum rtw89_dm_type { 4269 RTW89_DM_DYNAMIC_EDCCA, 4270 }; 4271 4272 struct rtw89_hal { 4273 u32 rx_fltr; 4274 u8 cv; 4275 u8 acv; 4276 u32 antenna_tx; 4277 u32 antenna_rx; 4278 u8 tx_nss; 4279 u8 rx_nss; 4280 bool tx_path_diversity; 4281 bool ant_diversity; 4282 bool ant_diversity_fixed; 4283 bool support_cckpd; 4284 bool support_igi; 4285 atomic_t roc_entity_idx; 4286 4287 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4288 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 4289 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 4290 struct cfg80211_chan_def roc_chandef; 4291 4292 bool entity_active; 4293 bool entity_pause; 4294 enum rtw89_entity_mode entity_mode; 4295 4296 struct rtw89_edcca_bak edcca_bak; 4297 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4298 }; 4299 4300 #define RTW89_MAX_MAC_ID_NUM 128 4301 #define RTW89_MAX_PKT_OFLD_NUM 255 4302 4303 enum rtw89_flags { 4304 RTW89_FLAG_POWERON, 4305 RTW89_FLAG_DMAC_FUNC, 4306 RTW89_FLAG_CMAC0_FUNC, 4307 RTW89_FLAG_CMAC1_FUNC, 4308 RTW89_FLAG_FW_RDY, 4309 RTW89_FLAG_RUNNING, 4310 RTW89_FLAG_PROBE_DONE, 4311 RTW89_FLAG_BFEE_MON, 4312 RTW89_FLAG_BFEE_EN, 4313 RTW89_FLAG_BFEE_TIMER_KEEP, 4314 RTW89_FLAG_NAPI_RUNNING, 4315 RTW89_FLAG_LEISURE_PS, 4316 RTW89_FLAG_LOW_POWER_MODE, 4317 RTW89_FLAG_INACTIVE_PS, 4318 RTW89_FLAG_CRASH_SIMULATING, 4319 RTW89_FLAG_SER_HANDLING, 4320 RTW89_FLAG_WOWLAN, 4321 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4322 RTW89_FLAG_CHANGING_INTERFACE, 4323 4324 NUM_OF_RTW89_FLAGS, 4325 }; 4326 4327 enum rtw89_pkt_drop_sel { 4328 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4329 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4330 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4331 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4332 RTW89_PKT_DROP_SEL_MACID_ALL, 4333 RTW89_PKT_DROP_SEL_MG0_ONCE, 4334 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4335 RTW89_PKT_DROP_SEL_HIQ_PORT, 4336 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4337 RTW89_PKT_DROP_SEL_BAND, 4338 RTW89_PKT_DROP_SEL_BAND_ONCE, 4339 RTW89_PKT_DROP_SEL_REL_MACID, 4340 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4341 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4342 }; 4343 4344 struct rtw89_pkt_drop_params { 4345 enum rtw89_pkt_drop_sel sel; 4346 enum rtw89_mac_idx mac_band; 4347 u8 macid; 4348 u8 port; 4349 u8 mbssid; 4350 bool tf_trs; 4351 u32 macid_band_sel[4]; 4352 }; 4353 4354 struct rtw89_pkt_stat { 4355 u16 beacon_nr; 4356 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4357 }; 4358 4359 DECLARE_EWMA(thermal, 4, 4); 4360 4361 struct rtw89_phy_stat { 4362 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4363 struct rtw89_pkt_stat cur_pkt_stat; 4364 struct rtw89_pkt_stat last_pkt_stat; 4365 }; 4366 4367 enum rtw89_rfk_report_state { 4368 RTW89_RFK_STATE_START = 0x0, 4369 RTW89_RFK_STATE_OK = 0x1, 4370 RTW89_RFK_STATE_FAIL = 0x2, 4371 RTW89_RFK_STATE_TIMEOUT = 0x3, 4372 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4373 }; 4374 4375 struct rtw89_rfk_wait_info { 4376 struct completion completion; 4377 ktime_t start_time; 4378 enum rtw89_rfk_report_state state; 4379 u8 version; 4380 }; 4381 4382 #define RTW89_DACK_PATH_NR 2 4383 #define RTW89_DACK_IDX_NR 2 4384 #define RTW89_DACK_MSBK_NR 16 4385 struct rtw89_dack_info { 4386 bool dack_done; 4387 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4388 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4389 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4390 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4391 u32 dack_cnt; 4392 bool addck_timeout[RTW89_DACK_PATH_NR]; 4393 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4394 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4395 }; 4396 4397 #define RTW89_RFK_CHS_NR 3 4398 4399 struct rtw89_rfk_mcc_info { 4400 u8 ch[RTW89_RFK_CHS_NR]; 4401 u8 band[RTW89_RFK_CHS_NR]; 4402 u8 bw[RTW89_RFK_CHS_NR]; 4403 u8 table_idx; 4404 }; 4405 4406 #define RTW89_IQK_CHS_NR 2 4407 #define RTW89_IQK_PATH_NR 4 4408 4409 struct rtw89_lck_info { 4410 u8 thermal[RF_PATH_MAX]; 4411 }; 4412 4413 struct rtw89_rx_dck_info { 4414 u8 thermal[RF_PATH_MAX]; 4415 }; 4416 4417 struct rtw89_iqk_info { 4418 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4419 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4420 bool lok_fail[RTW89_IQK_PATH_NR]; 4421 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4422 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4423 u32 iqk_fail_cnt; 4424 bool is_iqk_init; 4425 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4426 u8 iqk_band[RTW89_IQK_PATH_NR]; 4427 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4428 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4429 u8 iqk_times; 4430 u8 version; 4431 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4432 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4433 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4434 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4435 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4436 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4437 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4438 bool is_nbiqk; 4439 bool iqk_fft_en; 4440 bool iqk_xym_en; 4441 bool iqk_sram_en; 4442 bool iqk_cfir_en; 4443 u32 syn1to2; 4444 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4445 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4446 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4447 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4448 }; 4449 4450 #define RTW89_DPK_RF_PATH 2 4451 #define RTW89_DPK_AVG_THERMAL_NUM 8 4452 #define RTW89_DPK_BKUP_NUM 2 4453 struct rtw89_dpk_bkup_para { 4454 enum rtw89_band band; 4455 enum rtw89_bandwidth bw; 4456 u8 ch; 4457 bool path_ok; 4458 u8 mdpd_en; 4459 u8 txagc_dpk; 4460 u8 ther_dpk; 4461 u8 gs; 4462 u16 pwsf; 4463 }; 4464 4465 struct rtw89_dpk_info { 4466 bool is_dpk_enable; 4467 bool is_dpk_reload_en; 4468 u8 dpk_gs[RTW89_PHY_MAX]; 4469 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4470 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4471 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4472 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4473 u8 cur_idx[RTW89_DPK_RF_PATH]; 4474 u8 cur_k_set; 4475 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4476 }; 4477 4478 struct rtw89_fem_info { 4479 bool elna_2g; 4480 bool elna_5g; 4481 bool epa_2g; 4482 bool epa_5g; 4483 bool epa_6g; 4484 }; 4485 4486 struct rtw89_phy_ch_info { 4487 u8 rssi_min; 4488 u16 rssi_min_macid; 4489 u8 pre_rssi_min; 4490 u8 rssi_max; 4491 u16 rssi_max_macid; 4492 u8 rxsc_160; 4493 u8 rxsc_80; 4494 u8 rxsc_40; 4495 u8 rxsc_20; 4496 u8 rxsc_l; 4497 u8 is_noisy; 4498 }; 4499 4500 struct rtw89_agc_gaincode_set { 4501 u8 lna_idx; 4502 u8 tia_idx; 4503 u8 rxb_idx; 4504 }; 4505 4506 #define IGI_RSSI_TH_NUM 5 4507 #define FA_TH_NUM 4 4508 #define LNA_GAIN_NUM 7 4509 #define TIA_GAIN_NUM 2 4510 struct rtw89_dig_info { 4511 struct rtw89_agc_gaincode_set cur_gaincode; 4512 bool force_gaincode_idx_en; 4513 struct rtw89_agc_gaincode_set force_gaincode; 4514 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4515 u16 fa_th[FA_TH_NUM]; 4516 u8 igi_rssi; 4517 u8 igi_fa_rssi; 4518 u8 fa_rssi_ofst; 4519 u8 dyn_igi_max; 4520 u8 dyn_igi_min; 4521 bool dyn_pd_th_en; 4522 u8 dyn_pd_th_max; 4523 u8 pd_low_th_ofst; 4524 u8 ib_pbk; 4525 s8 ib_pkpwr; 4526 s8 lna_gain_a[LNA_GAIN_NUM]; 4527 s8 lna_gain_g[LNA_GAIN_NUM]; 4528 s8 *lna_gain; 4529 s8 tia_gain_a[TIA_GAIN_NUM]; 4530 s8 tia_gain_g[TIA_GAIN_NUM]; 4531 s8 *tia_gain; 4532 bool is_linked_pre; 4533 bool bypass_dig; 4534 }; 4535 4536 enum rtw89_multi_cfo_mode { 4537 RTW89_PKT_BASED_AVG_MODE = 0, 4538 RTW89_ENTRY_BASED_AVG_MODE = 1, 4539 RTW89_TP_BASED_AVG_MODE = 2, 4540 }; 4541 4542 enum rtw89_phy_cfo_status { 4543 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4544 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4545 RTW89_PHY_DCFO_STATE_HOLD = 2, 4546 RTW89_PHY_DCFO_STATE_MAX 4547 }; 4548 4549 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4550 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4551 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4552 }; 4553 4554 struct rtw89_cfo_tracking_info { 4555 u16 cfo_timer_ms; 4556 bool cfo_trig_by_timer_en; 4557 enum rtw89_phy_cfo_status phy_cfo_status; 4558 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 4559 u8 phy_cfo_trk_cnt; 4560 bool is_adjust; 4561 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 4562 bool apply_compensation; 4563 u8 crystal_cap; 4564 u8 crystal_cap_default; 4565 u8 def_x_cap; 4566 s8 x_cap_ofst; 4567 u32 sta_cfo_tolerance; 4568 s32 cfo_tail[CFO_TRACK_MAX_USER]; 4569 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 4570 s32 cfo_avg_pre; 4571 s32 cfo_avg[CFO_TRACK_MAX_USER]; 4572 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 4573 s32 dcfo_avg; 4574 s32 dcfo_avg_pre; 4575 u32 packet_count; 4576 u32 packet_count_pre; 4577 s32 residual_cfo_acc; 4578 u8 phy_cfotrk_state; 4579 u8 phy_cfotrk_cnt; 4580 bool divergence_lock_en; 4581 u8 x_cap_lb; 4582 u8 x_cap_ub; 4583 u8 lock_cnt; 4584 }; 4585 4586 enum rtw89_tssi_mode { 4587 RTW89_TSSI_NORMAL = 0, 4588 RTW89_TSSI_SCAN = 1, 4589 }; 4590 4591 enum rtw89_tssi_alimk_band { 4592 TSSI_ALIMK_2G = 0, 4593 TSSI_ALIMK_5GL, 4594 TSSI_ALIMK_5GM, 4595 TSSI_ALIMK_5GH, 4596 TSSI_ALIMK_MAX 4597 }; 4598 4599 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 4600 #define TSSI_TRIM_CH_GROUP_NUM 8 4601 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 4602 4603 #define TSSI_CCK_CH_GROUP_NUM 6 4604 #define TSSI_MCS_2G_CH_GROUP_NUM 5 4605 #define TSSI_MCS_5G_CH_GROUP_NUM 14 4606 #define TSSI_MCS_6G_CH_GROUP_NUM 32 4607 #define TSSI_MCS_CH_GROUP_NUM \ 4608 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 4609 #define TSSI_MAX_CH_NUM 67 4610 #define TSSI_ALIMK_VALUE_NUM 8 4611 4612 struct rtw89_tssi_info { 4613 u8 thermal[RF_PATH_MAX]; 4614 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 4615 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 4616 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 4617 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 4618 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 4619 s8 extra_ofst[RF_PATH_MAX]; 4620 bool tssi_tracking_check[RF_PATH_MAX]; 4621 u8 default_txagc_offset[RF_PATH_MAX]; 4622 u32 base_thermal[RF_PATH_MAX]; 4623 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 4624 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 4625 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 4626 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 4627 u32 tssi_alimk_time; 4628 }; 4629 4630 struct rtw89_power_trim_info { 4631 bool pg_thermal_trim; 4632 bool pg_pa_bias_trim; 4633 u8 thermal_trim[RF_PATH_MAX]; 4634 u8 pa_bias_trim[RF_PATH_MAX]; 4635 u8 pad_bias_trim[RF_PATH_MAX]; 4636 }; 4637 4638 struct rtw89_regd { 4639 char alpha2[3]; 4640 u8 txpwr_regd[RTW89_BAND_NUM]; 4641 }; 4642 4643 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 4644 4645 struct rtw89_regulatory_info { 4646 const struct rtw89_regd *regd; 4647 enum rtw89_reg_6ghz_power reg_6ghz_power; 4648 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 4649 }; 4650 4651 enum rtw89_ifs_clm_application { 4652 RTW89_IFS_CLM_INIT = 0, 4653 RTW89_IFS_CLM_BACKGROUND = 1, 4654 RTW89_IFS_CLM_ACS = 2, 4655 RTW89_IFS_CLM_DIG = 3, 4656 RTW89_IFS_CLM_TDMA_DIG = 4, 4657 RTW89_IFS_CLM_DBG = 5, 4658 RTW89_IFS_CLM_DBG_MANUAL = 6 4659 }; 4660 4661 enum rtw89_env_racing_lv { 4662 RTW89_RAC_RELEASE = 0, 4663 RTW89_RAC_LV_1 = 1, 4664 RTW89_RAC_LV_2 = 2, 4665 RTW89_RAC_LV_3 = 3, 4666 RTW89_RAC_LV_4 = 4, 4667 RTW89_RAC_MAX_NUM = 5 4668 }; 4669 4670 struct rtw89_ccx_para_info { 4671 enum rtw89_env_racing_lv rac_lv; 4672 u16 mntr_time; 4673 u8 nhm_manual_th_ofst; 4674 u8 nhm_manual_th0; 4675 enum rtw89_ifs_clm_application ifs_clm_app; 4676 u32 ifs_clm_manual_th_times; 4677 u32 ifs_clm_manual_th0; 4678 u8 fahm_manual_th_ofst; 4679 u8 fahm_manual_th0; 4680 u8 fahm_numer_opt; 4681 u8 fahm_denom_opt; 4682 }; 4683 4684 enum rtw89_ccx_edcca_opt_sc_idx { 4685 RTW89_CCX_EDCCA_SEG0_P0 = 0, 4686 RTW89_CCX_EDCCA_SEG0_S1 = 1, 4687 RTW89_CCX_EDCCA_SEG0_S2 = 2, 4688 RTW89_CCX_EDCCA_SEG0_S3 = 3, 4689 RTW89_CCX_EDCCA_SEG1_P0 = 4, 4690 RTW89_CCX_EDCCA_SEG1_S1 = 5, 4691 RTW89_CCX_EDCCA_SEG1_S2 = 6, 4692 RTW89_CCX_EDCCA_SEG1_S3 = 7 4693 }; 4694 4695 enum rtw89_ccx_edcca_opt_bw_idx { 4696 RTW89_CCX_EDCCA_BW20_0 = 0, 4697 RTW89_CCX_EDCCA_BW20_1 = 1, 4698 RTW89_CCX_EDCCA_BW20_2 = 2, 4699 RTW89_CCX_EDCCA_BW20_3 = 3, 4700 RTW89_CCX_EDCCA_BW20_4 = 4, 4701 RTW89_CCX_EDCCA_BW20_5 = 5, 4702 RTW89_CCX_EDCCA_BW20_6 = 6, 4703 RTW89_CCX_EDCCA_BW20_7 = 7 4704 }; 4705 4706 #define RTW89_NHM_TH_NUM 11 4707 #define RTW89_FAHM_TH_NUM 11 4708 #define RTW89_NHM_RPT_NUM 12 4709 #define RTW89_FAHM_RPT_NUM 12 4710 #define RTW89_IFS_CLM_NUM 4 4711 struct rtw89_env_monitor_info { 4712 u8 ccx_watchdog_result; 4713 bool ccx_ongoing; 4714 u8 ccx_rac_lv; 4715 bool ccx_manual_ctrl; 4716 u16 ifs_clm_mntr_time; 4717 enum rtw89_ifs_clm_application ifs_clm_app; 4718 u16 ccx_period; 4719 u8 ccx_unit_idx; 4720 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 4721 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 4722 u16 ifs_clm_tx; 4723 u16 ifs_clm_edcca_excl_cca; 4724 u16 ifs_clm_ofdmfa; 4725 u16 ifs_clm_ofdmcca_excl_fa; 4726 u16 ifs_clm_cckfa; 4727 u16 ifs_clm_cckcca_excl_fa; 4728 u16 ifs_clm_total_ifs; 4729 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 4730 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 4731 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 4732 u8 ifs_clm_tx_ratio; 4733 u8 ifs_clm_edcca_excl_cca_ratio; 4734 u8 ifs_clm_cck_fa_ratio; 4735 u8 ifs_clm_ofdm_fa_ratio; 4736 u8 ifs_clm_cck_cca_excl_fa_ratio; 4737 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 4738 u16 ifs_clm_cck_fa_permil; 4739 u16 ifs_clm_ofdm_fa_permil; 4740 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 4741 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 4742 }; 4743 4744 enum rtw89_ser_rcvy_step { 4745 RTW89_SER_DRV_STOP_TX, 4746 RTW89_SER_DRV_STOP_RX, 4747 RTW89_SER_DRV_STOP_RUN, 4748 RTW89_SER_HAL_STOP_DMA, 4749 RTW89_SER_SUPPRESS_LOG, 4750 RTW89_NUM_OF_SER_FLAGS 4751 }; 4752 4753 struct rtw89_ser { 4754 u8 state; 4755 u8 alarm_event; 4756 bool prehandle_l1; 4757 4758 struct work_struct ser_hdl_work; 4759 struct delayed_work ser_alarm_work; 4760 const struct state_ent *st_tbl; 4761 const struct event_ent *ev_tbl; 4762 struct list_head msg_q; 4763 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 4764 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 4765 }; 4766 4767 enum rtw89_mac_ax_ps_mode { 4768 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 4769 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 4770 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 4771 RTW89_MAC_AX_PS_MODE_MAX = 3, 4772 }; 4773 4774 enum rtw89_last_rpwm_mode { 4775 RTW89_LAST_RPWM_PS = 0x0, 4776 RTW89_LAST_RPWM_ACTIVE = 0x6, 4777 }; 4778 4779 struct rtw89_lps_parm { 4780 u8 macid; 4781 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 4782 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 4783 }; 4784 4785 struct rtw89_ppdu_sts_info { 4786 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 4787 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 4788 }; 4789 4790 struct rtw89_early_h2c { 4791 struct list_head list; 4792 u8 *h2c; 4793 u16 h2c_len; 4794 }; 4795 4796 struct rtw89_hw_scan_info { 4797 struct ieee80211_vif *scanning_vif; 4798 struct list_head pkt_list[NUM_NL80211_BANDS]; 4799 struct rtw89_chan op_chan; 4800 bool abort; 4801 u32 last_chan_idx; 4802 }; 4803 4804 enum rtw89_phy_bb_gain_band { 4805 RTW89_BB_GAIN_BAND_2G = 0, 4806 RTW89_BB_GAIN_BAND_5G_L = 1, 4807 RTW89_BB_GAIN_BAND_5G_M = 2, 4808 RTW89_BB_GAIN_BAND_5G_H = 3, 4809 RTW89_BB_GAIN_BAND_6G_L = 4, 4810 RTW89_BB_GAIN_BAND_6G_M = 5, 4811 RTW89_BB_GAIN_BAND_6G_H = 6, 4812 RTW89_BB_GAIN_BAND_6G_UH = 7, 4813 4814 RTW89_BB_GAIN_BAND_NR, 4815 }; 4816 4817 enum rtw89_phy_gain_band_be { 4818 RTW89_BB_GAIN_BAND_2G_BE = 0, 4819 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 4820 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 4821 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 4822 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 4823 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 4824 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 4825 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 4826 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 4827 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 4828 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 4829 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 4830 4831 RTW89_BB_GAIN_BAND_NR_BE, 4832 }; 4833 4834 enum rtw89_phy_bb_bw_be { 4835 RTW89_BB_BW_20_40 = 0, 4836 RTW89_BB_BW_80_160_320 = 1, 4837 4838 RTW89_BB_BW_NR_BE, 4839 }; 4840 4841 enum rtw89_bw20_sc { 4842 RTW89_BW20_SC_20M = 1, 4843 RTW89_BW20_SC_40M = 2, 4844 RTW89_BW20_SC_80M = 4, 4845 RTW89_BW20_SC_160M = 8, 4846 RTW89_BW20_SC_320M = 16, 4847 }; 4848 4849 enum rtw89_cmac_table_bw { 4850 RTW89_CMAC_BW_20M = 0, 4851 RTW89_CMAC_BW_40M = 1, 4852 RTW89_CMAC_BW_80M = 2, 4853 RTW89_CMAC_BW_160M = 3, 4854 RTW89_CMAC_BW_320M = 4, 4855 4856 RTW89_CMAC_BW_NR, 4857 }; 4858 4859 enum rtw89_phy_bb_rxsc_num { 4860 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 4861 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 4862 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 4863 }; 4864 4865 struct rtw89_phy_bb_gain_info { 4866 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4867 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 4868 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4869 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4870 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4871 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 4872 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 4873 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4874 [RTW89_BB_RXSC_NUM_40]; 4875 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4876 [RTW89_BB_RXSC_NUM_80]; 4877 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4878 [RTW89_BB_RXSC_NUM_160]; 4879 }; 4880 4881 struct rtw89_phy_bb_gain_info_be { 4882 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 4883 [LNA_GAIN_NUM]; 4884 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 4885 [TIA_GAIN_NUM]; 4886 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 4887 [RF_PATH_MAX][LNA_GAIN_NUM]; 4888 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 4889 [RF_PATH_MAX][LNA_GAIN_NUM]; 4890 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 4891 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 4892 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 4893 [RTW89_BW20_SC_20M]; 4894 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 4895 [RTW89_BW20_SC_40M]; 4896 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 4897 [RTW89_BW20_SC_80M]; 4898 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 4899 [RTW89_BW20_SC_160M]; 4900 }; 4901 4902 struct rtw89_phy_efuse_gain { 4903 bool offset_valid; 4904 bool comp_valid; 4905 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 4906 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4907 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4908 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 4909 }; 4910 4911 #define RTW89_MAX_PATTERN_NUM 18 4912 #define RTW89_MAX_PATTERN_MASK_SIZE 4 4913 #define RTW89_MAX_PATTERN_SIZE 128 4914 4915 struct rtw89_wow_cam_info { 4916 bool r_w; 4917 u8 idx; 4918 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 4919 u16 crc; 4920 bool negative_pattern_match; 4921 bool skip_mac_hdr; 4922 bool uc; 4923 bool mc; 4924 bool bc; 4925 bool valid; 4926 }; 4927 4928 struct rtw89_wow_param { 4929 struct ieee80211_vif *wow_vif; 4930 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 4931 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 4932 u8 pattern_cnt; 4933 }; 4934 4935 struct rtw89_mcc_limit { 4936 bool enable; 4937 u16 max_tob; /* TU; max time offset behind */ 4938 u16 max_toa; /* TU; max time offset ahead */ 4939 u16 max_dur; /* TU */ 4940 }; 4941 4942 struct rtw89_mcc_policy { 4943 u8 c2h_rpt; 4944 u8 tx_null_early; 4945 u8 dis_tx_null; 4946 u8 in_curr_ch; 4947 u8 dis_sw_retry; 4948 u8 sw_retry_count; 4949 }; 4950 4951 struct rtw89_mcc_role { 4952 struct rtw89_vif *rtwvif; 4953 struct rtw89_mcc_policy policy; 4954 struct rtw89_mcc_limit limit; 4955 4956 /* only valid when running with FW MRC mechanism */ 4957 u8 slot_idx; 4958 4959 /* byte-array in LE order for FW */ 4960 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 4961 4962 u16 duration; /* TU */ 4963 u16 beacon_interval; /* TU */ 4964 bool is_2ghz; 4965 bool is_go; 4966 bool is_gc; 4967 }; 4968 4969 struct rtw89_mcc_bt_role { 4970 u16 duration; /* TU */ 4971 }; 4972 4973 struct rtw89_mcc_courtesy { 4974 bool enable; 4975 u8 slot_num; 4976 u8 macid_src; 4977 u8 macid_tgt; 4978 }; 4979 4980 enum rtw89_mcc_plan { 4981 RTW89_MCC_PLAN_TAIL_BT, 4982 RTW89_MCC_PLAN_MID_BT, 4983 RTW89_MCC_PLAN_NO_BT, 4984 4985 NUM_OF_RTW89_MCC_PLAN, 4986 }; 4987 4988 struct rtw89_mcc_pattern { 4989 s16 tob_ref; /* TU; time offset behind of reference role */ 4990 s16 toa_ref; /* TU; time offset ahead of reference role */ 4991 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 4992 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 4993 4994 enum rtw89_mcc_plan plan; 4995 struct rtw89_mcc_courtesy courtesy; 4996 }; 4997 4998 struct rtw89_mcc_sync { 4999 bool enable; 5000 u16 offset; /* TU */ 5001 u8 macid_src; 5002 u8 band_src; 5003 u8 port_src; 5004 u8 macid_tgt; 5005 u8 band_tgt; 5006 u8 port_tgt; 5007 }; 5008 5009 struct rtw89_mcc_config { 5010 struct rtw89_mcc_pattern pattern; 5011 struct rtw89_mcc_sync sync; 5012 u64 start_tsf; 5013 u16 mcc_interval; /* TU */ 5014 u16 beacon_offset; /* TU */ 5015 }; 5016 5017 enum rtw89_mcc_mode { 5018 RTW89_MCC_MODE_GO_STA, 5019 RTW89_MCC_MODE_GC_STA, 5020 }; 5021 5022 struct rtw89_mcc_info { 5023 struct rtw89_wait_info wait; 5024 5025 u8 group; 5026 enum rtw89_mcc_mode mode; 5027 struct rtw89_mcc_role role_ref; /* reference role */ 5028 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5029 struct rtw89_mcc_bt_role bt_role; 5030 struct rtw89_mcc_config config; 5031 }; 5032 5033 struct rtw89_dev { 5034 struct ieee80211_hw *hw; 5035 struct device *dev; 5036 const struct ieee80211_ops *ops; 5037 5038 bool dbcc_en; 5039 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5040 struct rtw89_hw_scan_info scan_info; 5041 const struct rtw89_chip_info *chip; 5042 const struct rtw89_pci_info *pci_info; 5043 const struct rtw89_rfe_parms *rfe_parms; 5044 struct rtw89_hal hal; 5045 struct rtw89_mcc_info mcc; 5046 struct rtw89_mac_info mac; 5047 struct rtw89_fw_info fw; 5048 struct rtw89_hci_info hci; 5049 struct rtw89_efuse efuse; 5050 struct rtw89_traffic_stats stats; 5051 struct rtw89_rfe_data *rfe_data; 5052 5053 /* ensures exclusive access from mac80211 callbacks */ 5054 struct mutex mutex; 5055 struct list_head rtwvifs_list; 5056 /* used to protect rf read write */ 5057 struct mutex rf_mutex; 5058 struct workqueue_struct *txq_wq; 5059 struct work_struct txq_work; 5060 struct delayed_work txq_reinvoke_work; 5061 /* used to protect ba_list and forbid_ba_list */ 5062 spinlock_t ba_lock; 5063 /* txqs to setup ba session */ 5064 struct list_head ba_list; 5065 /* txqs to forbid ba session */ 5066 struct list_head forbid_ba_list; 5067 struct work_struct ba_work; 5068 /* used to protect rpwm */ 5069 spinlock_t rpwm_lock; 5070 5071 struct rtw89_cam_info cam_info; 5072 5073 struct sk_buff_head c2h_queue; 5074 struct work_struct c2h_work; 5075 struct work_struct ips_work; 5076 struct work_struct load_firmware_work; 5077 struct work_struct cancel_6ghz_probe_work; 5078 5079 struct list_head early_h2c_list; 5080 5081 struct rtw89_ser ser; 5082 5083 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5084 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5085 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5086 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5087 5088 struct rtw89_phy_stat phystat; 5089 struct rtw89_rfk_wait_info rfk_wait; 5090 struct rtw89_dack_info dack; 5091 struct rtw89_iqk_info iqk; 5092 struct rtw89_dpk_info dpk; 5093 struct rtw89_rfk_mcc_info rfk_mcc; 5094 struct rtw89_lck_info lck; 5095 struct rtw89_rx_dck_info rx_dck; 5096 bool is_tssi_mode[RF_PATH_MAX]; 5097 bool is_bt_iqk_timeout; 5098 5099 struct rtw89_fem_info fem; 5100 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5101 struct rtw89_tssi_info tssi; 5102 struct rtw89_power_trim_info pwr_trim; 5103 5104 struct rtw89_cfo_tracking_info cfo_tracking; 5105 struct rtw89_env_monitor_info env_monitor; 5106 struct rtw89_dig_info dig; 5107 struct rtw89_phy_ch_info ch_info; 5108 union { 5109 struct rtw89_phy_bb_gain_info ax; 5110 struct rtw89_phy_bb_gain_info_be be; 5111 } bb_gain; 5112 struct rtw89_phy_efuse_gain efuse_gain; 5113 struct rtw89_phy_ul_tb_info ul_tb_info; 5114 struct rtw89_antdiv_info antdiv; 5115 5116 struct delayed_work track_work; 5117 struct delayed_work chanctx_work; 5118 struct delayed_work coex_act1_work; 5119 struct delayed_work coex_bt_devinfo_work; 5120 struct delayed_work coex_rfk_chk_work; 5121 struct delayed_work cfo_track_work; 5122 struct delayed_work forbid_ba_work; 5123 struct delayed_work roc_work; 5124 struct delayed_work antdiv_work; 5125 struct rtw89_ppdu_sts_info ppdu_sts; 5126 u8 total_sta_assoc; 5127 bool scanning; 5128 5129 struct rtw89_regulatory_info regulatory; 5130 struct rtw89_sar_info sar; 5131 struct rtw89_tas_info tas; 5132 5133 struct rtw89_btc btc; 5134 enum rtw89_ps_mode ps_mode; 5135 bool lps_enabled; 5136 5137 struct rtw89_wow_param wow; 5138 5139 /* napi structure */ 5140 struct net_device netdev; 5141 struct napi_struct napi; 5142 int napi_budget_countdown; 5143 5144 /* HCI related data, keep last */ 5145 u8 priv[] __aligned(sizeof(void *)); 5146 }; 5147 5148 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5149 struct rtw89_core_tx_request *tx_req) 5150 { 5151 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5152 } 5153 5154 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5155 { 5156 rtwdev->hci.ops->reset(rtwdev); 5157 } 5158 5159 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5160 { 5161 return rtwdev->hci.ops->start(rtwdev); 5162 } 5163 5164 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5165 { 5166 rtwdev->hci.ops->stop(rtwdev); 5167 } 5168 5169 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5170 { 5171 return rtwdev->hci.ops->deinit(rtwdev); 5172 } 5173 5174 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5175 { 5176 rtwdev->hci.ops->pause(rtwdev, pause); 5177 } 5178 5179 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5180 { 5181 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5182 } 5183 5184 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5185 { 5186 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5187 } 5188 5189 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5190 { 5191 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5192 } 5193 5194 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5195 { 5196 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5197 } 5198 5199 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5200 { 5201 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5202 } 5203 5204 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5205 bool drop) 5206 { 5207 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5208 return; 5209 5210 if (rtwdev->hci.ops->flush_queues) 5211 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 5212 } 5213 5214 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 5215 { 5216 if (rtwdev->hci.ops->recovery_start) 5217 rtwdev->hci.ops->recovery_start(rtwdev); 5218 } 5219 5220 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 5221 { 5222 if (rtwdev->hci.ops->recovery_complete) 5223 rtwdev->hci.ops->recovery_complete(rtwdev); 5224 } 5225 5226 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 5227 { 5228 if (rtwdev->hci.ops->enable_intr) 5229 rtwdev->hci.ops->enable_intr(rtwdev); 5230 } 5231 5232 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 5233 { 5234 if (rtwdev->hci.ops->disable_intr) 5235 rtwdev->hci.ops->disable_intr(rtwdev); 5236 } 5237 5238 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 5239 { 5240 if (rtwdev->hci.ops->ctrl_txdma_ch) 5241 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 5242 } 5243 5244 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 5245 { 5246 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 5247 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 5248 } 5249 5250 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 5251 { 5252 if (rtwdev->hci.ops->ctrl_trxhci) 5253 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 5254 } 5255 5256 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 5257 { 5258 int ret = 0; 5259 5260 if (rtwdev->hci.ops->poll_txdma_ch_idle) 5261 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 5262 return ret; 5263 } 5264 5265 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 5266 { 5267 if (rtwdev->hci.ops->clr_idx_all) 5268 rtwdev->hci.ops->clr_idx_all(rtwdev); 5269 } 5270 5271 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 5272 { 5273 int ret = 0; 5274 5275 if (rtwdev->hci.ops->rst_bdram) 5276 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 5277 return ret; 5278 } 5279 5280 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 5281 { 5282 if (rtwdev->hci.ops->clear) 5283 rtwdev->hci.ops->clear(rtwdev, pdev); 5284 } 5285 5286 static inline 5287 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 5288 { 5289 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 5290 5291 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 5292 } 5293 5294 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 5295 { 5296 return rtwdev->hci.ops->read8(rtwdev, addr); 5297 } 5298 5299 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 5300 { 5301 return rtwdev->hci.ops->read16(rtwdev, addr); 5302 } 5303 5304 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 5305 { 5306 return rtwdev->hci.ops->read32(rtwdev, addr); 5307 } 5308 5309 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 5310 { 5311 rtwdev->hci.ops->write8(rtwdev, addr, data); 5312 } 5313 5314 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 5315 { 5316 rtwdev->hci.ops->write16(rtwdev, addr, data); 5317 } 5318 5319 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 5320 { 5321 rtwdev->hci.ops->write32(rtwdev, addr, data); 5322 } 5323 5324 static inline void 5325 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5326 { 5327 u8 val; 5328 5329 val = rtw89_read8(rtwdev, addr); 5330 rtw89_write8(rtwdev, addr, val | bit); 5331 } 5332 5333 static inline void 5334 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5335 { 5336 u16 val; 5337 5338 val = rtw89_read16(rtwdev, addr); 5339 rtw89_write16(rtwdev, addr, val | bit); 5340 } 5341 5342 static inline void 5343 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5344 { 5345 u32 val; 5346 5347 val = rtw89_read32(rtwdev, addr); 5348 rtw89_write32(rtwdev, addr, val | bit); 5349 } 5350 5351 static inline void 5352 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5353 { 5354 u8 val; 5355 5356 val = rtw89_read8(rtwdev, addr); 5357 rtw89_write8(rtwdev, addr, val & ~bit); 5358 } 5359 5360 static inline void 5361 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5362 { 5363 u16 val; 5364 5365 val = rtw89_read16(rtwdev, addr); 5366 rtw89_write16(rtwdev, addr, val & ~bit); 5367 } 5368 5369 static inline void 5370 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5371 { 5372 u32 val; 5373 5374 val = rtw89_read32(rtwdev, addr); 5375 rtw89_write32(rtwdev, addr, val & ~bit); 5376 } 5377 5378 static inline u32 5379 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5380 { 5381 u32 shift = __ffs(mask); 5382 u32 orig; 5383 u32 ret; 5384 5385 orig = rtw89_read32(rtwdev, addr); 5386 ret = (orig & mask) >> shift; 5387 5388 return ret; 5389 } 5390 5391 static inline u16 5392 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5393 { 5394 u32 shift = __ffs(mask); 5395 u32 orig; 5396 u32 ret; 5397 5398 orig = rtw89_read16(rtwdev, addr); 5399 ret = (orig & mask) >> shift; 5400 5401 return ret; 5402 } 5403 5404 static inline u8 5405 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5406 { 5407 u32 shift = __ffs(mask); 5408 u32 orig; 5409 u32 ret; 5410 5411 orig = rtw89_read8(rtwdev, addr); 5412 ret = (orig & mask) >> shift; 5413 5414 return ret; 5415 } 5416 5417 static inline void 5418 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 5419 { 5420 u32 shift = __ffs(mask); 5421 u32 orig; 5422 u32 set; 5423 5424 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 5425 5426 orig = rtw89_read32(rtwdev, addr); 5427 set = (orig & ~mask) | ((data << shift) & mask); 5428 rtw89_write32(rtwdev, addr, set); 5429 } 5430 5431 static inline void 5432 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 5433 { 5434 u32 shift; 5435 u16 orig, set; 5436 5437 mask &= 0xffff; 5438 shift = __ffs(mask); 5439 5440 orig = rtw89_read16(rtwdev, addr); 5441 set = (orig & ~mask) | ((data << shift) & mask); 5442 rtw89_write16(rtwdev, addr, set); 5443 } 5444 5445 static inline void 5446 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 5447 { 5448 u32 shift; 5449 u8 orig, set; 5450 5451 mask &= 0xff; 5452 shift = __ffs(mask); 5453 5454 orig = rtw89_read8(rtwdev, addr); 5455 set = (orig & ~mask) | ((data << shift) & mask); 5456 rtw89_write8(rtwdev, addr, set); 5457 } 5458 5459 static inline u32 5460 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5461 u32 addr, u32 mask) 5462 { 5463 u32 val; 5464 5465 mutex_lock(&rtwdev->rf_mutex); 5466 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 5467 mutex_unlock(&rtwdev->rf_mutex); 5468 5469 return val; 5470 } 5471 5472 static inline void 5473 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5474 u32 addr, u32 mask, u32 data) 5475 { 5476 mutex_lock(&rtwdev->rf_mutex); 5477 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 5478 mutex_unlock(&rtwdev->rf_mutex); 5479 } 5480 5481 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 5482 { 5483 void *p = rtwtxq; 5484 5485 return container_of(p, struct ieee80211_txq, drv_priv); 5486 } 5487 5488 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 5489 struct ieee80211_txq *txq) 5490 { 5491 struct rtw89_txq *rtwtxq; 5492 5493 if (!txq) 5494 return; 5495 5496 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5497 INIT_LIST_HEAD(&rtwtxq->list); 5498 } 5499 5500 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 5501 { 5502 void *p = rtwvif; 5503 5504 return container_of(p, struct ieee80211_vif, drv_priv); 5505 } 5506 5507 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 5508 { 5509 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 5510 } 5511 5512 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 5513 { 5514 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 5515 } 5516 5517 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 5518 { 5519 void *p = rtwsta; 5520 5521 return container_of(p, struct ieee80211_sta, drv_priv); 5522 } 5523 5524 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 5525 { 5526 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 5527 } 5528 5529 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 5530 { 5531 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 5532 } 5533 5534 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 5535 { 5536 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 5537 return RATE_INFO_BW_160; 5538 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 5539 return RATE_INFO_BW_80; 5540 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 5541 return RATE_INFO_BW_40; 5542 else 5543 return RATE_INFO_BW_20; 5544 } 5545 5546 static inline 5547 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 5548 { 5549 switch (hw_band) { 5550 default: 5551 case RTW89_BAND_2G: 5552 return NL80211_BAND_2GHZ; 5553 case RTW89_BAND_5G: 5554 return NL80211_BAND_5GHZ; 5555 case RTW89_BAND_6G: 5556 return NL80211_BAND_6GHZ; 5557 } 5558 } 5559 5560 static inline 5561 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 5562 { 5563 switch (nl_band) { 5564 default: 5565 case NL80211_BAND_2GHZ: 5566 return RTW89_BAND_2G; 5567 case NL80211_BAND_5GHZ: 5568 return RTW89_BAND_5G; 5569 case NL80211_BAND_6GHZ: 5570 return RTW89_BAND_6G; 5571 } 5572 } 5573 5574 static inline 5575 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 5576 { 5577 switch (width) { 5578 default: 5579 WARN(1, "Not support bandwidth %d\n", width); 5580 fallthrough; 5581 case NL80211_CHAN_WIDTH_20_NOHT: 5582 case NL80211_CHAN_WIDTH_20: 5583 return RTW89_CHANNEL_WIDTH_20; 5584 case NL80211_CHAN_WIDTH_40: 5585 return RTW89_CHANNEL_WIDTH_40; 5586 case NL80211_CHAN_WIDTH_80: 5587 return RTW89_CHANNEL_WIDTH_80; 5588 case NL80211_CHAN_WIDTH_160: 5589 return RTW89_CHANNEL_WIDTH_160; 5590 } 5591 } 5592 5593 static inline 5594 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 5595 { 5596 switch (rua) { 5597 default: 5598 WARN(1, "Invalid RU allocation: %d\n", rua); 5599 fallthrough; 5600 case 0 ... 36: 5601 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 5602 case 37 ... 52: 5603 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 5604 case 53 ... 60: 5605 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 5606 case 61 ... 64: 5607 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 5608 case 65 ... 66: 5609 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 5610 case 67: 5611 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 5612 case 68: 5613 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 5614 } 5615 } 5616 5617 static inline 5618 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 5619 struct rtw89_sta *rtwsta) 5620 { 5621 if (rtwsta) { 5622 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5623 5624 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 5625 return &rtwsta->addr_cam; 5626 } 5627 return &rtwvif->addr_cam; 5628 } 5629 5630 static inline 5631 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 5632 struct rtw89_sta *rtwsta) 5633 { 5634 if (rtwsta) { 5635 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5636 5637 if (sta->tdls) 5638 return &rtwsta->bssid_cam; 5639 } 5640 return &rtwvif->bssid_cam; 5641 } 5642 5643 static inline 5644 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 5645 struct rtw89_channel_help_params *p, 5646 const struct rtw89_chan *chan, 5647 enum rtw89_mac_idx mac_idx, 5648 enum rtw89_phy_idx phy_idx) 5649 { 5650 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 5651 mac_idx, phy_idx); 5652 } 5653 5654 static inline 5655 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 5656 struct rtw89_channel_help_params *p, 5657 const struct rtw89_chan *chan, 5658 enum rtw89_mac_idx mac_idx, 5659 enum rtw89_phy_idx phy_idx) 5660 { 5661 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 5662 mac_idx, phy_idx); 5663 } 5664 5665 static inline 5666 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 5667 enum rtw89_sub_entity_idx idx) 5668 { 5669 struct rtw89_hal *hal = &rtwdev->hal; 5670 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 5671 5672 if (roc_idx == idx) 5673 return &hal->roc_chandef; 5674 5675 return &hal->sub[idx].chandef; 5676 } 5677 5678 static inline 5679 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 5680 enum rtw89_sub_entity_idx idx) 5681 { 5682 struct rtw89_hal *hal = &rtwdev->hal; 5683 5684 return &hal->sub[idx].chan; 5685 } 5686 5687 static inline 5688 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 5689 enum rtw89_sub_entity_idx idx) 5690 { 5691 struct rtw89_hal *hal = &rtwdev->hal; 5692 5693 return &hal->sub[idx].rcd; 5694 } 5695 5696 static inline 5697 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 5698 { 5699 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 5700 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 5701 5702 if (rtwvif) 5703 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx); 5704 else 5705 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 5706 } 5707 5708 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 5709 { 5710 const struct rtw89_chip_info *chip = rtwdev->chip; 5711 5712 if (chip->ops->fem_setup) 5713 chip->ops->fem_setup(rtwdev); 5714 } 5715 5716 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 5717 { 5718 const struct rtw89_chip_info *chip = rtwdev->chip; 5719 5720 if (chip->ops->rfe_gpio) 5721 chip->ops->rfe_gpio(rtwdev); 5722 } 5723 5724 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 5725 { 5726 const struct rtw89_chip_info *chip = rtwdev->chip; 5727 5728 if (chip->ops->rfk_hw_init) 5729 chip->ops->rfk_hw_init(rtwdev); 5730 } 5731 5732 static inline 5733 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 5734 { 5735 const struct rtw89_chip_info *chip = rtwdev->chip; 5736 5737 if (chip->ops->bb_preinit) 5738 chip->ops->bb_preinit(rtwdev, phy_idx); 5739 } 5740 5741 static inline 5742 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 5743 { 5744 const struct rtw89_chip_info *chip = rtwdev->chip; 5745 5746 if (!chip->ops->bb_postinit) 5747 return; 5748 5749 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 5750 5751 if (rtwdev->dbcc_en) 5752 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 5753 } 5754 5755 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 5756 { 5757 const struct rtw89_chip_info *chip = rtwdev->chip; 5758 5759 if (chip->ops->bb_sethw) 5760 chip->ops->bb_sethw(rtwdev); 5761 } 5762 5763 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 5764 { 5765 const struct rtw89_chip_info *chip = rtwdev->chip; 5766 5767 if (chip->ops->rfk_init) 5768 chip->ops->rfk_init(rtwdev); 5769 } 5770 5771 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 5772 { 5773 const struct rtw89_chip_info *chip = rtwdev->chip; 5774 5775 if (chip->ops->rfk_init_late) 5776 chip->ops->rfk_init_late(rtwdev); 5777 } 5778 5779 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 5780 { 5781 const struct rtw89_chip_info *chip = rtwdev->chip; 5782 5783 if (chip->ops->rfk_channel) 5784 chip->ops->rfk_channel(rtwdev); 5785 } 5786 5787 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 5788 enum rtw89_phy_idx phy_idx) 5789 { 5790 const struct rtw89_chip_info *chip = rtwdev->chip; 5791 5792 if (chip->ops->rfk_band_changed) 5793 chip->ops->rfk_band_changed(rtwdev, phy_idx); 5794 } 5795 5796 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 5797 { 5798 const struct rtw89_chip_info *chip = rtwdev->chip; 5799 5800 if (chip->ops->rfk_scan) 5801 chip->ops->rfk_scan(rtwdev, start); 5802 } 5803 5804 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 5805 { 5806 const struct rtw89_chip_info *chip = rtwdev->chip; 5807 5808 if (chip->ops->rfk_track) 5809 chip->ops->rfk_track(rtwdev); 5810 } 5811 5812 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 5813 { 5814 const struct rtw89_chip_info *chip = rtwdev->chip; 5815 5816 if (chip->ops->set_txpwr_ctrl) 5817 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 5818 } 5819 5820 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 5821 { 5822 const struct rtw89_chip_info *chip = rtwdev->chip; 5823 5824 if (chip->ops->power_trim) 5825 chip->ops->power_trim(rtwdev); 5826 } 5827 5828 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 5829 enum rtw89_phy_idx phy_idx) 5830 { 5831 const struct rtw89_chip_info *chip = rtwdev->chip; 5832 5833 if (chip->ops->init_txpwr_unit) 5834 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 5835 } 5836 5837 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 5838 enum rtw89_rf_path rf_path) 5839 { 5840 const struct rtw89_chip_info *chip = rtwdev->chip; 5841 5842 if (!chip->ops->get_thermal) 5843 return 0x10; 5844 5845 return chip->ops->get_thermal(rtwdev, rf_path); 5846 } 5847 5848 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 5849 struct rtw89_rx_phy_ppdu *phy_ppdu, 5850 struct ieee80211_rx_status *status) 5851 { 5852 const struct rtw89_chip_info *chip = rtwdev->chip; 5853 5854 if (chip->ops->query_ppdu) 5855 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 5856 } 5857 5858 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 5859 enum rtw89_phy_idx phy_idx) 5860 { 5861 const struct rtw89_chip_info *chip = rtwdev->chip; 5862 5863 if (chip->ops->ctrl_nbtg_bt_tx) 5864 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 5865 } 5866 5867 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 5868 { 5869 const struct rtw89_chip_info *chip = rtwdev->chip; 5870 5871 if (chip->ops->cfg_txrx_path) 5872 chip->ops->cfg_txrx_path(rtwdev); 5873 } 5874 5875 static inline 5876 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5877 struct ieee80211_vif *vif) 5878 { 5879 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5880 const struct rtw89_chip_info *chip = rtwdev->chip; 5881 5882 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 5883 return; 5884 5885 if (chip->ops->set_txpwr_ul_tb_offset) 5886 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 5887 } 5888 5889 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 5890 const struct rtw89_txpwr_table *tbl) 5891 { 5892 tbl->load(rtwdev, tbl); 5893 } 5894 5895 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 5896 { 5897 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 5898 5899 return regd->txpwr_regd[band]; 5900 } 5901 5902 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 5903 enum rtw89_phy_idx phy_idx) 5904 { 5905 const struct rtw89_chip_info *chip = rtwdev->chip; 5906 5907 if (chip->ops->ctrl_btg_bt_rx) 5908 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 5909 } 5910 5911 static inline 5912 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 5913 struct rtw89_rx_desc_info *desc_info, 5914 u8 *data, u32 data_offset) 5915 { 5916 const struct rtw89_chip_info *chip = rtwdev->chip; 5917 5918 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 5919 } 5920 5921 static inline 5922 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 5923 struct rtw89_tx_desc_info *desc_info, 5924 void *txdesc) 5925 { 5926 const struct rtw89_chip_info *chip = rtwdev->chip; 5927 5928 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 5929 } 5930 5931 static inline 5932 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 5933 struct rtw89_tx_desc_info *desc_info, 5934 void *txdesc) 5935 { 5936 const struct rtw89_chip_info *chip = rtwdev->chip; 5937 5938 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 5939 } 5940 5941 static inline 5942 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5943 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5944 { 5945 const struct rtw89_chip_info *chip = rtwdev->chip; 5946 5947 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 5948 } 5949 5950 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5951 { 5952 const struct rtw89_chip_info *chip = rtwdev->chip; 5953 5954 chip->ops->cfg_ctrl_path(rtwdev, wl); 5955 } 5956 5957 static inline 5958 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 5959 u32 *tx_en, enum rtw89_sch_tx_sel sel) 5960 { 5961 const struct rtw89_chip_info *chip = rtwdev->chip; 5962 5963 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 5964 } 5965 5966 static inline 5967 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 5968 { 5969 const struct rtw89_chip_info *chip = rtwdev->chip; 5970 5971 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 5972 } 5973 5974 static inline 5975 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 5976 struct rtw89_vif *rtwvif, 5977 struct rtw89_sta *rtwsta) 5978 { 5979 const struct rtw89_chip_info *chip = rtwdev->chip; 5980 5981 if (!chip->ops->h2c_dctl_sec_cam) 5982 return 0; 5983 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 5984 } 5985 5986 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 5987 { 5988 __le16 fc = hdr->frame_control; 5989 5990 if (ieee80211_has_tods(fc)) 5991 return hdr->addr1; 5992 else if (ieee80211_has_fromds(fc)) 5993 return hdr->addr2; 5994 else 5995 return hdr->addr3; 5996 } 5997 5998 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 5999 { 6000 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6001 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 6002 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 6003 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6004 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 6005 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 6006 return true; 6007 return false; 6008 } 6009 6010 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 6011 enum rtw89_fw_type type) 6012 { 6013 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6014 6015 switch (type) { 6016 case RTW89_FW_WOWLAN: 6017 return &fw_info->wowlan; 6018 case RTW89_FW_LOGFMT: 6019 return &fw_info->log.suit; 6020 case RTW89_FW_BBMCU0: 6021 return &fw_info->bbmcu0; 6022 case RTW89_FW_BBMCU1: 6023 return &fw_info->bbmcu1; 6024 default: 6025 break; 6026 } 6027 6028 return &fw_info->normal; 6029 } 6030 6031 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 6032 unsigned int length) 6033 { 6034 struct sk_buff *skb; 6035 6036 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 6037 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 6038 if (!skb) 6039 return NULL; 6040 6041 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 6042 return skb; 6043 } 6044 6045 return dev_alloc_skb(length); 6046 } 6047 6048 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 6049 struct rtw89_tx_skb_data *skb_data, 6050 bool tx_done) 6051 { 6052 struct rtw89_tx_wait_info *wait; 6053 6054 rcu_read_lock(); 6055 6056 wait = rcu_dereference(skb_data->wait); 6057 if (!wait) 6058 goto out; 6059 6060 wait->tx_done = tx_done; 6061 complete(&wait->completion); 6062 6063 out: 6064 rcu_read_unlock(); 6065 } 6066 6067 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 6068 { 6069 switch (rtwdev->mlo_dbcc_mode) { 6070 case MLO_1_PLUS_1_1RF: 6071 case MLO_1_PLUS_1_2RF: 6072 case DBCC_LEGACY: 6073 return true; 6074 default: 6075 return false; 6076 } 6077 } 6078 6079 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6080 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 6081 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 6082 struct sk_buff *skb, bool fwdl); 6083 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 6084 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6085 int qsel, unsigned int timeout); 6086 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 6087 struct rtw89_tx_desc_info *desc_info, 6088 void *txdesc); 6089 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 6090 struct rtw89_tx_desc_info *desc_info, 6091 void *txdesc); 6092 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 6093 struct rtw89_tx_desc_info *desc_info, 6094 void *txdesc); 6095 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 6096 struct rtw89_tx_desc_info *desc_info, 6097 void *txdesc); 6098 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 6099 struct rtw89_tx_desc_info *desc_info, 6100 void *txdesc); 6101 void rtw89_core_rx(struct rtw89_dev *rtwdev, 6102 struct rtw89_rx_desc_info *desc_info, 6103 struct sk_buff *skb); 6104 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 6105 struct rtw89_rx_desc_info *desc_info, 6106 u8 *data, u32 data_offset); 6107 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 6108 struct rtw89_rx_desc_info *desc_info, 6109 u8 *data, u32 data_offset); 6110 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 6111 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 6112 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 6113 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 6114 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 6115 struct ieee80211_vif *vif, 6116 struct ieee80211_sta *sta); 6117 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 6118 struct ieee80211_vif *vif, 6119 struct ieee80211_sta *sta); 6120 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 6121 struct ieee80211_vif *vif, 6122 struct ieee80211_sta *sta); 6123 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 6124 struct ieee80211_vif *vif, 6125 struct ieee80211_sta *sta); 6126 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 6127 struct ieee80211_vif *vif, 6128 struct ieee80211_sta *sta); 6129 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 6130 struct ieee80211_sta *sta, 6131 struct cfg80211_tid_config *tid_config); 6132 int rtw89_core_init(struct rtw89_dev *rtwdev); 6133 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 6134 int rtw89_core_register(struct rtw89_dev *rtwdev); 6135 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 6136 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 6137 u32 bus_data_size, 6138 const struct rtw89_chip_info *chip); 6139 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 6140 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 6141 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 6142 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 6143 struct rtw89_chan *chan); 6144 int rtw89_set_channel(struct rtw89_dev *rtwdev); 6145 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6146 struct rtw89_chan *chan); 6147 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 6148 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 6149 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 6150 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 6151 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6152 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 6153 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6154 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 6155 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 6156 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 6157 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 6158 int rtw89_regd_init(struct rtw89_dev *rtwdev, 6159 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 6160 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 6161 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 6162 struct rtw89_traffic_stats *stats); 6163 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 6164 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 6165 const struct rtw89_completion_data *data); 6166 int rtw89_core_start(struct rtw89_dev *rtwdev); 6167 void rtw89_core_stop(struct rtw89_dev *rtwdev); 6168 void rtw89_core_update_beacon_work(struct work_struct *work); 6169 void rtw89_roc_work(struct work_struct *work); 6170 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6171 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6172 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6173 const u8 *mac_addr, bool hw_scan); 6174 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 6175 struct ieee80211_vif *vif, bool hw_scan); 6176 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev, 6177 struct rtw89_vif *rtwvif, bool active); 6178 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 6179 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 6180 6181 #endif 6182