1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 18 extern const struct ieee80211_ops rtw89_ops; 19 20 #define MASKBYTE0 0xff 21 #define MASKBYTE1 0xff00 22 #define MASKBYTE2 0xff0000 23 #define MASKBYTE3 0xff000000 24 #define MASKBYTE4 0xff00000000ULL 25 #define MASKHWORD 0xffff0000 26 #define MASKLWORD 0x0000ffff 27 #define MASKDWORD 0xffffffff 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 32 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 33 #define CFO_TRACK_MAX_USER 64 34 #define MAX_RSSI 110 35 #define RSSI_FACTOR 1 36 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 37 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 38 39 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 40 #define RTW89_HTC_VARIANT_HE 3 41 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 42 #define RTW89_HTC_VARIANT_HE_CID_OM 1 43 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 44 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 45 46 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 47 enum htc_om_channel_width { 48 HTC_OM_CHANNEL_WIDTH_20 = 0, 49 HTC_OM_CHANNEL_WIDTH_40 = 1, 50 HTC_OM_CHANNEL_WIDTH_80 = 2, 51 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 52 }; 53 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 54 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 55 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 56 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 57 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 58 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 59 60 #define RTW89_TF_PAD GENMASK(11, 0) 61 #define RTW89_TF_BASIC_USER_INFO_SZ 6 62 63 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 64 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 65 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 66 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 67 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 68 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 69 70 enum rtw89_subband { 71 RTW89_CH_2G = 0, 72 RTW89_CH_5G_BAND_1 = 1, 73 /* RTW89_CH_5G_BAND_2 = 2, unused */ 74 RTW89_CH_5G_BAND_3 = 3, 75 RTW89_CH_5G_BAND_4 = 4, 76 77 RTW89_CH_6G_BAND_IDX0, /* Low */ 78 RTW89_CH_6G_BAND_IDX1, /* Low */ 79 RTW89_CH_6G_BAND_IDX2, /* Mid */ 80 RTW89_CH_6G_BAND_IDX3, /* Mid */ 81 RTW89_CH_6G_BAND_IDX4, /* High */ 82 RTW89_CH_6G_BAND_IDX5, /* High */ 83 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 84 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 85 86 RTW89_SUBBAND_NR, 87 }; 88 89 enum rtw89_gain_offset { 90 RTW89_GAIN_OFFSET_2G_CCK, 91 RTW89_GAIN_OFFSET_2G_OFDM, 92 RTW89_GAIN_OFFSET_5G_LOW, 93 RTW89_GAIN_OFFSET_5G_MID, 94 RTW89_GAIN_OFFSET_5G_HIGH, 95 96 RTW89_GAIN_OFFSET_NR, 97 }; 98 99 enum rtw89_hci_type { 100 RTW89_HCI_TYPE_PCIE, 101 RTW89_HCI_TYPE_USB, 102 RTW89_HCI_TYPE_SDIO, 103 }; 104 105 enum rtw89_core_chip_id { 106 RTL8852A, 107 RTL8852B, 108 RTL8852C, 109 }; 110 111 enum rtw89_cv { 112 CHIP_CAV, 113 CHIP_CBV, 114 CHIP_CCV, 115 CHIP_CDV, 116 CHIP_CEV, 117 CHIP_CFV, 118 CHIP_CV_MAX, 119 CHIP_CV_INVALID = CHIP_CV_MAX, 120 }; 121 122 enum rtw89_core_tx_type { 123 RTW89_CORE_TX_TYPE_DATA, 124 RTW89_CORE_TX_TYPE_MGMT, 125 RTW89_CORE_TX_TYPE_FWCMD, 126 }; 127 128 enum rtw89_core_rx_type { 129 RTW89_CORE_RX_TYPE_WIFI = 0, 130 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 131 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 132 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 133 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 134 RTW89_CORE_RX_TYPE_SS2FW = 5, 135 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 136 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 137 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 138 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 139 RTW89_CORE_RX_TYPE_C2H = 10, 140 RTW89_CORE_RX_TYPE_CSI = 11, 141 RTW89_CORE_RX_TYPE_CQI = 12, 142 RTW89_CORE_RX_TYPE_H2C = 13, 143 RTW89_CORE_RX_TYPE_FWDL = 14, 144 }; 145 146 enum rtw89_txq_flags { 147 RTW89_TXQ_F_AMPDU = 0, 148 RTW89_TXQ_F_BLOCK_BA = 1, 149 RTW89_TXQ_F_FORBID_BA = 2, 150 }; 151 152 enum rtw89_net_type { 153 RTW89_NET_TYPE_NO_LINK = 0, 154 RTW89_NET_TYPE_AD_HOC = 1, 155 RTW89_NET_TYPE_INFRA = 2, 156 RTW89_NET_TYPE_AP_MODE = 3, 157 }; 158 159 enum rtw89_wifi_role { 160 RTW89_WIFI_ROLE_NONE, 161 RTW89_WIFI_ROLE_STATION, 162 RTW89_WIFI_ROLE_AP, 163 RTW89_WIFI_ROLE_AP_VLAN, 164 RTW89_WIFI_ROLE_ADHOC, 165 RTW89_WIFI_ROLE_ADHOC_MASTER, 166 RTW89_WIFI_ROLE_MESH_POINT, 167 RTW89_WIFI_ROLE_MONITOR, 168 RTW89_WIFI_ROLE_P2P_DEVICE, 169 RTW89_WIFI_ROLE_P2P_CLIENT, 170 RTW89_WIFI_ROLE_P2P_GO, 171 RTW89_WIFI_ROLE_NAN, 172 RTW89_WIFI_ROLE_MLME_MAX 173 }; 174 175 enum rtw89_upd_mode { 176 RTW89_ROLE_CREATE, 177 RTW89_ROLE_REMOVE, 178 RTW89_ROLE_TYPE_CHANGE, 179 RTW89_ROLE_INFO_CHANGE, 180 RTW89_ROLE_CON_DISCONN 181 }; 182 183 enum rtw89_self_role { 184 RTW89_SELF_ROLE_CLIENT, 185 RTW89_SELF_ROLE_AP, 186 RTW89_SELF_ROLE_AP_CLIENT 187 }; 188 189 enum rtw89_msk_sO_el { 190 RTW89_NO_MSK, 191 RTW89_SMA, 192 RTW89_TMA, 193 RTW89_BSSID 194 }; 195 196 enum rtw89_sch_tx_sel { 197 RTW89_SCH_TX_SEL_ALL, 198 RTW89_SCH_TX_SEL_HIQ, 199 RTW89_SCH_TX_SEL_MG0, 200 RTW89_SCH_TX_SEL_MACID, 201 }; 202 203 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 204 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 205 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 206 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 207 */ 208 enum rtw89_add_cam_sec_mode { 209 RTW89_ADDR_CAM_SEC_NONE = 0, 210 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 211 RTW89_ADDR_CAM_SEC_NORMAL = 2, 212 RTW89_ADDR_CAM_SEC_4GROUP = 3, 213 }; 214 215 enum rtw89_sec_key_type { 216 RTW89_SEC_KEY_TYPE_NONE = 0, 217 RTW89_SEC_KEY_TYPE_WEP40 = 1, 218 RTW89_SEC_KEY_TYPE_WEP104 = 2, 219 RTW89_SEC_KEY_TYPE_TKIP = 3, 220 RTW89_SEC_KEY_TYPE_WAPI = 4, 221 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 222 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 223 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 224 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 225 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 226 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 227 }; 228 229 enum rtw89_port { 230 RTW89_PORT_0 = 0, 231 RTW89_PORT_1 = 1, 232 RTW89_PORT_2 = 2, 233 RTW89_PORT_3 = 3, 234 RTW89_PORT_4 = 4, 235 RTW89_PORT_NUM 236 }; 237 238 enum rtw89_band { 239 RTW89_BAND_2G = 0, 240 RTW89_BAND_5G = 1, 241 RTW89_BAND_6G = 2, 242 RTW89_BAND_MAX, 243 }; 244 245 enum rtw89_hw_rate { 246 RTW89_HW_RATE_CCK1 = 0x0, 247 RTW89_HW_RATE_CCK2 = 0x1, 248 RTW89_HW_RATE_CCK5_5 = 0x2, 249 RTW89_HW_RATE_CCK11 = 0x3, 250 RTW89_HW_RATE_OFDM6 = 0x4, 251 RTW89_HW_RATE_OFDM9 = 0x5, 252 RTW89_HW_RATE_OFDM12 = 0x6, 253 RTW89_HW_RATE_OFDM18 = 0x7, 254 RTW89_HW_RATE_OFDM24 = 0x8, 255 RTW89_HW_RATE_OFDM36 = 0x9, 256 RTW89_HW_RATE_OFDM48 = 0xA, 257 RTW89_HW_RATE_OFDM54 = 0xB, 258 RTW89_HW_RATE_MCS0 = 0x80, 259 RTW89_HW_RATE_MCS1 = 0x81, 260 RTW89_HW_RATE_MCS2 = 0x82, 261 RTW89_HW_RATE_MCS3 = 0x83, 262 RTW89_HW_RATE_MCS4 = 0x84, 263 RTW89_HW_RATE_MCS5 = 0x85, 264 RTW89_HW_RATE_MCS6 = 0x86, 265 RTW89_HW_RATE_MCS7 = 0x87, 266 RTW89_HW_RATE_MCS8 = 0x88, 267 RTW89_HW_RATE_MCS9 = 0x89, 268 RTW89_HW_RATE_MCS10 = 0x8A, 269 RTW89_HW_RATE_MCS11 = 0x8B, 270 RTW89_HW_RATE_MCS12 = 0x8C, 271 RTW89_HW_RATE_MCS13 = 0x8D, 272 RTW89_HW_RATE_MCS14 = 0x8E, 273 RTW89_HW_RATE_MCS15 = 0x8F, 274 RTW89_HW_RATE_MCS16 = 0x90, 275 RTW89_HW_RATE_MCS17 = 0x91, 276 RTW89_HW_RATE_MCS18 = 0x92, 277 RTW89_HW_RATE_MCS19 = 0x93, 278 RTW89_HW_RATE_MCS20 = 0x94, 279 RTW89_HW_RATE_MCS21 = 0x95, 280 RTW89_HW_RATE_MCS22 = 0x96, 281 RTW89_HW_RATE_MCS23 = 0x97, 282 RTW89_HW_RATE_MCS24 = 0x98, 283 RTW89_HW_RATE_MCS25 = 0x99, 284 RTW89_HW_RATE_MCS26 = 0x9A, 285 RTW89_HW_RATE_MCS27 = 0x9B, 286 RTW89_HW_RATE_MCS28 = 0x9C, 287 RTW89_HW_RATE_MCS29 = 0x9D, 288 RTW89_HW_RATE_MCS30 = 0x9E, 289 RTW89_HW_RATE_MCS31 = 0x9F, 290 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 291 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 292 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 293 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 294 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 295 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 296 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 297 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 298 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 299 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 300 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 301 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 302 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 303 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 304 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 305 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 306 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 307 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 308 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 309 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 310 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 311 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 312 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 313 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 314 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 315 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 316 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 317 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 318 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 319 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 320 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 321 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 322 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 323 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 324 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 325 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 326 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 327 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 328 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 329 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 330 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 331 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 332 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 333 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 334 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 335 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 336 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 337 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 338 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 339 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 340 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 341 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 342 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 343 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 344 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 345 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 346 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 347 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 348 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 349 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 350 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 351 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 352 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 353 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 354 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 355 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 356 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 357 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 358 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 359 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 360 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 361 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 362 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 363 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 364 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 365 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 366 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 367 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 368 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 369 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 370 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 371 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 372 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 373 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 374 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 375 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 376 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 377 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 378 RTW89_HW_RATE_NR, 379 380 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 381 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 382 }; 383 384 /* 2G channels, 385 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 386 */ 387 #define RTW89_2G_CH_NUM 14 388 389 /* 5G channels, 390 * 36, 38, 40, 42, 44, 46, 48, 50, 391 * 52, 54, 56, 58, 60, 62, 64, 392 * 100, 102, 104, 106, 108, 110, 112, 114, 393 * 116, 118, 120, 122, 124, 126, 128, 130, 394 * 132, 134, 136, 138, 140, 142, 144, 395 * 149, 151, 153, 155, 157, 159, 161, 163, 396 * 165, 167, 169, 171, 173, 175, 177 397 */ 398 #define RTW89_5G_CH_NUM 53 399 400 /* 6G channels, 401 * 1, 3, 5, 7, 9, 11, 13, 15, 402 * 17, 19, 21, 23, 25, 27, 29, 33, 403 * 35, 37, 39, 41, 43, 45, 47, 49, 404 * 51, 53, 55, 57, 59, 61, 65, 67, 405 * 69, 71, 73, 75, 77, 79, 81, 83, 406 * 85, 87, 89, 91, 93, 97, 99, 101, 407 * 103, 105, 107, 109, 111, 113, 115, 117, 408 * 119, 121, 123, 125, 129, 131, 133, 135, 409 * 137, 139, 141, 143, 145, 147, 149, 151, 410 * 153, 155, 157, 161, 163, 165, 167, 169, 411 * 171, 173, 175, 177, 179, 181, 183, 185, 412 * 187, 189, 193, 195, 197, 199, 201, 203, 413 * 205, 207, 209, 211, 213, 215, 217, 219, 414 * 221, 225, 227, 229, 231, 233, 235, 237, 415 * 239, 241, 243, 245, 247, 249, 251, 253, 416 */ 417 #define RTW89_6G_CH_NUM 120 418 419 enum rtw89_rate_section { 420 RTW89_RS_CCK, 421 RTW89_RS_OFDM, 422 RTW89_RS_MCS, /* for HT/VHT/HE */ 423 RTW89_RS_HEDCM, 424 RTW89_RS_OFFSET, 425 RTW89_RS_MAX, 426 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 427 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 428 }; 429 430 enum rtw89_rate_max { 431 RTW89_RATE_CCK_MAX = 4, 432 RTW89_RATE_OFDM_MAX = 8, 433 RTW89_RATE_MCS_MAX = 12, 434 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 435 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 436 }; 437 438 enum rtw89_nss { 439 RTW89_NSS_1 = 0, 440 RTW89_NSS_2 = 1, 441 /* HE DCM only support 1ss and 2ss */ 442 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 443 RTW89_NSS_3 = 2, 444 RTW89_NSS_4 = 3, 445 RTW89_NSS_MAX, 446 }; 447 448 enum rtw89_ntx { 449 RTW89_1TX = 0, 450 RTW89_2TX = 1, 451 RTW89_NTX_NUM, 452 }; 453 454 enum rtw89_beamforming_type { 455 RTW89_NONBF = 0, 456 RTW89_BF = 1, 457 RTW89_BF_NUM, 458 }; 459 460 enum rtw89_regulation_type { 461 RTW89_WW = 0, 462 RTW89_ETSI = 1, 463 RTW89_FCC = 2, 464 RTW89_MKK = 3, 465 RTW89_NA = 4, 466 RTW89_IC = 5, 467 RTW89_KCC = 6, 468 RTW89_ACMA = 7, 469 RTW89_NCC = 8, 470 RTW89_MEXICO = 9, 471 RTW89_CHILE = 10, 472 RTW89_UKRAINE = 11, 473 RTW89_CN = 12, 474 RTW89_QATAR = 13, 475 RTW89_UK = 14, 476 RTW89_REGD_NUM, 477 }; 478 479 struct rtw89_txpwr_byrate { 480 s8 cck[RTW89_RATE_CCK_MAX]; 481 s8 ofdm[RTW89_RATE_OFDM_MAX]; 482 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 483 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 484 s8 offset[RTW89_RATE_OFFSET_MAX]; 485 }; 486 487 enum rtw89_bandwidth_section_num { 488 RTW89_BW20_SEC_NUM = 8, 489 RTW89_BW40_SEC_NUM = 4, 490 RTW89_BW80_SEC_NUM = 2, 491 }; 492 493 struct rtw89_txpwr_limit { 494 s8 cck_20m[RTW89_BF_NUM]; 495 s8 cck_40m[RTW89_BF_NUM]; 496 s8 ofdm[RTW89_BF_NUM]; 497 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 498 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 499 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 500 s8 mcs_160m[RTW89_BF_NUM]; 501 s8 mcs_40m_0p5[RTW89_BF_NUM]; 502 s8 mcs_40m_2p5[RTW89_BF_NUM]; 503 }; 504 505 #define RTW89_RU_SEC_NUM 8 506 507 struct rtw89_txpwr_limit_ru { 508 s8 ru26[RTW89_RU_SEC_NUM]; 509 s8 ru52[RTW89_RU_SEC_NUM]; 510 s8 ru106[RTW89_RU_SEC_NUM]; 511 }; 512 513 struct rtw89_rate_desc { 514 enum rtw89_nss nss; 515 enum rtw89_rate_section rs; 516 u8 idx; 517 }; 518 519 #define PHY_STS_HDR_LEN 8 520 #define RF_PATH_MAX 4 521 #define RTW89_MAX_PPDU_CNT 8 522 struct rtw89_rx_phy_ppdu { 523 u8 *buf; 524 u32 len; 525 u8 rssi_avg; 526 u8 rssi[RF_PATH_MAX]; 527 u8 mac_id; 528 u8 chan_idx; 529 u8 ie; 530 u16 rate; 531 bool to_self; 532 bool valid; 533 }; 534 535 enum rtw89_mac_idx { 536 RTW89_MAC_0 = 0, 537 RTW89_MAC_1 = 1, 538 }; 539 540 enum rtw89_phy_idx { 541 RTW89_PHY_0 = 0, 542 RTW89_PHY_1 = 1, 543 RTW89_PHY_MAX 544 }; 545 546 enum rtw89_sub_entity_idx { 547 RTW89_SUB_ENTITY_0 = 0, 548 549 NUM_OF_RTW89_SUB_ENTITY, 550 }; 551 552 enum rtw89_rf_path { 553 RF_PATH_A = 0, 554 RF_PATH_B = 1, 555 RF_PATH_C = 2, 556 RF_PATH_D = 3, 557 RF_PATH_AB, 558 RF_PATH_AC, 559 RF_PATH_AD, 560 RF_PATH_BC, 561 RF_PATH_BD, 562 RF_PATH_CD, 563 RF_PATH_ABC, 564 RF_PATH_ABD, 565 RF_PATH_ACD, 566 RF_PATH_BCD, 567 RF_PATH_ABCD, 568 }; 569 570 enum rtw89_rf_path_bit { 571 RF_A = BIT(0), 572 RF_B = BIT(1), 573 RF_C = BIT(2), 574 RF_D = BIT(3), 575 576 RF_AB = (RF_A | RF_B), 577 RF_AC = (RF_A | RF_C), 578 RF_AD = (RF_A | RF_D), 579 RF_BC = (RF_B | RF_C), 580 RF_BD = (RF_B | RF_D), 581 RF_CD = (RF_C | RF_D), 582 583 RF_ABC = (RF_A | RF_B | RF_C), 584 RF_ABD = (RF_A | RF_B | RF_D), 585 RF_ACD = (RF_A | RF_C | RF_D), 586 RF_BCD = (RF_B | RF_C | RF_D), 587 588 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 589 }; 590 591 enum rtw89_bandwidth { 592 RTW89_CHANNEL_WIDTH_20 = 0, 593 RTW89_CHANNEL_WIDTH_40 = 1, 594 RTW89_CHANNEL_WIDTH_80 = 2, 595 RTW89_CHANNEL_WIDTH_160 = 3, 596 RTW89_CHANNEL_WIDTH_80_80 = 4, 597 RTW89_CHANNEL_WIDTH_5 = 5, 598 RTW89_CHANNEL_WIDTH_10 = 6, 599 }; 600 601 enum rtw89_ps_mode { 602 RTW89_PS_MODE_NONE = 0, 603 RTW89_PS_MODE_RFOFF = 1, 604 RTW89_PS_MODE_CLK_GATED = 2, 605 RTW89_PS_MODE_PWR_GATED = 3, 606 }; 607 608 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 609 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 610 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 611 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 612 613 enum rtw89_ru_bandwidth { 614 RTW89_RU26 = 0, 615 RTW89_RU52 = 1, 616 RTW89_RU106 = 2, 617 RTW89_RU_NUM, 618 }; 619 620 enum rtw89_sc_offset { 621 RTW89_SC_DONT_CARE = 0, 622 RTW89_SC_20_UPPER = 1, 623 RTW89_SC_20_LOWER = 2, 624 RTW89_SC_20_UPMOST = 3, 625 RTW89_SC_20_LOWEST = 4, 626 RTW89_SC_20_UP2X = 5, 627 RTW89_SC_20_LOW2X = 6, 628 RTW89_SC_20_UP3X = 7, 629 RTW89_SC_20_LOW3X = 8, 630 RTW89_SC_40_UPPER = 9, 631 RTW89_SC_40_LOWER = 10, 632 }; 633 634 struct rtw89_chan { 635 u8 channel; 636 u8 primary_channel; 637 enum rtw89_band band_type; 638 enum rtw89_bandwidth band_width; 639 640 /* The follow-up are derived from the above. We must ensure that it 641 * is assigned correctly in rtw89_chan_create() if new one is added. 642 */ 643 u32 freq; 644 enum rtw89_subband subband_type; 645 enum rtw89_sc_offset pri_ch_idx; 646 }; 647 648 struct rtw89_chan_rcd { 649 u8 prev_primary_channel; 650 enum rtw89_band prev_band_type; 651 }; 652 653 struct rtw89_channel_help_params { 654 u32 tx_en; 655 }; 656 657 struct rtw89_port_reg { 658 u32 port_cfg; 659 u32 tbtt_prohib; 660 u32 bcn_area; 661 u32 bcn_early; 662 u32 tbtt_early; 663 u32 tbtt_agg; 664 u32 bcn_space; 665 u32 bcn_forcetx; 666 u32 bcn_err_cnt; 667 u32 bcn_err_flag; 668 u32 dtim_ctrl; 669 u32 tbtt_shift; 670 u32 bcn_cnt_tmr; 671 u32 tsftr_l; 672 u32 tsftr_h; 673 }; 674 675 struct rtw89_txwd_body { 676 __le32 dword0; 677 __le32 dword1; 678 __le32 dword2; 679 __le32 dword3; 680 __le32 dword4; 681 __le32 dword5; 682 } __packed; 683 684 struct rtw89_txwd_body_v1 { 685 __le32 dword0; 686 __le32 dword1; 687 __le32 dword2; 688 __le32 dword3; 689 __le32 dword4; 690 __le32 dword5; 691 __le32 dword6; 692 __le32 dword7; 693 } __packed; 694 695 struct rtw89_txwd_info { 696 __le32 dword0; 697 __le32 dword1; 698 __le32 dword2; 699 __le32 dword3; 700 __le32 dword4; 701 __le32 dword5; 702 } __packed; 703 704 struct rtw89_rx_desc_info { 705 u16 pkt_size; 706 u8 pkt_type; 707 u8 drv_info_size; 708 u8 shift; 709 u8 wl_hd_iv_len; 710 bool long_rxdesc; 711 bool bb_sel; 712 bool mac_info_valid; 713 u16 data_rate; 714 u8 gi_ltf; 715 u8 bw; 716 u32 free_run_cnt; 717 u8 user_id; 718 bool sr_en; 719 u8 ppdu_cnt; 720 u8 ppdu_type; 721 bool icv_err; 722 bool crc32_err; 723 bool hw_dec; 724 bool sw_dec; 725 bool addr1_match; 726 u8 frag; 727 u16 seq; 728 u8 frame_type; 729 u8 rx_pl_id; 730 bool addr_cam_valid; 731 u8 addr_cam_id; 732 u8 sec_cam_id; 733 u8 mac_id; 734 u16 offset; 735 bool ready; 736 }; 737 738 struct rtw89_rxdesc_short { 739 __le32 dword0; 740 __le32 dword1; 741 __le32 dword2; 742 __le32 dword3; 743 } __packed; 744 745 struct rtw89_rxdesc_long { 746 __le32 dword0; 747 __le32 dword1; 748 __le32 dword2; 749 __le32 dword3; 750 __le32 dword4; 751 __le32 dword5; 752 __le32 dword6; 753 __le32 dword7; 754 } __packed; 755 756 struct rtw89_tx_desc_info { 757 u16 pkt_size; 758 u8 wp_offset; 759 u8 mac_id; 760 u8 qsel; 761 u8 ch_dma; 762 u8 hdr_llc_len; 763 bool is_bmc; 764 bool en_wd_info; 765 bool wd_page; 766 bool use_rate; 767 bool dis_data_fb; 768 bool tid_indicate; 769 bool agg_en; 770 bool bk; 771 u8 ampdu_density; 772 u8 ampdu_num; 773 bool sec_en; 774 u8 addr_info_nr; 775 u8 sec_keyid; 776 u8 sec_type; 777 u8 sec_cam_idx; 778 u8 sec_seq[6]; 779 u16 data_rate; 780 u16 data_retry_lowest_rate; 781 bool fw_dl; 782 u16 seq; 783 bool a_ctrl_bsr; 784 u8 hw_ssn_sel; 785 #define RTW89_MGMT_HW_SSN_SEL 1 786 u8 hw_seq_mode; 787 #define RTW89_MGMT_HW_SEQ_MODE 1 788 bool hiq; 789 u8 port; 790 }; 791 792 struct rtw89_core_tx_request { 793 enum rtw89_core_tx_type tx_type; 794 795 struct sk_buff *skb; 796 struct ieee80211_vif *vif; 797 struct ieee80211_sta *sta; 798 struct rtw89_tx_desc_info desc_info; 799 }; 800 801 struct rtw89_txq { 802 struct list_head list; 803 unsigned long flags; 804 int wait_cnt; 805 }; 806 807 struct rtw89_mac_ax_gnt { 808 u8 gnt_bt_sw_en; 809 u8 gnt_bt; 810 u8 gnt_wl_sw_en; 811 u8 gnt_wl; 812 } __packed; 813 814 #define RTW89_MAC_AX_COEX_GNT_NR 2 815 struct rtw89_mac_ax_coex_gnt { 816 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 817 }; 818 819 enum rtw89_btc_ncnt { 820 BTC_NCNT_POWER_ON = 0x0, 821 BTC_NCNT_POWER_OFF, 822 BTC_NCNT_INIT_COEX, 823 BTC_NCNT_SCAN_START, 824 BTC_NCNT_SCAN_FINISH, 825 BTC_NCNT_SPECIAL_PACKET, 826 BTC_NCNT_SWITCH_BAND, 827 BTC_NCNT_RFK_TIMEOUT, 828 BTC_NCNT_SHOW_COEX_INFO, 829 BTC_NCNT_ROLE_INFO, 830 BTC_NCNT_CONTROL, 831 BTC_NCNT_RADIO_STATE, 832 BTC_NCNT_CUSTOMERIZE, 833 BTC_NCNT_WL_RFK, 834 BTC_NCNT_WL_STA, 835 BTC_NCNT_FWINFO, 836 BTC_NCNT_TIMER, 837 BTC_NCNT_NUM 838 }; 839 840 enum rtw89_btc_btinfo { 841 BTC_BTINFO_L0 = 0, 842 BTC_BTINFO_L1, 843 BTC_BTINFO_L2, 844 BTC_BTINFO_L3, 845 BTC_BTINFO_H0, 846 BTC_BTINFO_H1, 847 BTC_BTINFO_H2, 848 BTC_BTINFO_H3, 849 BTC_BTINFO_MAX 850 }; 851 852 enum rtw89_btc_dcnt { 853 BTC_DCNT_RUN = 0x0, 854 BTC_DCNT_CX_RUNINFO, 855 BTC_DCNT_RPT, 856 BTC_DCNT_RPT_FREEZE, 857 BTC_DCNT_CYCLE, 858 BTC_DCNT_CYCLE_FREEZE, 859 BTC_DCNT_W1, 860 BTC_DCNT_W1_FREEZE, 861 BTC_DCNT_B1, 862 BTC_DCNT_B1_FREEZE, 863 BTC_DCNT_TDMA_NONSYNC, 864 BTC_DCNT_SLOT_NONSYNC, 865 BTC_DCNT_BTCNT_FREEZE, 866 BTC_DCNT_WL_SLOT_DRIFT, 867 BTC_DCNT_BT_SLOT_DRIFT, 868 BTC_DCNT_WL_STA_LAST, 869 BTC_DCNT_NUM, 870 }; 871 872 enum rtw89_btc_wl_state_cnt { 873 BTC_WCNT_SCANAP = 0x0, 874 BTC_WCNT_DHCP, 875 BTC_WCNT_EAPOL, 876 BTC_WCNT_ARP, 877 BTC_WCNT_SCBDUPDATE, 878 BTC_WCNT_RFK_REQ, 879 BTC_WCNT_RFK_GO, 880 BTC_WCNT_RFK_REJECT, 881 BTC_WCNT_RFK_TIMEOUT, 882 BTC_WCNT_CH_UPDATE, 883 BTC_WCNT_NUM 884 }; 885 886 enum rtw89_btc_bt_state_cnt { 887 BTC_BCNT_RETRY = 0x0, 888 BTC_BCNT_REINIT, 889 BTC_BCNT_REENABLE, 890 BTC_BCNT_SCBDREAD, 891 BTC_BCNT_RELINK, 892 BTC_BCNT_IGNOWL, 893 BTC_BCNT_INQPAG, 894 BTC_BCNT_INQ, 895 BTC_BCNT_PAGE, 896 BTC_BCNT_ROLESW, 897 BTC_BCNT_AFH, 898 BTC_BCNT_INFOUPDATE, 899 BTC_BCNT_INFOSAME, 900 BTC_BCNT_SCBDUPDATE, 901 BTC_BCNT_HIPRI_TX, 902 BTC_BCNT_HIPRI_RX, 903 BTC_BCNT_LOPRI_TX, 904 BTC_BCNT_LOPRI_RX, 905 BTC_BCNT_POLUT, 906 BTC_BCNT_RATECHG, 907 BTC_BCNT_NUM 908 }; 909 910 enum rtw89_btc_bt_profile { 911 BTC_BT_NOPROFILE = 0, 912 BTC_BT_HFP = BIT(0), 913 BTC_BT_HID = BIT(1), 914 BTC_BT_A2DP = BIT(2), 915 BTC_BT_PAN = BIT(3), 916 BTC_PROFILE_MAX = 4, 917 }; 918 919 struct rtw89_btc_ant_info { 920 u8 type; /* shared, dedicated */ 921 u8 num; 922 u8 isolation; 923 924 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 925 u8 diversity: 1; 926 }; 927 928 enum rtw89_tfc_dir { 929 RTW89_TFC_UL, 930 RTW89_TFC_DL, 931 }; 932 933 struct rtw89_btc_wl_smap { 934 u32 busy: 1; 935 u32 scan: 1; 936 u32 connecting: 1; 937 u32 roaming: 1; 938 u32 _4way: 1; 939 u32 rf_off: 1; 940 u32 lps: 2; 941 u32 ips: 1; 942 u32 init_ok: 1; 943 u32 traffic_dir : 2; 944 u32 rf_off_pre: 1; 945 u32 lps_pre: 2; 946 }; 947 948 enum rtw89_tfc_lv { 949 RTW89_TFC_IDLE, 950 RTW89_TFC_ULTRA_LOW, 951 RTW89_TFC_LOW, 952 RTW89_TFC_MID, 953 RTW89_TFC_HIGH, 954 }; 955 956 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 957 DECLARE_EWMA(tp, 10, 2); 958 959 struct rtw89_traffic_stats { 960 /* units in bytes */ 961 u64 tx_unicast; 962 u64 rx_unicast; 963 u32 tx_avg_len; 964 u32 rx_avg_len; 965 966 /* count for packets */ 967 u64 tx_cnt; 968 u64 rx_cnt; 969 970 /* units in Mbps */ 971 u32 tx_throughput; 972 u32 rx_throughput; 973 u32 tx_throughput_raw; 974 u32 rx_throughput_raw; 975 976 u32 rx_tf_acc; 977 u32 rx_tf_periodic; 978 979 enum rtw89_tfc_lv tx_tfc_lv; 980 enum rtw89_tfc_lv rx_tfc_lv; 981 struct ewma_tp tx_ewma_tp; 982 struct ewma_tp rx_ewma_tp; 983 984 u16 tx_rate; 985 u16 rx_rate; 986 }; 987 988 struct rtw89_btc_statistic { 989 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 990 struct rtw89_traffic_stats traffic; 991 }; 992 993 #define BTC_WL_RSSI_THMAX 4 994 995 struct rtw89_btc_wl_link_info { 996 struct rtw89_btc_statistic stat; 997 enum rtw89_tfc_dir dir; 998 u8 rssi_state[BTC_WL_RSSI_THMAX]; 999 u8 mac_addr[ETH_ALEN]; 1000 u8 busy; 1001 u8 ch; 1002 u8 bw; 1003 u8 band; 1004 u8 role; 1005 u8 pid; 1006 u8 phy; 1007 u8 dtim_period; 1008 u8 mode; 1009 1010 u8 mac_id; 1011 u8 tx_retry; 1012 1013 u32 bcn_period; 1014 u32 busy_t; 1015 u32 tx_time; 1016 u32 client_cnt; 1017 u32 rx_rate_drop_cnt; 1018 1019 u32 active: 1; 1020 u32 noa: 1; 1021 u32 client_ps: 1; 1022 u32 connected: 2; 1023 }; 1024 1025 union rtw89_btc_wl_state_map { 1026 u32 val; 1027 struct rtw89_btc_wl_smap map; 1028 }; 1029 1030 struct rtw89_btc_bt_hfp_desc { 1031 u32 exist: 1; 1032 u32 type: 2; 1033 u32 rsvd: 29; 1034 }; 1035 1036 struct rtw89_btc_bt_hid_desc { 1037 u32 exist: 1; 1038 u32 slot_info: 2; 1039 u32 pair_cnt: 2; 1040 u32 type: 8; 1041 u32 rsvd: 19; 1042 }; 1043 1044 struct rtw89_btc_bt_a2dp_desc { 1045 u8 exist: 1; 1046 u8 exist_last: 1; 1047 u8 play_latency: 1; 1048 u8 type: 3; 1049 u8 active: 1; 1050 u8 sink: 1; 1051 1052 u8 bitpool; 1053 u16 vendor_id; 1054 u32 device_name; 1055 u32 flush_time; 1056 }; 1057 1058 struct rtw89_btc_bt_pan_desc { 1059 u32 exist: 1; 1060 u32 type: 1; 1061 u32 active: 1; 1062 u32 rsvd: 29; 1063 }; 1064 1065 struct rtw89_btc_bt_rfk_info { 1066 u32 run: 1; 1067 u32 req: 1; 1068 u32 timeout: 1; 1069 u32 rsvd: 29; 1070 }; 1071 1072 union rtw89_btc_bt_rfk_info_map { 1073 u32 val; 1074 struct rtw89_btc_bt_rfk_info map; 1075 }; 1076 1077 struct rtw89_btc_bt_ver_info { 1078 u32 fw_coex; /* match with which coex_ver */ 1079 u32 fw; 1080 }; 1081 1082 struct rtw89_btc_bool_sta_chg { 1083 u32 now: 1; 1084 u32 last: 1; 1085 u32 remain: 1; 1086 u32 srvd: 29; 1087 }; 1088 1089 struct rtw89_btc_u8_sta_chg { 1090 u8 now; 1091 u8 last; 1092 u8 remain; 1093 u8 rsvd; 1094 }; 1095 1096 struct rtw89_btc_wl_scan_info { 1097 u8 band[RTW89_PHY_MAX]; 1098 u8 phy_map; 1099 u8 rsvd; 1100 }; 1101 1102 struct rtw89_btc_wl_dbcc_info { 1103 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1104 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1105 u8 real_band[RTW89_PHY_MAX]; 1106 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1107 }; 1108 1109 struct rtw89_btc_wl_active_role { 1110 u8 connected: 1; 1111 u8 pid: 3; 1112 u8 phy: 1; 1113 u8 noa: 1; 1114 u8 band: 2; 1115 1116 u8 client_ps: 1; 1117 u8 bw: 7; 1118 1119 u8 role; 1120 u8 ch; 1121 1122 u16 tx_lvl; 1123 u16 rx_lvl; 1124 u16 tx_rate; 1125 u16 rx_rate; 1126 }; 1127 1128 struct rtw89_btc_wl_active_role_v1 { 1129 u8 connected: 1; 1130 u8 pid: 3; 1131 u8 phy: 1; 1132 u8 noa: 1; 1133 u8 band: 2; 1134 1135 u8 client_ps: 1; 1136 u8 bw: 7; 1137 1138 u8 role; 1139 u8 ch; 1140 1141 u16 tx_lvl; 1142 u16 rx_lvl; 1143 u16 tx_rate; 1144 u16 rx_rate; 1145 1146 u32 noa_duration; /* ms */ 1147 }; 1148 1149 struct rtw89_btc_wl_role_info_bpos { 1150 u16 none: 1; 1151 u16 station: 1; 1152 u16 ap: 1; 1153 u16 vap: 1; 1154 u16 adhoc: 1; 1155 u16 adhoc_master: 1; 1156 u16 mesh: 1; 1157 u16 moniter: 1; 1158 u16 p2p_device: 1; 1159 u16 p2p_gc: 1; 1160 u16 p2p_go: 1; 1161 u16 nan: 1; 1162 }; 1163 1164 struct rtw89_btc_wl_scc_ctrl { 1165 u8 null_role1; 1166 u8 null_role2; 1167 u8 ebt_null; /* if tx null at EBT slot */ 1168 }; 1169 1170 union rtw89_btc_wl_role_info_map { 1171 u16 val; 1172 struct rtw89_btc_wl_role_info_bpos role; 1173 }; 1174 1175 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1176 u8 connect_cnt; 1177 u8 link_mode; 1178 union rtw89_btc_wl_role_info_map role_map; 1179 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1180 }; 1181 1182 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1183 u8 connect_cnt; 1184 u8 link_mode; 1185 union rtw89_btc_wl_role_info_map role_map; 1186 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1187 u32 mrole_type; /* btc_wl_mrole_type */ 1188 u32 mrole_noa_duration; /* ms */ 1189 1190 u32 dbcc_en: 1; 1191 u32 dbcc_chg: 1; 1192 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1193 u32 link_mode_chg: 1; 1194 u32 rsvd: 27; 1195 }; 1196 1197 struct rtw89_btc_wl_ver_info { 1198 u32 fw_coex; /* match with which coex_ver */ 1199 u32 fw; 1200 u32 mac; 1201 u32 bb; 1202 u32 rf; 1203 }; 1204 1205 struct rtw89_btc_wl_afh_info { 1206 u8 en; 1207 u8 ch; 1208 u8 bw; 1209 u8 rsvd; 1210 } __packed; 1211 1212 struct rtw89_btc_wl_rfk_info { 1213 u32 state: 2; 1214 u32 path_map: 4; 1215 u32 phy_map: 2; 1216 u32 band: 2; 1217 u32 type: 8; 1218 u32 rsvd: 14; 1219 }; 1220 1221 struct rtw89_btc_bt_smap { 1222 u32 connect: 1; 1223 u32 ble_connect: 1; 1224 u32 acl_busy: 1; 1225 u32 sco_busy: 1; 1226 u32 mesh_busy: 1; 1227 u32 inq_pag: 1; 1228 }; 1229 1230 union rtw89_btc_bt_state_map { 1231 u32 val; 1232 struct rtw89_btc_bt_smap map; 1233 }; 1234 1235 #define BTC_BT_RSSI_THMAX 4 1236 #define BTC_BT_AFH_GROUP 12 1237 1238 struct rtw89_btc_bt_link_info { 1239 struct rtw89_btc_u8_sta_chg profile_cnt; 1240 struct rtw89_btc_bool_sta_chg multi_link; 1241 struct rtw89_btc_bool_sta_chg relink; 1242 struct rtw89_btc_bt_hfp_desc hfp_desc; 1243 struct rtw89_btc_bt_hid_desc hid_desc; 1244 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1245 struct rtw89_btc_bt_pan_desc pan_desc; 1246 union rtw89_btc_bt_state_map status; 1247 1248 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1249 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1250 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1251 u8 afh_map[BTC_BT_AFH_GROUP]; 1252 1253 u32 role_sw: 1; 1254 u32 slave_role: 1; 1255 u32 afh_update: 1; 1256 u32 cqddr: 1; 1257 u32 rssi: 8; 1258 u32 tx_3m: 1; 1259 u32 rsvd: 19; 1260 }; 1261 1262 struct rtw89_btc_3rdcx_info { 1263 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1264 u8 hw_coex; 1265 u16 rsvd; 1266 }; 1267 1268 struct rtw89_btc_dm_emap { 1269 u32 init: 1; 1270 u32 pta_owner: 1; 1271 u32 wl_rfk_timeout: 1; 1272 u32 bt_rfk_timeout: 1; 1273 1274 u32 wl_fw_hang: 1; 1275 u32 offload_mismatch: 1; 1276 u32 cycle_hang: 1; 1277 u32 w1_hang: 1; 1278 1279 u32 b1_hang: 1; 1280 u32 tdma_no_sync: 1; 1281 u32 wl_slot_drift: 1; 1282 }; 1283 1284 union rtw89_btc_dm_error_map { 1285 u32 val; 1286 struct rtw89_btc_dm_emap map; 1287 }; 1288 1289 struct rtw89_btc_rf_para { 1290 u32 tx_pwr_freerun; 1291 u32 rx_gain_freerun; 1292 u32 tx_pwr_perpkt; 1293 u32 rx_gain_perpkt; 1294 }; 1295 1296 struct rtw89_btc_wl_info { 1297 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1298 struct rtw89_btc_wl_rfk_info rfk_info; 1299 struct rtw89_btc_wl_ver_info ver_info; 1300 struct rtw89_btc_wl_afh_info afh_info; 1301 struct rtw89_btc_wl_role_info role_info; 1302 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1303 struct rtw89_btc_wl_scan_info scan_info; 1304 struct rtw89_btc_wl_dbcc_info dbcc_info; 1305 struct rtw89_btc_rf_para rf_para; 1306 union rtw89_btc_wl_state_map status; 1307 1308 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1309 u8 rssi_level; 1310 1311 bool scbd_change; 1312 u32 scbd; 1313 }; 1314 1315 struct rtw89_btc_module { 1316 struct rtw89_btc_ant_info ant; 1317 u8 rfe_type; 1318 u8 cv; 1319 1320 u8 bt_solo: 1; 1321 u8 bt_pos: 1; 1322 u8 switch_type: 1; 1323 1324 u8 rsvd; 1325 }; 1326 1327 #define RTW89_BTC_DM_MAXSTEP 30 1328 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1329 1330 struct rtw89_btc_dm_step { 1331 u16 step[RTW89_BTC_DM_MAXSTEP]; 1332 u8 step_pos; 1333 bool step_ov; 1334 }; 1335 1336 struct rtw89_btc_init_info { 1337 struct rtw89_btc_module module; 1338 u8 wl_guard_ch; 1339 1340 u8 wl_only: 1; 1341 u8 wl_init_ok: 1; 1342 u8 dbcc_en: 1; 1343 u8 cx_other: 1; 1344 u8 bt_only: 1; 1345 1346 u16 rsvd; 1347 }; 1348 1349 struct rtw89_btc_wl_tx_limit_para { 1350 u16 enable; 1351 u32 tx_time; /* unit: us */ 1352 u16 tx_retry; 1353 }; 1354 1355 struct rtw89_btc_bt_scan_info { 1356 u16 win; 1357 u16 intvl; 1358 u32 enable: 1; 1359 u32 interlace: 1; 1360 u32 rsvd: 30; 1361 }; 1362 1363 enum rtw89_btc_bt_scan_type { 1364 BTC_SCAN_INQ = 0, 1365 BTC_SCAN_PAGE, 1366 BTC_SCAN_BLE, 1367 BTC_SCAN_INIT, 1368 BTC_SCAN_TV, 1369 BTC_SCAN_ADV, 1370 BTC_SCAN_MAX1, 1371 }; 1372 1373 struct rtw89_btc_bt_info { 1374 struct rtw89_btc_bt_link_info link_info; 1375 struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; 1376 struct rtw89_btc_bt_ver_info ver_info; 1377 struct rtw89_btc_bool_sta_chg enable; 1378 struct rtw89_btc_bool_sta_chg inq_pag; 1379 struct rtw89_btc_rf_para rf_para; 1380 union rtw89_btc_bt_rfk_info_map rfk_info; 1381 1382 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1383 1384 u32 scbd; 1385 u32 feature; 1386 1387 u32 mbx_avl: 1; 1388 u32 whql_test: 1; 1389 u32 igno_wl: 1; 1390 u32 reinit: 1; 1391 u32 ble_scan_en: 1; 1392 u32 btg_type: 1; 1393 u32 inq: 1; 1394 u32 pag: 1; 1395 u32 run_patch_code: 1; 1396 u32 hi_lna_rx: 1; 1397 u32 scan_rx_low_pri: 1; 1398 u32 rsvd: 21; 1399 }; 1400 1401 struct rtw89_btc_cx { 1402 struct rtw89_btc_wl_info wl; 1403 struct rtw89_btc_bt_info bt; 1404 struct rtw89_btc_3rdcx_info other; 1405 u32 state_map; 1406 u32 cnt_bt[BTC_BCNT_NUM]; 1407 u32 cnt_wl[BTC_WCNT_NUM]; 1408 }; 1409 1410 struct rtw89_btc_fbtc_tdma { 1411 u8 type; /* chip_info::fcxtdma_ver */ 1412 u8 rxflctrl; 1413 u8 txpause; 1414 u8 wtgle_n; 1415 u8 leak_n; 1416 u8 ext_ctrl; 1417 u8 rxflctrl_role; 1418 u8 option_ctrl; 1419 } __packed; 1420 1421 struct rtw89_btc_fbtc_tdma_v1 { 1422 u8 fver; /* chip_info::fcxtdma_ver */ 1423 u8 rsvd; 1424 __le16 rsvd1; 1425 struct rtw89_btc_fbtc_tdma tdma; 1426 } __packed; 1427 1428 #define CXMREG_MAX 30 1429 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1430 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1431 1432 enum rtw89_btc_bt_sta_counter { 1433 BTC_BCNT_RFK_REQ = 0, 1434 BTC_BCNT_RFK_GO = 1, 1435 BTC_BCNT_RFK_REJECT = 2, 1436 BTC_BCNT_RFK_FAIL = 3, 1437 BTC_BCNT_RFK_TIMEOUT = 4, 1438 BTC_BCNT_HI_TX = 5, 1439 BTC_BCNT_HI_RX = 6, 1440 BTC_BCNT_LO_TX = 7, 1441 BTC_BCNT_LO_RX = 8, 1442 BTC_BCNT_POLLUTED = 9, 1443 BTC_BCNT_STA_MAX 1444 }; 1445 1446 struct rtw89_btc_fbtc_rpt_ctrl { 1447 u16 fver; /* chip_info::fcxbtcrpt_ver */ 1448 u16 rpt_cnt; /* tmr counters */ 1449 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1450 u32 wl_fw_cx_offload; 1451 u32 wl_fw_ver; 1452 u32 rpt_enable; 1453 u32 rpt_para; /* ms */ 1454 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1455 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1456 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1457 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1458 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1459 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1460 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1461 u32 c2h_cnt; /* fw send c2h counter */ 1462 u32 h2c_cnt; /* fw recv h2c counter */ 1463 } __packed; 1464 1465 struct rtw89_btc_fbtc_rpt_ctrl_info { 1466 __le32 cnt; /* fw report counter */ 1467 __le32 en; /* report map */ 1468 __le32 para; /* not used */ 1469 1470 __le32 cnt_c2h; /* fw send c2h counter */ 1471 __le32 cnt_h2c; /* fw recv h2c counter */ 1472 __le32 len_c2h; /* The total length of the last C2H */ 1473 1474 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1475 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1476 } __packed; 1477 1478 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1479 __le32 cx_ver; /* match which driver's coex version */ 1480 __le32 cx_offload; 1481 __le32 fw_ver; 1482 } __packed; 1483 1484 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1485 __le32 cnt_empty; /* a2dp empty count */ 1486 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1487 __le32 cnt_tx; 1488 __le32 cnt_ack; 1489 __le32 cnt_nack; 1490 } __packed; 1491 1492 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1493 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1494 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1495 __le32 cnt_recv; /* fw recv mailbox counter */ 1496 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1497 } __packed; 1498 1499 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1500 u8 fver; 1501 u8 rsvd; 1502 __le16 rsvd1; 1503 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1504 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1505 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1506 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1507 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1508 } __packed; 1509 1510 enum rtw89_fbtc_ext_ctrl_type { 1511 CXECTL_OFF = 0x0, /* tdma off */ 1512 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1513 CXECTL_EXT = 0x2, 1514 CXECTL_MAX 1515 }; 1516 1517 union rtw89_btc_fbtc_rxflct { 1518 u8 val; 1519 u8 type: 3; 1520 u8 tgln_n: 5; 1521 }; 1522 1523 enum rtw89_btc_cxst_state { 1524 CXST_OFF = 0x0, 1525 CXST_B2W = 0x1, 1526 CXST_W1 = 0x2, 1527 CXST_W2 = 0x3, 1528 CXST_W2B = 0x4, 1529 CXST_B1 = 0x5, 1530 CXST_B2 = 0x6, 1531 CXST_B3 = 0x7, 1532 CXST_B4 = 0x8, 1533 CXST_LK = 0x9, 1534 CXST_BLK = 0xa, 1535 CXST_E2G = 0xb, 1536 CXST_E5G = 0xc, 1537 CXST_EBT = 0xd, 1538 CXST_ENULL = 0xe, 1539 CXST_WLK = 0xf, 1540 CXST_W1FDD = 0x10, 1541 CXST_B1FDD = 0x11, 1542 CXST_MAX = 0x12, 1543 }; 1544 1545 enum { 1546 CXBCN_ALL = 0x0, 1547 CXBCN_ALL_OK, 1548 CXBCN_BT_SLOT, 1549 CXBCN_BT_OK, 1550 CXBCN_MAX 1551 }; 1552 1553 enum btc_slot_type { 1554 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1555 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1556 CXSTYPE_NUM, 1557 }; 1558 1559 enum { /* TIME */ 1560 CXT_BT = 0x0, 1561 CXT_WL = 0x1, 1562 CXT_MAX 1563 }; 1564 1565 enum { /* TIME-A2DP */ 1566 CXT_FLCTRL_OFF = 0x0, 1567 CXT_FLCTRL_ON = 0x1, 1568 CXT_FLCTRL_MAX 1569 }; 1570 1571 enum { /* STEP TYPE */ 1572 CXSTEP_NONE = 0x0, 1573 CXSTEP_EVNT = 0x1, 1574 CXSTEP_SLOT = 0x2, 1575 CXSTEP_MAX, 1576 }; 1577 1578 #define BTC_DBG_MAX1 32 1579 struct rtw89_btc_fbtc_gpio_dbg { 1580 u8 fver; /* chip_info::fcxgpiodbg_ver */ 1581 u8 rsvd; 1582 u16 rsvd2; 1583 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1584 u32 pre_state; /* the debug signal is 1 or 0 */ 1585 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1586 } __packed; 1587 1588 struct rtw89_btc_fbtc_mreg_val { 1589 u8 fver; /* chip_info::fcxmreg_ver */ 1590 u8 reg_num; 1591 __le16 rsvd; 1592 __le32 mreg_val[CXMREG_MAX]; 1593 } __packed; 1594 1595 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1596 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1597 .offset = cpu_to_le32(__offset), } 1598 1599 struct rtw89_btc_fbtc_mreg { 1600 __le16 type; 1601 __le16 bytes; 1602 __le32 offset; 1603 } __packed; 1604 1605 struct rtw89_btc_fbtc_slot { 1606 __le16 dur; 1607 __le32 cxtbl; 1608 __le16 cxtype; 1609 } __packed; 1610 1611 struct rtw89_btc_fbtc_slots { 1612 u8 fver; /* chip_info::fcxslots_ver */ 1613 u8 tbl_num; 1614 __le16 rsvd; 1615 __le32 update_map; 1616 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1617 } __packed; 1618 1619 struct rtw89_btc_fbtc_step { 1620 u8 type; 1621 u8 val; 1622 __le16 difft; 1623 } __packed; 1624 1625 struct rtw89_btc_fbtc_steps { 1626 u8 fver; /* chip_info::fcxstep_ver */ 1627 u8 rsvd; 1628 __le16 cnt; 1629 __le16 pos_old; 1630 __le16 pos_new; 1631 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1632 } __packed; 1633 1634 struct rtw89_btc_fbtc_steps_v1 { 1635 u8 fver; 1636 u8 en; 1637 __le16 rsvd; 1638 __le32 cnt; 1639 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1640 } __packed; 1641 1642 struct rtw89_btc_fbtc_cysta { /* statistics for cycles */ 1643 u8 fver; /* chip_info::fcxcysta_ver */ 1644 u8 rsvd; 1645 __le16 cycles; /* total cycle number */ 1646 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1647 __le16 a2dpept; /* a2dp empty cnt */ 1648 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1649 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1650 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1651 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1652 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1653 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1654 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1655 __le16 tmax_a2dpept; /* max a2dp empty time */ 1656 __le16 tavg_lk; /* avg leak-slot time */ 1657 __le16 tmax_lk; /* max leak-slot time */ 1658 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1659 __le32 bcn_cnt[CXBCN_MAX]; 1660 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1661 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1662 __le32 skip_cnt; 1663 __le32 exception; 1664 __le32 except_cnt; 1665 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1666 } __packed; 1667 1668 struct rtw89_btc_fbtc_fdd_try_info { 1669 __le16 cycles[CXT_FLCTRL_MAX]; 1670 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 1671 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 1672 } __packed; 1673 1674 struct rtw89_btc_fbtc_cycle_time_info { 1675 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1676 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1677 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1678 } __packed; 1679 1680 struct rtw89_btc_fbtc_a2dp_trx_stat { 1681 u8 empty_cnt; 1682 u8 retry_cnt; 1683 u8 tx_rate; 1684 u8 tx_cnt; 1685 u8 ack_cnt; 1686 u8 nack_cnt; 1687 u8 rsvd1; 1688 u8 rsvd2; 1689 } __packed; 1690 1691 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 1692 __le16 cnt; /* a2dp empty cnt */ 1693 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 1694 __le16 tavg; /* avg a2dp empty time */ 1695 __le16 tmax; /* max a2dp empty time */ 1696 } __packed; 1697 1698 struct rtw89_btc_fbtc_cycle_leak_info { 1699 __le32 cnt_rximr; /* the rximr occur at leak slot */ 1700 __le16 tavg; /* avg leak-slot time */ 1701 __le16 tmax; /* max leak-slot time */ 1702 } __packed; 1703 1704 struct rtw89_btc_fbtc_cysta_v1 { /* statistics for cycles */ 1705 u8 fver; 1706 u8 rsvd; 1707 __le16 cycles; /* total cycle number */ 1708 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 1709 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 1710 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 1711 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 1712 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 1713 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 1714 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1715 __le32 bcn_cnt[CXBCN_MAX]; 1716 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 1717 __le32 skip_cnt; 1718 __le32 except_cnt; 1719 __le32 except_map; 1720 } __packed; 1721 1722 struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */ 1723 u8 fver; /* chip_info::fcxnullsta_ver */ 1724 u8 rsvd; 1725 __le16 rsvd2; 1726 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1727 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1728 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 1729 } __packed; 1730 1731 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 1732 u8 fver; /* chip_info::fcxnullsta_ver */ 1733 u8 rsvd; 1734 __le16 rsvd2; 1735 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1736 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1737 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 1738 } __packed; 1739 1740 struct rtw89_btc_fbtc_btver { 1741 u8 fver; /* chip_info::fcxbtver_ver */ 1742 u8 rsvd; 1743 __le16 rsvd2; 1744 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 1745 __le32 fw_ver; 1746 __le32 feature; 1747 } __packed; 1748 1749 struct rtw89_btc_fbtc_btscan { 1750 u8 fver; /* chip_info::fcxbtscan_ver */ 1751 u8 rsvd; 1752 __le16 rsvd2; 1753 u8 scan[6]; 1754 } __packed; 1755 1756 struct rtw89_btc_fbtc_btafh { 1757 u8 fver; /* chip_info::fcxbtafh_ver */ 1758 u8 rsvd; 1759 __le16 rsvd2; 1760 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 1761 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 1762 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 1763 } __packed; 1764 1765 struct rtw89_btc_fbtc_btdevinfo { 1766 u8 fver; /* chip_info::fcxbtdevinfo_ver */ 1767 u8 rsvd; 1768 __le16 vendor_id; 1769 __le32 dev_name; /* only 24 bits valid */ 1770 __le32 flush_time; 1771 } __packed; 1772 1773 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 1774 struct rtw89_btc_rf_trx_para { 1775 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1776 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 1777 u8 bt_tx_power; /* decrease Tx power (dB) */ 1778 u8 bt_rx_gain; /* LNA constrain level */ 1779 }; 1780 1781 struct rtw89_btc_dm { 1782 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1783 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 1784 struct rtw89_btc_fbtc_tdma tdma; 1785 struct rtw89_btc_fbtc_tdma tdma_now; 1786 struct rtw89_mac_ax_coex_gnt gnt; 1787 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 1788 struct rtw89_btc_rf_trx_para rf_trx_para; 1789 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 1790 struct rtw89_btc_dm_step dm_step; 1791 struct rtw89_btc_wl_scc_ctrl wl_scc; 1792 union rtw89_btc_dm_error_map error; 1793 u32 cnt_dm[BTC_DCNT_NUM]; 1794 u32 cnt_notify[BTC_NCNT_NUM]; 1795 1796 u32 update_slot_map; 1797 u32 set_ant_path; 1798 1799 u32 wl_only: 1; 1800 u32 wl_fw_cx_offload: 1; 1801 u32 freerun: 1; 1802 u32 wl_ps_ctrl: 2; 1803 u32 wl_mimo_ps: 1; 1804 u32 leak_ap: 1; 1805 u32 noisy_level: 3; 1806 u32 coex_info_map: 8; 1807 u32 bt_only: 1; 1808 u32 wl_btg_rx: 1; 1809 u32 trx_para_level: 8; 1810 u32 wl_stb_chg: 1; 1811 u32 pta_owner: 1; 1812 u32 tdma_instant_excute: 1; 1813 u32 rsvd: 1; 1814 1815 u16 slot_dur[CXST_MAX]; 1816 1817 u8 run_reason; 1818 u8 run_action; 1819 }; 1820 1821 struct rtw89_btc_ctrl { 1822 u32 manual: 1; 1823 u32 igno_bt: 1; 1824 u32 always_freerun: 1; 1825 u32 trace_step: 16; 1826 u32 rsvd: 12; 1827 }; 1828 1829 struct rtw89_btc_dbg { 1830 /* cmd "rb" */ 1831 bool rb_done; 1832 u32 rb_val; 1833 }; 1834 1835 enum rtw89_btc_btf_fw_event { 1836 BTF_EVNT_RPT = 0, 1837 BTF_EVNT_BT_INFO = 1, 1838 BTF_EVNT_BT_SCBD = 2, 1839 BTF_EVNT_BT_REG = 3, 1840 BTF_EVNT_CX_RUNINFO = 4, 1841 BTF_EVNT_BT_PSD = 5, 1842 BTF_EVNT_BUF_OVERFLOW, 1843 BTF_EVNT_C2H_LOOPBACK, 1844 BTF_EVNT_MAX, 1845 }; 1846 1847 enum btf_fw_event_report { 1848 BTC_RPT_TYPE_CTRL = 0x0, 1849 BTC_RPT_TYPE_TDMA, 1850 BTC_RPT_TYPE_SLOT, 1851 BTC_RPT_TYPE_CYSTA, 1852 BTC_RPT_TYPE_STEP, 1853 BTC_RPT_TYPE_NULLSTA, 1854 BTC_RPT_TYPE_MREG, 1855 BTC_RPT_TYPE_GPIO_DBG, 1856 BTC_RPT_TYPE_BT_VER, 1857 BTC_RPT_TYPE_BT_SCAN, 1858 BTC_RPT_TYPE_BT_AFH, 1859 BTC_RPT_TYPE_BT_DEVICE, 1860 BTC_RPT_TYPE_TEST, 1861 BTC_RPT_TYPE_MAX = 31 1862 }; 1863 1864 enum rtw_btc_btf_reg_type { 1865 REG_MAC = 0x0, 1866 REG_BB = 0x1, 1867 REG_RF = 0x2, 1868 REG_BT_RF = 0x3, 1869 REG_BT_MODEM = 0x4, 1870 REG_BT_BLUEWIZE = 0x5, 1871 REG_BT_VENDOR = 0x6, 1872 REG_BT_LE = 0x7, 1873 REG_MAX_TYPE, 1874 }; 1875 1876 struct rtw89_btc_rpt_cmn_info { 1877 u32 rx_cnt; 1878 u32 rx_len; 1879 u32 req_len; /* expected rsp len */ 1880 u8 req_fver; /* expected rsp fver */ 1881 u8 rsp_fver; /* fver from fw */ 1882 u8 valid; 1883 } __packed; 1884 1885 struct rtw89_btc_report_ctrl_state { 1886 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1887 union { 1888 struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw for 52A*/ 1889 struct rtw89_btc_fbtc_rpt_ctrl_v1 finfo_v1; /* info from fw for 52C*/ 1890 }; 1891 }; 1892 1893 struct rtw89_btc_rpt_fbtc_tdma { 1894 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1895 union { 1896 struct rtw89_btc_fbtc_tdma finfo; /* info from fw */ 1897 struct rtw89_btc_fbtc_tdma_v1 finfo_v1; /* info from fw for 52C*/ 1898 }; 1899 }; 1900 1901 struct rtw89_btc_rpt_fbtc_slots { 1902 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1903 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 1904 }; 1905 1906 struct rtw89_btc_rpt_fbtc_cysta { 1907 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1908 union { 1909 struct rtw89_btc_fbtc_cysta finfo; /* info from fw for 52A*/ 1910 struct rtw89_btc_fbtc_cysta_v1 finfo_v1; /* info from fw for 52C*/ 1911 }; 1912 }; 1913 1914 struct rtw89_btc_rpt_fbtc_step { 1915 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1916 union { 1917 struct rtw89_btc_fbtc_steps finfo; /* info from fw */ 1918 struct rtw89_btc_fbtc_steps_v1 finfo_v1; /* info from fw */ 1919 }; 1920 }; 1921 1922 struct rtw89_btc_rpt_fbtc_nullsta { 1923 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1924 union { 1925 struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */ 1926 struct rtw89_btc_fbtc_cynullsta_v1 finfo_v1; /* info from fw */ 1927 }; 1928 }; 1929 1930 struct rtw89_btc_rpt_fbtc_mreg { 1931 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1932 struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 1933 }; 1934 1935 struct rtw89_btc_rpt_fbtc_gpio_dbg { 1936 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1937 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 1938 }; 1939 1940 struct rtw89_btc_rpt_fbtc_btver { 1941 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1942 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 1943 }; 1944 1945 struct rtw89_btc_rpt_fbtc_btscan { 1946 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1947 struct rtw89_btc_fbtc_btscan finfo; /* info from fw */ 1948 }; 1949 1950 struct rtw89_btc_rpt_fbtc_btafh { 1951 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1952 struct rtw89_btc_fbtc_btafh finfo; /* info from fw */ 1953 }; 1954 1955 struct rtw89_btc_rpt_fbtc_btdev { 1956 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1957 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 1958 }; 1959 1960 enum rtw89_btc_btfre_type { 1961 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 1962 BTFRE_UNDEF_TYPE, 1963 BTFRE_EXCEPTION, 1964 BTFRE_MAX, 1965 }; 1966 1967 struct rtw89_btc_btf_fwinfo { 1968 u32 cnt_c2h; 1969 u32 cnt_h2c; 1970 u32 cnt_h2c_fail; 1971 u32 event[BTF_EVNT_MAX]; 1972 1973 u32 err[BTFRE_MAX]; 1974 u32 len_mismch; 1975 u32 fver_mismch; 1976 u32 rpt_en_map; 1977 1978 struct rtw89_btc_report_ctrl_state rpt_ctrl; 1979 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 1980 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 1981 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 1982 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 1983 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 1984 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 1985 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 1986 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 1987 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 1988 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 1989 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 1990 }; 1991 1992 #define RTW89_BTC_POLICY_MAXLEN 512 1993 1994 struct rtw89_btc { 1995 struct rtw89_btc_cx cx; 1996 struct rtw89_btc_dm dm; 1997 struct rtw89_btc_ctrl ctrl; 1998 struct rtw89_btc_module mdinfo; 1999 struct rtw89_btc_btf_fwinfo fwinfo; 2000 struct rtw89_btc_dbg dbg; 2001 2002 struct work_struct eapol_notify_work; 2003 struct work_struct arp_notify_work; 2004 struct work_struct dhcp_notify_work; 2005 struct work_struct icmp_notify_work; 2006 2007 u32 bt_req_len; 2008 2009 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2010 u16 policy_len; 2011 u16 policy_type; 2012 bool bt_req_en; 2013 bool update_policy_force; 2014 bool lps; 2015 }; 2016 2017 enum rtw89_ra_mode { 2018 RTW89_RA_MODE_CCK = BIT(0), 2019 RTW89_RA_MODE_OFDM = BIT(1), 2020 RTW89_RA_MODE_HT = BIT(2), 2021 RTW89_RA_MODE_VHT = BIT(3), 2022 RTW89_RA_MODE_HE = BIT(4), 2023 }; 2024 2025 enum rtw89_ra_report_mode { 2026 RTW89_RA_RPT_MODE_LEGACY, 2027 RTW89_RA_RPT_MODE_HT, 2028 RTW89_RA_RPT_MODE_VHT, 2029 RTW89_RA_RPT_MODE_HE, 2030 }; 2031 2032 enum rtw89_dig_noisy_level { 2033 RTW89_DIG_NOISY_LEVEL0 = -1, 2034 RTW89_DIG_NOISY_LEVEL1 = 0, 2035 RTW89_DIG_NOISY_LEVEL2 = 1, 2036 RTW89_DIG_NOISY_LEVEL3 = 2, 2037 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2038 }; 2039 2040 enum rtw89_gi_ltf { 2041 RTW89_GILTF_LGI_4XHE32 = 0, 2042 RTW89_GILTF_SGI_4XHE08 = 1, 2043 RTW89_GILTF_2XHE16 = 2, 2044 RTW89_GILTF_2XHE08 = 3, 2045 RTW89_GILTF_1XHE16 = 4, 2046 RTW89_GILTF_1XHE08 = 5, 2047 RTW89_GILTF_MAX 2048 }; 2049 2050 enum rtw89_rx_frame_type { 2051 RTW89_RX_TYPE_MGNT = 0, 2052 RTW89_RX_TYPE_CTRL = 1, 2053 RTW89_RX_TYPE_DATA = 2, 2054 RTW89_RX_TYPE_RSVD = 3, 2055 }; 2056 2057 struct rtw89_ra_info { 2058 u8 is_dis_ra:1; 2059 /* Bit0 : CCK 2060 * Bit1 : OFDM 2061 * Bit2 : HT 2062 * Bit3 : VHT 2063 * Bit4 : HE 2064 */ 2065 u8 mode_ctrl:5; 2066 u8 bw_cap:2; 2067 u8 macid; 2068 u8 dcm_cap:1; 2069 u8 er_cap:1; 2070 u8 init_rate_lv:2; 2071 u8 upd_all:1; 2072 u8 en_sgi:1; 2073 u8 ldpc_cap:1; 2074 u8 stbc_cap:1; 2075 u8 ss_num:3; 2076 u8 giltf:3; 2077 u8 upd_bw_nss_mask:1; 2078 u8 upd_mask:1; 2079 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2080 /* BFee CSI */ 2081 u8 band_num; 2082 u8 ra_csi_rate_en:1; 2083 u8 fixed_csi_rate_en:1; 2084 u8 cr_tbl_sel:1; 2085 u8 fix_giltf_en:1; 2086 u8 fix_giltf:3; 2087 u8 rsvd2:1; 2088 u8 csi_mcs_ss_idx; 2089 u8 csi_mode:2; 2090 u8 csi_gi_ltf:3; 2091 u8 csi_bw:3; 2092 }; 2093 2094 #define RTW89_PPDU_MAX_USR 4 2095 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2096 #define RTW89_PPDU_MAC_INFO_SIZE 8 2097 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2098 2099 #define RTW89_MAX_RX_AGG_NUM 64 2100 #define RTW89_MAX_TX_AGG_NUM 128 2101 2102 struct rtw89_ampdu_params { 2103 u16 agg_num; 2104 bool amsdu; 2105 }; 2106 2107 struct rtw89_ra_report { 2108 struct rate_info txrate; 2109 u32 bit_rate; 2110 u16 hw_rate; 2111 bool might_fallback_legacy; 2112 }; 2113 2114 DECLARE_EWMA(rssi, 10, 16); 2115 2116 struct rtw89_ba_cam_entry { 2117 struct list_head list; 2118 u8 tid; 2119 }; 2120 2121 #define RTW89_MAX_ADDR_CAM_NUM 128 2122 #define RTW89_MAX_BSSID_CAM_NUM 20 2123 #define RTW89_MAX_SEC_CAM_NUM 128 2124 #define RTW89_MAX_BA_CAM_NUM 8 2125 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2126 2127 struct rtw89_addr_cam_entry { 2128 u8 addr_cam_idx; 2129 u8 offset; 2130 u8 len; 2131 u8 valid : 1; 2132 u8 addr_mask : 6; 2133 u8 wapi : 1; 2134 u8 mask_sel : 2; 2135 u8 bssid_cam_idx: 6; 2136 2137 u8 sec_ent_mode; 2138 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2139 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2140 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2141 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2142 }; 2143 2144 struct rtw89_bssid_cam_entry { 2145 u8 bssid[ETH_ALEN]; 2146 u8 phy_idx; 2147 u8 bssid_cam_idx; 2148 u8 offset; 2149 u8 len; 2150 u8 valid : 1; 2151 u8 num; 2152 }; 2153 2154 struct rtw89_sec_cam_entry { 2155 u8 sec_cam_idx; 2156 u8 offset; 2157 u8 len; 2158 u8 type : 4; 2159 u8 ext_key : 1; 2160 u8 spp_mode : 1; 2161 /* 256 bits */ 2162 u8 key[32]; 2163 }; 2164 2165 struct rtw89_sta { 2166 u8 mac_id; 2167 bool disassoc; 2168 struct rtw89_dev *rtwdev; 2169 struct rtw89_vif *rtwvif; 2170 struct rtw89_ra_info ra; 2171 struct rtw89_ra_report ra_report; 2172 int max_agg_wait; 2173 u8 prev_rssi; 2174 struct ewma_rssi avg_rssi; 2175 struct ewma_rssi rssi[RF_PATH_MAX]; 2176 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2177 struct ieee80211_rx_status rx_status; 2178 u16 rx_hw_rate; 2179 __le32 htc_template; 2180 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2181 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2182 struct list_head ba_cam_list; 2183 2184 bool use_cfg_mask; 2185 struct cfg80211_bitrate_mask mask; 2186 2187 bool cctl_tx_time; 2188 u32 ampdu_max_time:4; 2189 bool cctl_tx_retry_limit; 2190 u32 data_tx_cnt_lmt:6; 2191 }; 2192 2193 struct rtw89_efuse { 2194 bool valid; 2195 u8 xtal_cap; 2196 u8 addr[ETH_ALEN]; 2197 u8 rfe_type; 2198 char country_code[2]; 2199 }; 2200 2201 struct rtw89_phy_rate_pattern { 2202 u64 ra_mask; 2203 u16 rate; 2204 u8 ra_mode; 2205 bool enable; 2206 }; 2207 2208 #define RTW89_P2P_MAX_NOA_NUM 2 2209 2210 struct rtw89_vif { 2211 struct list_head list; 2212 struct rtw89_dev *rtwdev; 2213 u8 mac_id; 2214 u8 port; 2215 u8 mac_addr[ETH_ALEN]; 2216 u8 bssid[ETH_ALEN]; 2217 u8 phy_idx; 2218 u8 mac_idx; 2219 u8 net_type; 2220 u8 wifi_role; 2221 u8 self_role; 2222 u8 wmm; 2223 u8 bcn_hit_cond; 2224 u8 hit_rule; 2225 u8 last_noa_nr; 2226 bool trigger; 2227 bool lsig_txop; 2228 u8 tgt_ind; 2229 u8 frm_tgt_ind; 2230 bool wowlan_pattern; 2231 bool wowlan_uc; 2232 bool wowlan_magic; 2233 bool is_hesta; 2234 bool last_a_ctrl; 2235 struct work_struct update_beacon_work; 2236 struct rtw89_addr_cam_entry addr_cam; 2237 struct rtw89_bssid_cam_entry bssid_cam; 2238 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 2239 struct rtw89_traffic_stats stats; 2240 struct rtw89_phy_rate_pattern rate_pattern; 2241 struct cfg80211_scan_request *scan_req; 2242 struct ieee80211_scan_ies *scan_ies; 2243 }; 2244 2245 enum rtw89_lv1_rcvy_step { 2246 RTW89_LV1_RCVY_STEP_1, 2247 RTW89_LV1_RCVY_STEP_2, 2248 }; 2249 2250 struct rtw89_hci_ops { 2251 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2252 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2253 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2254 void (*reset)(struct rtw89_dev *rtwdev); 2255 int (*start)(struct rtw89_dev *rtwdev); 2256 void (*stop)(struct rtw89_dev *rtwdev); 2257 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 2258 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 2259 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2260 2261 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2262 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2263 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2264 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2265 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2266 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2267 2268 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2269 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2270 int (*deinit)(struct rtw89_dev *rtwdev); 2271 2272 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2273 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2274 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2275 int (*napi_poll)(struct napi_struct *napi, int budget); 2276 2277 /* Deal with locks inside recovery_start and recovery_complete callbacks 2278 * by hci instance, and handle things which need to consider under SER. 2279 * e.g. turn on/off interrupts except for the one for halt notification. 2280 */ 2281 void (*recovery_start)(struct rtw89_dev *rtwdev); 2282 void (*recovery_complete)(struct rtw89_dev *rtwdev); 2283 }; 2284 2285 struct rtw89_hci_info { 2286 const struct rtw89_hci_ops *ops; 2287 enum rtw89_hci_type type; 2288 u32 rpwm_addr; 2289 u32 cpwm_addr; 2290 bool paused; 2291 }; 2292 2293 struct rtw89_chip_ops { 2294 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 2295 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 2296 void (*bb_reset)(struct rtw89_dev *rtwdev, 2297 enum rtw89_phy_idx phy_idx); 2298 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2299 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2300 u32 addr, u32 mask); 2301 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2302 u32 addr, u32 mask, u32 data); 2303 void (*set_channel)(struct rtw89_dev *rtwdev, 2304 const struct rtw89_chan *chan, 2305 enum rtw89_mac_idx mac_idx, 2306 enum rtw89_phy_idx phy_idx); 2307 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2308 struct rtw89_channel_help_params *p, 2309 const struct rtw89_chan *chan, 2310 enum rtw89_mac_idx mac_idx, 2311 enum rtw89_phy_idx phy_idx); 2312 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2313 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2314 void (*fem_setup)(struct rtw89_dev *rtwdev); 2315 void (*rfk_init)(struct rtw89_dev *rtwdev); 2316 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2317 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 2318 enum rtw89_phy_idx phy_idx); 2319 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2320 void (*rfk_track)(struct rtw89_dev *rtwdev); 2321 void (*power_trim)(struct rtw89_dev *rtwdev); 2322 void (*set_txpwr)(struct rtw89_dev *rtwdev, 2323 const struct rtw89_chan *chan, 2324 enum rtw89_phy_idx phy_idx); 2325 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 2326 enum rtw89_phy_idx phy_idx); 2327 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2328 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2329 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2330 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2331 struct rtw89_rx_phy_ppdu *phy_ppdu, 2332 struct ieee80211_rx_status *status); 2333 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2334 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 2335 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2336 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 2337 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 2338 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 2339 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 2340 struct rtw89_tx_desc_info *desc_info, 2341 void *txdesc); 2342 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 2343 struct rtw89_tx_desc_info *desc_info, 2344 void *txdesc); 2345 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 2346 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 2347 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 2348 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 2349 u32 *tx_en, enum rtw89_sch_tx_sel sel); 2350 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 2351 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 2352 struct rtw89_vif *rtwvif, 2353 struct rtw89_sta *rtwsta); 2354 2355 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2356 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2357 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2358 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2359 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2360 void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev); 2361 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2362 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2363 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 2364 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 2365 }; 2366 2367 enum rtw89_dma_ch { 2368 RTW89_DMA_ACH0 = 0, 2369 RTW89_DMA_ACH1 = 1, 2370 RTW89_DMA_ACH2 = 2, 2371 RTW89_DMA_ACH3 = 3, 2372 RTW89_DMA_ACH4 = 4, 2373 RTW89_DMA_ACH5 = 5, 2374 RTW89_DMA_ACH6 = 6, 2375 RTW89_DMA_ACH7 = 7, 2376 RTW89_DMA_B0MG = 8, 2377 RTW89_DMA_B0HI = 9, 2378 RTW89_DMA_B1MG = 10, 2379 RTW89_DMA_B1HI = 11, 2380 RTW89_DMA_H2C = 12, 2381 RTW89_DMA_CH_NUM = 13 2382 }; 2383 2384 enum rtw89_qta_mode { 2385 RTW89_QTA_SCC, 2386 RTW89_QTA_DLFW, 2387 2388 /* keep last */ 2389 RTW89_QTA_INVALID, 2390 }; 2391 2392 struct rtw89_hfc_ch_cfg { 2393 u16 min; 2394 u16 max; 2395 #define grp_0 0 2396 #define grp_1 1 2397 #define grp_num 2 2398 u8 grp; 2399 }; 2400 2401 struct rtw89_hfc_ch_info { 2402 u16 aval; 2403 u16 used; 2404 }; 2405 2406 struct rtw89_hfc_pub_cfg { 2407 u16 grp0; 2408 u16 grp1; 2409 u16 pub_max; 2410 u16 wp_thrd; 2411 }; 2412 2413 struct rtw89_hfc_pub_info { 2414 u16 g0_used; 2415 u16 g1_used; 2416 u16 g0_aval; 2417 u16 g1_aval; 2418 u16 pub_aval; 2419 u16 wp_aval; 2420 }; 2421 2422 struct rtw89_hfc_prec_cfg { 2423 u16 ch011_prec; 2424 u16 h2c_prec; 2425 u16 wp_ch07_prec; 2426 u16 wp_ch811_prec; 2427 u8 ch011_full_cond; 2428 u8 h2c_full_cond; 2429 u8 wp_ch07_full_cond; 2430 u8 wp_ch811_full_cond; 2431 }; 2432 2433 struct rtw89_hfc_param { 2434 bool en; 2435 bool h2c_en; 2436 u8 mode; 2437 const struct rtw89_hfc_ch_cfg *ch_cfg; 2438 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2439 struct rtw89_hfc_pub_cfg pub_cfg; 2440 struct rtw89_hfc_pub_info pub_info; 2441 struct rtw89_hfc_prec_cfg prec_cfg; 2442 }; 2443 2444 struct rtw89_hfc_param_ini { 2445 const struct rtw89_hfc_ch_cfg *ch_cfg; 2446 const struct rtw89_hfc_pub_cfg *pub_cfg; 2447 const struct rtw89_hfc_prec_cfg *prec_cfg; 2448 u8 mode; 2449 }; 2450 2451 struct rtw89_dle_size { 2452 u16 pge_size; 2453 u16 lnk_pge_num; 2454 u16 unlnk_pge_num; 2455 }; 2456 2457 struct rtw89_wde_quota { 2458 u16 hif; 2459 u16 wcpu; 2460 u16 pkt_in; 2461 u16 cpu_io; 2462 }; 2463 2464 struct rtw89_ple_quota { 2465 u16 cma0_tx; 2466 u16 cma1_tx; 2467 u16 c2h; 2468 u16 h2c; 2469 u16 wcpu; 2470 u16 mpdu_proc; 2471 u16 cma0_dma; 2472 u16 cma1_dma; 2473 u16 bb_rpt; 2474 u16 wd_rel; 2475 u16 cpu_io; 2476 u16 tx_rpt; 2477 }; 2478 2479 struct rtw89_dle_mem { 2480 enum rtw89_qta_mode mode; 2481 const struct rtw89_dle_size *wde_size; 2482 const struct rtw89_dle_size *ple_size; 2483 const struct rtw89_wde_quota *wde_min_qt; 2484 const struct rtw89_wde_quota *wde_max_qt; 2485 const struct rtw89_ple_quota *ple_min_qt; 2486 const struct rtw89_ple_quota *ple_max_qt; 2487 }; 2488 2489 struct rtw89_reg_def { 2490 u32 addr; 2491 u32 mask; 2492 }; 2493 2494 struct rtw89_reg2_def { 2495 u32 addr; 2496 u32 data; 2497 }; 2498 2499 struct rtw89_reg3_def { 2500 u32 addr; 2501 u32 mask; 2502 u32 data; 2503 }; 2504 2505 struct rtw89_reg5_def { 2506 u8 flag; /* recognized by parsers */ 2507 u8 path; 2508 u32 addr; 2509 u32 mask; 2510 u32 data; 2511 }; 2512 2513 struct rtw89_phy_table { 2514 const struct rtw89_reg2_def *regs; 2515 u32 n_regs; 2516 enum rtw89_rf_path rf_path; 2517 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 2518 enum rtw89_rf_path rf_path, void *data); 2519 }; 2520 2521 struct rtw89_txpwr_table { 2522 const void *data; 2523 u32 size; 2524 void (*load)(struct rtw89_dev *rtwdev, 2525 const struct rtw89_txpwr_table *tbl); 2526 }; 2527 2528 struct rtw89_page_regs { 2529 u32 hci_fc_ctrl; 2530 u32 ch_page_ctrl; 2531 u32 ach_page_ctrl; 2532 u32 ach_page_info; 2533 u32 pub_page_info3; 2534 u32 pub_page_ctrl1; 2535 u32 pub_page_ctrl2; 2536 u32 pub_page_info1; 2537 u32 pub_page_info2; 2538 u32 wp_page_ctrl1; 2539 u32 wp_page_ctrl2; 2540 u32 wp_page_info1; 2541 }; 2542 2543 struct rtw89_imr_info { 2544 u32 wdrls_imr_set; 2545 u32 wsec_imr_reg; 2546 u32 wsec_imr_set; 2547 u32 mpdu_tx_imr_set; 2548 u32 mpdu_rx_imr_set; 2549 u32 sta_sch_imr_set; 2550 u32 txpktctl_imr_b0_reg; 2551 u32 txpktctl_imr_b0_clr; 2552 u32 txpktctl_imr_b0_set; 2553 u32 txpktctl_imr_b1_reg; 2554 u32 txpktctl_imr_b1_clr; 2555 u32 txpktctl_imr_b1_set; 2556 u32 wde_imr_clr; 2557 u32 wde_imr_set; 2558 u32 ple_imr_clr; 2559 u32 ple_imr_set; 2560 u32 host_disp_imr_clr; 2561 u32 host_disp_imr_set; 2562 u32 cpu_disp_imr_clr; 2563 u32 cpu_disp_imr_set; 2564 u32 other_disp_imr_clr; 2565 u32 other_disp_imr_set; 2566 u32 bbrpt_com_err_imr_reg; 2567 u32 bbrpt_chinfo_err_imr_reg; 2568 u32 bbrpt_err_imr_set; 2569 u32 bbrpt_dfs_err_imr_reg; 2570 u32 ptcl_imr_clr; 2571 u32 ptcl_imr_set; 2572 u32 cdma_imr_0_reg; 2573 u32 cdma_imr_0_clr; 2574 u32 cdma_imr_0_set; 2575 u32 cdma_imr_1_reg; 2576 u32 cdma_imr_1_clr; 2577 u32 cdma_imr_1_set; 2578 u32 phy_intf_imr_reg; 2579 u32 phy_intf_imr_clr; 2580 u32 phy_intf_imr_set; 2581 u32 rmac_imr_reg; 2582 u32 rmac_imr_clr; 2583 u32 rmac_imr_set; 2584 u32 tmac_imr_reg; 2585 u32 tmac_imr_clr; 2586 u32 tmac_imr_set; 2587 }; 2588 2589 struct rtw89_rrsr_cfgs { 2590 struct rtw89_reg3_def ref_rate; 2591 struct rtw89_reg3_def rsc; 2592 }; 2593 2594 struct rtw89_dig_regs { 2595 u32 seg0_pd_reg; 2596 u32 pd_lower_bound_mask; 2597 u32 pd_spatial_reuse_en; 2598 struct rtw89_reg_def p0_lna_init; 2599 struct rtw89_reg_def p1_lna_init; 2600 struct rtw89_reg_def p0_tia_init; 2601 struct rtw89_reg_def p1_tia_init; 2602 struct rtw89_reg_def p0_rxb_init; 2603 struct rtw89_reg_def p1_rxb_init; 2604 struct rtw89_reg_def p0_p20_pagcugc_en; 2605 struct rtw89_reg_def p0_s20_pagcugc_en; 2606 struct rtw89_reg_def p1_p20_pagcugc_en; 2607 struct rtw89_reg_def p1_s20_pagcugc_en; 2608 }; 2609 2610 struct rtw89_chip_info { 2611 enum rtw89_core_chip_id chip_id; 2612 const struct rtw89_chip_ops *ops; 2613 const char *fw_name; 2614 u32 fifo_size; 2615 u32 dle_scc_rsvd_size; 2616 u16 max_amsdu_limit; 2617 bool dis_2g_40m_ul_ofdma; 2618 u32 rsvd_ple_ofst; 2619 const struct rtw89_hfc_param_ini *hfc_param_ini; 2620 const struct rtw89_dle_mem *dle_mem; 2621 u32 rf_base_addr[2]; 2622 u8 support_chanctx_num; 2623 u8 support_bands; 2624 bool support_bw160; 2625 bool hw_sec_hdr; 2626 u8 rf_path_num; 2627 u8 tx_nss; 2628 u8 rx_nss; 2629 u8 acam_num; 2630 u8 bcam_num; 2631 u8 scam_num; 2632 u8 bacam_num; 2633 u8 bacam_dynamic_num; 2634 bool bacam_v1; 2635 2636 u8 sec_ctrl_efuse_size; 2637 u32 physical_efuse_size; 2638 u32 logical_efuse_size; 2639 u32 limit_efuse_size; 2640 u32 dav_phy_efuse_size; 2641 u32 dav_log_efuse_size; 2642 u32 phycap_addr; 2643 u32 phycap_size; 2644 2645 const struct rtw89_pwr_cfg * const *pwr_on_seq; 2646 const struct rtw89_pwr_cfg * const *pwr_off_seq; 2647 const struct rtw89_phy_table *bb_table; 2648 const struct rtw89_phy_table *bb_gain_table; 2649 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 2650 const struct rtw89_phy_table *nctl_table; 2651 const struct rtw89_txpwr_table *byr_table; 2652 const struct rtw89_phy_dig_gain_table *dig_table; 2653 const struct rtw89_dig_regs *dig_regs; 2654 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 2655 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 2656 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2657 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2658 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 2659 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2660 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2661 const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 2662 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2663 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2664 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2665 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2666 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2667 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2668 const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2669 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2670 2671 u8 txpwr_factor_rf; 2672 u8 txpwr_factor_mac; 2673 2674 u32 para_ver; 2675 u32 wlcx_desired; 2676 u8 btcx_desired; 2677 u8 scbd; 2678 u8 mailbox; 2679 u16 btc_fwinfo_buf; 2680 2681 u8 fcxbtcrpt_ver; 2682 u8 fcxtdma_ver; 2683 u8 fcxslots_ver; 2684 u8 fcxcysta_ver; 2685 u8 fcxstep_ver; 2686 u8 fcxnullsta_ver; 2687 u8 fcxmreg_ver; 2688 u8 fcxgpiodbg_ver; 2689 u8 fcxbtver_ver; 2690 u8 fcxbtscan_ver; 2691 u8 fcxbtafh_ver; 2692 u8 fcxbtdevinfo_ver; 2693 2694 u8 afh_guard_ch; 2695 const u8 *wl_rssi_thres; 2696 const u8 *bt_rssi_thres; 2697 u8 rssi_tol; 2698 2699 u8 mon_reg_num; 2700 const struct rtw89_btc_fbtc_mreg *mon_reg; 2701 u8 rf_para_ulink_num; 2702 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 2703 u8 rf_para_dlink_num; 2704 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 2705 u8 ps_mode_supported; 2706 u8 low_power_hci_modes; 2707 2708 u32 h2c_cctl_func_id; 2709 u32 hci_func_en_addr; 2710 u32 h2c_desc_size; 2711 u32 txwd_body_size; 2712 u32 h2c_ctrl_reg; 2713 const u32 *h2c_regs; 2714 u32 c2h_ctrl_reg; 2715 const u32 *c2h_regs; 2716 const struct rtw89_page_regs *page_regs; 2717 const struct rtw89_reg_def *dcfo_comp; 2718 u8 dcfo_comp_sft; 2719 const struct rtw89_imr_info *imr_info; 2720 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 2721 u32 dma_ch_mask; 2722 }; 2723 2724 union rtw89_bus_info { 2725 const struct rtw89_pci_info *pci; 2726 }; 2727 2728 struct rtw89_driver_info { 2729 const struct rtw89_chip_info *chip; 2730 union rtw89_bus_info bus; 2731 }; 2732 2733 enum rtw89_hcifc_mode { 2734 RTW89_HCIFC_POH = 0, 2735 RTW89_HCIFC_STF = 1, 2736 RTW89_HCIFC_SDIO = 2, 2737 2738 /* keep last */ 2739 RTW89_HCIFC_MODE_INVALID, 2740 }; 2741 2742 struct rtw89_dle_info { 2743 enum rtw89_qta_mode qta_mode; 2744 u16 wde_pg_size; 2745 u16 ple_pg_size; 2746 u16 c0_rx_qta; 2747 u16 c1_rx_qta; 2748 }; 2749 2750 enum rtw89_host_rpr_mode { 2751 RTW89_RPR_MODE_POH = 0, 2752 RTW89_RPR_MODE_STF 2753 }; 2754 2755 struct rtw89_mac_info { 2756 struct rtw89_dle_info dle_info; 2757 struct rtw89_hfc_param hfc_param; 2758 enum rtw89_qta_mode qta_mode; 2759 u8 rpwm_seq_num; 2760 u8 cpwm_seq_num; 2761 }; 2762 2763 enum rtw89_fw_type { 2764 RTW89_FW_NORMAL = 1, 2765 RTW89_FW_WOWLAN = 3, 2766 }; 2767 2768 enum rtw89_fw_feature { 2769 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 2770 RTW89_FW_FEATURE_SCAN_OFFLOAD, 2771 RTW89_FW_FEATURE_TX_WAKE, 2772 RTW89_FW_FEATURE_CRASH_TRIGGER, 2773 RTW89_FW_FEATURE_PACKET_DROP, 2774 RTW89_FW_FEATURE_NO_DEEP_PS, 2775 }; 2776 2777 struct rtw89_fw_suit { 2778 const u8 *data; 2779 u32 size; 2780 u8 major_ver; 2781 u8 minor_ver; 2782 u8 sub_ver; 2783 u8 sub_idex; 2784 u16 build_year; 2785 u16 build_mon; 2786 u16 build_date; 2787 u16 build_hour; 2788 u16 build_min; 2789 u8 cmd_ver; 2790 }; 2791 2792 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 2793 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 2794 #define RTW89_FW_SUIT_VER_CODE(s) \ 2795 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 2796 2797 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 2798 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 2799 (mfw_hdr)->ver.minor, \ 2800 (mfw_hdr)->ver.sub, \ 2801 (mfw_hdr)->ver.idx) 2802 2803 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 2804 RTW89_FW_VER_CODE(GET_FW_HDR_MAJOR_VERSION(fw_hdr), \ 2805 GET_FW_HDR_MINOR_VERSION(fw_hdr), \ 2806 GET_FW_HDR_SUBVERSION(fw_hdr), \ 2807 GET_FW_HDR_SUBINDEX(fw_hdr)) 2808 2809 struct rtw89_fw_info { 2810 const struct firmware *firmware; 2811 struct rtw89_dev *rtwdev; 2812 struct completion completion; 2813 u8 h2c_seq; 2814 u8 rec_seq; 2815 struct rtw89_fw_suit normal; 2816 struct rtw89_fw_suit wowlan; 2817 bool fw_log_enable; 2818 u32 feature_map; 2819 }; 2820 2821 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 2822 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 2823 2824 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 2825 ((_fw)->feature_map |= BIT(_fw_feature)) 2826 2827 struct rtw89_cam_info { 2828 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 2829 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 2830 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 2831 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 2832 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 2833 }; 2834 2835 enum rtw89_sar_sources { 2836 RTW89_SAR_SOURCE_NONE, 2837 RTW89_SAR_SOURCE_COMMON, 2838 2839 RTW89_SAR_SOURCE_NR, 2840 }; 2841 2842 enum rtw89_sar_subband { 2843 RTW89_SAR_2GHZ_SUBBAND, 2844 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 2845 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 2846 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 2847 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 2848 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 2849 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 2850 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 2851 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 2852 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 2853 2854 RTW89_SAR_SUBBAND_NR, 2855 }; 2856 2857 struct rtw89_sar_cfg_common { 2858 bool set[RTW89_SAR_SUBBAND_NR]; 2859 s32 cfg[RTW89_SAR_SUBBAND_NR]; 2860 }; 2861 2862 struct rtw89_sar_info { 2863 /* used to decide how to acces SAR cfg union */ 2864 enum rtw89_sar_sources src; 2865 2866 /* reserved for different knids of SAR cfg struct. 2867 * supposed that a single cfg struct cannot handle various SAR sources. 2868 */ 2869 union { 2870 struct rtw89_sar_cfg_common cfg_common; 2871 }; 2872 }; 2873 2874 struct rtw89_chanctx_cfg { 2875 enum rtw89_sub_entity_idx idx; 2876 }; 2877 2878 enum rtw89_entity_mode { 2879 RTW89_ENTITY_MODE_SCC, 2880 }; 2881 2882 struct rtw89_hal { 2883 u32 rx_fltr; 2884 u8 cv; 2885 u32 sw_amsdu_max_size; 2886 u32 antenna_tx; 2887 u32 antenna_rx; 2888 u8 tx_nss; 2889 u8 rx_nss; 2890 bool tx_path_diversity; 2891 bool support_cckpd; 2892 bool support_igi; 2893 2894 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 2895 struct cfg80211_chan_def chandef[NUM_OF_RTW89_SUB_ENTITY]; 2896 2897 bool entity_active; 2898 enum rtw89_entity_mode entity_mode; 2899 2900 struct rtw89_chan chan[NUM_OF_RTW89_SUB_ENTITY]; 2901 struct rtw89_chan_rcd chan_rcd[NUM_OF_RTW89_SUB_ENTITY]; 2902 }; 2903 2904 #define RTW89_MAX_MAC_ID_NUM 128 2905 #define RTW89_MAX_PKT_OFLD_NUM 255 2906 2907 enum rtw89_flags { 2908 RTW89_FLAG_POWERON, 2909 RTW89_FLAG_FW_RDY, 2910 RTW89_FLAG_RUNNING, 2911 RTW89_FLAG_BFEE_MON, 2912 RTW89_FLAG_BFEE_EN, 2913 RTW89_FLAG_NAPI_RUNNING, 2914 RTW89_FLAG_LEISURE_PS, 2915 RTW89_FLAG_LOW_POWER_MODE, 2916 RTW89_FLAG_INACTIVE_PS, 2917 RTW89_FLAG_CRASH_SIMULATING, 2918 2919 NUM_OF_RTW89_FLAGS, 2920 }; 2921 2922 enum rtw89_pkt_drop_sel { 2923 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 2924 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 2925 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 2926 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 2927 RTW89_PKT_DROP_SEL_MACID_ALL, 2928 RTW89_PKT_DROP_SEL_MG0_ONCE, 2929 RTW89_PKT_DROP_SEL_HIQ_ONCE, 2930 RTW89_PKT_DROP_SEL_HIQ_PORT, 2931 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 2932 RTW89_PKT_DROP_SEL_BAND, 2933 RTW89_PKT_DROP_SEL_BAND_ONCE, 2934 RTW89_PKT_DROP_SEL_REL_MACID, 2935 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 2936 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 2937 }; 2938 2939 struct rtw89_pkt_drop_params { 2940 enum rtw89_pkt_drop_sel sel; 2941 enum rtw89_mac_idx mac_band; 2942 u8 macid; 2943 u8 port; 2944 u8 mbssid; 2945 bool tf_trs; 2946 }; 2947 2948 struct rtw89_pkt_stat { 2949 u16 beacon_nr; 2950 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 2951 }; 2952 2953 DECLARE_EWMA(thermal, 4, 4); 2954 2955 struct rtw89_phy_stat { 2956 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 2957 struct rtw89_pkt_stat cur_pkt_stat; 2958 struct rtw89_pkt_stat last_pkt_stat; 2959 }; 2960 2961 #define RTW89_DACK_PATH_NR 2 2962 #define RTW89_DACK_IDX_NR 2 2963 #define RTW89_DACK_MSBK_NR 16 2964 struct rtw89_dack_info { 2965 bool dack_done; 2966 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 2967 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2968 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2969 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2970 u32 dack_cnt; 2971 bool addck_timeout[RTW89_DACK_PATH_NR]; 2972 bool dadck_timeout[RTW89_DACK_PATH_NR]; 2973 bool msbk_timeout[RTW89_DACK_PATH_NR]; 2974 }; 2975 2976 #define RTW89_IQK_CHS_NR 2 2977 #define RTW89_IQK_PATH_NR 4 2978 2979 struct rtw89_mcc_info { 2980 u8 ch[RTW89_IQK_CHS_NR]; 2981 u8 band[RTW89_IQK_CHS_NR]; 2982 u8 table_idx; 2983 }; 2984 2985 struct rtw89_lck_info { 2986 u8 thermal[RF_PATH_MAX]; 2987 }; 2988 2989 struct rtw89_rx_dck_info { 2990 u8 thermal[RF_PATH_MAX]; 2991 }; 2992 2993 struct rtw89_iqk_info { 2994 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2995 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2996 bool lok_fail[RTW89_IQK_PATH_NR]; 2997 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2998 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2999 u32 iqk_fail_cnt; 3000 bool is_iqk_init; 3001 u32 iqk_channel[RTW89_IQK_CHS_NR]; 3002 u8 iqk_band[RTW89_IQK_PATH_NR]; 3003 u8 iqk_ch[RTW89_IQK_PATH_NR]; 3004 u8 iqk_bw[RTW89_IQK_PATH_NR]; 3005 u8 kcount; 3006 u8 iqk_times; 3007 u8 version; 3008 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 3009 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 3010 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 3011 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 3012 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 3013 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 3014 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 3015 bool is_nbiqk; 3016 bool iqk_fft_en; 3017 bool iqk_xym_en; 3018 bool iqk_sram_en; 3019 bool iqk_cfir_en; 3020 u8 thermal[RTW89_IQK_PATH_NR]; 3021 bool thermal_rek_en; 3022 u32 syn1to2; 3023 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3024 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 3025 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3026 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3027 }; 3028 3029 #define RTW89_DPK_RF_PATH 2 3030 #define RTW89_DPK_AVG_THERMAL_NUM 8 3031 #define RTW89_DPK_BKUP_NUM 2 3032 struct rtw89_dpk_bkup_para { 3033 enum rtw89_band band; 3034 enum rtw89_bandwidth bw; 3035 u8 ch; 3036 bool path_ok; 3037 u8 mdpd_en; 3038 u8 txagc_dpk; 3039 u8 ther_dpk; 3040 u8 gs; 3041 u16 pwsf; 3042 }; 3043 3044 struct rtw89_dpk_info { 3045 bool is_dpk_enable; 3046 bool is_dpk_reload_en; 3047 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3048 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3049 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3050 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3051 u8 cur_idx[RTW89_DPK_RF_PATH]; 3052 u8 cur_k_set; 3053 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3054 }; 3055 3056 struct rtw89_fem_info { 3057 bool elna_2g; 3058 bool elna_5g; 3059 bool epa_2g; 3060 bool epa_5g; 3061 bool epa_6g; 3062 }; 3063 3064 struct rtw89_phy_ch_info { 3065 u8 rssi_min; 3066 u16 rssi_min_macid; 3067 u8 pre_rssi_min; 3068 u8 rssi_max; 3069 u16 rssi_max_macid; 3070 u8 rxsc_160; 3071 u8 rxsc_80; 3072 u8 rxsc_40; 3073 u8 rxsc_20; 3074 u8 rxsc_l; 3075 u8 is_noisy; 3076 }; 3077 3078 struct rtw89_agc_gaincode_set { 3079 u8 lna_idx; 3080 u8 tia_idx; 3081 u8 rxb_idx; 3082 }; 3083 3084 #define IGI_RSSI_TH_NUM 5 3085 #define FA_TH_NUM 4 3086 #define LNA_GAIN_NUM 7 3087 #define TIA_GAIN_NUM 2 3088 struct rtw89_dig_info { 3089 struct rtw89_agc_gaincode_set cur_gaincode; 3090 bool force_gaincode_idx_en; 3091 struct rtw89_agc_gaincode_set force_gaincode; 3092 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 3093 u16 fa_th[FA_TH_NUM]; 3094 u8 igi_rssi; 3095 u8 igi_fa_rssi; 3096 u8 fa_rssi_ofst; 3097 u8 dyn_igi_max; 3098 u8 dyn_igi_min; 3099 bool dyn_pd_th_en; 3100 u8 dyn_pd_th_max; 3101 u8 pd_low_th_ofst; 3102 u8 ib_pbk; 3103 s8 ib_pkpwr; 3104 s8 lna_gain_a[LNA_GAIN_NUM]; 3105 s8 lna_gain_g[LNA_GAIN_NUM]; 3106 s8 *lna_gain; 3107 s8 tia_gain_a[TIA_GAIN_NUM]; 3108 s8 tia_gain_g[TIA_GAIN_NUM]; 3109 s8 *tia_gain; 3110 bool is_linked_pre; 3111 bool bypass_dig; 3112 }; 3113 3114 enum rtw89_multi_cfo_mode { 3115 RTW89_PKT_BASED_AVG_MODE = 0, 3116 RTW89_ENTRY_BASED_AVG_MODE = 1, 3117 RTW89_TP_BASED_AVG_MODE = 2, 3118 }; 3119 3120 enum rtw89_phy_cfo_status { 3121 RTW89_PHY_DCFO_STATE_NORMAL = 0, 3122 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 3123 RTW89_PHY_DCFO_STATE_HOLD = 2, 3124 RTW89_PHY_DCFO_STATE_MAX 3125 }; 3126 3127 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 3128 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 3129 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 3130 }; 3131 3132 struct rtw89_cfo_tracking_info { 3133 u16 cfo_timer_ms; 3134 bool cfo_trig_by_timer_en; 3135 enum rtw89_phy_cfo_status phy_cfo_status; 3136 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 3137 u8 phy_cfo_trk_cnt; 3138 bool is_adjust; 3139 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 3140 bool apply_compensation; 3141 u8 crystal_cap; 3142 u8 crystal_cap_default; 3143 u8 def_x_cap; 3144 s8 x_cap_ofst; 3145 u32 sta_cfo_tolerance; 3146 s32 cfo_tail[CFO_TRACK_MAX_USER]; 3147 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 3148 s32 cfo_avg_pre; 3149 s32 cfo_avg[CFO_TRACK_MAX_USER]; 3150 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 3151 u32 packet_count; 3152 u32 packet_count_pre; 3153 s32 residual_cfo_acc; 3154 u8 phy_cfotrk_state; 3155 u8 phy_cfotrk_cnt; 3156 bool divergence_lock_en; 3157 u8 x_cap_lb; 3158 u8 x_cap_ub; 3159 u8 lock_cnt; 3160 }; 3161 3162 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 3163 #define TSSI_TRIM_CH_GROUP_NUM 8 3164 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 3165 3166 #define TSSI_CCK_CH_GROUP_NUM 6 3167 #define TSSI_MCS_2G_CH_GROUP_NUM 5 3168 #define TSSI_MCS_5G_CH_GROUP_NUM 14 3169 #define TSSI_MCS_6G_CH_GROUP_NUM 32 3170 #define TSSI_MCS_CH_GROUP_NUM \ 3171 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 3172 3173 struct rtw89_tssi_info { 3174 u8 thermal[RF_PATH_MAX]; 3175 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 3176 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 3177 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 3178 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 3179 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 3180 s8 extra_ofst[RF_PATH_MAX]; 3181 bool tssi_tracking_check[RF_PATH_MAX]; 3182 u8 default_txagc_offset[RF_PATH_MAX]; 3183 u32 base_thermal[RF_PATH_MAX]; 3184 }; 3185 3186 struct rtw89_power_trim_info { 3187 bool pg_thermal_trim; 3188 bool pg_pa_bias_trim; 3189 u8 thermal_trim[RF_PATH_MAX]; 3190 u8 pa_bias_trim[RF_PATH_MAX]; 3191 }; 3192 3193 struct rtw89_regulatory { 3194 char alpha2[3]; 3195 u8 txpwr_regd[RTW89_BAND_MAX]; 3196 }; 3197 3198 enum rtw89_ifs_clm_application { 3199 RTW89_IFS_CLM_INIT = 0, 3200 RTW89_IFS_CLM_BACKGROUND = 1, 3201 RTW89_IFS_CLM_ACS = 2, 3202 RTW89_IFS_CLM_DIG = 3, 3203 RTW89_IFS_CLM_TDMA_DIG = 4, 3204 RTW89_IFS_CLM_DBG = 5, 3205 RTW89_IFS_CLM_DBG_MANUAL = 6 3206 }; 3207 3208 enum rtw89_env_racing_lv { 3209 RTW89_RAC_RELEASE = 0, 3210 RTW89_RAC_LV_1 = 1, 3211 RTW89_RAC_LV_2 = 2, 3212 RTW89_RAC_LV_3 = 3, 3213 RTW89_RAC_LV_4 = 4, 3214 RTW89_RAC_MAX_NUM = 5 3215 }; 3216 3217 struct rtw89_ccx_para_info { 3218 enum rtw89_env_racing_lv rac_lv; 3219 u16 mntr_time; 3220 u8 nhm_manual_th_ofst; 3221 u8 nhm_manual_th0; 3222 enum rtw89_ifs_clm_application ifs_clm_app; 3223 u32 ifs_clm_manual_th_times; 3224 u32 ifs_clm_manual_th0; 3225 u8 fahm_manual_th_ofst; 3226 u8 fahm_manual_th0; 3227 u8 fahm_numer_opt; 3228 u8 fahm_denom_opt; 3229 }; 3230 3231 enum rtw89_ccx_edcca_opt_sc_idx { 3232 RTW89_CCX_EDCCA_SEG0_P0 = 0, 3233 RTW89_CCX_EDCCA_SEG0_S1 = 1, 3234 RTW89_CCX_EDCCA_SEG0_S2 = 2, 3235 RTW89_CCX_EDCCA_SEG0_S3 = 3, 3236 RTW89_CCX_EDCCA_SEG1_P0 = 4, 3237 RTW89_CCX_EDCCA_SEG1_S1 = 5, 3238 RTW89_CCX_EDCCA_SEG1_S2 = 6, 3239 RTW89_CCX_EDCCA_SEG1_S3 = 7 3240 }; 3241 3242 enum rtw89_ccx_edcca_opt_bw_idx { 3243 RTW89_CCX_EDCCA_BW20_0 = 0, 3244 RTW89_CCX_EDCCA_BW20_1 = 1, 3245 RTW89_CCX_EDCCA_BW20_2 = 2, 3246 RTW89_CCX_EDCCA_BW20_3 = 3, 3247 RTW89_CCX_EDCCA_BW20_4 = 4, 3248 RTW89_CCX_EDCCA_BW20_5 = 5, 3249 RTW89_CCX_EDCCA_BW20_6 = 6, 3250 RTW89_CCX_EDCCA_BW20_7 = 7 3251 }; 3252 3253 #define RTW89_NHM_TH_NUM 11 3254 #define RTW89_FAHM_TH_NUM 11 3255 #define RTW89_NHM_RPT_NUM 12 3256 #define RTW89_FAHM_RPT_NUM 12 3257 #define RTW89_IFS_CLM_NUM 4 3258 struct rtw89_env_monitor_info { 3259 u32 ccx_trigger_time; 3260 u64 start_time; 3261 u8 ccx_rpt_stamp; 3262 u8 ccx_watchdog_result; 3263 bool ccx_ongoing; 3264 u8 ccx_rac_lv; 3265 bool ccx_manual_ctrl; 3266 u8 ccx_pre_rssi; 3267 u16 clm_mntr_time; 3268 u16 nhm_mntr_time; 3269 u16 ifs_clm_mntr_time; 3270 enum rtw89_ifs_clm_application ifs_clm_app; 3271 u16 fahm_mntr_time; 3272 u16 edcca_clm_mntr_time; 3273 u16 ccx_period; 3274 u8 ccx_unit_idx; 3275 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 3276 u8 nhm_th[RTW89_NHM_TH_NUM]; 3277 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 3278 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 3279 u8 fahm_numer_opt; 3280 u8 fahm_denom_opt; 3281 u8 fahm_th[RTW89_FAHM_TH_NUM]; 3282 u16 clm_result; 3283 u16 nhm_result[RTW89_NHM_RPT_NUM]; 3284 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 3285 u16 nhm_tx_cnt; 3286 u16 nhm_cca_cnt; 3287 u16 nhm_idle_cnt; 3288 u16 ifs_clm_tx; 3289 u16 ifs_clm_edcca_excl_cca; 3290 u16 ifs_clm_ofdmfa; 3291 u16 ifs_clm_ofdmcca_excl_fa; 3292 u16 ifs_clm_cckfa; 3293 u16 ifs_clm_cckcca_excl_fa; 3294 u16 ifs_clm_total_ifs; 3295 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 3296 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 3297 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 3298 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 3299 u16 fahm_denom_result; 3300 u16 edcca_clm_result; 3301 u8 clm_ratio; 3302 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 3303 u8 nhm_tx_ratio; 3304 u8 nhm_cca_ratio; 3305 u8 nhm_idle_ratio; 3306 u8 nhm_ratio; 3307 u16 nhm_result_sum; 3308 u8 nhm_pwr; 3309 u8 ifs_clm_tx_ratio; 3310 u8 ifs_clm_edcca_excl_cca_ratio; 3311 u8 ifs_clm_cck_fa_ratio; 3312 u8 ifs_clm_ofdm_fa_ratio; 3313 u8 ifs_clm_cck_cca_excl_fa_ratio; 3314 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 3315 u16 ifs_clm_cck_fa_permil; 3316 u16 ifs_clm_ofdm_fa_permil; 3317 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 3318 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 3319 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 3320 u16 fahm_result_sum; 3321 u8 fahm_ratio; 3322 u8 fahm_denom_ratio; 3323 u8 fahm_pwr; 3324 u8 edcca_clm_ratio; 3325 }; 3326 3327 enum rtw89_ser_rcvy_step { 3328 RTW89_SER_DRV_STOP_TX, 3329 RTW89_SER_DRV_STOP_RX, 3330 RTW89_SER_DRV_STOP_RUN, 3331 RTW89_SER_HAL_STOP_DMA, 3332 RTW89_NUM_OF_SER_FLAGS 3333 }; 3334 3335 struct rtw89_ser { 3336 u8 state; 3337 u8 alarm_event; 3338 3339 struct work_struct ser_hdl_work; 3340 struct delayed_work ser_alarm_work; 3341 const struct state_ent *st_tbl; 3342 const struct event_ent *ev_tbl; 3343 struct list_head msg_q; 3344 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 3345 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 3346 }; 3347 3348 enum rtw89_mac_ax_ps_mode { 3349 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 3350 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 3351 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 3352 RTW89_MAC_AX_PS_MODE_MAX = 3, 3353 }; 3354 3355 enum rtw89_last_rpwm_mode { 3356 RTW89_LAST_RPWM_PS = 0x0, 3357 RTW89_LAST_RPWM_ACTIVE = 0x6, 3358 }; 3359 3360 struct rtw89_lps_parm { 3361 u8 macid; 3362 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 3363 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 3364 }; 3365 3366 struct rtw89_ppdu_sts_info { 3367 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 3368 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 3369 }; 3370 3371 struct rtw89_early_h2c { 3372 struct list_head list; 3373 u8 *h2c; 3374 u16 h2c_len; 3375 }; 3376 3377 struct rtw89_hw_scan_info { 3378 struct ieee80211_vif *scanning_vif; 3379 struct list_head pkt_list[NUM_NL80211_BANDS]; 3380 u8 op_pri_ch; 3381 u8 op_chan; 3382 u8 op_bw; 3383 u8 op_band; 3384 u32 last_chan_idx; 3385 }; 3386 3387 enum rtw89_phy_bb_gain_band { 3388 RTW89_BB_GAIN_BAND_2G = 0, 3389 RTW89_BB_GAIN_BAND_5G_L = 1, 3390 RTW89_BB_GAIN_BAND_5G_M = 2, 3391 RTW89_BB_GAIN_BAND_5G_H = 3, 3392 RTW89_BB_GAIN_BAND_6G_L = 4, 3393 RTW89_BB_GAIN_BAND_6G_M = 5, 3394 RTW89_BB_GAIN_BAND_6G_H = 6, 3395 RTW89_BB_GAIN_BAND_6G_UH = 7, 3396 3397 RTW89_BB_GAIN_BAND_NR, 3398 }; 3399 3400 enum rtw89_phy_bb_rxsc_num { 3401 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 3402 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 3403 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 3404 }; 3405 3406 struct rtw89_phy_bb_gain_info { 3407 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3408 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 3409 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3410 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3411 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3412 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 3413 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 3414 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3415 [RTW89_BB_RXSC_NUM_40]; 3416 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3417 [RTW89_BB_RXSC_NUM_80]; 3418 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3419 [RTW89_BB_RXSC_NUM_160]; 3420 }; 3421 3422 struct rtw89_phy_efuse_gain { 3423 bool offset_valid; 3424 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 3425 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3426 }; 3427 3428 struct rtw89_dev { 3429 struct ieee80211_hw *hw; 3430 struct device *dev; 3431 const struct ieee80211_ops *ops; 3432 3433 bool dbcc_en; 3434 struct rtw89_hw_scan_info scan_info; 3435 const struct rtw89_chip_info *chip; 3436 const struct rtw89_pci_info *pci_info; 3437 struct rtw89_hal hal; 3438 struct rtw89_mac_info mac; 3439 struct rtw89_fw_info fw; 3440 struct rtw89_hci_info hci; 3441 struct rtw89_efuse efuse; 3442 struct rtw89_traffic_stats stats; 3443 3444 /* ensures exclusive access from mac80211 callbacks */ 3445 struct mutex mutex; 3446 struct list_head rtwvifs_list; 3447 /* used to protect rf read write */ 3448 struct mutex rf_mutex; 3449 struct workqueue_struct *txq_wq; 3450 struct work_struct txq_work; 3451 struct delayed_work txq_reinvoke_work; 3452 /* used to protect ba_list and forbid_ba_list */ 3453 spinlock_t ba_lock; 3454 /* txqs to setup ba session */ 3455 struct list_head ba_list; 3456 /* txqs to forbid ba session */ 3457 struct list_head forbid_ba_list; 3458 struct work_struct ba_work; 3459 /* used to protect rpwm */ 3460 spinlock_t rpwm_lock; 3461 3462 struct rtw89_cam_info cam_info; 3463 3464 struct sk_buff_head c2h_queue; 3465 struct work_struct c2h_work; 3466 struct work_struct ips_work; 3467 3468 struct list_head early_h2c_list; 3469 3470 struct rtw89_ser ser; 3471 3472 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 3473 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 3474 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 3475 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 3476 3477 struct rtw89_phy_stat phystat; 3478 struct rtw89_dack_info dack; 3479 struct rtw89_iqk_info iqk; 3480 struct rtw89_dpk_info dpk; 3481 struct rtw89_mcc_info mcc; 3482 struct rtw89_lck_info lck; 3483 struct rtw89_rx_dck_info rx_dck; 3484 bool is_tssi_mode[RF_PATH_MAX]; 3485 bool is_bt_iqk_timeout; 3486 3487 struct rtw89_fem_info fem; 3488 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 3489 struct rtw89_tssi_info tssi; 3490 struct rtw89_power_trim_info pwr_trim; 3491 3492 struct rtw89_cfo_tracking_info cfo_tracking; 3493 struct rtw89_env_monitor_info env_monitor; 3494 struct rtw89_dig_info dig; 3495 struct rtw89_phy_ch_info ch_info; 3496 struct rtw89_phy_bb_gain_info bb_gain; 3497 struct rtw89_phy_efuse_gain efuse_gain; 3498 3499 struct delayed_work track_work; 3500 struct delayed_work coex_act1_work; 3501 struct delayed_work coex_bt_devinfo_work; 3502 struct delayed_work coex_rfk_chk_work; 3503 struct delayed_work cfo_track_work; 3504 struct delayed_work forbid_ba_work; 3505 struct rtw89_ppdu_sts_info ppdu_sts; 3506 u8 total_sta_assoc; 3507 bool scanning; 3508 3509 const struct rtw89_regulatory *regd; 3510 struct rtw89_sar_info sar; 3511 3512 struct rtw89_btc btc; 3513 enum rtw89_ps_mode ps_mode; 3514 bool lps_enabled; 3515 3516 /* napi structure */ 3517 struct net_device netdev; 3518 struct napi_struct napi; 3519 int napi_budget_countdown; 3520 3521 /* HCI related data, keep last */ 3522 u8 priv[] __aligned(sizeof(void *)); 3523 }; 3524 3525 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 3526 struct rtw89_core_tx_request *tx_req) 3527 { 3528 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 3529 } 3530 3531 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 3532 { 3533 rtwdev->hci.ops->reset(rtwdev); 3534 } 3535 3536 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 3537 { 3538 return rtwdev->hci.ops->start(rtwdev); 3539 } 3540 3541 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 3542 { 3543 rtwdev->hci.ops->stop(rtwdev); 3544 } 3545 3546 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 3547 { 3548 return rtwdev->hci.ops->deinit(rtwdev); 3549 } 3550 3551 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 3552 { 3553 rtwdev->hci.ops->pause(rtwdev, pause); 3554 } 3555 3556 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 3557 { 3558 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 3559 } 3560 3561 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 3562 { 3563 rtwdev->hci.ops->recalc_int_mit(rtwdev); 3564 } 3565 3566 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 3567 { 3568 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 3569 } 3570 3571 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 3572 { 3573 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 3574 } 3575 3576 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 3577 bool drop) 3578 { 3579 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3580 return; 3581 3582 if (rtwdev->hci.ops->flush_queues) 3583 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 3584 } 3585 3586 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 3587 { 3588 if (rtwdev->hci.ops->recovery_start) 3589 rtwdev->hci.ops->recovery_start(rtwdev); 3590 } 3591 3592 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 3593 { 3594 if (rtwdev->hci.ops->recovery_complete) 3595 rtwdev->hci.ops->recovery_complete(rtwdev); 3596 } 3597 3598 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 3599 { 3600 return rtwdev->hci.ops->read8(rtwdev, addr); 3601 } 3602 3603 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 3604 { 3605 return rtwdev->hci.ops->read16(rtwdev, addr); 3606 } 3607 3608 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 3609 { 3610 return rtwdev->hci.ops->read32(rtwdev, addr); 3611 } 3612 3613 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 3614 { 3615 rtwdev->hci.ops->write8(rtwdev, addr, data); 3616 } 3617 3618 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 3619 { 3620 rtwdev->hci.ops->write16(rtwdev, addr, data); 3621 } 3622 3623 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 3624 { 3625 rtwdev->hci.ops->write32(rtwdev, addr, data); 3626 } 3627 3628 static inline void 3629 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3630 { 3631 u8 val; 3632 3633 val = rtw89_read8(rtwdev, addr); 3634 rtw89_write8(rtwdev, addr, val | bit); 3635 } 3636 3637 static inline void 3638 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3639 { 3640 u16 val; 3641 3642 val = rtw89_read16(rtwdev, addr); 3643 rtw89_write16(rtwdev, addr, val | bit); 3644 } 3645 3646 static inline void 3647 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3648 { 3649 u32 val; 3650 3651 val = rtw89_read32(rtwdev, addr); 3652 rtw89_write32(rtwdev, addr, val | bit); 3653 } 3654 3655 static inline void 3656 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3657 { 3658 u8 val; 3659 3660 val = rtw89_read8(rtwdev, addr); 3661 rtw89_write8(rtwdev, addr, val & ~bit); 3662 } 3663 3664 static inline void 3665 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3666 { 3667 u16 val; 3668 3669 val = rtw89_read16(rtwdev, addr); 3670 rtw89_write16(rtwdev, addr, val & ~bit); 3671 } 3672 3673 static inline void 3674 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3675 { 3676 u32 val; 3677 3678 val = rtw89_read32(rtwdev, addr); 3679 rtw89_write32(rtwdev, addr, val & ~bit); 3680 } 3681 3682 static inline u32 3683 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3684 { 3685 u32 shift = __ffs(mask); 3686 u32 orig; 3687 u32 ret; 3688 3689 orig = rtw89_read32(rtwdev, addr); 3690 ret = (orig & mask) >> shift; 3691 3692 return ret; 3693 } 3694 3695 static inline u16 3696 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3697 { 3698 u32 shift = __ffs(mask); 3699 u32 orig; 3700 u32 ret; 3701 3702 orig = rtw89_read16(rtwdev, addr); 3703 ret = (orig & mask) >> shift; 3704 3705 return ret; 3706 } 3707 3708 static inline u8 3709 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3710 { 3711 u32 shift = __ffs(mask); 3712 u32 orig; 3713 u32 ret; 3714 3715 orig = rtw89_read8(rtwdev, addr); 3716 ret = (orig & mask) >> shift; 3717 3718 return ret; 3719 } 3720 3721 static inline void 3722 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 3723 { 3724 u32 shift = __ffs(mask); 3725 u32 orig; 3726 u32 set; 3727 3728 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 3729 3730 orig = rtw89_read32(rtwdev, addr); 3731 set = (orig & ~mask) | ((data << shift) & mask); 3732 rtw89_write32(rtwdev, addr, set); 3733 } 3734 3735 static inline void 3736 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 3737 { 3738 u32 shift; 3739 u16 orig, set; 3740 3741 mask &= 0xffff; 3742 shift = __ffs(mask); 3743 3744 orig = rtw89_read16(rtwdev, addr); 3745 set = (orig & ~mask) | ((data << shift) & mask); 3746 rtw89_write16(rtwdev, addr, set); 3747 } 3748 3749 static inline void 3750 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 3751 { 3752 u32 shift; 3753 u8 orig, set; 3754 3755 mask &= 0xff; 3756 shift = __ffs(mask); 3757 3758 orig = rtw89_read8(rtwdev, addr); 3759 set = (orig & ~mask) | ((data << shift) & mask); 3760 rtw89_write8(rtwdev, addr, set); 3761 } 3762 3763 static inline u32 3764 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3765 u32 addr, u32 mask) 3766 { 3767 u32 val; 3768 3769 mutex_lock(&rtwdev->rf_mutex); 3770 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 3771 mutex_unlock(&rtwdev->rf_mutex); 3772 3773 return val; 3774 } 3775 3776 static inline void 3777 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3778 u32 addr, u32 mask, u32 data) 3779 { 3780 mutex_lock(&rtwdev->rf_mutex); 3781 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 3782 mutex_unlock(&rtwdev->rf_mutex); 3783 } 3784 3785 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 3786 { 3787 void *p = rtwtxq; 3788 3789 return container_of(p, struct ieee80211_txq, drv_priv); 3790 } 3791 3792 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 3793 struct ieee80211_txq *txq) 3794 { 3795 struct rtw89_txq *rtwtxq; 3796 3797 if (!txq) 3798 return; 3799 3800 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3801 INIT_LIST_HEAD(&rtwtxq->list); 3802 } 3803 3804 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 3805 { 3806 void *p = rtwvif; 3807 3808 return container_of(p, struct ieee80211_vif, drv_priv); 3809 } 3810 3811 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 3812 { 3813 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 3814 } 3815 3816 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 3817 { 3818 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 3819 } 3820 3821 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 3822 { 3823 void *p = rtwsta; 3824 3825 return container_of(p, struct ieee80211_sta, drv_priv); 3826 } 3827 3828 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 3829 { 3830 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 3831 } 3832 3833 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 3834 { 3835 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 3836 } 3837 3838 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 3839 { 3840 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 3841 return RATE_INFO_BW_160; 3842 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 3843 return RATE_INFO_BW_80; 3844 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 3845 return RATE_INFO_BW_40; 3846 else 3847 return RATE_INFO_BW_20; 3848 } 3849 3850 static inline 3851 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 3852 { 3853 switch (hw_band) { 3854 default: 3855 case RTW89_BAND_2G: 3856 return NL80211_BAND_2GHZ; 3857 case RTW89_BAND_5G: 3858 return NL80211_BAND_5GHZ; 3859 case RTW89_BAND_6G: 3860 return NL80211_BAND_6GHZ; 3861 } 3862 } 3863 3864 static inline 3865 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 3866 { 3867 switch (nl_band) { 3868 default: 3869 case NL80211_BAND_2GHZ: 3870 return RTW89_BAND_2G; 3871 case NL80211_BAND_5GHZ: 3872 return RTW89_BAND_5G; 3873 case NL80211_BAND_6GHZ: 3874 return RTW89_BAND_6G; 3875 } 3876 } 3877 3878 static inline 3879 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 3880 { 3881 switch (width) { 3882 default: 3883 WARN(1, "Not support bandwidth %d\n", width); 3884 fallthrough; 3885 case NL80211_CHAN_WIDTH_20_NOHT: 3886 case NL80211_CHAN_WIDTH_20: 3887 return RTW89_CHANNEL_WIDTH_20; 3888 case NL80211_CHAN_WIDTH_40: 3889 return RTW89_CHANNEL_WIDTH_40; 3890 case NL80211_CHAN_WIDTH_80: 3891 return RTW89_CHANNEL_WIDTH_80; 3892 case NL80211_CHAN_WIDTH_160: 3893 return RTW89_CHANNEL_WIDTH_160; 3894 } 3895 } 3896 3897 static inline 3898 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 3899 struct rtw89_sta *rtwsta) 3900 { 3901 if (rtwsta) { 3902 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 3903 3904 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 3905 return &rtwsta->addr_cam; 3906 } 3907 return &rtwvif->addr_cam; 3908 } 3909 3910 static inline 3911 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 3912 struct rtw89_sta *rtwsta) 3913 { 3914 if (rtwsta) { 3915 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 3916 3917 if (sta->tdls) 3918 return &rtwsta->bssid_cam; 3919 } 3920 return &rtwvif->bssid_cam; 3921 } 3922 3923 static inline 3924 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 3925 struct rtw89_channel_help_params *p, 3926 const struct rtw89_chan *chan, 3927 enum rtw89_mac_idx mac_idx, 3928 enum rtw89_phy_idx phy_idx) 3929 { 3930 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 3931 mac_idx, phy_idx); 3932 } 3933 3934 static inline 3935 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 3936 struct rtw89_channel_help_params *p, 3937 const struct rtw89_chan *chan, 3938 enum rtw89_mac_idx mac_idx, 3939 enum rtw89_phy_idx phy_idx) 3940 { 3941 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 3942 mac_idx, phy_idx); 3943 } 3944 3945 static inline 3946 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 3947 enum rtw89_sub_entity_idx idx) 3948 { 3949 struct rtw89_hal *hal = &rtwdev->hal; 3950 3951 return &hal->chandef[idx]; 3952 } 3953 3954 static inline 3955 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 3956 enum rtw89_sub_entity_idx idx) 3957 { 3958 struct rtw89_hal *hal = &rtwdev->hal; 3959 3960 return &hal->chan[idx]; 3961 } 3962 3963 static inline 3964 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 3965 enum rtw89_sub_entity_idx idx) 3966 { 3967 struct rtw89_hal *hal = &rtwdev->hal; 3968 3969 return &hal->chan_rcd[idx]; 3970 } 3971 3972 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 3973 { 3974 const struct rtw89_chip_info *chip = rtwdev->chip; 3975 3976 if (chip->ops->fem_setup) 3977 chip->ops->fem_setup(rtwdev); 3978 } 3979 3980 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 3981 { 3982 const struct rtw89_chip_info *chip = rtwdev->chip; 3983 3984 if (chip->ops->bb_sethw) 3985 chip->ops->bb_sethw(rtwdev); 3986 } 3987 3988 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 3989 { 3990 const struct rtw89_chip_info *chip = rtwdev->chip; 3991 3992 if (chip->ops->rfk_init) 3993 chip->ops->rfk_init(rtwdev); 3994 } 3995 3996 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 3997 { 3998 const struct rtw89_chip_info *chip = rtwdev->chip; 3999 4000 if (chip->ops->rfk_channel) 4001 chip->ops->rfk_channel(rtwdev); 4002 } 4003 4004 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 4005 enum rtw89_phy_idx phy_idx) 4006 { 4007 const struct rtw89_chip_info *chip = rtwdev->chip; 4008 4009 if (chip->ops->rfk_band_changed) 4010 chip->ops->rfk_band_changed(rtwdev, phy_idx); 4011 } 4012 4013 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 4014 { 4015 const struct rtw89_chip_info *chip = rtwdev->chip; 4016 4017 if (chip->ops->rfk_scan) 4018 chip->ops->rfk_scan(rtwdev, start); 4019 } 4020 4021 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 4022 { 4023 const struct rtw89_chip_info *chip = rtwdev->chip; 4024 4025 if (chip->ops->rfk_track) 4026 chip->ops->rfk_track(rtwdev); 4027 } 4028 4029 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 4030 { 4031 const struct rtw89_chip_info *chip = rtwdev->chip; 4032 4033 if (chip->ops->set_txpwr_ctrl) 4034 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 4035 } 4036 4037 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 4038 { 4039 const struct rtw89_chip_info *chip = rtwdev->chip; 4040 4041 if (chip->ops->power_trim) 4042 chip->ops->power_trim(rtwdev); 4043 } 4044 4045 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 4046 enum rtw89_phy_idx phy_idx) 4047 { 4048 const struct rtw89_chip_info *chip = rtwdev->chip; 4049 4050 if (chip->ops->init_txpwr_unit) 4051 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 4052 } 4053 4054 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 4055 enum rtw89_rf_path rf_path) 4056 { 4057 const struct rtw89_chip_info *chip = rtwdev->chip; 4058 4059 if (!chip->ops->get_thermal) 4060 return 0x10; 4061 4062 return chip->ops->get_thermal(rtwdev, rf_path); 4063 } 4064 4065 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 4066 struct rtw89_rx_phy_ppdu *phy_ppdu, 4067 struct ieee80211_rx_status *status) 4068 { 4069 const struct rtw89_chip_info *chip = rtwdev->chip; 4070 4071 if (chip->ops->query_ppdu) 4072 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 4073 } 4074 4075 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 4076 bool bt_en) 4077 { 4078 const struct rtw89_chip_info *chip = rtwdev->chip; 4079 4080 if (chip->ops->bb_ctrl_btc_preagc) 4081 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 4082 } 4083 4084 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 4085 { 4086 const struct rtw89_chip_info *chip = rtwdev->chip; 4087 4088 if (chip->ops->cfg_txrx_path) 4089 chip->ops->cfg_txrx_path(rtwdev); 4090 } 4091 4092 static inline 4093 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 4094 struct ieee80211_vif *vif) 4095 { 4096 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4097 const struct rtw89_chip_info *chip = rtwdev->chip; 4098 4099 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4100 return; 4101 4102 if (chip->ops->set_txpwr_ul_tb_offset) 4103 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 4104 } 4105 4106 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 4107 const struct rtw89_txpwr_table *tbl) 4108 { 4109 tbl->load(rtwdev, tbl); 4110 } 4111 4112 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 4113 { 4114 return rtwdev->regd->txpwr_regd[band]; 4115 } 4116 4117 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 4118 { 4119 const struct rtw89_chip_info *chip = rtwdev->chip; 4120 4121 if (chip->ops->ctrl_btg) 4122 chip->ops->ctrl_btg(rtwdev, btg); 4123 } 4124 4125 static inline 4126 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 4127 struct rtw89_tx_desc_info *desc_info, 4128 void *txdesc) 4129 { 4130 const struct rtw89_chip_info *chip = rtwdev->chip; 4131 4132 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 4133 } 4134 4135 static inline 4136 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 4137 struct rtw89_tx_desc_info *desc_info, 4138 void *txdesc) 4139 { 4140 const struct rtw89_chip_info *chip = rtwdev->chip; 4141 4142 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 4143 } 4144 4145 static inline 4146 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4147 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4148 { 4149 const struct rtw89_chip_info *chip = rtwdev->chip; 4150 4151 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 4152 } 4153 4154 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4155 { 4156 const struct rtw89_chip_info *chip = rtwdev->chip; 4157 4158 chip->ops->cfg_ctrl_path(rtwdev, wl); 4159 } 4160 4161 static inline 4162 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 4163 u32 *tx_en, enum rtw89_sch_tx_sel sel) 4164 { 4165 const struct rtw89_chip_info *chip = rtwdev->chip; 4166 4167 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 4168 } 4169 4170 static inline 4171 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 4172 { 4173 const struct rtw89_chip_info *chip = rtwdev->chip; 4174 4175 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 4176 } 4177 4178 static inline 4179 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 4180 struct rtw89_vif *rtwvif, 4181 struct rtw89_sta *rtwsta) 4182 { 4183 const struct rtw89_chip_info *chip = rtwdev->chip; 4184 4185 if (!chip->ops->h2c_dctl_sec_cam) 4186 return 0; 4187 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 4188 } 4189 4190 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 4191 { 4192 __le16 fc = hdr->frame_control; 4193 4194 if (ieee80211_has_tods(fc)) 4195 return hdr->addr1; 4196 else if (ieee80211_has_fromds(fc)) 4197 return hdr->addr2; 4198 else 4199 return hdr->addr3; 4200 } 4201 4202 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 4203 { 4204 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4205 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 4206 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 4207 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4208 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 4209 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 4210 return true; 4211 return false; 4212 } 4213 4214 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 4215 enum rtw89_fw_type type) 4216 { 4217 struct rtw89_fw_info *fw_info = &rtwdev->fw; 4218 4219 if (type == RTW89_FW_WOWLAN) 4220 return &fw_info->wowlan; 4221 return &fw_info->normal; 4222 } 4223 4224 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4225 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 4226 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 4227 struct sk_buff *skb, bool fwdl); 4228 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 4229 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 4230 struct rtw89_tx_desc_info *desc_info, 4231 void *txdesc); 4232 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 4233 struct rtw89_tx_desc_info *desc_info, 4234 void *txdesc); 4235 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 4236 struct rtw89_tx_desc_info *desc_info, 4237 void *txdesc); 4238 void rtw89_core_rx(struct rtw89_dev *rtwdev, 4239 struct rtw89_rx_desc_info *desc_info, 4240 struct sk_buff *skb); 4241 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 4242 struct rtw89_rx_desc_info *desc_info, 4243 u8 *data, u32 data_offset); 4244 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 4245 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 4246 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 4247 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 4248 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 4249 struct ieee80211_vif *vif, 4250 struct ieee80211_sta *sta); 4251 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 4252 struct ieee80211_vif *vif, 4253 struct ieee80211_sta *sta); 4254 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 4255 struct ieee80211_vif *vif, 4256 struct ieee80211_sta *sta); 4257 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 4258 struct ieee80211_vif *vif, 4259 struct ieee80211_sta *sta); 4260 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 4261 struct ieee80211_vif *vif, 4262 struct ieee80211_sta *sta); 4263 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4264 struct ieee80211_sta *sta, 4265 struct cfg80211_tid_config *tid_config); 4266 int rtw89_core_init(struct rtw89_dev *rtwdev); 4267 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 4268 int rtw89_core_register(struct rtw89_dev *rtwdev); 4269 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 4270 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4271 u32 bus_data_size, 4272 const struct rtw89_chip_info *chip); 4273 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 4274 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 4275 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 4276 void rtw89_set_channel(struct rtw89_dev *rtwdev); 4277 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 4278 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 4279 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 4280 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 4281 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4282 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 4283 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4284 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 4285 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 4286 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 4287 int rtw89_regd_init(struct rtw89_dev *rtwdev, 4288 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 4289 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 4290 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 4291 struct rtw89_traffic_stats *stats); 4292 int rtw89_core_start(struct rtw89_dev *rtwdev); 4293 void rtw89_core_stop(struct rtw89_dev *rtwdev); 4294 void rtw89_core_update_beacon_work(struct work_struct *work); 4295 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4296 const u8 *mac_addr, bool hw_scan); 4297 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4298 struct ieee80211_vif *vif, bool hw_scan); 4299 4300 #endif 4301