1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_MAC_H__ 6 #define __RTW89_MAC_H__ 7 8 #include "core.h" 9 #include "reg.h" 10 11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000 12 #define ADDR_CAM_ENT_SIZE 0x40 13 #define BSSID_CAM_ENT_SIZE 0x08 14 #define HFC_PAGE_UNIT 64 15 #define RPWM_TRY_CNT 3 16 17 enum rtw89_mac_hwmod_sel { 18 RTW89_DMAC_SEL = 0, 19 RTW89_CMAC_SEL = 1, 20 21 RTW89_MAC_INVALID, 22 }; 23 24 enum rtw89_mac_fwd_target { 25 RTW89_FWD_DONT_CARE = 0, 26 RTW89_FWD_TO_HOST = 1, 27 RTW89_FWD_TO_WLAN_CPU = 2 28 }; 29 30 enum rtw89_mac_wd_dma_intvl { 31 RTW89_MAC_WD_DMA_INTVL_0S, 32 RTW89_MAC_WD_DMA_INTVL_256NS, 33 RTW89_MAC_WD_DMA_INTVL_512NS, 34 RTW89_MAC_WD_DMA_INTVL_768NS, 35 RTW89_MAC_WD_DMA_INTVL_1US, 36 RTW89_MAC_WD_DMA_INTVL_1_5US, 37 RTW89_MAC_WD_DMA_INTVL_2US, 38 RTW89_MAC_WD_DMA_INTVL_4US, 39 RTW89_MAC_WD_DMA_INTVL_8US, 40 RTW89_MAC_WD_DMA_INTVL_16US, 41 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE 42 }; 43 44 enum rtw89_mac_multi_tag_num { 45 RTW89_MAC_TAG_NUM_1, 46 RTW89_MAC_TAG_NUM_2, 47 RTW89_MAC_TAG_NUM_3, 48 RTW89_MAC_TAG_NUM_4, 49 RTW89_MAC_TAG_NUM_5, 50 RTW89_MAC_TAG_NUM_6, 51 RTW89_MAC_TAG_NUM_7, 52 RTW89_MAC_TAG_NUM_8, 53 RTW89_MAC_TAG_NUM_DEF = 0xFE 54 }; 55 56 enum rtw89_mac_lbc_tmr { 57 RTW89_MAC_LBC_TMR_8US = 0, 58 RTW89_MAC_LBC_TMR_16US, 59 RTW89_MAC_LBC_TMR_32US, 60 RTW89_MAC_LBC_TMR_64US, 61 RTW89_MAC_LBC_TMR_128US, 62 RTW89_MAC_LBC_TMR_256US, 63 RTW89_MAC_LBC_TMR_512US, 64 RTW89_MAC_LBC_TMR_1MS, 65 RTW89_MAC_LBC_TMR_2MS, 66 RTW89_MAC_LBC_TMR_4MS, 67 RTW89_MAC_LBC_TMR_8MS, 68 RTW89_MAC_LBC_TMR_DEF = 0xFE 69 }; 70 71 enum rtw89_mac_cpuio_op_cmd_type { 72 CPUIO_OP_CMD_GET_1ST_PID = 0, 73 CPUIO_OP_CMD_GET_NEXT_PID = 1, 74 CPUIO_OP_CMD_ENQ_TO_TAIL = 4, 75 CPUIO_OP_CMD_ENQ_TO_HEAD = 5, 76 CPUIO_OP_CMD_DEQ = 8, 77 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, 78 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 79 }; 80 81 enum rtw89_mac_wde_dle_port_id { 82 WDE_DLE_PORT_ID_DISPATCH = 0, 83 WDE_DLE_PORT_ID_PKTIN = 1, 84 WDE_DLE_PORT_ID_CMAC0 = 3, 85 WDE_DLE_PORT_ID_CMAC1 = 4, 86 WDE_DLE_PORT_ID_CPU_IO = 6, 87 WDE_DLE_PORT_ID_WDRLS = 7, 88 WDE_DLE_PORT_ID_END = 8 89 }; 90 91 enum rtw89_mac_wde_dle_queid_wdrls { 92 WDE_DLE_QUEID_TXOK = 0, 93 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, 94 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, 95 WDE_DLE_QUEID_DROP_MACID_DROP = 3, 96 WDE_DLE_QUEID_NO_REPORT = 4 97 }; 98 99 enum rtw89_mac_ple_dle_port_id { 100 PLE_DLE_PORT_ID_DISPATCH = 0, 101 PLE_DLE_PORT_ID_MPDU = 1, 102 PLE_DLE_PORT_ID_SEC = 2, 103 PLE_DLE_PORT_ID_CMAC0 = 3, 104 PLE_DLE_PORT_ID_CMAC1 = 4, 105 PLE_DLE_PORT_ID_WDRLS = 5, 106 PLE_DLE_PORT_ID_CPU_IO = 6, 107 PLE_DLE_PORT_ID_PLRLS = 7, 108 PLE_DLE_PORT_ID_END = 8 109 }; 110 111 enum rtw89_mac_ple_dle_queid_plrls { 112 PLE_DLE_QUEID_NO_REPORT = 0x0 113 }; 114 115 enum rtw89_machdr_frame_type { 116 RTW89_MGNT = 0, 117 RTW89_CTRL = 1, 118 RTW89_DATA = 2, 119 }; 120 121 enum rtw89_mac_dle_dfi_type { 122 DLE_DFI_TYPE_FREEPG = 0, 123 DLE_DFI_TYPE_QUOTA = 1, 124 DLE_DFI_TYPE_PAGELLT = 2, 125 DLE_DFI_TYPE_PKTINFO = 3, 126 DLE_DFI_TYPE_PREPKTLLT = 4, 127 DLE_DFI_TYPE_NXTPKTLLT = 5, 128 DLE_DFI_TYPE_QLNKTBL = 6, 129 DLE_DFI_TYPE_QEMPTY = 7, 130 }; 131 132 enum rtw89_mac_dle_wde_quota_id { 133 WDE_QTAID_HOST_IF = 0, 134 WDE_QTAID_WLAN_CPU = 1, 135 WDE_QTAID_DATA_CPU = 2, 136 WDE_QTAID_PKTIN = 3, 137 WDE_QTAID_CPUIO = 4, 138 }; 139 140 enum rtw89_mac_dle_ple_quota_id { 141 PLE_QTAID_B0_TXPL = 0, 142 PLE_QTAID_B1_TXPL = 1, 143 PLE_QTAID_C2H = 2, 144 PLE_QTAID_H2C = 3, 145 PLE_QTAID_WLAN_CPU = 4, 146 PLE_QTAID_MPDU = 5, 147 PLE_QTAID_CMAC0_RX = 6, 148 PLE_QTAID_CMAC1_RX = 7, 149 PLE_QTAID_CMAC1_BBRPT = 8, 150 PLE_QTAID_WDRLS = 9, 151 PLE_QTAID_CPUIO = 10, 152 }; 153 154 enum rtw89_mac_dle_ctrl_type { 155 DLE_CTRL_TYPE_WDE = 0, 156 DLE_CTRL_TYPE_PLE = 1, 157 DLE_CTRL_TYPE_NUM = 2, 158 }; 159 160 enum rtw89_mac_ax_l0_to_l1_event { 161 MAC_AX_L0_TO_L1_CHIF_IDLE = 0, 162 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, 163 MAC_AX_L0_TO_L1_RLS_PKID = 2, 164 MAC_AX_L0_TO_L1_PTCL_IDLE = 3, 165 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, 166 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, 167 MAC_AX_L0_TO_L1_PCIE_STUCK = 6, 168 MAC_AX_L0_TO_L1_EVENT_MAX = 15, 169 }; 170 171 #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32) 172 173 enum rtw89_mac_dbg_port_sel { 174 /* CMAC 0 related */ 175 RTW89_DBG_PORT_SEL_PTCL_C0 = 0, 176 RTW89_DBG_PORT_SEL_SCH_C0, 177 RTW89_DBG_PORT_SEL_TMAC_C0, 178 RTW89_DBG_PORT_SEL_RMAC_C0, 179 RTW89_DBG_PORT_SEL_RMACST_C0, 180 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, 181 RTW89_DBG_PORT_SEL_TRXPTCL_C0, 182 RTW89_DBG_PORT_SEL_TX_INFOL_C0, 183 RTW89_DBG_PORT_SEL_TX_INFOH_C0, 184 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, 185 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, 186 /* CMAC 1 related */ 187 RTW89_DBG_PORT_SEL_PTCL_C1, 188 RTW89_DBG_PORT_SEL_SCH_C1, 189 RTW89_DBG_PORT_SEL_TMAC_C1, 190 RTW89_DBG_PORT_SEL_RMAC_C1, 191 RTW89_DBG_PORT_SEL_RMACST_C1, 192 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, 193 RTW89_DBG_PORT_SEL_TRXPTCL_C1, 194 RTW89_DBG_PORT_SEL_TX_INFOL_C1, 195 RTW89_DBG_PORT_SEL_TX_INFOH_C1, 196 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, 197 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, 198 /* DLE related */ 199 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, 200 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, 201 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, 202 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, 203 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, 204 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, 205 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, 206 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, 207 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, 208 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, 209 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, 210 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, 211 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, 212 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, 213 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, 214 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, 215 RTW89_DBG_PORT_SEL_PKTINFO, 216 /* DISPATCHER related */ 217 RTW89_DBG_PORT_SEL_DSPT_HDT_TX0, 218 RTW89_DBG_PORT_SEL_DSPT_HDT_TX1, 219 RTW89_DBG_PORT_SEL_DSPT_HDT_TX2, 220 RTW89_DBG_PORT_SEL_DSPT_HDT_TX3, 221 RTW89_DBG_PORT_SEL_DSPT_HDT_TX4, 222 RTW89_DBG_PORT_SEL_DSPT_HDT_TX5, 223 RTW89_DBG_PORT_SEL_DSPT_HDT_TX6, 224 RTW89_DBG_PORT_SEL_DSPT_HDT_TX7, 225 RTW89_DBG_PORT_SEL_DSPT_HDT_TX8, 226 RTW89_DBG_PORT_SEL_DSPT_HDT_TX9, 227 RTW89_DBG_PORT_SEL_DSPT_HDT_TXA, 228 RTW89_DBG_PORT_SEL_DSPT_HDT_TXB, 229 RTW89_DBG_PORT_SEL_DSPT_HDT_TXC, 230 RTW89_DBG_PORT_SEL_DSPT_HDT_TXD, 231 RTW89_DBG_PORT_SEL_DSPT_HDT_TXE, 232 RTW89_DBG_PORT_SEL_DSPT_HDT_TXF, 233 RTW89_DBG_PORT_SEL_DSPT_CDT_TX0, 234 RTW89_DBG_PORT_SEL_DSPT_CDT_TX1, 235 RTW89_DBG_PORT_SEL_DSPT_CDT_TX3, 236 RTW89_DBG_PORT_SEL_DSPT_CDT_TX4, 237 RTW89_DBG_PORT_SEL_DSPT_CDT_TX5, 238 RTW89_DBG_PORT_SEL_DSPT_CDT_TX6, 239 RTW89_DBG_PORT_SEL_DSPT_CDT_TX7, 240 RTW89_DBG_PORT_SEL_DSPT_CDT_TX8, 241 RTW89_DBG_PORT_SEL_DSPT_CDT_TX9, 242 RTW89_DBG_PORT_SEL_DSPT_CDT_TXA, 243 RTW89_DBG_PORT_SEL_DSPT_CDT_TXB, 244 RTW89_DBG_PORT_SEL_DSPT_CDT_TXC, 245 RTW89_DBG_PORT_SEL_DSPT_HDT_RX0, 246 RTW89_DBG_PORT_SEL_DSPT_HDT_RX1, 247 RTW89_DBG_PORT_SEL_DSPT_HDT_RX2, 248 RTW89_DBG_PORT_SEL_DSPT_HDT_RX3, 249 RTW89_DBG_PORT_SEL_DSPT_HDT_RX4, 250 RTW89_DBG_PORT_SEL_DSPT_HDT_RX5, 251 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0, 252 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0, 253 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1, 254 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2, 255 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1, 256 RTW89_DBG_PORT_SEL_DSPT_STF_CTRL, 257 RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL, 258 RTW89_DBG_PORT_SEL_DSPT_WDE_INTF, 259 RTW89_DBG_PORT_SEL_DSPT_PLE_INTF, 260 RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL, 261 /* PCIE related */ 262 RTW89_DBG_PORT_SEL_PCIE_TXDMA, 263 RTW89_DBG_PORT_SEL_PCIE_RXDMA, 264 RTW89_DBG_PORT_SEL_PCIE_CVT, 265 RTW89_DBG_PORT_SEL_PCIE_CXPL, 266 RTW89_DBG_PORT_SEL_PCIE_IO, 267 RTW89_DBG_PORT_SEL_PCIE_MISC, 268 RTW89_DBG_PORT_SEL_PCIE_MISC2, 269 270 /* keep last */ 271 RTW89_DBG_PORT_SEL_LAST, 272 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, 273 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, 274 }; 275 276 /* SRAM mem dump */ 277 #define R_AX_INDIR_ACCESS_ENTRY 0x40000 278 #define R_BE_INDIR_ACCESS_ENTRY 0x80000 279 280 #define AXIDMA_BASE_ADDR 0x18006000 281 #define STA_SCHED_BASE_ADDR 0x18808000 282 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 283 #define SECURITY_CAM_BASE_ADDR 0x18814000 284 #define WOW_CAM_BASE_ADDR 0x18815000 285 #define CMAC_TBL_BASE_ADDR 0x18840000 286 #define ADDR_CAM_BASE_ADDR 0x18850000 287 #define BSSID_CAM_BASE_ADDR 0x18853000 288 #define BA_CAM_BASE_ADDR 0x18854000 289 #define BCN_IE_CAM0_BASE_ADDR 0x18855000 290 #define SHARED_BUF_BASE_ADDR 0x18700000 291 #define DMAC_TBL_BASE_ADDR 0x18800000 292 #define SHCUT_MACHDR_BASE_ADDR 0x18800800 293 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000 294 #define TXD_FIFO_0_BASE_ADDR 0x18856200 295 #define TXD_FIFO_1_BASE_ADDR 0x188A1080 296 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */ 297 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */ 298 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000 299 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 300 #define CPU_LOCAL_BASE_ADDR 0x18003000 301 302 #define WD_PAGE_BASE_ADDR_BE 0x0 303 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000 304 #define AXIDMA_BASE_ADDR_BE 0x18006000 305 #define SHARED_BUF_BASE_ADDR_BE 0x18700000 306 #define DMAC_TBL_BASE_ADDR_BE 0x18800000 307 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800 308 #define STA_SCHED_BASE_ADDR_BE 0x18818000 309 #define NAT25_CAM_BASE_ADDR_BE 0x18820000 310 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000 311 #define SEC_CAM_BASE_ADDR_BE 0x18824000 312 #define WOW_CAM_BASE_ADDR_BE 0x18828000 313 #define MLD_TBL_BASE_ADDR_BE 0x18829000 314 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000 315 #define CMAC_TBL_BASE_ADDR_BE 0x18840000 316 #define ADDR_CAM_BASE_ADDR_BE 0x18850000 317 #define BSSID_CAM_BASE_ADDR_BE 0x18858000 318 #define BA_CAM_BASE_ADDR_BE 0x18859000 319 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000 320 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000 321 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000 322 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000 323 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000 324 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800 325 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000 326 327 #define CCTL_INFO_SIZE 32 328 329 enum rtw89_mac_mem_sel { 330 RTW89_MAC_MEM_AXIDMA, 331 RTW89_MAC_MEM_SHARED_BUF, 332 RTW89_MAC_MEM_DMAC_TBL, 333 RTW89_MAC_MEM_SHCUT_MACHDR, 334 RTW89_MAC_MEM_STA_SCHED, 335 RTW89_MAC_MEM_RXPLD_FLTR_CAM, 336 RTW89_MAC_MEM_SECURITY_CAM, 337 RTW89_MAC_MEM_WOW_CAM, 338 RTW89_MAC_MEM_CMAC_TBL, 339 RTW89_MAC_MEM_ADDR_CAM, 340 RTW89_MAC_MEM_BA_CAM, 341 RTW89_MAC_MEM_BCN_IE_CAM0, 342 RTW89_MAC_MEM_BCN_IE_CAM1, 343 RTW89_MAC_MEM_TXD_FIFO_0, 344 RTW89_MAC_MEM_TXD_FIFO_1, 345 RTW89_MAC_MEM_TXDATA_FIFO_0, 346 RTW89_MAC_MEM_TXDATA_FIFO_1, 347 RTW89_MAC_MEM_CPU_LOCAL, 348 RTW89_MAC_MEM_BSSID_CAM, 349 RTW89_MAC_MEM_TXD_FIFO_0_V1, 350 RTW89_MAC_MEM_TXD_FIFO_1_V1, 351 RTW89_MAC_MEM_WD_PAGE, 352 353 /* keep last */ 354 RTW89_MAC_MEM_NUM, 355 }; 356 357 enum rtw89_rpwm_req_pwr_state { 358 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, 359 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, 360 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, 361 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, 362 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, 363 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, 364 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, 365 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, 366 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, 367 }; 368 369 struct rtw89_pwr_cfg { 370 u16 addr; 371 u8 cv_msk; 372 u8 intf_msk; 373 u8 base:4; 374 u8 cmd:4; 375 u8 msk; 376 u8 val; 377 }; 378 379 enum rtw89_mac_c2h_ofld_func { 380 RTW89_MAC_C2H_FUNC_EFUSE_DUMP, 381 RTW89_MAC_C2H_FUNC_READ_RSP, 382 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, 383 RTW89_MAC_C2H_FUNC_BCN_RESEND, 384 RTW89_MAC_C2H_FUNC_MACID_PAUSE, 385 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6, 386 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9, 387 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd, 388 RTW89_MAC_C2H_FUNC_OFLD_MAX, 389 }; 390 391 enum rtw89_mac_c2h_info_func { 392 RTW89_MAC_C2H_FUNC_REC_ACK, 393 RTW89_MAC_C2H_FUNC_DONE_ACK, 394 RTW89_MAC_C2H_FUNC_C2H_LOG, 395 RTW89_MAC_C2H_FUNC_BCN_CNT, 396 RTW89_MAC_C2H_FUNC_INFO_MAX, 397 }; 398 399 enum rtw89_mac_c2h_mcc_func { 400 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0, 401 RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1, 402 RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2, 403 RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3, 404 405 NUM_OF_RTW89_MAC_C2H_FUNC_MCC, 406 }; 407 408 enum rtw89_mac_c2h_class { 409 RTW89_MAC_C2H_CLASS_INFO, 410 RTW89_MAC_C2H_CLASS_OFLD, 411 RTW89_MAC_C2H_CLASS_TWT, 412 RTW89_MAC_C2H_CLASS_WOW, 413 RTW89_MAC_C2H_CLASS_MCC, 414 RTW89_MAC_C2H_CLASS_FWDBG, 415 RTW89_MAC_C2H_CLASS_MAX, 416 }; 417 418 enum rtw89_mac_mcc_status { 419 RTW89_MAC_MCC_ADD_ROLE_OK = 0, 420 RTW89_MAC_MCC_START_GROUP_OK = 1, 421 RTW89_MAC_MCC_STOP_GROUP_OK = 2, 422 RTW89_MAC_MCC_DEL_GROUP_OK = 3, 423 RTW89_MAC_MCC_RESET_GROUP_OK = 4, 424 RTW89_MAC_MCC_SWITCH_CH_OK = 5, 425 RTW89_MAC_MCC_TXNULL0_OK = 6, 426 RTW89_MAC_MCC_TXNULL1_OK = 7, 427 428 RTW89_MAC_MCC_SWITCH_EARLY = 10, 429 RTW89_MAC_MCC_TBTT = 11, 430 RTW89_MAC_MCC_DURATION_START = 12, 431 RTW89_MAC_MCC_DURATION_END = 13, 432 433 RTW89_MAC_MCC_ADD_ROLE_FAIL = 20, 434 RTW89_MAC_MCC_START_GROUP_FAIL = 21, 435 RTW89_MAC_MCC_STOP_GROUP_FAIL = 22, 436 RTW89_MAC_MCC_DEL_GROUP_FAIL = 23, 437 RTW89_MAC_MCC_RESET_GROUP_FAIL = 24, 438 RTW89_MAC_MCC_SWITCH_CH_FAIL = 25, 439 RTW89_MAC_MCC_TXNULL0_FAIL = 26, 440 RTW89_MAC_MCC_TXNULL1_FAIL = 27, 441 }; 442 443 struct rtw89_mac_ax_coex { 444 #define RTW89_MAC_AX_COEX_RTK_MODE 0 445 #define RTW89_MAC_AX_COEX_CSR_MODE 1 446 u8 pta_mode; 447 #define RTW89_MAC_AX_COEX_INNER 0 448 #define RTW89_MAC_AX_COEX_OUTPUT 1 449 #define RTW89_MAC_AX_COEX_INPUT 2 450 u8 direction; 451 }; 452 453 struct rtw89_mac_ax_plt { 454 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0) 455 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) 456 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) 457 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3) 458 u8 band; 459 u8 tx; 460 u8 rx; 461 }; 462 463 enum rtw89_mac_bf_rrsc_rate { 464 RTW89_MAC_BF_RRSC_6M = 0, 465 RTW89_MAC_BF_RRSC_9M = 1, 466 RTW89_MAC_BF_RRSC_12M, 467 RTW89_MAC_BF_RRSC_18M, 468 RTW89_MAC_BF_RRSC_24M, 469 RTW89_MAC_BF_RRSC_36M, 470 RTW89_MAC_BF_RRSC_48M, 471 RTW89_MAC_BF_RRSC_54M, 472 RTW89_MAC_BF_RRSC_HT_MSC0, 473 RTW89_MAC_BF_RRSC_HT_MSC1, 474 RTW89_MAC_BF_RRSC_HT_MSC2, 475 RTW89_MAC_BF_RRSC_HT_MSC3, 476 RTW89_MAC_BF_RRSC_HT_MSC4, 477 RTW89_MAC_BF_RRSC_HT_MSC5, 478 RTW89_MAC_BF_RRSC_HT_MSC6, 479 RTW89_MAC_BF_RRSC_HT_MSC7, 480 RTW89_MAC_BF_RRSC_VHT_MSC0, 481 RTW89_MAC_BF_RRSC_VHT_MSC1, 482 RTW89_MAC_BF_RRSC_VHT_MSC2, 483 RTW89_MAC_BF_RRSC_VHT_MSC3, 484 RTW89_MAC_BF_RRSC_VHT_MSC4, 485 RTW89_MAC_BF_RRSC_VHT_MSC5, 486 RTW89_MAC_BF_RRSC_VHT_MSC6, 487 RTW89_MAC_BF_RRSC_VHT_MSC7, 488 RTW89_MAC_BF_RRSC_HE_MSC0, 489 RTW89_MAC_BF_RRSC_HE_MSC1, 490 RTW89_MAC_BF_RRSC_HE_MSC2, 491 RTW89_MAC_BF_RRSC_HE_MSC3, 492 RTW89_MAC_BF_RRSC_HE_MSC4, 493 RTW89_MAC_BF_RRSC_HE_MSC5, 494 RTW89_MAC_BF_RRSC_HE_MSC6, 495 RTW89_MAC_BF_RRSC_HE_MSC7 = 31, 496 RTW89_MAC_BF_RRSC_MAX = 32 497 }; 498 499 #define RTW89_R32_EA 0xEAEAEAEA 500 #define RTW89_R32_DEAD 0xDEADBEEF 501 #define MAC_REG_POOL_COUNT 10 502 #define ACCESS_CMAC(_addr) \ 503 ({typeof(_addr) __addr = (_addr); \ 504 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) 505 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000 506 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000 507 508 #define PTCL_IDLE_POLL_CNT 10000 509 #define SW_CVR_DUR_US 8 510 #define SW_CVR_CNT 8 511 512 #define DLE_BOUND_UNIT (8 * 1024) 513 #define DLE_WAIT_CNT 2000 514 #define TRXCFG_WAIT_CNT 2000 515 516 #define RTW89_WDE_PG_64 64 517 #define RTW89_WDE_PG_128 128 518 #define RTW89_WDE_PG_256 256 519 520 #define S_AX_WDE_PAGE_SEL_64 0 521 #define S_AX_WDE_PAGE_SEL_128 1 522 #define S_AX_WDE_PAGE_SEL_256 2 523 524 #define RTW89_PLE_PG_64 64 525 #define RTW89_PLE_PG_128 128 526 #define RTW89_PLE_PG_256 256 527 528 #define S_AX_PLE_PAGE_SEL_64 0 529 #define S_AX_PLE_PAGE_SEL_128 1 530 #define S_AX_PLE_PAGE_SEL_256 2 531 532 #define B_CMAC0_MGQ_NORMAL BIT(2) 533 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3) 534 #define B_CMAC0_CPUMGQ BIT(4) 535 #define B_CMAC1_MGQ_NORMAL BIT(10) 536 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11) 537 #define B_CMAC1_CPUMGQ BIT(12) 538 539 #define QEMP_ACQ_GRP_MACID_NUM 8 540 #define QEMP_ACQ_GRP_QSEL_SH 4 541 #define QEMP_ACQ_GRP_QSEL_MASK 0xF 542 543 #define SDIO_LOCAL_BASE_ADDR 0x80000000 544 545 #define PWR_CMD_WRITE 0 546 #define PWR_CMD_POLL 1 547 #define PWR_CMD_DELAY 2 548 #define PWR_CMD_END 3 549 550 #define PWR_INTF_MSK_SDIO BIT(0) 551 #define PWR_INTF_MSK_USB BIT(1) 552 #define PWR_INTF_MSK_PCIE BIT(2) 553 #define PWR_INTF_MSK_ALL 0x7 554 555 #define PWR_BASE_MAC 0 556 #define PWR_BASE_USB 1 557 #define PWR_BASE_PCIE 2 558 #define PWR_BASE_SDIO 3 559 560 #define PWR_CV_MSK_A BIT(0) 561 #define PWR_CV_MSK_B BIT(1) 562 #define PWR_CV_MSK_C BIT(2) 563 #define PWR_CV_MSK_D BIT(3) 564 #define PWR_CV_MSK_E BIT(4) 565 #define PWR_CV_MSK_F BIT(5) 566 #define PWR_CV_MSK_G BIT(6) 567 #define PWR_CV_MSK_TEST BIT(7) 568 #define PWR_CV_MSK_ALL 0xFF 569 570 #define PWR_DELAY_US 0 571 #define PWR_DELAY_MS 1 572 573 /* STA scheduler */ 574 #define SS_MACID_SH 8 575 #define SS_TX_LEN_MSK 0x1FFFFF 576 #define SS_CTRL1_R_TX_LEN 5 577 #define SS_CTRL1_R_NEXT_LINK 20 578 #define SS_LINK_SIZE 256 579 580 /* MAC debug port */ 581 #define TMAC_DBG_SEL_C0 0xA5 582 #define RMAC_DBG_SEL_C0 0xA6 583 #define TRXPTCL_DBG_SEL_C0 0xA7 584 #define TMAC_DBG_SEL_C1 0xB5 585 #define RMAC_DBG_SEL_C1 0xB6 586 #define TRXPTCL_DBG_SEL_C1 0xB7 587 #define FW_PROG_CNTR_DBG_SEL 0xF2 588 #define PCIE_TXDMA_DBG_SEL 0x30 589 #define PCIE_RXDMA_DBG_SEL 0x31 590 #define PCIE_CVT_DBG_SEL 0x32 591 #define PCIE_CXPL_DBG_SEL 0x33 592 #define PCIE_IO_DBG_SEL 0x37 593 #define PCIE_MISC_DBG_SEL 0x38 594 #define PCIE_MISC2_DBG_SEL 0x00 595 #define MAC_DBG_SEL 1 596 #define RMAC_CMAC_DBG_SEL 1 597 598 /* TRXPTCL dbg port sel */ 599 #define TRXPTRL_DBG_SEL_TMAC 0 600 #define TRXPTRL_DBG_SEL_RMAC 1 601 602 struct rtw89_cpuio_ctrl { 603 u16 pkt_num; 604 u16 start_pktid; 605 u16 end_pktid; 606 u8 cmd_type; 607 u8 macid; 608 u8 src_pid; 609 u8 src_qid; 610 u8 dst_pid; 611 u8 dst_qid; 612 u16 pktid; 613 }; 614 615 struct rtw89_mac_dbg_port_info { 616 u32 sel_addr; 617 u8 sel_byte; 618 u32 sel_msk; 619 u32 srt; 620 u32 end; 621 u32 rd_addr; 622 u8 rd_byte; 623 u32 rd_msk; 624 }; 625 626 #define QLNKTBL_ADDR_INFO_SEL BIT(0) 627 #define QLNKTBL_ADDR_INFO_SEL_0 0 628 #define QLNKTBL_ADDR_INFO_SEL_1 1 629 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) 630 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) 631 632 struct rtw89_mac_dle_dfi_ctrl { 633 enum rtw89_mac_dle_ctrl_type type; 634 u32 target; 635 u32 addr; 636 u32 out_data; 637 }; 638 639 struct rtw89_mac_dle_dfi_quota { 640 enum rtw89_mac_dle_ctrl_type dle_type; 641 u32 qtaid; 642 u16 rsv_pgnum; 643 u16 use_pgnum; 644 }; 645 646 struct rtw89_mac_dle_dfi_qempty { 647 enum rtw89_mac_dle_ctrl_type dle_type; 648 u32 grpsel; 649 u32 qempty; 650 }; 651 652 enum rtw89_mac_error_scenario { 653 RTW89_RXI300_ERROR = 1, 654 RTW89_WCPU_CPU_EXCEPTION = 2, 655 RTW89_WCPU_ASSERTION = 3, 656 }; 657 658 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28) 659 660 /* Define DBG and recovery enum */ 661 enum mac_ax_err_info { 662 /* Get error info */ 663 664 /* L0 */ 665 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, 666 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, 667 MAC_AX_ERR_L0_RESET_DONE = 0x0003, 668 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, 669 670 /* L1 */ 671 MAC_AX_ERR_L1_PREERR_DMAC = 0x999, 672 MAC_AX_ERR_L1_ERR_DMAC = 0x1000, 673 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, 674 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, 675 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, 676 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, 677 678 /* L2 */ 679 /* address hole (master) */ 680 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, 681 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, 682 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, 683 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, 684 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, 685 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, 686 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, 687 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, 688 689 /* AHB bridge timeout (master) */ 690 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, 691 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, 692 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, 693 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, 694 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, 695 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, 696 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, 697 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, 698 699 /* APB_SA bridge timeout (master + slave) */ 700 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, 701 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, 702 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, 703 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, 704 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, 705 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, 706 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, 707 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, 708 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, 709 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, 710 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, 711 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, 712 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, 713 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, 714 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, 715 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, 716 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, 717 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, 718 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, 719 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, 720 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, 721 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, 722 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, 723 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, 724 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, 725 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, 726 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, 727 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, 728 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, 729 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, 730 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, 731 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, 732 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, 733 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, 734 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, 735 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, 736 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, 737 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, 738 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, 739 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, 740 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, 741 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, 742 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, 743 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, 744 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, 745 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, 746 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, 747 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, 748 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, 749 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, 750 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, 751 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, 752 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, 753 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, 754 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, 755 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, 756 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, 757 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, 758 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, 759 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, 760 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, 761 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, 762 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, 763 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, 764 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, 765 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, 766 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, 767 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, 768 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, 769 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, 770 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, 771 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, 772 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, 773 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, 774 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, 775 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, 776 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, 777 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, 778 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, 779 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, 780 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, 781 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, 782 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, 783 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, 784 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, 785 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, 786 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, 787 788 /* APB_BBRF bridge timeout (master) */ 789 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, 790 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, 791 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, 792 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, 793 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, 794 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, 795 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, 796 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, 797 MAC_AX_ERR_L2_RESET_DONE = 0x2400, 798 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599, 799 MAC_AX_ERR_CPU_EXCEPTION = 0x3000, 800 MAC_AX_ERR_ASSERTION = 0x4000, 801 MAC_AX_ERR_RXI300 = 0x5000, 802 MAC_AX_GET_ERR_MAX, 803 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, 804 805 /* set error info */ 806 MAC_AX_ERR_L1_DISABLE_EN = 0x0001, 807 MAC_AX_ERR_L1_RCVY_EN = 0x0002, 808 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, 809 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, 810 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A, 811 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, 812 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, 813 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, 814 MAC_AX_ERR_L0_RCVY_EN = 0x0013, 815 MAC_AX_SET_ERR_MAX, 816 }; 817 818 struct rtw89_mac_size_set { 819 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie; 820 const struct rtw89_dle_size wde_size0; 821 const struct rtw89_dle_size wde_size4; 822 const struct rtw89_dle_size wde_size6; 823 const struct rtw89_dle_size wde_size7; 824 const struct rtw89_dle_size wde_size9; 825 const struct rtw89_dle_size wde_size18; 826 const struct rtw89_dle_size wde_size19; 827 const struct rtw89_dle_size ple_size0; 828 const struct rtw89_dle_size ple_size4; 829 const struct rtw89_dle_size ple_size6; 830 const struct rtw89_dle_size ple_size8; 831 const struct rtw89_dle_size ple_size18; 832 const struct rtw89_dle_size ple_size19; 833 const struct rtw89_wde_quota wde_qt0; 834 const struct rtw89_wde_quota wde_qt4; 835 const struct rtw89_wde_quota wde_qt6; 836 const struct rtw89_wde_quota wde_qt7; 837 const struct rtw89_wde_quota wde_qt17; 838 const struct rtw89_wde_quota wde_qt18; 839 const struct rtw89_ple_quota ple_qt4; 840 const struct rtw89_ple_quota ple_qt5; 841 const struct rtw89_ple_quota ple_qt13; 842 const struct rtw89_ple_quota ple_qt18; 843 const struct rtw89_ple_quota ple_qt44; 844 const struct rtw89_ple_quota ple_qt45; 845 const struct rtw89_ple_quota ple_qt46; 846 const struct rtw89_ple_quota ple_qt47; 847 const struct rtw89_ple_quota ple_qt58; 848 const struct rtw89_ple_quota ple_qt_52a_wow; 849 const struct rtw89_ple_quota ple_qt_52b_wow; 850 const struct rtw89_ple_quota ple_qt_51b_wow; 851 }; 852 853 extern const struct rtw89_mac_size_set rtw89_mac_size; 854 855 struct rtw89_mac_gen_def { 856 u32 band1_offset; 857 u32 filter_model_addr; 858 u32 indir_access_addr; 859 const u32 *mem_base_addrs; 860 u32 rx_fltr; 861 const struct rtw89_port_reg *port_base; 862 u32 agg_len_ht; 863 864 struct rtw89_reg_def muedca_ctrl; 865 struct rtw89_reg_def bfee_ctrl; 866 867 void (*bf_assoc)(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 868 struct ieee80211_sta *sta); 869 870 void (*disable_cpu)(struct rtw89_dev *rtwdev); 871 int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason, 872 bool dlfw, bool include_bb); 873 u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type); 874 int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl); 875 876 bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev, 877 enum rtw89_phy_idx phy_idx, 878 u32 reg_base, u32 *cr); 879 }; 880 881 extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax; 882 extern const struct rtw89_mac_gen_def rtw89_mac_gen_be; 883 884 static inline 885 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band) 886 { 887 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 888 889 return band == 0 ? reg_base : (reg_base + mac->band1_offset); 890 } 891 892 static inline 893 u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx) 894 { 895 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx); 896 } 897 898 static inline u32 899 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base) 900 { 901 u32 reg; 902 903 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 904 return rtw89_read32(rtwdev, reg); 905 } 906 907 static inline u32 908 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 909 u32 base, u32 mask) 910 { 911 u32 reg; 912 913 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 914 return rtw89_read32_mask(rtwdev, reg, mask); 915 } 916 917 static inline void 918 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, 919 u32 data) 920 { 921 u32 reg; 922 923 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 924 rtw89_write32(rtwdev, reg, data); 925 } 926 927 static inline void 928 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 929 u32 base, u32 mask, u32 data) 930 { 931 u32 reg; 932 933 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 934 rtw89_write32_mask(rtwdev, reg, mask, data); 935 } 936 937 static inline void 938 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 939 u32 base, u32 mask, u16 data) 940 { 941 u32 reg; 942 943 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 944 rtw89_write16_mask(rtwdev, reg, mask, data); 945 } 946 947 static inline void 948 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 949 u32 base, u32 bit) 950 { 951 u32 reg; 952 953 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 954 rtw89_write32_clr(rtwdev, reg, bit); 955 } 956 957 static inline void 958 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 959 u32 base, u16 bit) 960 { 961 u32 reg; 962 963 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 964 rtw89_write16_clr(rtwdev, reg, bit); 965 } 966 967 static inline void 968 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 969 u32 base, u32 bit) 970 { 971 u32 reg; 972 973 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 974 rtw89_write32_set(rtwdev, reg, bit); 975 } 976 977 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); 978 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb); 979 int rtw89_mac_init(struct rtw89_dev *rtwdev); 980 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, 981 enum rtw89_mac_hwmod_sel sel); 982 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); 983 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); 984 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 985 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 986 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 987 struct rtw89_vif *rtwvif, 988 struct rtw89_vif *rtwvif_src, 989 u16 offset_tu); 990 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 991 u64 *tsf); 992 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 993 struct ieee80211_vif *vif); 994 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 995 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 996 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); 997 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); 998 999 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev) 1000 { 1001 const struct rtw89_chip_info *chip = rtwdev->chip; 1002 1003 return chip->ops->enable_bb_rf(rtwdev); 1004 } 1005 1006 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev) 1007 { 1008 const struct rtw89_chip_info *chip = rtwdev->chip; 1009 1010 return chip->ops->disable_bb_rf(rtwdev); 1011 } 1012 1013 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); 1014 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); 1015 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func); 1016 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1017 u32 len, u8 class, u8 func); 1018 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); 1019 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 1020 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1021 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 1022 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1023 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1024 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1025 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable); 1026 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx); 1027 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); 1028 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); 1029 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 1030 const struct rtw89_mac_ax_coex *coex); 1031 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 1032 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1033 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 1034 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1035 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); 1036 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band); 1037 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); 1038 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); 1039 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); 1040 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); 1041 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); 1042 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); 1043 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); 1044 1045 static inline 1046 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1047 struct ieee80211_sta *sta) 1048 { 1049 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1050 1051 if (mac->bf_assoc) 1052 mac->bf_assoc(rtwdev, vif, sta); 1053 } 1054 1055 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1056 struct ieee80211_sta *sta); 1057 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1058 struct ieee80211_bss_conf *conf); 1059 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 1060 struct ieee80211_sta *sta, bool disconnect); 1061 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); 1062 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en); 1063 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1064 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1065 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 1066 struct rtw89_vif *rtwvif, bool en); 1067 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause); 1068 1069 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 1070 { 1071 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 1072 return; 1073 1074 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) 1075 return; 1076 1077 _rtw89_mac_bf_monitor_track(rtwdev); 1078 } 1079 1080 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, 1081 enum rtw89_phy_idx phy_idx, 1082 u32 reg_base, u32 *val) 1083 { 1084 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1085 u32 cr; 1086 1087 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1088 return -EINVAL; 1089 1090 *val = rtw89_read32(rtwdev, cr); 1091 return 0; 1092 } 1093 1094 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, 1095 enum rtw89_phy_idx phy_idx, 1096 u32 reg_base, u32 val) 1097 { 1098 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1099 u32 cr; 1100 1101 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1102 return -EINVAL; 1103 1104 rtw89_write32(rtwdev, cr, val); 1105 return 0; 1106 } 1107 1108 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, 1109 enum rtw89_phy_idx phy_idx, 1110 u32 reg_base, u32 mask, u32 val) 1111 { 1112 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1113 u32 cr; 1114 1115 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1116 return -EINVAL; 1117 1118 rtw89_write32_mask(rtwdev, cr, mask, val); 1119 return 0; 1120 } 1121 1122 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev, 1123 bool enable) 1124 { 1125 const struct rtw89_chip_info *chip = rtwdev->chip; 1126 1127 if (enable) 1128 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1129 B_AX_HCI_TXDMA_EN); 1130 else 1131 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1132 B_AX_HCI_TXDMA_EN); 1133 } 1134 1135 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev, 1136 bool enable) 1137 { 1138 const struct rtw89_chip_info *chip = rtwdev->chip; 1139 1140 if (enable) 1141 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1142 B_AX_HCI_RXDMA_EN); 1143 else 1144 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1145 B_AX_HCI_RXDMA_EN); 1146 } 1147 1148 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev, 1149 bool enable) 1150 { 1151 const struct rtw89_chip_info *chip = rtwdev->chip; 1152 1153 if (enable) 1154 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1155 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1156 else 1157 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1158 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1159 } 1160 1161 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev) 1162 { 1163 u32 val; 1164 1165 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, 1166 B_AX_WLMAC_PWR_STE_MASK); 1167 1168 return !!val; 1169 } 1170 1171 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 1172 bool resume, u32 tx_time); 1173 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 1174 u32 *tx_time); 1175 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 1176 struct rtw89_sta *rtwsta, 1177 bool resume, u8 tx_retry); 1178 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 1179 struct rtw89_sta *rtwsta, u8 *tx_retry); 1180 1181 enum rtw89_mac_xtal_si_offset { 1182 XTAL0 = 0x0, 1183 XTAL3 = 0x3, 1184 XTAL_SI_XTAL_SC_XI = 0x04, 1185 #define XTAL_SC_XI_MASK GENMASK(7, 0) 1186 XTAL_SI_XTAL_SC_XO = 0x05, 1187 #define XTAL_SC_XO_MASK GENMASK(7, 0) 1188 XTAL_SI_PWR_CUT = 0x10, 1189 #define XTAL_SI_SMALL_PWR_CUT BIT(0) 1190 #define XTAL_SI_BIG_PWR_CUT BIT(1) 1191 XTAL_SI_XTAL_DRV = 0x15, 1192 #define XTAL_SI_DRV_LATCH BIT(4) 1193 XTAL_SI_XTAL_XMD_2 = 0x24, 1194 #define XTAL_SI_LDO_LPS GENMASK(6, 4) 1195 XTAL_SI_XTAL_XMD_4 = 0x26, 1196 #define XTAL_SI_LPS_CAP GENMASK(3, 0) 1197 XTAL_SI_CV = 0x41, 1198 #define XTAL_SI_ACV_MASK GENMASK(3, 0) 1199 XTAL_SI_LOW_ADDR = 0x62, 1200 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0) 1201 XTAL_SI_CTRL = 0x63, 1202 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6) 1203 #define XTAL_SI_RDY BIT(5) 1204 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0) 1205 XTAL_SI_READ_VAL = 0x7A, 1206 XTAL_SI_WL_RFC_S0 = 0x80, 1207 #define XTAL_SI_RF00S_EN GENMASK(2, 0) 1208 #define XTAL_SI_RF00 BIT(0) 1209 XTAL_SI_WL_RFC_S1 = 0x81, 1210 #define XTAL_SI_RF10S_EN GENMASK(2, 0) 1211 #define XTAL_SI_RF10 BIT(0) 1212 XTAL_SI_ANAPAR_WL = 0x90, 1213 #define XTAL_SI_SRAM2RFC BIT(7) 1214 #define XTAL_SI_GND_SHDN_WL BIT(6) 1215 #define XTAL_SI_SHDN_WL BIT(5) 1216 #define XTAL_SI_RFC2RF BIT(4) 1217 #define XTAL_SI_OFF_EI BIT(3) 1218 #define XTAL_SI_OFF_WEI BIT(2) 1219 #define XTAL_SI_PON_EI BIT(1) 1220 #define XTAL_SI_PON_WEI BIT(0) 1221 XTAL_SI_SRAM_CTRL = 0xA1, 1222 #define XTAL_SI_SRAM_DIS BIT(1) 1223 #define FULL_BIT_MASK GENMASK(7, 0) 1224 }; 1225 1226 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); 1227 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val); 1228 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1229 int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id); 1230 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 1231 struct rtw89_cpuio_ctrl *ctrl_para, bool wd); 1232 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 1233 enum rtw89_machdr_frame_type type, 1234 enum rtw89_mac_fwd_target fwd_target, u8 mac_idx); 1235 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow); 1236 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 1237 enum rtw89_mac_idx band); 1238 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow); 1239 1240 #endif 1241