1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Freescale i.MX6 SoCs 4 * 5 * Copyright (C) 2013 Kosagi 6 * https://www.kosagi.com 7 * 8 * Author: Sean Cross <xobs@kosagi.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio.h> 15 #include <linux/kernel.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_address.h> 23 #include <linux/pci.h> 24 #include <linux/platform_device.h> 25 #include <linux/regmap.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/resource.h> 28 #include <linux/signal.h> 29 #include <linux/types.h> 30 #include <linux/interrupt.h> 31 #include <linux/reset.h> 32 #include <linux/phy/phy.h> 33 #include <linux/pm_domain.h> 34 #include <linux/pm_runtime.h> 35 36 #include "pcie-designware.h" 37 38 #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) 39 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) 40 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) 41 #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) 42 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) 43 #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 44 45 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) 46 47 enum imx6_pcie_variants { 48 IMX6Q, 49 IMX6SX, 50 IMX6QP, 51 IMX7D, 52 IMX8MQ, 53 IMX8MM, 54 IMX8MP, 55 IMX8MQ_EP, 56 IMX8MM_EP, 57 IMX8MP_EP, 58 }; 59 60 #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) 61 #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) 62 #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) 63 64 struct imx6_pcie_drvdata { 65 enum imx6_pcie_variants variant; 66 enum dw_pcie_device_mode mode; 67 u32 flags; 68 int dbi_length; 69 const char *gpr; 70 }; 71 72 struct imx6_pcie { 73 struct dw_pcie *pci; 74 int reset_gpio; 75 bool gpio_active_high; 76 bool link_is_up; 77 struct clk *pcie_bus; 78 struct clk *pcie_phy; 79 struct clk *pcie_inbound_axi; 80 struct clk *pcie; 81 struct clk *pcie_aux; 82 struct regmap *iomuxc_gpr; 83 u16 msi_ctrl; 84 u32 controller_id; 85 struct reset_control *pciephy_reset; 86 struct reset_control *apps_reset; 87 struct reset_control *turnoff_reset; 88 u32 tx_deemph_gen1; 89 u32 tx_deemph_gen2_3p5db; 90 u32 tx_deemph_gen2_6db; 91 u32 tx_swing_full; 92 u32 tx_swing_low; 93 struct regulator *vpcie; 94 struct regulator *vph; 95 void __iomem *phy_base; 96 97 /* power domain for pcie */ 98 struct device *pd_pcie; 99 /* power domain for pcie phy */ 100 struct device *pd_pcie_phy; 101 struct phy *phy; 102 const struct imx6_pcie_drvdata *drvdata; 103 }; 104 105 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ 106 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 107 #define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX) 108 109 /* PCIe Port Logic registers (memory-mapped) */ 110 #define PL_OFFSET 0x700 111 112 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 113 #define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x)) 114 #define PCIE_PHY_CTRL_CAP_ADR BIT(16) 115 #define PCIE_PHY_CTRL_CAP_DAT BIT(17) 116 #define PCIE_PHY_CTRL_WR BIT(18) 117 #define PCIE_PHY_CTRL_RD BIT(19) 118 119 #define PCIE_PHY_STAT (PL_OFFSET + 0x110) 120 #define PCIE_PHY_STAT_ACK BIT(16) 121 122 /* PHY registers (not memory-mapped) */ 123 #define PCIE_PHY_ATEOVRD 0x10 124 #define PCIE_PHY_ATEOVRD_EN BIT(2) 125 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0 126 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1 127 128 #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11 129 #define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2 130 #define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f 131 #define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9) 132 133 #define PCIE_PHY_RX_ASIC_OUT 0x100D 134 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0) 135 136 /* iMX7 PCIe PHY registers */ 137 #define PCIE_PHY_CMN_REG4 0x14 138 /* These are probably the bits that *aren't* DCC_FB_EN */ 139 #define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29 140 141 #define PCIE_PHY_CMN_REG15 0x54 142 #define PCIE_PHY_CMN_REG15_DLY_4 BIT(2) 143 #define PCIE_PHY_CMN_REG15_PLL_PD BIT(5) 144 #define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7) 145 146 #define PCIE_PHY_CMN_REG24 0x90 147 #define PCIE_PHY_CMN_REG24_RX_EQ BIT(6) 148 #define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3) 149 150 #define PCIE_PHY_CMN_REG26 0x98 151 #define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC 152 153 #define PHY_RX_OVRD_IN_LO 0x1005 154 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) 155 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) 156 157 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) 158 { 159 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && 160 imx6_pcie->drvdata->variant != IMX8MQ_EP && 161 imx6_pcie->drvdata->variant != IMX8MM && 162 imx6_pcie->drvdata->variant != IMX8MM_EP && 163 imx6_pcie->drvdata->variant != IMX8MP && 164 imx6_pcie->drvdata->variant != IMX8MP_EP); 165 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; 166 } 167 168 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) 169 { 170 unsigned int mask, val, mode; 171 172 if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) 173 mode = PCI_EXP_TYPE_ENDPOINT; 174 else 175 mode = PCI_EXP_TYPE_ROOT_PORT; 176 177 switch (imx6_pcie->drvdata->variant) { 178 case IMX8MQ: 179 case IMX8MQ_EP: 180 if (imx6_pcie->controller_id == 1) { 181 mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; 182 val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, 183 mode); 184 } else { 185 mask = IMX6Q_GPR12_DEVICE_TYPE; 186 val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); 187 } 188 break; 189 default: 190 mask = IMX6Q_GPR12_DEVICE_TYPE; 191 val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); 192 break; 193 } 194 195 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); 196 } 197 198 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) 199 { 200 struct dw_pcie *pci = imx6_pcie->pci; 201 bool val; 202 u32 max_iterations = 10; 203 u32 wait_counter = 0; 204 205 do { 206 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) & 207 PCIE_PHY_STAT_ACK; 208 wait_counter++; 209 210 if (val == exp_val) 211 return 0; 212 213 udelay(1); 214 } while (wait_counter < max_iterations); 215 216 return -ETIMEDOUT; 217 } 218 219 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) 220 { 221 struct dw_pcie *pci = imx6_pcie->pci; 222 u32 val; 223 int ret; 224 225 val = PCIE_PHY_CTRL_DATA(addr); 226 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 227 228 val |= PCIE_PHY_CTRL_CAP_ADR; 229 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 230 231 ret = pcie_phy_poll_ack(imx6_pcie, true); 232 if (ret) 233 return ret; 234 235 val = PCIE_PHY_CTRL_DATA(addr); 236 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 237 238 return pcie_phy_poll_ack(imx6_pcie, false); 239 } 240 241 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 242 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) 243 { 244 struct dw_pcie *pci = imx6_pcie->pci; 245 u32 phy_ctl; 246 int ret; 247 248 ret = pcie_phy_wait_ack(imx6_pcie, addr); 249 if (ret) 250 return ret; 251 252 /* assert Read signal */ 253 phy_ctl = PCIE_PHY_CTRL_RD; 254 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); 255 256 ret = pcie_phy_poll_ack(imx6_pcie, true); 257 if (ret) 258 return ret; 259 260 *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 261 262 /* deassert Read signal */ 263 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); 264 265 return pcie_phy_poll_ack(imx6_pcie, false); 266 } 267 268 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) 269 { 270 struct dw_pcie *pci = imx6_pcie->pci; 271 u32 var; 272 int ret; 273 274 /* write addr */ 275 /* cap addr */ 276 ret = pcie_phy_wait_ack(imx6_pcie, addr); 277 if (ret) 278 return ret; 279 280 var = PCIE_PHY_CTRL_DATA(data); 281 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 282 283 /* capture data */ 284 var |= PCIE_PHY_CTRL_CAP_DAT; 285 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 286 287 ret = pcie_phy_poll_ack(imx6_pcie, true); 288 if (ret) 289 return ret; 290 291 /* deassert cap data */ 292 var = PCIE_PHY_CTRL_DATA(data); 293 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 294 295 /* wait for ack de-assertion */ 296 ret = pcie_phy_poll_ack(imx6_pcie, false); 297 if (ret) 298 return ret; 299 300 /* assert wr signal */ 301 var = PCIE_PHY_CTRL_WR; 302 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 303 304 /* wait for ack */ 305 ret = pcie_phy_poll_ack(imx6_pcie, true); 306 if (ret) 307 return ret; 308 309 /* deassert wr signal */ 310 var = PCIE_PHY_CTRL_DATA(data); 311 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 312 313 /* wait for ack de-assertion */ 314 ret = pcie_phy_poll_ack(imx6_pcie, false); 315 if (ret) 316 return ret; 317 318 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0); 319 320 return 0; 321 } 322 323 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 324 { 325 switch (imx6_pcie->drvdata->variant) { 326 case IMX8MM: 327 case IMX8MM_EP: 328 case IMX8MP: 329 case IMX8MP_EP: 330 /* 331 * The PHY initialization had been done in the PHY 332 * driver, break here directly. 333 */ 334 break; 335 case IMX8MQ: 336 case IMX8MQ_EP: 337 /* 338 * TODO: Currently this code assumes external 339 * oscillator is being used 340 */ 341 regmap_update_bits(imx6_pcie->iomuxc_gpr, 342 imx6_pcie_grp_offset(imx6_pcie), 343 IMX8MQ_GPR_PCIE_REF_USE_PAD, 344 IMX8MQ_GPR_PCIE_REF_USE_PAD); 345 /* 346 * Regarding the datasheet, the PCIE_VPH is suggested 347 * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the 348 * VREG_BYPASS should be cleared to zero. 349 */ 350 if (imx6_pcie->vph && 351 regulator_get_voltage(imx6_pcie->vph) > 3000000) 352 regmap_update_bits(imx6_pcie->iomuxc_gpr, 353 imx6_pcie_grp_offset(imx6_pcie), 354 IMX8MQ_GPR_PCIE_VREG_BYPASS, 355 0); 356 break; 357 case IMX7D: 358 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 359 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); 360 break; 361 case IMX6SX: 362 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 363 IMX6SX_GPR12_PCIE_RX_EQ_MASK, 364 IMX6SX_GPR12_PCIE_RX_EQ_2); 365 fallthrough; 366 default: 367 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 368 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); 369 370 /* configure constant input signal to the pcie ctrl and phy */ 371 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 372 IMX6Q_GPR12_LOS_LEVEL, 9 << 4); 373 374 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 375 IMX6Q_GPR8_TX_DEEMPH_GEN1, 376 imx6_pcie->tx_deemph_gen1 << 0); 377 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 378 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 379 imx6_pcie->tx_deemph_gen2_3p5db << 6); 380 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 381 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 382 imx6_pcie->tx_deemph_gen2_6db << 12); 383 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 384 IMX6Q_GPR8_TX_SWING_FULL, 385 imx6_pcie->tx_swing_full << 18); 386 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 387 IMX6Q_GPR8_TX_SWING_LOW, 388 imx6_pcie->tx_swing_low << 25); 389 break; 390 } 391 392 imx6_pcie_configure_type(imx6_pcie); 393 } 394 395 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) 396 { 397 u32 val; 398 struct device *dev = imx6_pcie->pci->dev; 399 400 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, 401 IOMUXC_GPR22, val, 402 val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, 403 PHY_PLL_LOCK_WAIT_USLEEP_MAX, 404 PHY_PLL_LOCK_WAIT_TIMEOUT)) 405 dev_err(dev, "PCIe PLL lock timeout\n"); 406 } 407 408 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) 409 { 410 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy); 411 int mult, div; 412 u16 val; 413 414 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 415 return 0; 416 417 switch (phy_rate) { 418 case 125000000: 419 /* 420 * The default settings of the MPLL are for a 125MHz input 421 * clock, so no need to reconfigure anything in that case. 422 */ 423 return 0; 424 case 100000000: 425 mult = 25; 426 div = 0; 427 break; 428 case 200000000: 429 mult = 25; 430 div = 1; 431 break; 432 default: 433 dev_err(imx6_pcie->pci->dev, 434 "Unsupported PHY reference clock rate %lu\n", phy_rate); 435 return -EINVAL; 436 } 437 438 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); 439 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << 440 PCIE_PHY_MPLL_MULTIPLIER_SHIFT); 441 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; 442 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; 443 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); 444 445 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); 446 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << 447 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); 448 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; 449 val |= PCIE_PHY_ATEOVRD_EN; 450 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); 451 452 return 0; 453 } 454 455 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) 456 { 457 u16 tmp; 458 459 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 460 return; 461 462 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 463 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | 464 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 465 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 466 467 usleep_range(2000, 3000); 468 469 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 470 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | 471 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 472 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 473 } 474 475 #ifdef CONFIG_ARM 476 /* Added for PCI abort handling */ 477 static int imx6q_pcie_abort_handler(unsigned long addr, 478 unsigned int fsr, struct pt_regs *regs) 479 { 480 unsigned long pc = instruction_pointer(regs); 481 unsigned long instr = *(unsigned long *)pc; 482 int reg = (instr >> 12) & 15; 483 484 /* 485 * If the instruction being executed was a read, 486 * make it look like it read all-ones. 487 */ 488 if ((instr & 0x0c100000) == 0x04100000) { 489 unsigned long val; 490 491 if (instr & 0x00400000) 492 val = 255; 493 else 494 val = -1; 495 496 regs->uregs[reg] = val; 497 regs->ARM_pc += 4; 498 return 0; 499 } 500 501 if ((instr & 0x0e100090) == 0x00100090) { 502 regs->uregs[reg] = -1; 503 regs->ARM_pc += 4; 504 return 0; 505 } 506 507 return 1; 508 } 509 #endif 510 511 static int imx6_pcie_attach_pd(struct device *dev) 512 { 513 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 514 struct device_link *link; 515 516 /* Do nothing when in a single power domain */ 517 if (dev->pm_domain) 518 return 0; 519 520 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); 521 if (IS_ERR(imx6_pcie->pd_pcie)) 522 return PTR_ERR(imx6_pcie->pd_pcie); 523 /* Do nothing when power domain missing */ 524 if (!imx6_pcie->pd_pcie) 525 return 0; 526 link = device_link_add(dev, imx6_pcie->pd_pcie, 527 DL_FLAG_STATELESS | 528 DL_FLAG_PM_RUNTIME | 529 DL_FLAG_RPM_ACTIVE); 530 if (!link) { 531 dev_err(dev, "Failed to add device_link to pcie pd.\n"); 532 return -EINVAL; 533 } 534 535 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); 536 if (IS_ERR(imx6_pcie->pd_pcie_phy)) 537 return PTR_ERR(imx6_pcie->pd_pcie_phy); 538 539 link = device_link_add(dev, imx6_pcie->pd_pcie_phy, 540 DL_FLAG_STATELESS | 541 DL_FLAG_PM_RUNTIME | 542 DL_FLAG_RPM_ACTIVE); 543 if (!link) { 544 dev_err(dev, "Failed to add device_link to pcie_phy pd.\n"); 545 return -EINVAL; 546 } 547 548 return 0; 549 } 550 551 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 552 { 553 struct dw_pcie *pci = imx6_pcie->pci; 554 struct device *dev = pci->dev; 555 unsigned int offset; 556 int ret = 0; 557 558 switch (imx6_pcie->drvdata->variant) { 559 case IMX6SX: 560 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); 561 if (ret) { 562 dev_err(dev, "unable to enable pcie_axi clock\n"); 563 break; 564 } 565 566 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 567 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); 568 break; 569 case IMX6QP: 570 case IMX6Q: 571 /* power up core phy and enable ref clock */ 572 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 573 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); 574 /* 575 * the async reset input need ref clock to sync internally, 576 * when the ref clock comes after reset, internal synced 577 * reset time is too short, cannot meet the requirement. 578 * add one ~10us delay here. 579 */ 580 usleep_range(10, 100); 581 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 582 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); 583 break; 584 case IMX7D: 585 break; 586 case IMX8MM: 587 case IMX8MM_EP: 588 case IMX8MQ: 589 case IMX8MQ_EP: 590 case IMX8MP: 591 case IMX8MP_EP: 592 ret = clk_prepare_enable(imx6_pcie->pcie_aux); 593 if (ret) { 594 dev_err(dev, "unable to enable pcie_aux clock\n"); 595 break; 596 } 597 598 offset = imx6_pcie_grp_offset(imx6_pcie); 599 /* 600 * Set the over ride low and enabled 601 * make sure that REF_CLK is turned on. 602 */ 603 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 604 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, 605 0); 606 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 607 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, 608 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); 609 break; 610 } 611 612 return ret; 613 } 614 615 static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) 616 { 617 switch (imx6_pcie->drvdata->variant) { 618 case IMX6SX: 619 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); 620 break; 621 case IMX6QP: 622 case IMX6Q: 623 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 624 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); 625 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 626 IMX6Q_GPR1_PCIE_TEST_PD, 627 IMX6Q_GPR1_PCIE_TEST_PD); 628 break; 629 case IMX7D: 630 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 631 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 632 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); 633 break; 634 case IMX8MM: 635 case IMX8MM_EP: 636 case IMX8MQ: 637 case IMX8MQ_EP: 638 case IMX8MP: 639 case IMX8MP_EP: 640 clk_disable_unprepare(imx6_pcie->pcie_aux); 641 break; 642 default: 643 break; 644 } 645 } 646 647 static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) 648 { 649 struct dw_pcie *pci = imx6_pcie->pci; 650 struct device *dev = pci->dev; 651 int ret; 652 653 ret = clk_prepare_enable(imx6_pcie->pcie_phy); 654 if (ret) { 655 dev_err(dev, "unable to enable pcie_phy clock\n"); 656 return ret; 657 } 658 659 ret = clk_prepare_enable(imx6_pcie->pcie_bus); 660 if (ret) { 661 dev_err(dev, "unable to enable pcie_bus clock\n"); 662 goto err_pcie_bus; 663 } 664 665 ret = clk_prepare_enable(imx6_pcie->pcie); 666 if (ret) { 667 dev_err(dev, "unable to enable pcie clock\n"); 668 goto err_pcie; 669 } 670 671 ret = imx6_pcie_enable_ref_clk(imx6_pcie); 672 if (ret) { 673 dev_err(dev, "unable to enable pcie ref clock\n"); 674 goto err_ref_clk; 675 } 676 677 /* allow the clocks to stabilize */ 678 usleep_range(200, 500); 679 return 0; 680 681 err_ref_clk: 682 clk_disable_unprepare(imx6_pcie->pcie); 683 err_pcie: 684 clk_disable_unprepare(imx6_pcie->pcie_bus); 685 err_pcie_bus: 686 clk_disable_unprepare(imx6_pcie->pcie_phy); 687 688 return ret; 689 } 690 691 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) 692 { 693 imx6_pcie_disable_ref_clk(imx6_pcie); 694 clk_disable_unprepare(imx6_pcie->pcie); 695 clk_disable_unprepare(imx6_pcie->pcie_bus); 696 clk_disable_unprepare(imx6_pcie->pcie_phy); 697 } 698 699 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) 700 { 701 switch (imx6_pcie->drvdata->variant) { 702 case IMX7D: 703 case IMX8MQ: 704 case IMX8MQ_EP: 705 reset_control_assert(imx6_pcie->pciephy_reset); 706 fallthrough; 707 case IMX8MM: 708 case IMX8MM_EP: 709 case IMX8MP: 710 case IMX8MP_EP: 711 reset_control_assert(imx6_pcie->apps_reset); 712 break; 713 case IMX6SX: 714 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 715 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 716 IMX6SX_GPR12_PCIE_TEST_POWERDOWN); 717 /* Force PCIe PHY reset */ 718 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 719 IMX6SX_GPR5_PCIE_BTNRST_RESET, 720 IMX6SX_GPR5_PCIE_BTNRST_RESET); 721 break; 722 case IMX6QP: 723 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 724 IMX6Q_GPR1_PCIE_SW_RST, 725 IMX6Q_GPR1_PCIE_SW_RST); 726 break; 727 case IMX6Q: 728 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 729 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); 730 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 731 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); 732 break; 733 } 734 735 /* Some boards don't have PCIe reset GPIO. */ 736 if (gpio_is_valid(imx6_pcie->reset_gpio)) 737 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 738 imx6_pcie->gpio_active_high); 739 } 740 741 static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) 742 { 743 struct dw_pcie *pci = imx6_pcie->pci; 744 struct device *dev = pci->dev; 745 746 switch (imx6_pcie->drvdata->variant) { 747 case IMX8MQ: 748 case IMX8MQ_EP: 749 reset_control_deassert(imx6_pcie->pciephy_reset); 750 break; 751 case IMX7D: 752 reset_control_deassert(imx6_pcie->pciephy_reset); 753 754 /* Workaround for ERR010728, failure of PCI-e PLL VCO to 755 * oscillate, especially when cold. This turns off "Duty-cycle 756 * Corrector" and other mysterious undocumented things. 757 */ 758 if (likely(imx6_pcie->phy_base)) { 759 /* De-assert DCC_FB_EN */ 760 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, 761 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); 762 /* Assert RX_EQS and RX_EQS_SEL */ 763 writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL 764 | PCIE_PHY_CMN_REG24_RX_EQ, 765 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); 766 /* Assert ATT_MODE */ 767 writel(PCIE_PHY_CMN_REG26_ATT_MODE, 768 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); 769 } else { 770 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); 771 } 772 773 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); 774 break; 775 case IMX6SX: 776 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 777 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); 778 break; 779 case IMX6QP: 780 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 781 IMX6Q_GPR1_PCIE_SW_RST, 0); 782 783 usleep_range(200, 500); 784 break; 785 case IMX6Q: /* Nothing to do */ 786 case IMX8MM: 787 case IMX8MM_EP: 788 case IMX8MP: 789 case IMX8MP_EP: 790 break; 791 } 792 793 /* Some boards don't have PCIe reset GPIO. */ 794 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 795 msleep(100); 796 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 797 !imx6_pcie->gpio_active_high); 798 /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ 799 msleep(100); 800 } 801 802 return 0; 803 } 804 805 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) 806 { 807 struct dw_pcie *pci = imx6_pcie->pci; 808 struct device *dev = pci->dev; 809 u32 tmp; 810 unsigned int retries; 811 812 for (retries = 0; retries < 200; retries++) { 813 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 814 /* Test if the speed change finished. */ 815 if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) 816 return 0; 817 usleep_range(100, 1000); 818 } 819 820 dev_err(dev, "Speed change timeout\n"); 821 return -ETIMEDOUT; 822 } 823 824 static void imx6_pcie_ltssm_enable(struct device *dev) 825 { 826 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 827 828 switch (imx6_pcie->drvdata->variant) { 829 case IMX6Q: 830 case IMX6SX: 831 case IMX6QP: 832 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 833 IMX6Q_GPR12_PCIE_CTL_2, 834 IMX6Q_GPR12_PCIE_CTL_2); 835 break; 836 case IMX7D: 837 case IMX8MQ: 838 case IMX8MQ_EP: 839 case IMX8MM: 840 case IMX8MM_EP: 841 case IMX8MP: 842 case IMX8MP_EP: 843 reset_control_deassert(imx6_pcie->apps_reset); 844 break; 845 } 846 } 847 848 static void imx6_pcie_ltssm_disable(struct device *dev) 849 { 850 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 851 852 switch (imx6_pcie->drvdata->variant) { 853 case IMX6Q: 854 case IMX6SX: 855 case IMX6QP: 856 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 857 IMX6Q_GPR12_PCIE_CTL_2, 0); 858 break; 859 case IMX7D: 860 case IMX8MQ: 861 case IMX8MQ_EP: 862 case IMX8MM: 863 case IMX8MM_EP: 864 case IMX8MP: 865 case IMX8MP_EP: 866 reset_control_assert(imx6_pcie->apps_reset); 867 break; 868 } 869 } 870 871 static int imx6_pcie_start_link(struct dw_pcie *pci) 872 { 873 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 874 struct device *dev = pci->dev; 875 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 876 u32 tmp; 877 int ret; 878 879 /* 880 * Force Gen1 operation when starting the link. In case the link is 881 * started in Gen2 mode, there is a possibility the devices on the 882 * bus will not be detected at all. This happens with PCIe switches. 883 */ 884 dw_pcie_dbi_ro_wr_en(pci); 885 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 886 tmp &= ~PCI_EXP_LNKCAP_SLS; 887 tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; 888 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 889 dw_pcie_dbi_ro_wr_dis(pci); 890 891 /* Start LTSSM. */ 892 imx6_pcie_ltssm_enable(dev); 893 894 ret = dw_pcie_wait_for_link(pci); 895 if (ret) 896 goto err_reset_phy; 897 898 if (pci->link_gen > 1) { 899 /* Allow faster modes after the link is up */ 900 dw_pcie_dbi_ro_wr_en(pci); 901 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 902 tmp &= ~PCI_EXP_LNKCAP_SLS; 903 tmp |= pci->link_gen; 904 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 905 906 /* 907 * Start Directed Speed Change so the best possible 908 * speed both link partners support can be negotiated. 909 */ 910 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 911 tmp |= PORT_LOGIC_SPEED_CHANGE; 912 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); 913 dw_pcie_dbi_ro_wr_dis(pci); 914 915 if (imx6_pcie->drvdata->flags & 916 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) { 917 /* 918 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently 919 * from i.MX6 family when no link speed transition 920 * occurs and we go Gen1 -> yep, Gen1. The difference 921 * is that, in such case, it will not be cleared by HW 922 * which will cause the following code to report false 923 * failure. 924 */ 925 926 ret = imx6_pcie_wait_for_speed_change(imx6_pcie); 927 if (ret) { 928 dev_err(dev, "Failed to bring link up!\n"); 929 goto err_reset_phy; 930 } 931 } 932 933 /* Make sure link training is finished as well! */ 934 ret = dw_pcie_wait_for_link(pci); 935 if (ret) 936 goto err_reset_phy; 937 } else { 938 dev_info(dev, "Link: Only Gen1 is enabled\n"); 939 } 940 941 imx6_pcie->link_is_up = true; 942 tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 943 dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); 944 return 0; 945 946 err_reset_phy: 947 imx6_pcie->link_is_up = false; 948 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", 949 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), 950 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); 951 imx6_pcie_reset_phy(imx6_pcie); 952 return 0; 953 } 954 955 static void imx6_pcie_stop_link(struct dw_pcie *pci) 956 { 957 struct device *dev = pci->dev; 958 959 /* Turn off PCIe LTSSM */ 960 imx6_pcie_ltssm_disable(dev); 961 } 962 963 static int imx6_pcie_host_init(struct dw_pcie_rp *pp) 964 { 965 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 966 struct device *dev = pci->dev; 967 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 968 int ret; 969 970 if (imx6_pcie->vpcie) { 971 ret = regulator_enable(imx6_pcie->vpcie); 972 if (ret) { 973 dev_err(dev, "failed to enable vpcie regulator: %d\n", 974 ret); 975 return ret; 976 } 977 } 978 979 imx6_pcie_assert_core_reset(imx6_pcie); 980 imx6_pcie_init_phy(imx6_pcie); 981 982 ret = imx6_pcie_clk_enable(imx6_pcie); 983 if (ret) { 984 dev_err(dev, "unable to enable pcie clocks: %d\n", ret); 985 goto err_reg_disable; 986 } 987 988 if (imx6_pcie->phy) { 989 ret = phy_init(imx6_pcie->phy); 990 if (ret) { 991 dev_err(dev, "pcie PHY power up failed\n"); 992 goto err_clk_disable; 993 } 994 } 995 996 if (imx6_pcie->phy) { 997 ret = phy_power_on(imx6_pcie->phy); 998 if (ret) { 999 dev_err(dev, "waiting for PHY ready timeout!\n"); 1000 goto err_phy_off; 1001 } 1002 } 1003 1004 ret = imx6_pcie_deassert_core_reset(imx6_pcie); 1005 if (ret < 0) { 1006 dev_err(dev, "pcie deassert core reset failed: %d\n", ret); 1007 goto err_phy_off; 1008 } 1009 1010 imx6_setup_phy_mpll(imx6_pcie); 1011 1012 return 0; 1013 1014 err_phy_off: 1015 if (imx6_pcie->phy) 1016 phy_exit(imx6_pcie->phy); 1017 err_clk_disable: 1018 imx6_pcie_clk_disable(imx6_pcie); 1019 err_reg_disable: 1020 if (imx6_pcie->vpcie) 1021 regulator_disable(imx6_pcie->vpcie); 1022 return ret; 1023 } 1024 1025 static void imx6_pcie_host_exit(struct dw_pcie_rp *pp) 1026 { 1027 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1028 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 1029 1030 if (imx6_pcie->phy) { 1031 if (phy_power_off(imx6_pcie->phy)) 1032 dev_err(pci->dev, "unable to power off PHY\n"); 1033 phy_exit(imx6_pcie->phy); 1034 } 1035 imx6_pcie_clk_disable(imx6_pcie); 1036 1037 if (imx6_pcie->vpcie) 1038 regulator_disable(imx6_pcie->vpcie); 1039 } 1040 1041 static const struct dw_pcie_host_ops imx6_pcie_host_ops = { 1042 .init = imx6_pcie_host_init, 1043 .deinit = imx6_pcie_host_exit, 1044 }; 1045 1046 static const struct dw_pcie_ops dw_pcie_ops = { 1047 .start_link = imx6_pcie_start_link, 1048 .stop_link = imx6_pcie_stop_link, 1049 }; 1050 1051 static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) 1052 { 1053 enum pci_barno bar; 1054 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1055 1056 for (bar = BAR_0; bar <= BAR_5; bar++) 1057 dw_pcie_ep_reset_bar(pci, bar); 1058 } 1059 1060 static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 1061 unsigned int type, u16 interrupt_num) 1062 { 1063 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1064 1065 switch (type) { 1066 case PCI_IRQ_INTX: 1067 return dw_pcie_ep_raise_intx_irq(ep, func_no); 1068 case PCI_IRQ_MSI: 1069 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 1070 case PCI_IRQ_MSIX: 1071 return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 1072 default: 1073 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 1074 return -EINVAL; 1075 } 1076 1077 return 0; 1078 } 1079 1080 static const struct pci_epc_features imx8m_pcie_epc_features = { 1081 .linkup_notifier = false, 1082 .msi_capable = true, 1083 .msix_capable = false, 1084 .reserved_bar = 1 << BAR_1 | 1 << BAR_3, 1085 .align = SZ_64K, 1086 }; 1087 1088 static const struct pci_epc_features* 1089 imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) 1090 { 1091 return &imx8m_pcie_epc_features; 1092 } 1093 1094 static const struct dw_pcie_ep_ops pcie_ep_ops = { 1095 .init = imx6_pcie_ep_init, 1096 .raise_irq = imx6_pcie_ep_raise_irq, 1097 .get_features = imx6_pcie_ep_get_features, 1098 }; 1099 1100 static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, 1101 struct platform_device *pdev) 1102 { 1103 int ret; 1104 unsigned int pcie_dbi2_offset; 1105 struct dw_pcie_ep *ep; 1106 struct resource *res; 1107 struct dw_pcie *pci = imx6_pcie->pci; 1108 struct dw_pcie_rp *pp = &pci->pp; 1109 struct device *dev = pci->dev; 1110 1111 imx6_pcie_host_init(pp); 1112 ep = &pci->ep; 1113 ep->ops = &pcie_ep_ops; 1114 1115 switch (imx6_pcie->drvdata->variant) { 1116 case IMX8MQ_EP: 1117 case IMX8MM_EP: 1118 case IMX8MP_EP: 1119 pcie_dbi2_offset = SZ_1M; 1120 break; 1121 default: 1122 pcie_dbi2_offset = SZ_4K; 1123 break; 1124 } 1125 pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; 1126 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 1127 if (!res) 1128 return -EINVAL; 1129 1130 ep->phys_base = res->start; 1131 ep->addr_size = resource_size(res); 1132 ep->page_size = SZ_64K; 1133 1134 ret = dw_pcie_ep_init(ep); 1135 if (ret) { 1136 dev_err(dev, "failed to initialize endpoint\n"); 1137 return ret; 1138 } 1139 /* Start LTSSM. */ 1140 imx6_pcie_ltssm_enable(dev); 1141 1142 return 0; 1143 } 1144 1145 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) 1146 { 1147 struct device *dev = imx6_pcie->pci->dev; 1148 1149 /* Some variants have a turnoff reset in DT */ 1150 if (imx6_pcie->turnoff_reset) { 1151 reset_control_assert(imx6_pcie->turnoff_reset); 1152 reset_control_deassert(imx6_pcie->turnoff_reset); 1153 goto pm_turnoff_sleep; 1154 } 1155 1156 /* Others poke directly at IOMUXC registers */ 1157 switch (imx6_pcie->drvdata->variant) { 1158 case IMX6SX: 1159 case IMX6QP: 1160 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 1161 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 1162 IMX6SX_GPR12_PCIE_PM_TURN_OFF); 1163 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 1164 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); 1165 break; 1166 default: 1167 dev_err(dev, "PME_Turn_Off not implemented\n"); 1168 return; 1169 } 1170 1171 /* 1172 * Components with an upstream port must respond to 1173 * PME_Turn_Off with PME_TO_Ack but we can't check. 1174 * 1175 * The standard recommends a 1-10ms timeout after which to 1176 * proceed anyway as if acks were received. 1177 */ 1178 pm_turnoff_sleep: 1179 usleep_range(1000, 10000); 1180 } 1181 1182 static void imx6_pcie_msi_save_restore(struct imx6_pcie *imx6_pcie, bool save) 1183 { 1184 u8 offset; 1185 u16 val; 1186 struct dw_pcie *pci = imx6_pcie->pci; 1187 1188 if (pci_msi_enabled()) { 1189 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); 1190 if (save) { 1191 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); 1192 imx6_pcie->msi_ctrl = val; 1193 } else { 1194 dw_pcie_dbi_ro_wr_en(pci); 1195 val = imx6_pcie->msi_ctrl; 1196 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); 1197 dw_pcie_dbi_ro_wr_dis(pci); 1198 } 1199 } 1200 } 1201 1202 static int imx6_pcie_suspend_noirq(struct device *dev) 1203 { 1204 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1205 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 1206 1207 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 1208 return 0; 1209 1210 imx6_pcie_msi_save_restore(imx6_pcie, true); 1211 imx6_pcie_pm_turnoff(imx6_pcie); 1212 imx6_pcie_stop_link(imx6_pcie->pci); 1213 imx6_pcie_host_exit(pp); 1214 1215 return 0; 1216 } 1217 1218 static int imx6_pcie_resume_noirq(struct device *dev) 1219 { 1220 int ret; 1221 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1222 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 1223 1224 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 1225 return 0; 1226 1227 ret = imx6_pcie_host_init(pp); 1228 if (ret) 1229 return ret; 1230 imx6_pcie_msi_save_restore(imx6_pcie, false); 1231 dw_pcie_setup_rc(pp); 1232 1233 if (imx6_pcie->link_is_up) 1234 imx6_pcie_start_link(imx6_pcie->pci); 1235 1236 return 0; 1237 } 1238 1239 static const struct dev_pm_ops imx6_pcie_pm_ops = { 1240 NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, 1241 imx6_pcie_resume_noirq) 1242 }; 1243 1244 static int imx6_pcie_probe(struct platform_device *pdev) 1245 { 1246 struct device *dev = &pdev->dev; 1247 struct dw_pcie *pci; 1248 struct imx6_pcie *imx6_pcie; 1249 struct device_node *np; 1250 struct resource *dbi_base; 1251 struct device_node *node = dev->of_node; 1252 int ret; 1253 u16 val; 1254 1255 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); 1256 if (!imx6_pcie) 1257 return -ENOMEM; 1258 1259 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1260 if (!pci) 1261 return -ENOMEM; 1262 1263 pci->dev = dev; 1264 pci->ops = &dw_pcie_ops; 1265 pci->pp.ops = &imx6_pcie_host_ops; 1266 1267 imx6_pcie->pci = pci; 1268 imx6_pcie->drvdata = of_device_get_match_data(dev); 1269 1270 /* Find the PHY if one is defined, only imx7d uses it */ 1271 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); 1272 if (np) { 1273 struct resource res; 1274 1275 ret = of_address_to_resource(np, 0, &res); 1276 if (ret) { 1277 dev_err(dev, "Unable to map PCIe PHY\n"); 1278 return ret; 1279 } 1280 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); 1281 if (IS_ERR(imx6_pcie->phy_base)) 1282 return PTR_ERR(imx6_pcie->phy_base); 1283 } 1284 1285 pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base); 1286 if (IS_ERR(pci->dbi_base)) 1287 return PTR_ERR(pci->dbi_base); 1288 1289 /* Fetch GPIOs */ 1290 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); 1291 imx6_pcie->gpio_active_high = of_property_read_bool(node, 1292 "reset-gpio-active-high"); 1293 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 1294 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, 1295 imx6_pcie->gpio_active_high ? 1296 GPIOF_OUT_INIT_HIGH : 1297 GPIOF_OUT_INIT_LOW, 1298 "PCIe reset"); 1299 if (ret) { 1300 dev_err(dev, "unable to get reset gpio\n"); 1301 return ret; 1302 } 1303 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) { 1304 return imx6_pcie->reset_gpio; 1305 } 1306 1307 /* Fetch clocks */ 1308 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus"); 1309 if (IS_ERR(imx6_pcie->pcie_bus)) 1310 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus), 1311 "pcie_bus clock source missing or invalid\n"); 1312 1313 imx6_pcie->pcie = devm_clk_get(dev, "pcie"); 1314 if (IS_ERR(imx6_pcie->pcie)) 1315 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie), 1316 "pcie clock source missing or invalid\n"); 1317 1318 switch (imx6_pcie->drvdata->variant) { 1319 case IMX6SX: 1320 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, 1321 "pcie_inbound_axi"); 1322 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) 1323 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi), 1324 "pcie_inbound_axi clock missing or invalid\n"); 1325 break; 1326 case IMX8MQ: 1327 case IMX8MQ_EP: 1328 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); 1329 if (IS_ERR(imx6_pcie->pcie_aux)) 1330 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), 1331 "pcie_aux clock source missing or invalid\n"); 1332 fallthrough; 1333 case IMX7D: 1334 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) 1335 imx6_pcie->controller_id = 1; 1336 1337 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, 1338 "pciephy"); 1339 if (IS_ERR(imx6_pcie->pciephy_reset)) { 1340 dev_err(dev, "Failed to get PCIEPHY reset control\n"); 1341 return PTR_ERR(imx6_pcie->pciephy_reset); 1342 } 1343 1344 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, 1345 "apps"); 1346 if (IS_ERR(imx6_pcie->apps_reset)) { 1347 dev_err(dev, "Failed to get PCIE APPS reset control\n"); 1348 return PTR_ERR(imx6_pcie->apps_reset); 1349 } 1350 break; 1351 case IMX8MM: 1352 case IMX8MM_EP: 1353 case IMX8MP: 1354 case IMX8MP_EP: 1355 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); 1356 if (IS_ERR(imx6_pcie->pcie_aux)) 1357 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), 1358 "pcie_aux clock source missing or invalid\n"); 1359 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, 1360 "apps"); 1361 if (IS_ERR(imx6_pcie->apps_reset)) 1362 return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), 1363 "failed to get pcie apps reset control\n"); 1364 1365 imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); 1366 if (IS_ERR(imx6_pcie->phy)) 1367 return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), 1368 "failed to get pcie phy\n"); 1369 1370 break; 1371 default: 1372 break; 1373 } 1374 /* Don't fetch the pcie_phy clock, if it has abstract PHY driver */ 1375 if (imx6_pcie->phy == NULL) { 1376 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy"); 1377 if (IS_ERR(imx6_pcie->pcie_phy)) 1378 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy), 1379 "pcie_phy clock source missing or invalid\n"); 1380 } 1381 1382 1383 /* Grab turnoff reset */ 1384 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); 1385 if (IS_ERR(imx6_pcie->turnoff_reset)) { 1386 dev_err(dev, "Failed to get TURNOFF reset control\n"); 1387 return PTR_ERR(imx6_pcie->turnoff_reset); 1388 } 1389 1390 /* Grab GPR config register range */ 1391 imx6_pcie->iomuxc_gpr = 1392 syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); 1393 if (IS_ERR(imx6_pcie->iomuxc_gpr)) { 1394 dev_err(dev, "unable to find iomuxc registers\n"); 1395 return PTR_ERR(imx6_pcie->iomuxc_gpr); 1396 } 1397 1398 /* Grab PCIe PHY Tx Settings */ 1399 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", 1400 &imx6_pcie->tx_deemph_gen1)) 1401 imx6_pcie->tx_deemph_gen1 = 0; 1402 1403 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", 1404 &imx6_pcie->tx_deemph_gen2_3p5db)) 1405 imx6_pcie->tx_deemph_gen2_3p5db = 0; 1406 1407 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", 1408 &imx6_pcie->tx_deemph_gen2_6db)) 1409 imx6_pcie->tx_deemph_gen2_6db = 20; 1410 1411 if (of_property_read_u32(node, "fsl,tx-swing-full", 1412 &imx6_pcie->tx_swing_full)) 1413 imx6_pcie->tx_swing_full = 127; 1414 1415 if (of_property_read_u32(node, "fsl,tx-swing-low", 1416 &imx6_pcie->tx_swing_low)) 1417 imx6_pcie->tx_swing_low = 127; 1418 1419 /* Limit link speed */ 1420 pci->link_gen = 1; 1421 of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); 1422 1423 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); 1424 if (IS_ERR(imx6_pcie->vpcie)) { 1425 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) 1426 return PTR_ERR(imx6_pcie->vpcie); 1427 imx6_pcie->vpcie = NULL; 1428 } 1429 1430 imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); 1431 if (IS_ERR(imx6_pcie->vph)) { 1432 if (PTR_ERR(imx6_pcie->vph) != -ENODEV) 1433 return PTR_ERR(imx6_pcie->vph); 1434 imx6_pcie->vph = NULL; 1435 } 1436 1437 platform_set_drvdata(pdev, imx6_pcie); 1438 1439 ret = imx6_pcie_attach_pd(dev); 1440 if (ret) 1441 return ret; 1442 1443 if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { 1444 ret = imx6_add_pcie_ep(imx6_pcie, pdev); 1445 if (ret < 0) 1446 return ret; 1447 } else { 1448 ret = dw_pcie_host_init(&pci->pp); 1449 if (ret < 0) 1450 return ret; 1451 1452 if (pci_msi_enabled()) { 1453 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); 1454 1455 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); 1456 val |= PCI_MSI_FLAGS_ENABLE; 1457 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); 1458 } 1459 } 1460 1461 return 0; 1462 } 1463 1464 static void imx6_pcie_shutdown(struct platform_device *pdev) 1465 { 1466 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); 1467 1468 /* bring down link, so bootloader gets clean state in case of reboot */ 1469 imx6_pcie_assert_core_reset(imx6_pcie); 1470 } 1471 1472 static const struct imx6_pcie_drvdata drvdata[] = { 1473 [IMX6Q] = { 1474 .variant = IMX6Q, 1475 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1476 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, 1477 .dbi_length = 0x200, 1478 .gpr = "fsl,imx6q-iomuxc-gpr", 1479 }, 1480 [IMX6SX] = { 1481 .variant = IMX6SX, 1482 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1483 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1484 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1485 .gpr = "fsl,imx6q-iomuxc-gpr", 1486 }, 1487 [IMX6QP] = { 1488 .variant = IMX6QP, 1489 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1490 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1491 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1492 .dbi_length = 0x200, 1493 .gpr = "fsl,imx6q-iomuxc-gpr", 1494 }, 1495 [IMX7D] = { 1496 .variant = IMX7D, 1497 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1498 .gpr = "fsl,imx7d-iomuxc-gpr", 1499 }, 1500 [IMX8MQ] = { 1501 .variant = IMX8MQ, 1502 .gpr = "fsl,imx8mq-iomuxc-gpr", 1503 }, 1504 [IMX8MM] = { 1505 .variant = IMX8MM, 1506 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1507 .gpr = "fsl,imx8mm-iomuxc-gpr", 1508 }, 1509 [IMX8MP] = { 1510 .variant = IMX8MP, 1511 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1512 .gpr = "fsl,imx8mp-iomuxc-gpr", 1513 }, 1514 [IMX8MQ_EP] = { 1515 .variant = IMX8MQ_EP, 1516 .mode = DW_PCIE_EP_TYPE, 1517 .gpr = "fsl,imx8mq-iomuxc-gpr", 1518 }, 1519 [IMX8MM_EP] = { 1520 .variant = IMX8MM_EP, 1521 .mode = DW_PCIE_EP_TYPE, 1522 .gpr = "fsl,imx8mm-iomuxc-gpr", 1523 }, 1524 [IMX8MP_EP] = { 1525 .variant = IMX8MP_EP, 1526 .mode = DW_PCIE_EP_TYPE, 1527 .gpr = "fsl,imx8mp-iomuxc-gpr", 1528 }, 1529 }; 1530 1531 static const struct of_device_id imx6_pcie_of_match[] = { 1532 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], }, 1533 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, 1534 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, 1535 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], }, 1536 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], }, 1537 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], }, 1538 { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], }, 1539 { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, 1540 { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, 1541 { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, 1542 {}, 1543 }; 1544 1545 static struct platform_driver imx6_pcie_driver = { 1546 .driver = { 1547 .name = "imx6q-pcie", 1548 .of_match_table = imx6_pcie_of_match, 1549 .suppress_bind_attrs = true, 1550 .pm = &imx6_pcie_pm_ops, 1551 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1552 }, 1553 .probe = imx6_pcie_probe, 1554 .shutdown = imx6_pcie_shutdown, 1555 }; 1556 1557 static void imx6_pcie_quirk(struct pci_dev *dev) 1558 { 1559 struct pci_bus *bus = dev->bus; 1560 struct dw_pcie_rp *pp = bus->sysdata; 1561 1562 /* Bus parent is the PCI bridge, its parent is this platform driver */ 1563 if (!bus->dev.parent || !bus->dev.parent->parent) 1564 return; 1565 1566 /* Make sure we only quirk devices associated with this driver */ 1567 if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) 1568 return; 1569 1570 if (pci_is_root_bus(bus)) { 1571 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1572 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 1573 1574 /* 1575 * Limit config length to avoid the kernel reading beyond 1576 * the register set and causing an abort on i.MX 6Quad 1577 */ 1578 if (imx6_pcie->drvdata->dbi_length) { 1579 dev->cfg_size = imx6_pcie->drvdata->dbi_length; 1580 dev_info(&dev->dev, "Limiting cfg_size to %d\n", 1581 dev->cfg_size); 1582 } 1583 } 1584 } 1585 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, 1586 PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk); 1587 1588 static int __init imx6_pcie_init(void) 1589 { 1590 #ifdef CONFIG_ARM 1591 struct device_node *np; 1592 1593 np = of_find_matching_node(NULL, imx6_pcie_of_match); 1594 if (!np) 1595 return -ENODEV; 1596 of_node_put(np); 1597 1598 /* 1599 * Since probe() can be deferred we need to make sure that 1600 * hook_fault_code is not called after __init memory is freed 1601 * by kernel and since imx6q_pcie_abort_handler() is a no-op, 1602 * we can install the handler here without risking it 1603 * accessing some uninitialized driver state. 1604 */ 1605 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0, 1606 "external abort on non-linefetch"); 1607 #endif 1608 1609 return platform_driver_register(&imx6_pcie_driver); 1610 } 1611 device_initcall(imx6_pcie_init); 1612