1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for UniPhier SoCs 4 * Copyright 2018 Socionext Inc. 5 * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/module.h> 17 #include <linux/of_irq.h> 18 #include <linux/pci.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 #include <linux/reset.h> 22 23 #include "pcie-designware.h" 24 25 #define PCL_PINCTRL0 0x002c 26 #define PCL_PERST_PLDN_REGEN BIT(12) 27 #define PCL_PERST_NOE_REGEN BIT(11) 28 #define PCL_PERST_OUT_REGEN BIT(8) 29 #define PCL_PERST_PLDN_REGVAL BIT(4) 30 #define PCL_PERST_NOE_REGVAL BIT(3) 31 #define PCL_PERST_OUT_REGVAL BIT(0) 32 33 #define PCL_PIPEMON 0x0044 34 #define PCL_PCLK_ALIVE BIT(15) 35 36 #define PCL_MODE 0x8000 37 #define PCL_MODE_REGEN BIT(8) 38 #define PCL_MODE_REGVAL BIT(0) 39 40 #define PCL_APP_READY_CTRL 0x8008 41 #define PCL_APP_LTSSM_ENABLE BIT(0) 42 43 #define PCL_APP_PM0 0x8078 44 #define PCL_SYS_AUX_PWR_DET BIT(8) 45 46 #define PCL_RCV_INT 0x8108 47 #define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17) 48 #define PCL_CFG_BW_MGT_STATUS BIT(4) 49 #define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3) 50 #define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2) 51 #define PCL_CFG_PME_MSI_STATUS BIT(1) 52 53 #define PCL_RCV_INTX 0x810c 54 #define PCL_RCV_INTX_ALL_ENABLE GENMASK(19, 16) 55 #define PCL_RCV_INTX_ALL_MASK GENMASK(11, 8) 56 #define PCL_RCV_INTX_MASK_SHIFT 8 57 #define PCL_RCV_INTX_ALL_STATUS GENMASK(3, 0) 58 #define PCL_RCV_INTX_STATUS_SHIFT 0 59 60 #define PCL_STATUS_LINK 0x8140 61 #define PCL_RDLH_LINK_UP BIT(1) 62 #define PCL_XMLH_LINK_UP BIT(0) 63 64 struct uniphier_pcie_priv { 65 void __iomem *base; 66 struct dw_pcie pci; 67 struct clk *clk; 68 struct reset_control *rst; 69 struct phy *phy; 70 struct irq_domain *legacy_irq_domain; 71 }; 72 73 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev) 74 75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv, 76 bool enable) 77 { 78 u32 val; 79 80 val = readl(priv->base + PCL_APP_READY_CTRL); 81 if (enable) 82 val |= PCL_APP_LTSSM_ENABLE; 83 else 84 val &= ~PCL_APP_LTSSM_ENABLE; 85 writel(val, priv->base + PCL_APP_READY_CTRL); 86 } 87 88 static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv) 89 { 90 u32 val; 91 92 /* set RC MODE */ 93 val = readl(priv->base + PCL_MODE); 94 val |= PCL_MODE_REGEN; 95 val &= ~PCL_MODE_REGVAL; 96 writel(val, priv->base + PCL_MODE); 97 98 /* use auxiliary power detection */ 99 val = readl(priv->base + PCL_APP_PM0); 100 val |= PCL_SYS_AUX_PWR_DET; 101 writel(val, priv->base + PCL_APP_PM0); 102 103 /* assert PERST# */ 104 val = readl(priv->base + PCL_PINCTRL0); 105 val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL 106 | PCL_PERST_PLDN_REGVAL); 107 val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN 108 | PCL_PERST_PLDN_REGEN; 109 writel(val, priv->base + PCL_PINCTRL0); 110 111 uniphier_pcie_ltssm_enable(priv, false); 112 113 usleep_range(100000, 200000); 114 115 /* deassert PERST# */ 116 val = readl(priv->base + PCL_PINCTRL0); 117 val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN; 118 writel(val, priv->base + PCL_PINCTRL0); 119 } 120 121 static int uniphier_pcie_wait_rc(struct uniphier_pcie_priv *priv) 122 { 123 u32 status; 124 int ret; 125 126 /* wait PIPE clock */ 127 ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status, 128 status & PCL_PCLK_ALIVE, 100000, 1000000); 129 if (ret) { 130 dev_err(priv->pci.dev, 131 "Failed to initialize controller in RC mode\n"); 132 return ret; 133 } 134 135 return 0; 136 } 137 138 static int uniphier_pcie_link_up(struct dw_pcie *pci) 139 { 140 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); 141 u32 val, mask; 142 143 val = readl(priv->base + PCL_STATUS_LINK); 144 mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP; 145 146 return (val & mask) == mask; 147 } 148 149 static int uniphier_pcie_establish_link(struct dw_pcie *pci) 150 { 151 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); 152 153 if (dw_pcie_link_up(pci)) 154 return 0; 155 156 uniphier_pcie_ltssm_enable(priv, true); 157 158 return dw_pcie_wait_for_link(pci); 159 } 160 161 static void uniphier_pcie_stop_link(struct dw_pcie *pci) 162 { 163 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); 164 165 uniphier_pcie_ltssm_enable(priv, false); 166 } 167 168 static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv) 169 { 170 writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT); 171 writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX); 172 } 173 174 static void uniphier_pcie_irq_disable(struct uniphier_pcie_priv *priv) 175 { 176 writel(0, priv->base + PCL_RCV_INT); 177 writel(0, priv->base + PCL_RCV_INTX); 178 } 179 180 static void uniphier_pcie_irq_ack(struct irq_data *d) 181 { 182 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 183 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 184 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); 185 u32 val; 186 187 val = readl(priv->base + PCL_RCV_INTX); 188 val &= ~PCL_RCV_INTX_ALL_STATUS; 189 val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT); 190 writel(val, priv->base + PCL_RCV_INTX); 191 } 192 193 static void uniphier_pcie_irq_mask(struct irq_data *d) 194 { 195 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 196 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 197 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); 198 u32 val; 199 200 val = readl(priv->base + PCL_RCV_INTX); 201 val &= ~PCL_RCV_INTX_ALL_MASK; 202 val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT); 203 writel(val, priv->base + PCL_RCV_INTX); 204 } 205 206 static void uniphier_pcie_irq_unmask(struct irq_data *d) 207 { 208 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 209 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 210 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); 211 u32 val; 212 213 val = readl(priv->base + PCL_RCV_INTX); 214 val &= ~PCL_RCV_INTX_ALL_MASK; 215 val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT); 216 writel(val, priv->base + PCL_RCV_INTX); 217 } 218 219 static struct irq_chip uniphier_pcie_irq_chip = { 220 .name = "PCI", 221 .irq_ack = uniphier_pcie_irq_ack, 222 .irq_mask = uniphier_pcie_irq_mask, 223 .irq_unmask = uniphier_pcie_irq_unmask, 224 }; 225 226 static int uniphier_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 227 irq_hw_number_t hwirq) 228 { 229 irq_set_chip_and_handler(irq, &uniphier_pcie_irq_chip, 230 handle_level_irq); 231 irq_set_chip_data(irq, domain->host_data); 232 233 return 0; 234 } 235 236 static const struct irq_domain_ops uniphier_intx_domain_ops = { 237 .map = uniphier_pcie_intx_map, 238 }; 239 240 static void uniphier_pcie_irq_handler(struct irq_desc *desc) 241 { 242 struct pcie_port *pp = irq_desc_get_handler_data(desc); 243 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 244 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); 245 struct irq_chip *chip = irq_desc_get_chip(desc); 246 unsigned long reg; 247 u32 val, bit, virq; 248 249 /* INT for debug */ 250 val = readl(priv->base + PCL_RCV_INT); 251 252 if (val & PCL_CFG_BW_MGT_STATUS) 253 dev_dbg(pci->dev, "Link Bandwidth Management Event\n"); 254 if (val & PCL_CFG_LINK_AUTO_BW_STATUS) 255 dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n"); 256 if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS) 257 dev_dbg(pci->dev, "Root Error\n"); 258 if (val & PCL_CFG_PME_MSI_STATUS) 259 dev_dbg(pci->dev, "PME Interrupt\n"); 260 261 writel(val, priv->base + PCL_RCV_INT); 262 263 /* INTx */ 264 chained_irq_enter(chip, desc); 265 266 val = readl(priv->base + PCL_RCV_INTX); 267 reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val); 268 269 for_each_set_bit(bit, ®, PCI_NUM_INTX) { 270 virq = irq_linear_revmap(priv->legacy_irq_domain, bit); 271 generic_handle_irq(virq); 272 } 273 274 chained_irq_exit(chip, desc); 275 } 276 277 static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp) 278 { 279 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 280 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); 281 struct device_node *np = pci->dev->of_node; 282 struct device_node *np_intc; 283 int ret = 0; 284 285 np_intc = of_get_child_by_name(np, "legacy-interrupt-controller"); 286 if (!np_intc) { 287 dev_err(pci->dev, "Failed to get legacy-interrupt-controller node\n"); 288 return -EINVAL; 289 } 290 291 pp->irq = irq_of_parse_and_map(np_intc, 0); 292 if (!pp->irq) { 293 dev_err(pci->dev, "Failed to get an IRQ entry in legacy-interrupt-controller\n"); 294 ret = -EINVAL; 295 goto out_put_node; 296 } 297 298 priv->legacy_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX, 299 &uniphier_intx_domain_ops, pp); 300 if (!priv->legacy_irq_domain) { 301 dev_err(pci->dev, "Failed to get INTx domain\n"); 302 ret = -ENODEV; 303 goto out_put_node; 304 } 305 306 irq_set_chained_handler_and_data(pp->irq, uniphier_pcie_irq_handler, 307 pp); 308 309 out_put_node: 310 of_node_put(np_intc); 311 return ret; 312 } 313 314 static int uniphier_pcie_host_init(struct pcie_port *pp) 315 { 316 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 317 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); 318 int ret; 319 320 ret = uniphier_pcie_config_legacy_irq(pp); 321 if (ret) 322 return ret; 323 324 uniphier_pcie_irq_enable(priv); 325 326 dw_pcie_setup_rc(pp); 327 ret = uniphier_pcie_establish_link(pci); 328 if (ret) 329 return ret; 330 331 if (IS_ENABLED(CONFIG_PCI_MSI)) 332 dw_pcie_msi_init(pp); 333 334 return 0; 335 } 336 337 static const struct dw_pcie_host_ops uniphier_pcie_host_ops = { 338 .host_init = uniphier_pcie_host_init, 339 }; 340 341 static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv, 342 struct platform_device *pdev) 343 { 344 struct dw_pcie *pci = &priv->pci; 345 struct pcie_port *pp = &pci->pp; 346 struct device *dev = &pdev->dev; 347 int ret; 348 349 pp->ops = &uniphier_pcie_host_ops; 350 351 if (IS_ENABLED(CONFIG_PCI_MSI)) { 352 pp->msi_irq = platform_get_irq_byname(pdev, "msi"); 353 if (pp->msi_irq < 0) 354 return pp->msi_irq; 355 } 356 357 ret = dw_pcie_host_init(pp); 358 if (ret) { 359 dev_err(dev, "Failed to initialize host (%d)\n", ret); 360 return ret; 361 } 362 363 return 0; 364 } 365 366 static int uniphier_pcie_host_enable(struct uniphier_pcie_priv *priv) 367 { 368 int ret; 369 370 ret = clk_prepare_enable(priv->clk); 371 if (ret) 372 return ret; 373 374 ret = reset_control_deassert(priv->rst); 375 if (ret) 376 goto out_clk_disable; 377 378 uniphier_pcie_init_rc(priv); 379 380 ret = phy_init(priv->phy); 381 if (ret) 382 goto out_rst_assert; 383 384 ret = uniphier_pcie_wait_rc(priv); 385 if (ret) 386 goto out_phy_exit; 387 388 return 0; 389 390 out_phy_exit: 391 phy_exit(priv->phy); 392 out_rst_assert: 393 reset_control_assert(priv->rst); 394 out_clk_disable: 395 clk_disable_unprepare(priv->clk); 396 397 return ret; 398 } 399 400 static void uniphier_pcie_host_disable(struct uniphier_pcie_priv *priv) 401 { 402 uniphier_pcie_irq_disable(priv); 403 phy_exit(priv->phy); 404 reset_control_assert(priv->rst); 405 clk_disable_unprepare(priv->clk); 406 } 407 408 static const struct dw_pcie_ops dw_pcie_ops = { 409 .start_link = uniphier_pcie_establish_link, 410 .stop_link = uniphier_pcie_stop_link, 411 .link_up = uniphier_pcie_link_up, 412 }; 413 414 static int uniphier_pcie_probe(struct platform_device *pdev) 415 { 416 struct device *dev = &pdev->dev; 417 struct uniphier_pcie_priv *priv; 418 struct resource *res; 419 int ret; 420 421 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 422 if (!priv) 423 return -ENOMEM; 424 425 priv->pci.dev = dev; 426 priv->pci.ops = &dw_pcie_ops; 427 428 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 429 priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res); 430 if (IS_ERR(priv->pci.dbi_base)) 431 return PTR_ERR(priv->pci.dbi_base); 432 433 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "link"); 434 priv->base = devm_ioremap_resource(dev, res); 435 if (IS_ERR(priv->base)) 436 return PTR_ERR(priv->base); 437 438 priv->clk = devm_clk_get(dev, NULL); 439 if (IS_ERR(priv->clk)) 440 return PTR_ERR(priv->clk); 441 442 priv->rst = devm_reset_control_get_shared(dev, NULL); 443 if (IS_ERR(priv->rst)) 444 return PTR_ERR(priv->rst); 445 446 priv->phy = devm_phy_optional_get(dev, "pcie-phy"); 447 if (IS_ERR(priv->phy)) 448 return PTR_ERR(priv->phy); 449 450 platform_set_drvdata(pdev, priv); 451 452 ret = uniphier_pcie_host_enable(priv); 453 if (ret) 454 return ret; 455 456 return uniphier_add_pcie_port(priv, pdev); 457 } 458 459 static int uniphier_pcie_remove(struct platform_device *pdev) 460 { 461 struct uniphier_pcie_priv *priv = platform_get_drvdata(pdev); 462 463 uniphier_pcie_host_disable(priv); 464 465 return 0; 466 } 467 468 static const struct of_device_id uniphier_pcie_match[] = { 469 { .compatible = "socionext,uniphier-pcie", }, 470 { /* sentinel */ }, 471 }; 472 MODULE_DEVICE_TABLE(of, uniphier_pcie_match); 473 474 static struct platform_driver uniphier_pcie_driver = { 475 .probe = uniphier_pcie_probe, 476 .remove = uniphier_pcie_remove, 477 .driver = { 478 .name = "uniphier-pcie", 479 .of_match_table = uniphier_pcie_match, 480 }, 481 }; 482 builtin_platform_driver(uniphier_pcie_driver); 483 484 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>"); 485 MODULE_DESCRIPTION("UniPhier PCIe host controller driver"); 486 MODULE_LICENSE("GPL v2"); 487