1f7821b49SLinus Walleij // SPDX-License-Identifier: GPL-2.0
2f7821b49SLinus Walleij /*
3f7821b49SLinus Walleij * Support for Intel IXP4xx PCI host controller
4f7821b49SLinus Walleij *
5f7821b49SLinus Walleij * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
6f7821b49SLinus Walleij *
7f7821b49SLinus Walleij * Based on the IXP4xx arch/arm/mach-ixp4xx/common-pci.c driver
8f7821b49SLinus Walleij * Copyright (C) 2002 Intel Corporation
9f7821b49SLinus Walleij * Copyright (C) 2003 Greg Ungerer <gerg@linux-m68k.org>
10f7821b49SLinus Walleij * Copyright (C) 2003-2004 MontaVista Software, Inc.
11f7821b49SLinus Walleij * Copyright (C) 2005 Deepak Saxena <dsaxena@plexity.net>
12f7821b49SLinus Walleij * Copyright (C) 2005 Alessandro Zummo <a.zummo@towertech.it>
13f7821b49SLinus Walleij *
14f7821b49SLinus Walleij * TODO:
15f7821b49SLinus Walleij * - Test IO-space access
16f7821b49SLinus Walleij * - DMA support
17f7821b49SLinus Walleij */
18f7821b49SLinus Walleij
19f7821b49SLinus Walleij #include <linux/init.h>
20f7821b49SLinus Walleij #include <linux/io.h>
21f7821b49SLinus Walleij #include <linux/kernel.h>
22*c925cfafSRob Herring #include <linux/of.h>
23f7821b49SLinus Walleij #include <linux/of_pci.h>
24f7821b49SLinus Walleij #include <linux/pci.h>
25f7821b49SLinus Walleij #include <linux/platform_device.h>
26f7821b49SLinus Walleij #include <linux/slab.h>
27f7821b49SLinus Walleij #include <linux/bits.h>
286c6fa1f3SPali Rohár #include "../pci.h"
29f7821b49SLinus Walleij
30f7821b49SLinus Walleij /* Register offsets */
31f7821b49SLinus Walleij #define IXP4XX_PCI_NP_AD 0x00
32f7821b49SLinus Walleij #define IXP4XX_PCI_NP_CBE 0x04
33f7821b49SLinus Walleij #define IXP4XX_PCI_NP_WDATA 0x08
34f7821b49SLinus Walleij #define IXP4XX_PCI_NP_RDATA 0x0c
35f7821b49SLinus Walleij #define IXP4XX_PCI_CRP_AD_CBE 0x10
36f7821b49SLinus Walleij #define IXP4XX_PCI_CRP_WDATA 0x14
37f7821b49SLinus Walleij #define IXP4XX_PCI_CRP_RDATA 0x18
38f7821b49SLinus Walleij #define IXP4XX_PCI_CSR 0x1c
39f7821b49SLinus Walleij #define IXP4XX_PCI_ISR 0x20
40f7821b49SLinus Walleij #define IXP4XX_PCI_INTEN 0x24
41f7821b49SLinus Walleij #define IXP4XX_PCI_DMACTRL 0x28
42f7821b49SLinus Walleij #define IXP4XX_PCI_AHBMEMBASE 0x2c
43f7821b49SLinus Walleij #define IXP4XX_PCI_AHBIOBASE 0x30
44f7821b49SLinus Walleij #define IXP4XX_PCI_PCIMEMBASE 0x34
45f7821b49SLinus Walleij #define IXP4XX_PCI_AHBDOORBELL 0x38
46f7821b49SLinus Walleij #define IXP4XX_PCI_PCIDOORBELL 0x3c
47f7821b49SLinus Walleij #define IXP4XX_PCI_ATPDMA0_AHBADDR 0x40
48f7821b49SLinus Walleij #define IXP4XX_PCI_ATPDMA0_PCIADDR 0x44
49f7821b49SLinus Walleij #define IXP4XX_PCI_ATPDMA0_LENADDR 0x48
50f7821b49SLinus Walleij #define IXP4XX_PCI_ATPDMA1_AHBADDR 0x4c
51f7821b49SLinus Walleij #define IXP4XX_PCI_ATPDMA1_PCIADDR 0x50
52f7821b49SLinus Walleij #define IXP4XX_PCI_ATPDMA1_LENADDR 0x54
53f7821b49SLinus Walleij
54f7821b49SLinus Walleij /* CSR bit definitions */
55f7821b49SLinus Walleij #define IXP4XX_PCI_CSR_HOST BIT(0)
56f7821b49SLinus Walleij #define IXP4XX_PCI_CSR_ARBEN BIT(1)
57f7821b49SLinus Walleij #define IXP4XX_PCI_CSR_ADS BIT(2)
58f7821b49SLinus Walleij #define IXP4XX_PCI_CSR_PDS BIT(3)
59f7821b49SLinus Walleij #define IXP4XX_PCI_CSR_ABE BIT(4)
60f7821b49SLinus Walleij #define IXP4XX_PCI_CSR_DBT BIT(5)
61f7821b49SLinus Walleij #define IXP4XX_PCI_CSR_ASE BIT(8)
62f7821b49SLinus Walleij #define IXP4XX_PCI_CSR_IC BIT(15)
63f7821b49SLinus Walleij #define IXP4XX_PCI_CSR_PRST BIT(16)
64f7821b49SLinus Walleij
65f7821b49SLinus Walleij /* ISR (Interrupt status) Register bit definitions */
66f7821b49SLinus Walleij #define IXP4XX_PCI_ISR_PSE BIT(0)
67f7821b49SLinus Walleij #define IXP4XX_PCI_ISR_PFE BIT(1)
68f7821b49SLinus Walleij #define IXP4XX_PCI_ISR_PPE BIT(2)
69f7821b49SLinus Walleij #define IXP4XX_PCI_ISR_AHBE BIT(3)
70f7821b49SLinus Walleij #define IXP4XX_PCI_ISR_APDC BIT(4)
71f7821b49SLinus Walleij #define IXP4XX_PCI_ISR_PADC BIT(5)
72f7821b49SLinus Walleij #define IXP4XX_PCI_ISR_ADB BIT(6)
73f7821b49SLinus Walleij #define IXP4XX_PCI_ISR_PDB BIT(7)
74f7821b49SLinus Walleij
75f7821b49SLinus Walleij /* INTEN (Interrupt Enable) Register bit definitions */
76f7821b49SLinus Walleij #define IXP4XX_PCI_INTEN_PSE BIT(0)
77f7821b49SLinus Walleij #define IXP4XX_PCI_INTEN_PFE BIT(1)
78f7821b49SLinus Walleij #define IXP4XX_PCI_INTEN_PPE BIT(2)
79f7821b49SLinus Walleij #define IXP4XX_PCI_INTEN_AHBE BIT(3)
80f7821b49SLinus Walleij #define IXP4XX_PCI_INTEN_APDC BIT(4)
81f7821b49SLinus Walleij #define IXP4XX_PCI_INTEN_PADC BIT(5)
82f7821b49SLinus Walleij #define IXP4XX_PCI_INTEN_ADB BIT(6)
83f7821b49SLinus Walleij #define IXP4XX_PCI_INTEN_PDB BIT(7)
84f7821b49SLinus Walleij
85f7821b49SLinus Walleij /* Shift value for byte enable on NP cmd/byte enable register */
86f7821b49SLinus Walleij #define IXP4XX_PCI_NP_CBE_BESL 4
87f7821b49SLinus Walleij
88f7821b49SLinus Walleij /* PCI commands supported by NP access unit */
89f7821b49SLinus Walleij #define NP_CMD_IOREAD 0x2
90f7821b49SLinus Walleij #define NP_CMD_IOWRITE 0x3
91f7821b49SLinus Walleij #define NP_CMD_CONFIGREAD 0xa
92f7821b49SLinus Walleij #define NP_CMD_CONFIGWRITE 0xb
93f7821b49SLinus Walleij #define NP_CMD_MEMREAD 0x6
94f7821b49SLinus Walleij #define NP_CMD_MEMWRITE 0x7
95f7821b49SLinus Walleij
96f7821b49SLinus Walleij /* Constants for CRP access into local config space */
97f7821b49SLinus Walleij #define CRP_AD_CBE_BESL 20
98f7821b49SLinus Walleij #define CRP_AD_CBE_WRITE 0x00010000
99f7821b49SLinus Walleij
100f7821b49SLinus Walleij /* Special PCI configuration space registers for this controller */
101f7821b49SLinus Walleij #define IXP4XX_PCI_RTOTTO 0x40
102f7821b49SLinus Walleij
103f7821b49SLinus Walleij struct ixp4xx_pci {
104f7821b49SLinus Walleij struct device *dev;
105f7821b49SLinus Walleij void __iomem *base;
106f7821b49SLinus Walleij bool errata_hammer;
107f7821b49SLinus Walleij bool host_mode;
108f7821b49SLinus Walleij };
109f7821b49SLinus Walleij
110f7821b49SLinus Walleij /*
111f7821b49SLinus Walleij * The IXP4xx has a peculiar address bus that will change the
112f7821b49SLinus Walleij * byte order on SoC peripherals depending on whether the device
113f7821b49SLinus Walleij * operates in big-endian or little-endian mode. That means that
114f7821b49SLinus Walleij * readl() and writel() that always use little-endian access
115f7821b49SLinus Walleij * will not work for SoC peripherals such as the PCI controller
116f7821b49SLinus Walleij * when used in big-endian mode. The accesses to the individual
117f7821b49SLinus Walleij * PCI devices on the other hand, are always little-endian and
118f7821b49SLinus Walleij * can use readl() and writel().
119f7821b49SLinus Walleij *
120f7821b49SLinus Walleij * For local AHB bus access we need to use __raw_[readl|writel]()
121f7821b49SLinus Walleij * to make sure that we access the SoC devices in the CPU native
122f7821b49SLinus Walleij * endianness.
123f7821b49SLinus Walleij */
ixp4xx_readl(struct ixp4xx_pci * p,u32 reg)124f7821b49SLinus Walleij static inline u32 ixp4xx_readl(struct ixp4xx_pci *p, u32 reg)
125f7821b49SLinus Walleij {
126f7821b49SLinus Walleij return __raw_readl(p->base + reg);
127f7821b49SLinus Walleij }
128f7821b49SLinus Walleij
ixp4xx_writel(struct ixp4xx_pci * p,u32 reg,u32 val)129f7821b49SLinus Walleij static inline void ixp4xx_writel(struct ixp4xx_pci *p, u32 reg, u32 val)
130f7821b49SLinus Walleij {
131f7821b49SLinus Walleij __raw_writel(val, p->base + reg);
132f7821b49SLinus Walleij }
133f7821b49SLinus Walleij
ixp4xx_pci_check_master_abort(struct ixp4xx_pci * p)134f7821b49SLinus Walleij static int ixp4xx_pci_check_master_abort(struct ixp4xx_pci *p)
135f7821b49SLinus Walleij {
136f7821b49SLinus Walleij u32 isr = ixp4xx_readl(p, IXP4XX_PCI_ISR);
137f7821b49SLinus Walleij
138f7821b49SLinus Walleij if (isr & IXP4XX_PCI_ISR_PFE) {
139f7821b49SLinus Walleij /* Make sure the master abort bit is reset */
140f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE);
141f7821b49SLinus Walleij dev_dbg(p->dev, "master abort detected\n");
142f7821b49SLinus Walleij return -EINVAL;
143f7821b49SLinus Walleij }
144f7821b49SLinus Walleij
145f7821b49SLinus Walleij return 0;
146f7821b49SLinus Walleij }
147f7821b49SLinus Walleij
ixp4xx_pci_read_indirect(struct ixp4xx_pci * p,u32 addr,u32 cmd,u32 * data)148cbfece75SArnd Bergmann static int ixp4xx_pci_read_indirect(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 *data)
149f7821b49SLinus Walleij {
150f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr);
151f7821b49SLinus Walleij
152f7821b49SLinus Walleij if (p->errata_hammer) {
153f7821b49SLinus Walleij int i;
154f7821b49SLinus Walleij
155f7821b49SLinus Walleij /*
156f7821b49SLinus Walleij * PCI workaround - only works if NP PCI space reads have
157f7821b49SLinus Walleij * no side effects. Hammer the register and read twice 8
158f7821b49SLinus Walleij * times. last one will be good.
159f7821b49SLinus Walleij */
160f7821b49SLinus Walleij for (i = 0; i < 8; i++) {
161f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd);
162f7821b49SLinus Walleij *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA);
163f7821b49SLinus Walleij *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA);
164f7821b49SLinus Walleij }
165f7821b49SLinus Walleij } else {
166f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd);
167f7821b49SLinus Walleij *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA);
168f7821b49SLinus Walleij }
169f7821b49SLinus Walleij
170f7821b49SLinus Walleij return ixp4xx_pci_check_master_abort(p);
171f7821b49SLinus Walleij }
172f7821b49SLinus Walleij
ixp4xx_pci_write_indirect(struct ixp4xx_pci * p,u32 addr,u32 cmd,u32 data)173cbfece75SArnd Bergmann static int ixp4xx_pci_write_indirect(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 data)
174f7821b49SLinus Walleij {
175f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr);
176f7821b49SLinus Walleij
177f7821b49SLinus Walleij /* Set up the write */
178f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd);
179f7821b49SLinus Walleij
180f7821b49SLinus Walleij /* Execute the write by writing to NP_WDATA */
181f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_NP_WDATA, data);
182f7821b49SLinus Walleij
183f7821b49SLinus Walleij return ixp4xx_pci_check_master_abort(p);
184f7821b49SLinus Walleij }
185f7821b49SLinus Walleij
ixp4xx_config_addr(u8 bus_num,u16 devfn,int where)186f7821b49SLinus Walleij static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
187f7821b49SLinus Walleij {
188f7821b49SLinus Walleij /* Root bus is always 0 in this hardware */
189f7821b49SLinus Walleij if (bus_num == 0) {
190f7821b49SLinus Walleij /* type 0 */
1916c6fa1f3SPali Rohár return (PCI_CONF1_ADDRESS(0, 0, PCI_FUNC(devfn), where) &
1926c6fa1f3SPali Rohár ~PCI_CONF1_ENABLE) | BIT(32-PCI_SLOT(devfn));
193f7821b49SLinus Walleij } else {
194f7821b49SLinus Walleij /* type 1 */
1956c6fa1f3SPali Rohár return (PCI_CONF1_ADDRESS(bus_num, PCI_SLOT(devfn),
1966c6fa1f3SPali Rohár PCI_FUNC(devfn), where) &
1976c6fa1f3SPali Rohár ~PCI_CONF1_ENABLE) | 1;
198f7821b49SLinus Walleij }
199f7821b49SLinus Walleij }
200f7821b49SLinus Walleij
201f7821b49SLinus Walleij /*
202f7821b49SLinus Walleij * CRP functions are "Controller Configuration Port" accesses
203f7821b49SLinus Walleij * initiated from within this driver itself to read/write PCI
204f7821b49SLinus Walleij * control information in the config space.
205f7821b49SLinus Walleij */
ixp4xx_crp_byte_lane_enable_bits(u32 n,int size)206f7821b49SLinus Walleij static u32 ixp4xx_crp_byte_lane_enable_bits(u32 n, int size)
207f7821b49SLinus Walleij {
208f7821b49SLinus Walleij if (size == 1)
209f7821b49SLinus Walleij return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
210f7821b49SLinus Walleij if (size == 2)
211f7821b49SLinus Walleij return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
212f7821b49SLinus Walleij if (size == 4)
213f7821b49SLinus Walleij return 0;
214f7821b49SLinus Walleij return 0xffffffff;
215f7821b49SLinus Walleij }
216f7821b49SLinus Walleij
ixp4xx_crp_read_config(struct ixp4xx_pci * p,int where,int size,u32 * value)217f7821b49SLinus Walleij static int ixp4xx_crp_read_config(struct ixp4xx_pci *p, int where, int size,
218f7821b49SLinus Walleij u32 *value)
219f7821b49SLinus Walleij {
220f7821b49SLinus Walleij u32 n, cmd, val;
221f7821b49SLinus Walleij
222f7821b49SLinus Walleij n = where % 4;
223f7821b49SLinus Walleij cmd = where & ~3;
224f7821b49SLinus Walleij
225f7821b49SLinus Walleij dev_dbg(p->dev, "%s from %d size %d cmd %08x\n",
226f7821b49SLinus Walleij __func__, where, size, cmd);
227f7821b49SLinus Walleij
228f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd);
229f7821b49SLinus Walleij val = ixp4xx_readl(p, IXP4XX_PCI_CRP_RDATA);
230f7821b49SLinus Walleij
231f7821b49SLinus Walleij val >>= (8*n);
232f7821b49SLinus Walleij switch (size) {
233f7821b49SLinus Walleij case 1:
234f7821b49SLinus Walleij val &= U8_MAX;
235f7821b49SLinus Walleij dev_dbg(p->dev, "%s read byte %02x\n", __func__, val);
236f7821b49SLinus Walleij break;
237f7821b49SLinus Walleij case 2:
238f7821b49SLinus Walleij val &= U16_MAX;
239f7821b49SLinus Walleij dev_dbg(p->dev, "%s read word %04x\n", __func__, val);
240f7821b49SLinus Walleij break;
241f7821b49SLinus Walleij case 4:
242f7821b49SLinus Walleij val &= U32_MAX;
243f7821b49SLinus Walleij dev_dbg(p->dev, "%s read long %08x\n", __func__, val);
244f7821b49SLinus Walleij break;
245f7821b49SLinus Walleij default:
246f7821b49SLinus Walleij /* Should not happen */
247f7821b49SLinus Walleij dev_err(p->dev, "%s illegal size\n", __func__);
248f7821b49SLinus Walleij return PCIBIOS_DEVICE_NOT_FOUND;
249f7821b49SLinus Walleij }
250f7821b49SLinus Walleij *value = val;
251f7821b49SLinus Walleij
252f7821b49SLinus Walleij return PCIBIOS_SUCCESSFUL;
253f7821b49SLinus Walleij }
254f7821b49SLinus Walleij
ixp4xx_crp_write_config(struct ixp4xx_pci * p,int where,int size,u32 value)255f7821b49SLinus Walleij static int ixp4xx_crp_write_config(struct ixp4xx_pci *p, int where, int size,
256f7821b49SLinus Walleij u32 value)
257f7821b49SLinus Walleij {
258f7821b49SLinus Walleij u32 n, cmd, val;
259f7821b49SLinus Walleij
260f7821b49SLinus Walleij n = where % 4;
261f7821b49SLinus Walleij cmd = ixp4xx_crp_byte_lane_enable_bits(n, size);
262f7821b49SLinus Walleij if (cmd == 0xffffffff)
263f7821b49SLinus Walleij return PCIBIOS_BAD_REGISTER_NUMBER;
264f7821b49SLinus Walleij cmd |= where & ~3;
265f7821b49SLinus Walleij cmd |= CRP_AD_CBE_WRITE;
266f7821b49SLinus Walleij
267f7821b49SLinus Walleij val = value << (8*n);
268f7821b49SLinus Walleij
269f7821b49SLinus Walleij dev_dbg(p->dev, "%s to %d size %d cmd %08x val %08x\n",
270f7821b49SLinus Walleij __func__, where, size, cmd, val);
271f7821b49SLinus Walleij
272f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd);
273f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_CRP_WDATA, val);
274f7821b49SLinus Walleij
275f7821b49SLinus Walleij return PCIBIOS_SUCCESSFUL;
276f7821b49SLinus Walleij }
277f7821b49SLinus Walleij
278f7821b49SLinus Walleij /*
279f7821b49SLinus Walleij * Then follows the functions that read and write from the common PCI
280f7821b49SLinus Walleij * configuration space.
281f7821b49SLinus Walleij */
ixp4xx_byte_lane_enable_bits(u32 n,int size)282f7821b49SLinus Walleij static u32 ixp4xx_byte_lane_enable_bits(u32 n, int size)
283f7821b49SLinus Walleij {
284f7821b49SLinus Walleij if (size == 1)
285f7821b49SLinus Walleij return (0xf & ~BIT(n)) << 4;
286f7821b49SLinus Walleij if (size == 2)
287f7821b49SLinus Walleij return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
288f7821b49SLinus Walleij if (size == 4)
289f7821b49SLinus Walleij return 0;
290f7821b49SLinus Walleij return 0xffffffff;
291f7821b49SLinus Walleij }
292f7821b49SLinus Walleij
ixp4xx_pci_read_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)293f7821b49SLinus Walleij static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
294f7821b49SLinus Walleij int where, int size, u32 *value)
295f7821b49SLinus Walleij {
296f7821b49SLinus Walleij struct ixp4xx_pci *p = bus->sysdata;
297f7821b49SLinus Walleij u32 n, addr, val, cmd;
298f7821b49SLinus Walleij u8 bus_num = bus->number;
299f7821b49SLinus Walleij int ret;
300f7821b49SLinus Walleij
301f7821b49SLinus Walleij *value = 0xffffffff;
302f7821b49SLinus Walleij n = where % 4;
303f7821b49SLinus Walleij cmd = ixp4xx_byte_lane_enable_bits(n, size);
304f7821b49SLinus Walleij if (cmd == 0xffffffff)
305f7821b49SLinus Walleij return PCIBIOS_BAD_REGISTER_NUMBER;
306f7821b49SLinus Walleij
307f7821b49SLinus Walleij addr = ixp4xx_config_addr(bus_num, devfn, where);
308f7821b49SLinus Walleij cmd |= NP_CMD_CONFIGREAD;
309f7821b49SLinus Walleij dev_dbg(p->dev, "read_config from %d size %d dev %d:%d:%d address: %08x cmd: %08x\n",
310f7821b49SLinus Walleij where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd);
311f7821b49SLinus Walleij
312cbfece75SArnd Bergmann ret = ixp4xx_pci_read_indirect(p, addr, cmd, &val);
313f7821b49SLinus Walleij if (ret)
314f7821b49SLinus Walleij return PCIBIOS_DEVICE_NOT_FOUND;
315f7821b49SLinus Walleij
316f7821b49SLinus Walleij val >>= (8*n);
317f7821b49SLinus Walleij switch (size) {
318f7821b49SLinus Walleij case 1:
319f7821b49SLinus Walleij val &= U8_MAX;
320f7821b49SLinus Walleij dev_dbg(p->dev, "%s read byte %02x\n", __func__, val);
321f7821b49SLinus Walleij break;
322f7821b49SLinus Walleij case 2:
323f7821b49SLinus Walleij val &= U16_MAX;
324f7821b49SLinus Walleij dev_dbg(p->dev, "%s read word %04x\n", __func__, val);
325f7821b49SLinus Walleij break;
326f7821b49SLinus Walleij case 4:
327f7821b49SLinus Walleij val &= U32_MAX;
328f7821b49SLinus Walleij dev_dbg(p->dev, "%s read long %08x\n", __func__, val);
329f7821b49SLinus Walleij break;
330f7821b49SLinus Walleij default:
331f7821b49SLinus Walleij /* Should not happen */
332f7821b49SLinus Walleij dev_err(p->dev, "%s illegal size\n", __func__);
333f7821b49SLinus Walleij return PCIBIOS_DEVICE_NOT_FOUND;
334f7821b49SLinus Walleij }
335f7821b49SLinus Walleij *value = val;
336f7821b49SLinus Walleij
337f7821b49SLinus Walleij return PCIBIOS_SUCCESSFUL;
338f7821b49SLinus Walleij }
339f7821b49SLinus Walleij
ixp4xx_pci_write_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)340f7821b49SLinus Walleij static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
341f7821b49SLinus Walleij int where, int size, u32 value)
342f7821b49SLinus Walleij {
343f7821b49SLinus Walleij struct ixp4xx_pci *p = bus->sysdata;
344f7821b49SLinus Walleij u32 n, addr, val, cmd;
345f7821b49SLinus Walleij u8 bus_num = bus->number;
346f7821b49SLinus Walleij int ret;
347f7821b49SLinus Walleij
348f7821b49SLinus Walleij n = where % 4;
349f7821b49SLinus Walleij cmd = ixp4xx_byte_lane_enable_bits(n, size);
350f7821b49SLinus Walleij if (cmd == 0xffffffff)
351f7821b49SLinus Walleij return PCIBIOS_BAD_REGISTER_NUMBER;
352f7821b49SLinus Walleij
353f7821b49SLinus Walleij addr = ixp4xx_config_addr(bus_num, devfn, where);
354f7821b49SLinus Walleij cmd |= NP_CMD_CONFIGWRITE;
355f7821b49SLinus Walleij val = value << (8*n);
356f7821b49SLinus Walleij
357f7821b49SLinus Walleij dev_dbg(p->dev, "write_config_byte %#x to %d size %d dev %d:%d:%d addr: %08x cmd %08x\n",
358f7821b49SLinus Walleij value, where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd);
359f7821b49SLinus Walleij
360cbfece75SArnd Bergmann ret = ixp4xx_pci_write_indirect(p, addr, cmd, val);
361f7821b49SLinus Walleij if (ret)
362f7821b49SLinus Walleij return PCIBIOS_DEVICE_NOT_FOUND;
363f7821b49SLinus Walleij
364f7821b49SLinus Walleij return PCIBIOS_SUCCESSFUL;
365f7821b49SLinus Walleij }
366f7821b49SLinus Walleij
367f7821b49SLinus Walleij static struct pci_ops ixp4xx_pci_ops = {
368f7821b49SLinus Walleij .read = ixp4xx_pci_read_config,
369f7821b49SLinus Walleij .write = ixp4xx_pci_write_config,
370f7821b49SLinus Walleij };
371f7821b49SLinus Walleij
ixp4xx_pci_addr_to_64mconf(phys_addr_t addr)372f7821b49SLinus Walleij static u32 ixp4xx_pci_addr_to_64mconf(phys_addr_t addr)
373f7821b49SLinus Walleij {
374f7821b49SLinus Walleij u8 base;
375f7821b49SLinus Walleij
376f7821b49SLinus Walleij base = ((addr & 0xff000000) >> 24);
377f7821b49SLinus Walleij return (base << 24) | ((base + 1) << 16)
378f7821b49SLinus Walleij | ((base + 2) << 8) | (base + 3);
379f7821b49SLinus Walleij }
380f7821b49SLinus Walleij
ixp4xx_pci_parse_map_ranges(struct ixp4xx_pci * p)381f7821b49SLinus Walleij static int ixp4xx_pci_parse_map_ranges(struct ixp4xx_pci *p)
382f7821b49SLinus Walleij {
383f7821b49SLinus Walleij struct device *dev = p->dev;
384f7821b49SLinus Walleij struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p);
385f7821b49SLinus Walleij struct resource_entry *win;
386f7821b49SLinus Walleij struct resource *res;
387f7821b49SLinus Walleij phys_addr_t addr;
388f7821b49SLinus Walleij
389f7821b49SLinus Walleij win = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
390f7821b49SLinus Walleij if (win) {
391f7821b49SLinus Walleij u32 pcimembase;
392f7821b49SLinus Walleij
393f7821b49SLinus Walleij res = win->res;
394f7821b49SLinus Walleij addr = res->start - win->offset;
395f7821b49SLinus Walleij
396f7821b49SLinus Walleij if (res->flags & IORESOURCE_PREFETCH)
397f7821b49SLinus Walleij res->name = "IXP4xx PCI PRE-MEM";
398f7821b49SLinus Walleij else
399f7821b49SLinus Walleij res->name = "IXP4xx PCI NON-PRE-MEM";
400f7821b49SLinus Walleij
401f7821b49SLinus Walleij dev_dbg(dev, "%s window %pR, bus addr %pa\n",
402f7821b49SLinus Walleij res->name, res, &addr);
403f7821b49SLinus Walleij if (resource_size(res) != SZ_64M) {
404f7821b49SLinus Walleij dev_err(dev, "memory range is not 64MB\n");
405f7821b49SLinus Walleij return -EINVAL;
406f7821b49SLinus Walleij }
407f7821b49SLinus Walleij
408f7821b49SLinus Walleij pcimembase = ixp4xx_pci_addr_to_64mconf(addr);
409f7821b49SLinus Walleij /* Commit configuration */
410f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_PCIMEMBASE, pcimembase);
411f7821b49SLinus Walleij } else {
412f7821b49SLinus Walleij dev_err(dev, "no AHB memory mapping defined\n");
413f7821b49SLinus Walleij }
414f7821b49SLinus Walleij
415f7821b49SLinus Walleij win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
416f7821b49SLinus Walleij if (win) {
417f7821b49SLinus Walleij res = win->res;
418f7821b49SLinus Walleij
419f7821b49SLinus Walleij addr = pci_pio_to_address(res->start);
420f7821b49SLinus Walleij if (addr & 0xff) {
421f7821b49SLinus Walleij dev_err(dev, "IO mem at uneven address: %pa\n", &addr);
422f7821b49SLinus Walleij return -EINVAL;
423f7821b49SLinus Walleij }
424f7821b49SLinus Walleij
425f7821b49SLinus Walleij res->name = "IXP4xx PCI IO MEM";
426f7821b49SLinus Walleij /*
427f7821b49SLinus Walleij * Setup I/O space location for PCI->AHB access, the
428f7821b49SLinus Walleij * upper 24 bits of the address goes into the lower
429f7821b49SLinus Walleij * 24 bits of this register.
430f7821b49SLinus Walleij */
431f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_AHBIOBASE, (addr >> 8));
432f7821b49SLinus Walleij } else {
433f7821b49SLinus Walleij dev_info(dev, "no IO space AHB memory mapping defined\n");
434f7821b49SLinus Walleij }
435f7821b49SLinus Walleij
436f7821b49SLinus Walleij return 0;
437f7821b49SLinus Walleij }
438f7821b49SLinus Walleij
ixp4xx_pci_parse_map_dma_ranges(struct ixp4xx_pci * p)439f7821b49SLinus Walleij static int ixp4xx_pci_parse_map_dma_ranges(struct ixp4xx_pci *p)
440f7821b49SLinus Walleij {
441f7821b49SLinus Walleij struct device *dev = p->dev;
442f7821b49SLinus Walleij struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p);
443f7821b49SLinus Walleij struct resource_entry *win;
444f7821b49SLinus Walleij struct resource *res;
445f7821b49SLinus Walleij phys_addr_t addr;
446f7821b49SLinus Walleij u32 ahbmembase;
447f7821b49SLinus Walleij
448f7821b49SLinus Walleij win = resource_list_first_type(&bridge->dma_ranges, IORESOURCE_MEM);
449f7821b49SLinus Walleij if (win) {
450f7821b49SLinus Walleij res = win->res;
451f7821b49SLinus Walleij addr = res->start - win->offset;
452f7821b49SLinus Walleij
453f7821b49SLinus Walleij if (resource_size(res) != SZ_64M) {
454f7821b49SLinus Walleij dev_err(dev, "DMA memory range is not 64MB\n");
455f7821b49SLinus Walleij return -EINVAL;
456f7821b49SLinus Walleij }
457f7821b49SLinus Walleij
458f7821b49SLinus Walleij dev_dbg(dev, "DMA MEM BASE: %pa\n", &addr);
459f7821b49SLinus Walleij /*
460f7821b49SLinus Walleij * 4 PCI-to-AHB windows of 16 MB each, write the 8 high bits
461f7821b49SLinus Walleij * into each byte of the PCI_AHBMEMBASE register.
462f7821b49SLinus Walleij */
463f7821b49SLinus Walleij ahbmembase = ixp4xx_pci_addr_to_64mconf(addr);
464f7821b49SLinus Walleij /* Commit AHB membase */
465f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_AHBMEMBASE, ahbmembase);
466f7821b49SLinus Walleij } else {
467f7821b49SLinus Walleij dev_err(dev, "no DMA memory range defined\n");
468f7821b49SLinus Walleij }
469f7821b49SLinus Walleij
470f7821b49SLinus Walleij return 0;
471f7821b49SLinus Walleij }
472f7821b49SLinus Walleij
473f7821b49SLinus Walleij /* Only used to get context for abort handling */
474f7821b49SLinus Walleij static struct ixp4xx_pci *ixp4xx_pci_abort_singleton;
475f7821b49SLinus Walleij
ixp4xx_pci_abort_handler(unsigned long addr,unsigned int fsr,struct pt_regs * regs)476f7821b49SLinus Walleij static int ixp4xx_pci_abort_handler(unsigned long addr, unsigned int fsr,
477f7821b49SLinus Walleij struct pt_regs *regs)
478f7821b49SLinus Walleij {
479f7821b49SLinus Walleij struct ixp4xx_pci *p = ixp4xx_pci_abort_singleton;
480f7821b49SLinus Walleij u32 isr, status;
481f7821b49SLinus Walleij int ret;
482f7821b49SLinus Walleij
483f7821b49SLinus Walleij isr = ixp4xx_readl(p, IXP4XX_PCI_ISR);
484f7821b49SLinus Walleij ret = ixp4xx_crp_read_config(p, PCI_STATUS, 2, &status);
485f7821b49SLinus Walleij if (ret) {
486f7821b49SLinus Walleij dev_err(p->dev, "unable to read abort status\n");
487f7821b49SLinus Walleij return -EINVAL;
488f7821b49SLinus Walleij }
489f7821b49SLinus Walleij
490f7821b49SLinus Walleij dev_err(p->dev,
491f7821b49SLinus Walleij "PCI: abort_handler addr = %#lx, isr = %#x, status = %#x\n",
492f7821b49SLinus Walleij addr, isr, status);
493f7821b49SLinus Walleij
494f7821b49SLinus Walleij /* Make sure the Master Abort bit is reset */
495f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE);
496f7821b49SLinus Walleij status |= PCI_STATUS_REC_MASTER_ABORT;
497f7821b49SLinus Walleij ret = ixp4xx_crp_write_config(p, PCI_STATUS, 2, status);
498f7821b49SLinus Walleij if (ret)
499f7821b49SLinus Walleij dev_err(p->dev, "unable to clear abort status bit\n");
500f7821b49SLinus Walleij
501f7821b49SLinus Walleij /*
502f7821b49SLinus Walleij * If it was an imprecise abort, then we need to correct the
503f7821b49SLinus Walleij * return address to be _after_ the instruction.
504f7821b49SLinus Walleij */
505f7821b49SLinus Walleij if (fsr & (1 << 10)) {
506f7821b49SLinus Walleij dev_err(p->dev, "imprecise abort\n");
507f7821b49SLinus Walleij regs->ARM_pc += 4;
508f7821b49SLinus Walleij }
509f7821b49SLinus Walleij
510f7821b49SLinus Walleij return 0;
511f7821b49SLinus Walleij }
512f7821b49SLinus Walleij
ixp4xx_pci_probe(struct platform_device * pdev)513f7821b49SLinus Walleij static int __init ixp4xx_pci_probe(struct platform_device *pdev)
514f7821b49SLinus Walleij {
515f7821b49SLinus Walleij struct device *dev = &pdev->dev;
516f7821b49SLinus Walleij struct device_node *np = dev->of_node;
517f7821b49SLinus Walleij struct ixp4xx_pci *p;
518f7821b49SLinus Walleij struct pci_host_bridge *host;
519f7821b49SLinus Walleij int ret;
520f7821b49SLinus Walleij u32 val;
521f7821b49SLinus Walleij phys_addr_t addr;
522f7821b49SLinus Walleij u32 basereg[4] = {
523f7821b49SLinus Walleij PCI_BASE_ADDRESS_0,
524f7821b49SLinus Walleij PCI_BASE_ADDRESS_1,
525f7821b49SLinus Walleij PCI_BASE_ADDRESS_2,
526f7821b49SLinus Walleij PCI_BASE_ADDRESS_3,
527f7821b49SLinus Walleij };
528f7821b49SLinus Walleij int i;
529f7821b49SLinus Walleij
530f7821b49SLinus Walleij host = devm_pci_alloc_host_bridge(dev, sizeof(*p));
531f7821b49SLinus Walleij if (!host)
532f7821b49SLinus Walleij return -ENOMEM;
533f7821b49SLinus Walleij
534f7821b49SLinus Walleij host->ops = &ixp4xx_pci_ops;
535f7821b49SLinus Walleij p = pci_host_bridge_priv(host);
536f7821b49SLinus Walleij host->sysdata = p;
537f7821b49SLinus Walleij p->dev = dev;
538f7821b49SLinus Walleij dev_set_drvdata(dev, p);
539f7821b49SLinus Walleij
540f7821b49SLinus Walleij /*
541f7821b49SLinus Walleij * Set up quirk for erratic behaviour in the 42x variant
542f7821b49SLinus Walleij * when accessing config space.
543f7821b49SLinus Walleij */
544f7821b49SLinus Walleij if (of_device_is_compatible(np, "intel,ixp42x-pci")) {
545f7821b49SLinus Walleij p->errata_hammer = true;
546f7821b49SLinus Walleij dev_info(dev, "activate hammering errata\n");
547f7821b49SLinus Walleij }
548f7821b49SLinus Walleij
549f7821b49SLinus Walleij p->base = devm_platform_ioremap_resource(pdev, 0);
550f7821b49SLinus Walleij if (IS_ERR(p->base))
551f7821b49SLinus Walleij return PTR_ERR(p->base);
552f7821b49SLinus Walleij
553f7821b49SLinus Walleij val = ixp4xx_readl(p, IXP4XX_PCI_CSR);
554f7821b49SLinus Walleij p->host_mode = !!(val & IXP4XX_PCI_CSR_HOST);
555f7821b49SLinus Walleij dev_info(dev, "controller is in %s mode\n",
556f7821b49SLinus Walleij p->host_mode ? "host" : "option");
557f7821b49SLinus Walleij
558f7821b49SLinus Walleij /* Hook in our fault handler for PCI errors */
559f7821b49SLinus Walleij ixp4xx_pci_abort_singleton = p;
560f7821b49SLinus Walleij hook_fault_code(16+6, ixp4xx_pci_abort_handler, SIGBUS, 0,
561f7821b49SLinus Walleij "imprecise external abort");
562f7821b49SLinus Walleij
563f7821b49SLinus Walleij ret = ixp4xx_pci_parse_map_ranges(p);
564f7821b49SLinus Walleij if (ret)
565f7821b49SLinus Walleij return ret;
566f7821b49SLinus Walleij
567f7821b49SLinus Walleij ret = ixp4xx_pci_parse_map_dma_ranges(p);
568f7821b49SLinus Walleij if (ret)
569f7821b49SLinus Walleij return ret;
570f7821b49SLinus Walleij
571f7821b49SLinus Walleij /* This is only configured in host mode */
572f7821b49SLinus Walleij if (p->host_mode) {
573f7821b49SLinus Walleij addr = __pa(PAGE_OFFSET);
574f7821b49SLinus Walleij /* This is a noop (0x00) but explains what is going on */
575f7821b49SLinus Walleij addr |= PCI_BASE_ADDRESS_SPACE_MEMORY;
576f7821b49SLinus Walleij
577f7821b49SLinus Walleij for (i = 0; i < 4; i++) {
578f7821b49SLinus Walleij /* Write this directly into the config space */
579f7821b49SLinus Walleij ret = ixp4xx_crp_write_config(p, basereg[i], 4, addr);
580f7821b49SLinus Walleij if (ret)
581f7821b49SLinus Walleij dev_err(dev, "failed to set up PCI_BASE_ADDRESS_%d\n", i);
582f7821b49SLinus Walleij else
583f7821b49SLinus Walleij dev_info(dev, "set PCI_BASE_ADDR_%d to %pa\n", i, &addr);
584f7821b49SLinus Walleij addr += SZ_16M;
585f7821b49SLinus Walleij }
586f7821b49SLinus Walleij
587f7821b49SLinus Walleij /*
588f7821b49SLinus Walleij * Enable CSR window at 64 MiB to allow PCI masters to continue
589f7821b49SLinus Walleij * prefetching past the 64 MiB boundary, if all AHB to PCI
590f7821b49SLinus Walleij * windows are consecutive.
591f7821b49SLinus Walleij */
592f7821b49SLinus Walleij ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_4, 4, addr);
593f7821b49SLinus Walleij if (ret)
594f7821b49SLinus Walleij dev_err(dev, "failed to set up PCI_BASE_ADDRESS_4\n");
595f7821b49SLinus Walleij else
596f7821b49SLinus Walleij dev_info(dev, "set PCI_BASE_ADDR_4 to %pa\n", &addr);
597f7821b49SLinus Walleij
598f7821b49SLinus Walleij /*
599f7821b49SLinus Walleij * Put the IO memory window at the very end of physical memory
600f7821b49SLinus Walleij * at 0xfffffc00. This is when the system is trying to access IO
601f7821b49SLinus Walleij * memory over AHB.
602f7821b49SLinus Walleij */
603f7821b49SLinus Walleij addr = 0xfffffc00;
604f7821b49SLinus Walleij addr |= PCI_BASE_ADDRESS_SPACE_IO;
605f7821b49SLinus Walleij ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_5, 4, addr);
606f7821b49SLinus Walleij if (ret)
607f7821b49SLinus Walleij dev_err(dev, "failed to set up PCI_BASE_ADDRESS_5\n");
608f7821b49SLinus Walleij else
609f7821b49SLinus Walleij dev_info(dev, "set PCI_BASE_ADDR_5 to %pa\n", &addr);
610f7821b49SLinus Walleij
611f7821b49SLinus Walleij /*
612f7821b49SLinus Walleij * Retry timeout to 0x80
613f7821b49SLinus Walleij * Transfer ready timeout to 0xff
614f7821b49SLinus Walleij */
615f7821b49SLinus Walleij ret = ixp4xx_crp_write_config(p, IXP4XX_PCI_RTOTTO, 4,
616f7821b49SLinus Walleij 0x000080ff);
617f7821b49SLinus Walleij if (ret)
618f7821b49SLinus Walleij dev_err(dev, "failed to set up TRDY limit\n");
619f7821b49SLinus Walleij else
620f7821b49SLinus Walleij dev_info(dev, "set TRDY limit to 0x80ff\n");
621f7821b49SLinus Walleij }
622f7821b49SLinus Walleij
623f7821b49SLinus Walleij /* Clear interrupts */
624f7821b49SLinus Walleij val = IXP4XX_PCI_ISR_PSE | IXP4XX_PCI_ISR_PFE | IXP4XX_PCI_ISR_PPE | IXP4XX_PCI_ISR_AHBE;
625f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_ISR, val);
626f7821b49SLinus Walleij
627f7821b49SLinus Walleij /*
628f7821b49SLinus Walleij * Set Initialize Complete in PCI Control Register: allow IXP4XX to
629f7821b49SLinus Walleij * generate PCI configuration cycles. Specify that the AHB bus is
630f7821b49SLinus Walleij * operating in big-endian mode. Set up byte lane swapping between
631f7821b49SLinus Walleij * little-endian PCI and the big-endian AHB bus.
632f7821b49SLinus Walleij */
633f7821b49SLinus Walleij val = IXP4XX_PCI_CSR_IC | IXP4XX_PCI_CSR_ABE;
634f7821b49SLinus Walleij if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
635f7821b49SLinus Walleij val |= (IXP4XX_PCI_CSR_PDS | IXP4XX_PCI_CSR_ADS);
636f7821b49SLinus Walleij ixp4xx_writel(p, IXP4XX_PCI_CSR, val);
637f7821b49SLinus Walleij
638f7821b49SLinus Walleij ret = ixp4xx_crp_write_config(p, PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
639f7821b49SLinus Walleij if (ret)
640f7821b49SLinus Walleij dev_err(dev, "unable to initialize master and command memory\n");
641f7821b49SLinus Walleij else
642f7821b49SLinus Walleij dev_info(dev, "initialized as master\n");
643f7821b49SLinus Walleij
644f7821b49SLinus Walleij pci_host_probe(host);
645f7821b49SLinus Walleij
646f7821b49SLinus Walleij return 0;
647f7821b49SLinus Walleij }
648f7821b49SLinus Walleij
649f7821b49SLinus Walleij static const struct of_device_id ixp4xx_pci_of_match[] = {
650f7821b49SLinus Walleij {
651f7821b49SLinus Walleij .compatible = "intel,ixp42x-pci",
652f7821b49SLinus Walleij },
653f7821b49SLinus Walleij {
654f7821b49SLinus Walleij .compatible = "intel,ixp43x-pci",
655f7821b49SLinus Walleij },
656f7821b49SLinus Walleij {},
657f7821b49SLinus Walleij };
658f7821b49SLinus Walleij
659f7821b49SLinus Walleij /*
660f7821b49SLinus Walleij * This driver needs to be a builtin module with suppressed bind
661f7821b49SLinus Walleij * attributes since the probe() is initializing a hard exception
662f7821b49SLinus Walleij * handler and this can only be done from __init-tagged code
663f7821b49SLinus Walleij * sections. This module cannot be removed and inserted at all.
664f7821b49SLinus Walleij */
665f7821b49SLinus Walleij static struct platform_driver ixp4xx_pci_driver = {
666f7821b49SLinus Walleij .driver = {
667f7821b49SLinus Walleij .name = "ixp4xx-pci",
668f7821b49SLinus Walleij .suppress_bind_attrs = true,
669f7821b49SLinus Walleij .of_match_table = ixp4xx_pci_of_match,
670f7821b49SLinus Walleij },
671f7821b49SLinus Walleij };
672f7821b49SLinus Walleij builtin_platform_driver_probe(ixp4xx_pci_driver, ixp4xx_pci_probe);
673