1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved 4 * 5 * Author: Ley Foon Tan <lftan@altera.com> 6 * Description: Altera PCIe host controller driver 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/irqchip/chained_irq.h> 12 #include <linux/init.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_pci.h> 17 #include <linux/pci.h> 18 #include <linux/platform_device.h> 19 #include <linux/slab.h> 20 21 #include "../pci.h" 22 23 #define RP_TX_REG0 0x2000 24 #define RP_TX_REG1 0x2004 25 #define RP_TX_CNTRL 0x2008 26 #define RP_TX_EOP 0x2 27 #define RP_TX_SOP 0x1 28 #define RP_RXCPL_STATUS 0x2010 29 #define RP_RXCPL_EOP 0x2 30 #define RP_RXCPL_SOP 0x1 31 #define RP_RXCPL_REG0 0x2014 32 #define RP_RXCPL_REG1 0x2018 33 #define P2A_INT_STATUS 0x3060 34 #define P2A_INT_STS_ALL 0xf 35 #define P2A_INT_ENABLE 0x3070 36 #define P2A_INT_ENA_ALL 0xf 37 #define RP_LTSSM 0x3c64 38 #define RP_LTSSM_MASK 0x1f 39 #define LTSSM_L0 0xf 40 41 #define S10_RP_TX_CNTRL 0x2004 42 #define S10_RP_RXCPL_REG 0x2008 43 #define S10_RP_RXCPL_STATUS 0x200C 44 #define S10_RP_CFG_ADDR(pcie, reg) \ 45 (((pcie)->hip_base) + (reg) + (1 << 20)) 46 47 /* TLP configuration type 0 and 1 */ 48 #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */ 49 #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */ 50 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */ 51 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */ 52 #define TLP_PAYLOAD_SIZE 0x01 53 #define TLP_READ_TAG 0x1d 54 #define TLP_WRITE_TAG 0x10 55 #define RP_DEVFN 0 56 #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn)) 57 #define TLP_CFGRD_DW0(pcie, bus) \ 58 ((((bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0 \ 59 : pcie->pcie_data->cfgrd1) << 24) | \ 60 TLP_PAYLOAD_SIZE) 61 #define TLP_CFGWR_DW0(pcie, bus) \ 62 ((((bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \ 63 : pcie->pcie_data->cfgwr1) << 24) | \ 64 TLP_PAYLOAD_SIZE) 65 #define TLP_CFG_DW1(pcie, tag, be) \ 66 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be)) 67 #define TLP_CFG_DW2(bus, devfn, offset) \ 68 (((bus) << 24) | ((devfn) << 16) | (offset)) 69 #define TLP_COMP_STATUS(s) (((s) >> 13) & 7) 70 #define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff) 71 #define TLP_HDR_SIZE 3 72 #define TLP_LOOP 500 73 74 #define LINK_UP_TIMEOUT HZ 75 #define LINK_RETRAIN_TIMEOUT HZ 76 77 #define DWORD_MASK 3 78 79 #define S10_TLP_FMTTYPE_CFGRD0 0x05 80 #define S10_TLP_FMTTYPE_CFGRD1 0x04 81 #define S10_TLP_FMTTYPE_CFGWR0 0x45 82 #define S10_TLP_FMTTYPE_CFGWR1 0x44 83 84 enum altera_pcie_version { 85 ALTERA_PCIE_V1 = 0, 86 ALTERA_PCIE_V2, 87 }; 88 89 struct altera_pcie { 90 struct platform_device *pdev; 91 void __iomem *cra_base; 92 void __iomem *hip_base; 93 int irq; 94 u8 root_bus_nr; 95 struct irq_domain *irq_domain; 96 struct resource bus_range; 97 struct list_head resources; 98 const struct altera_pcie_data *pcie_data; 99 }; 100 101 struct altera_pcie_ops { 102 int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value); 103 void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers, 104 u32 data, bool align); 105 bool (*get_link_status)(struct altera_pcie *pcie); 106 int (*rp_read_cfg)(struct altera_pcie *pcie, int where, 107 int size, u32 *value); 108 int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno, 109 int where, int size, u32 value); 110 }; 111 112 struct altera_pcie_data { 113 const struct altera_pcie_ops *ops; 114 enum altera_pcie_version version; 115 u32 cap_offset; /* PCIe capability structure register offset */ 116 u32 cfgrd0; 117 u32 cfgrd1; 118 u32 cfgwr0; 119 u32 cfgwr1; 120 }; 121 122 struct tlp_rp_regpair_t { 123 u32 ctrl; 124 u32 reg0; 125 u32 reg1; 126 }; 127 128 static inline void cra_writel(struct altera_pcie *pcie, const u32 value, 129 const u32 reg) 130 { 131 writel_relaxed(value, pcie->cra_base + reg); 132 } 133 134 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg) 135 { 136 return readl_relaxed(pcie->cra_base + reg); 137 } 138 139 static bool altera_pcie_link_up(struct altera_pcie *pcie) 140 { 141 return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0); 142 } 143 144 static bool s10_altera_pcie_link_up(struct altera_pcie *pcie) 145 { 146 void __iomem *addr = S10_RP_CFG_ADDR(pcie, 147 pcie->pcie_data->cap_offset + 148 PCI_EXP_LNKSTA); 149 150 return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA); 151 } 152 153 /* 154 * Altera PCIe port uses BAR0 of RC's configuration space as the translation 155 * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space 156 * using these registers, so it can be reached by DMA from EP devices. 157 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt 158 * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge 159 * should be hidden during enumeration to avoid the sizing and resource 160 * allocation by PCIe core. 161 */ 162 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, 163 int offset) 164 { 165 if (pci_is_root_bus(bus) && (devfn == 0) && 166 (offset == PCI_BASE_ADDRESS_0)) 167 return true; 168 169 return false; 170 } 171 172 static void tlp_write_tx(struct altera_pcie *pcie, 173 struct tlp_rp_regpair_t *tlp_rp_regdata) 174 { 175 cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0); 176 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1); 177 cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL); 178 } 179 180 static void s10_tlp_write_tx(struct altera_pcie *pcie, u32 reg0, u32 ctrl) 181 { 182 cra_writel(pcie, reg0, RP_TX_REG0); 183 cra_writel(pcie, ctrl, S10_RP_TX_CNTRL); 184 } 185 186 static bool altera_pcie_valid_device(struct altera_pcie *pcie, 187 struct pci_bus *bus, int dev) 188 { 189 /* If there is no link, then there is no device */ 190 if (bus->number != pcie->root_bus_nr) { 191 if (!pcie->pcie_data->ops->get_link_status(pcie)) 192 return false; 193 } 194 195 /* access only one slot on each root port */ 196 if (bus->number == pcie->root_bus_nr && dev > 0) 197 return false; 198 199 return true; 200 } 201 202 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value) 203 { 204 int i; 205 bool sop = false; 206 u32 ctrl; 207 u32 reg0, reg1; 208 u32 comp_status = 1; 209 210 /* 211 * Minimum 2 loops to read TLP headers and 1 loop to read data 212 * payload. 213 */ 214 for (i = 0; i < TLP_LOOP; i++) { 215 ctrl = cra_readl(pcie, RP_RXCPL_STATUS); 216 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) { 217 reg0 = cra_readl(pcie, RP_RXCPL_REG0); 218 reg1 = cra_readl(pcie, RP_RXCPL_REG1); 219 220 if (ctrl & RP_RXCPL_SOP) { 221 sop = true; 222 comp_status = TLP_COMP_STATUS(reg1); 223 } 224 225 if (ctrl & RP_RXCPL_EOP) { 226 if (comp_status) 227 return PCIBIOS_DEVICE_NOT_FOUND; 228 229 if (value) 230 *value = reg0; 231 232 return PCIBIOS_SUCCESSFUL; 233 } 234 } 235 udelay(5); 236 } 237 238 return PCIBIOS_DEVICE_NOT_FOUND; 239 } 240 241 static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value) 242 { 243 u32 ctrl; 244 u32 comp_status; 245 u32 dw[4]; 246 u32 count; 247 struct device *dev = &pcie->pdev->dev; 248 249 for (count = 0; count < TLP_LOOP; count++) { 250 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS); 251 if (ctrl & RP_RXCPL_SOP) { 252 /* Read first DW */ 253 dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG); 254 break; 255 } 256 257 udelay(5); 258 } 259 260 /* SOP detection failed, return error */ 261 if (count == TLP_LOOP) 262 return PCIBIOS_DEVICE_NOT_FOUND; 263 264 count = 1; 265 266 /* Poll for EOP */ 267 while (count < ARRAY_SIZE(dw)) { 268 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS); 269 dw[count++] = cra_readl(pcie, S10_RP_RXCPL_REG); 270 if (ctrl & RP_RXCPL_EOP) { 271 comp_status = TLP_COMP_STATUS(dw[1]); 272 if (comp_status) 273 return PCIBIOS_DEVICE_NOT_FOUND; 274 275 if (value && TLP_BYTE_COUNT(dw[1]) == sizeof(u32) && 276 count == 4) 277 *value = dw[3]; 278 279 return PCIBIOS_SUCCESSFUL; 280 } 281 } 282 283 dev_warn(dev, "Malformed TLP packet\n"); 284 285 return PCIBIOS_DEVICE_NOT_FOUND; 286 } 287 288 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers, 289 u32 data, bool align) 290 { 291 struct tlp_rp_regpair_t tlp_rp_regdata; 292 293 tlp_rp_regdata.reg0 = headers[0]; 294 tlp_rp_regdata.reg1 = headers[1]; 295 tlp_rp_regdata.ctrl = RP_TX_SOP; 296 tlp_write_tx(pcie, &tlp_rp_regdata); 297 298 if (align) { 299 tlp_rp_regdata.reg0 = headers[2]; 300 tlp_rp_regdata.reg1 = 0; 301 tlp_rp_regdata.ctrl = 0; 302 tlp_write_tx(pcie, &tlp_rp_regdata); 303 304 tlp_rp_regdata.reg0 = data; 305 tlp_rp_regdata.reg1 = 0; 306 } else { 307 tlp_rp_regdata.reg0 = headers[2]; 308 tlp_rp_regdata.reg1 = data; 309 } 310 311 tlp_rp_regdata.ctrl = RP_TX_EOP; 312 tlp_write_tx(pcie, &tlp_rp_regdata); 313 } 314 315 static void s10_tlp_write_packet(struct altera_pcie *pcie, u32 *headers, 316 u32 data, bool dummy) 317 { 318 s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP); 319 s10_tlp_write_tx(pcie, headers[1], 0); 320 s10_tlp_write_tx(pcie, headers[2], 0); 321 s10_tlp_write_tx(pcie, data, RP_TX_EOP); 322 } 323 324 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn, 325 int where, u8 byte_en, u32 *value) 326 { 327 u32 headers[TLP_HDR_SIZE]; 328 329 headers[0] = TLP_CFGRD_DW0(pcie, bus); 330 headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en); 331 headers[2] = TLP_CFG_DW2(bus, devfn, where); 332 333 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false); 334 335 return pcie->pcie_data->ops->tlp_read_pkt(pcie, value); 336 } 337 338 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn, 339 int where, u8 byte_en, u32 value) 340 { 341 u32 headers[TLP_HDR_SIZE]; 342 int ret; 343 344 headers[0] = TLP_CFGWR_DW0(pcie, bus); 345 headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en); 346 headers[2] = TLP_CFG_DW2(bus, devfn, where); 347 348 /* check alignment to Qword */ 349 if ((where & 0x7) == 0) 350 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 351 value, true); 352 else 353 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 354 value, false); 355 356 ret = pcie->pcie_data->ops->tlp_read_pkt(pcie, NULL); 357 if (ret != PCIBIOS_SUCCESSFUL) 358 return ret; 359 360 /* 361 * Monitor changes to PCI_PRIMARY_BUS register on root port 362 * and update local copy of root bus number accordingly. 363 */ 364 if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS)) 365 pcie->root_bus_nr = (u8)(value); 366 367 return PCIBIOS_SUCCESSFUL; 368 } 369 370 static int s10_rp_read_cfg(struct altera_pcie *pcie, int where, 371 int size, u32 *value) 372 { 373 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where); 374 375 switch (size) { 376 case 1: 377 *value = readb(addr); 378 break; 379 case 2: 380 *value = readw(addr); 381 break; 382 default: 383 *value = readl(addr); 384 break; 385 } 386 387 return PCIBIOS_SUCCESSFUL; 388 } 389 390 static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno, 391 int where, int size, u32 value) 392 { 393 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where); 394 395 switch (size) { 396 case 1: 397 writeb(value, addr); 398 break; 399 case 2: 400 writew(value, addr); 401 break; 402 default: 403 writel(value, addr); 404 break; 405 } 406 407 /* 408 * Monitor changes to PCI_PRIMARY_BUS register on root port 409 * and update local copy of root bus number accordingly. 410 */ 411 if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS) 412 pcie->root_bus_nr = value & 0xff; 413 414 return PCIBIOS_SUCCESSFUL; 415 } 416 417 static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno, 418 unsigned int devfn, int where, int size, 419 u32 *value) 420 { 421 int ret; 422 u32 data; 423 u8 byte_en; 424 425 if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_read_cfg) 426 return pcie->pcie_data->ops->rp_read_cfg(pcie, where, 427 size, value); 428 429 switch (size) { 430 case 1: 431 byte_en = 1 << (where & 3); 432 break; 433 case 2: 434 byte_en = 3 << (where & 3); 435 break; 436 default: 437 byte_en = 0xf; 438 break; 439 } 440 441 ret = tlp_cfg_dword_read(pcie, busno, devfn, 442 (where & ~DWORD_MASK), byte_en, &data); 443 if (ret != PCIBIOS_SUCCESSFUL) 444 return ret; 445 446 switch (size) { 447 case 1: 448 *value = (data >> (8 * (where & 0x3))) & 0xff; 449 break; 450 case 2: 451 *value = (data >> (8 * (where & 0x2))) & 0xffff; 452 break; 453 default: 454 *value = data; 455 break; 456 } 457 458 return PCIBIOS_SUCCESSFUL; 459 } 460 461 static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno, 462 unsigned int devfn, int where, int size, 463 u32 value) 464 { 465 u32 data32; 466 u32 shift = 8 * (where & 3); 467 u8 byte_en; 468 469 if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_write_cfg) 470 return pcie->pcie_data->ops->rp_write_cfg(pcie, busno, 471 where, size, value); 472 473 switch (size) { 474 case 1: 475 data32 = (value & 0xff) << shift; 476 byte_en = 1 << (where & 3); 477 break; 478 case 2: 479 data32 = (value & 0xffff) << shift; 480 byte_en = 3 << (where & 3); 481 break; 482 default: 483 data32 = value; 484 byte_en = 0xf; 485 break; 486 } 487 488 return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK), 489 byte_en, data32); 490 } 491 492 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn, 493 int where, int size, u32 *value) 494 { 495 struct altera_pcie *pcie = bus->sysdata; 496 497 if (altera_pcie_hide_rc_bar(bus, devfn, where)) 498 return PCIBIOS_BAD_REGISTER_NUMBER; 499 500 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn))) { 501 *value = 0xffffffff; 502 return PCIBIOS_DEVICE_NOT_FOUND; 503 } 504 505 return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size, 506 value); 507 } 508 509 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn, 510 int where, int size, u32 value) 511 { 512 struct altera_pcie *pcie = bus->sysdata; 513 514 if (altera_pcie_hide_rc_bar(bus, devfn, where)) 515 return PCIBIOS_BAD_REGISTER_NUMBER; 516 517 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn))) 518 return PCIBIOS_DEVICE_NOT_FOUND; 519 520 return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size, 521 value); 522 } 523 524 static struct pci_ops altera_pcie_ops = { 525 .read = altera_pcie_cfg_read, 526 .write = altera_pcie_cfg_write, 527 }; 528 529 static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno, 530 unsigned int devfn, int offset, u16 *value) 531 { 532 u32 data; 533 int ret; 534 535 ret = _altera_pcie_cfg_read(pcie, busno, devfn, 536 pcie->pcie_data->cap_offset + offset, 537 sizeof(*value), 538 &data); 539 *value = data; 540 return ret; 541 } 542 543 static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno, 544 unsigned int devfn, int offset, u16 value) 545 { 546 return _altera_pcie_cfg_write(pcie, busno, devfn, 547 pcie->pcie_data->cap_offset + offset, 548 sizeof(value), 549 value); 550 } 551 552 static void altera_wait_link_retrain(struct altera_pcie *pcie) 553 { 554 struct device *dev = &pcie->pdev->dev; 555 u16 reg16; 556 unsigned long start_jiffies; 557 558 /* Wait for link training end. */ 559 start_jiffies = jiffies; 560 for (;;) { 561 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, 562 PCI_EXP_LNKSTA, ®16); 563 if (!(reg16 & PCI_EXP_LNKSTA_LT)) 564 break; 565 566 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) { 567 dev_err(dev, "link retrain timeout\n"); 568 break; 569 } 570 udelay(100); 571 } 572 573 /* Wait for link is up */ 574 start_jiffies = jiffies; 575 for (;;) { 576 if (pcie->pcie_data->ops->get_link_status(pcie)) 577 break; 578 579 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) { 580 dev_err(dev, "link up timeout\n"); 581 break; 582 } 583 udelay(100); 584 } 585 } 586 587 static void altera_pcie_retrain(struct altera_pcie *pcie) 588 { 589 u16 linkcap, linkstat, linkctl; 590 591 if (!pcie->pcie_data->ops->get_link_status(pcie)) 592 return; 593 594 /* 595 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but 596 * current speed is 2.5 GB/s. 597 */ 598 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP, 599 &linkcap); 600 if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) 601 return; 602 603 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA, 604 &linkstat); 605 if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { 606 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, 607 PCI_EXP_LNKCTL, &linkctl); 608 linkctl |= PCI_EXP_LNKCTL_RL; 609 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, 610 PCI_EXP_LNKCTL, linkctl); 611 612 altera_wait_link_retrain(pcie); 613 } 614 } 615 616 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 617 irq_hw_number_t hwirq) 618 { 619 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 620 irq_set_chip_data(irq, domain->host_data); 621 return 0; 622 } 623 624 static const struct irq_domain_ops intx_domain_ops = { 625 .map = altera_pcie_intx_map, 626 .xlate = pci_irqd_intx_xlate, 627 }; 628 629 static void altera_pcie_isr(struct irq_desc *desc) 630 { 631 struct irq_chip *chip = irq_desc_get_chip(desc); 632 struct altera_pcie *pcie; 633 struct device *dev; 634 unsigned long status; 635 u32 bit; 636 u32 virq; 637 638 chained_irq_enter(chip, desc); 639 pcie = irq_desc_get_handler_data(desc); 640 dev = &pcie->pdev->dev; 641 642 while ((status = cra_readl(pcie, P2A_INT_STATUS) 643 & P2A_INT_STS_ALL) != 0) { 644 for_each_set_bit(bit, &status, PCI_NUM_INTX) { 645 /* clear interrupts */ 646 cra_writel(pcie, 1 << bit, P2A_INT_STATUS); 647 648 virq = irq_find_mapping(pcie->irq_domain, bit); 649 if (virq) 650 generic_handle_irq(virq); 651 else 652 dev_err(dev, "unexpected IRQ, INT%d\n", bit); 653 } 654 } 655 656 chained_irq_exit(chip, desc); 657 } 658 659 static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie) 660 { 661 int err, res_valid = 0; 662 struct device *dev = &pcie->pdev->dev; 663 struct resource_entry *win; 664 665 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, 666 &pcie->resources, NULL); 667 if (err) 668 return err; 669 670 err = devm_request_pci_bus_resources(dev, &pcie->resources); 671 if (err) 672 goto out_release_res; 673 674 resource_list_for_each_entry(win, &pcie->resources) { 675 struct resource *res = win->res; 676 677 if (resource_type(res) == IORESOURCE_MEM) 678 res_valid |= !(res->flags & IORESOURCE_PREFETCH); 679 } 680 681 if (res_valid) 682 return 0; 683 684 dev_err(dev, "non-prefetchable memory resource required\n"); 685 err = -EINVAL; 686 687 out_release_res: 688 pci_free_resource_list(&pcie->resources); 689 return err; 690 } 691 692 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie) 693 { 694 struct device *dev = &pcie->pdev->dev; 695 struct device_node *node = dev->of_node; 696 697 /* Setup INTx */ 698 pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX, 699 &intx_domain_ops, pcie); 700 if (!pcie->irq_domain) { 701 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 702 return -ENOMEM; 703 } 704 705 return 0; 706 } 707 708 static int altera_pcie_parse_dt(struct altera_pcie *pcie) 709 { 710 struct device *dev = &pcie->pdev->dev; 711 struct platform_device *pdev = pcie->pdev; 712 struct resource *cra; 713 struct resource *hip; 714 715 cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra"); 716 pcie->cra_base = devm_ioremap_resource(dev, cra); 717 if (IS_ERR(pcie->cra_base)) 718 return PTR_ERR(pcie->cra_base); 719 720 if (pcie->pcie_data->version == ALTERA_PCIE_V2) { 721 hip = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Hip"); 722 pcie->hip_base = devm_ioremap_resource(&pdev->dev, hip); 723 if (IS_ERR(pcie->hip_base)) 724 return PTR_ERR(pcie->hip_base); 725 } 726 727 /* setup IRQ */ 728 pcie->irq = platform_get_irq(pdev, 0); 729 if (pcie->irq < 0) { 730 dev_err(dev, "failed to get IRQ: %d\n", pcie->irq); 731 return pcie->irq; 732 } 733 734 irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie); 735 return 0; 736 } 737 738 static void altera_pcie_host_init(struct altera_pcie *pcie) 739 { 740 altera_pcie_retrain(pcie); 741 } 742 743 static const struct altera_pcie_ops altera_pcie_ops_1_0 = { 744 .tlp_read_pkt = tlp_read_packet, 745 .tlp_write_pkt = tlp_write_packet, 746 .get_link_status = altera_pcie_link_up, 747 }; 748 749 static const struct altera_pcie_ops altera_pcie_ops_2_0 = { 750 .tlp_read_pkt = s10_tlp_read_packet, 751 .tlp_write_pkt = s10_tlp_write_packet, 752 .get_link_status = s10_altera_pcie_link_up, 753 .rp_read_cfg = s10_rp_read_cfg, 754 .rp_write_cfg = s10_rp_write_cfg, 755 }; 756 757 static const struct altera_pcie_data altera_pcie_1_0_data = { 758 .ops = &altera_pcie_ops_1_0, 759 .cap_offset = 0x80, 760 .version = ALTERA_PCIE_V1, 761 .cfgrd0 = TLP_FMTTYPE_CFGRD0, 762 .cfgrd1 = TLP_FMTTYPE_CFGRD1, 763 .cfgwr0 = TLP_FMTTYPE_CFGWR0, 764 .cfgwr1 = TLP_FMTTYPE_CFGWR1, 765 }; 766 767 static const struct altera_pcie_data altera_pcie_2_0_data = { 768 .ops = &altera_pcie_ops_2_0, 769 .version = ALTERA_PCIE_V2, 770 .cap_offset = 0x70, 771 .cfgrd0 = S10_TLP_FMTTYPE_CFGRD0, 772 .cfgrd1 = S10_TLP_FMTTYPE_CFGRD1, 773 .cfgwr0 = S10_TLP_FMTTYPE_CFGWR0, 774 .cfgwr1 = S10_TLP_FMTTYPE_CFGWR1, 775 }; 776 777 static const struct of_device_id altera_pcie_of_match[] = { 778 {.compatible = "altr,pcie-root-port-1.0", 779 .data = &altera_pcie_1_0_data }, 780 {.compatible = "altr,pcie-root-port-2.0", 781 .data = &altera_pcie_2_0_data }, 782 {}, 783 }; 784 785 static int altera_pcie_probe(struct platform_device *pdev) 786 { 787 struct device *dev = &pdev->dev; 788 struct altera_pcie *pcie; 789 struct pci_bus *bus; 790 struct pci_bus *child; 791 struct pci_host_bridge *bridge; 792 int ret; 793 const struct of_device_id *match; 794 795 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 796 if (!bridge) 797 return -ENOMEM; 798 799 pcie = pci_host_bridge_priv(bridge); 800 pcie->pdev = pdev; 801 802 match = of_match_device(altera_pcie_of_match, &pdev->dev); 803 if (!match) 804 return -ENODEV; 805 806 pcie->pcie_data = match->data; 807 808 ret = altera_pcie_parse_dt(pcie); 809 if (ret) { 810 dev_err(dev, "Parsing DT failed\n"); 811 return ret; 812 } 813 814 INIT_LIST_HEAD(&pcie->resources); 815 816 ret = altera_pcie_parse_request_of_pci_ranges(pcie); 817 if (ret) { 818 dev_err(dev, "Failed add resources\n"); 819 return ret; 820 } 821 822 ret = altera_pcie_init_irq_domain(pcie); 823 if (ret) { 824 dev_err(dev, "Failed creating IRQ Domain\n"); 825 return ret; 826 } 827 828 /* clear all interrupts */ 829 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS); 830 /* enable all interrupts */ 831 cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE); 832 altera_pcie_host_init(pcie); 833 834 list_splice_init(&pcie->resources, &bridge->windows); 835 bridge->dev.parent = dev; 836 bridge->sysdata = pcie; 837 bridge->busnr = pcie->root_bus_nr; 838 bridge->ops = &altera_pcie_ops; 839 bridge->map_irq = of_irq_parse_and_map_pci; 840 bridge->swizzle_irq = pci_common_swizzle; 841 842 ret = pci_scan_root_bus_bridge(bridge); 843 if (ret < 0) 844 return ret; 845 846 bus = bridge->bus; 847 848 pci_assign_unassigned_bus_resources(bus); 849 850 /* Configure PCI Express setting. */ 851 list_for_each_entry(child, &bus->children, node) 852 pcie_bus_configure_settings(child); 853 854 pci_bus_add_devices(bus); 855 return ret; 856 } 857 858 static struct platform_driver altera_pcie_driver = { 859 .probe = altera_pcie_probe, 860 .driver = { 861 .name = "altera-pcie", 862 .of_match_table = altera_pcie_of_match, 863 .suppress_bind_attrs = true, 864 }, 865 }; 866 867 builtin_platform_driver(altera_pcie_driver); 868