1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek PCIe host controller driver. 4 * 5 * Copyright (c) 2017 MediaTek Inc. 6 * Author: Ryder Lee <ryder.lee@mediatek.com> 7 * Honghui Zhang <honghui.zhang@mediatek.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/iopoll.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/kernel.h> 17 #include <linux/msi.h> 18 #include <linux/module.h> 19 #include <linux/of_address.h> 20 #include <linux/of_pci.h> 21 #include <linux/of_platform.h> 22 #include <linux/pci.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/reset.h> 27 28 #include "../pci.h" 29 30 /* PCIe shared registers */ 31 #define PCIE_SYS_CFG 0x00 32 #define PCIE_INT_ENABLE 0x0c 33 #define PCIE_CFG_ADDR 0x20 34 #define PCIE_CFG_DATA 0x24 35 36 /* PCIe per port registers */ 37 #define PCIE_BAR0_SETUP 0x10 38 #define PCIE_CLASS 0x34 39 #define PCIE_LINK_STATUS 0x50 40 41 #define PCIE_PORT_INT_EN(x) BIT(20 + (x)) 42 #define PCIE_PORT_PERST(x) BIT(1 + (x)) 43 #define PCIE_PORT_LINKUP BIT(0) 44 #define PCIE_BAR_MAP_MAX GENMASK(31, 16) 45 46 #define PCIE_BAR_ENABLE BIT(0) 47 #define PCIE_REVISION_ID BIT(0) 48 #define PCIE_CLASS_CODE (0x60400 << 8) 49 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \ 50 ((((regn) >> 8) & GENMASK(3, 0)) << 24)) 51 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8)) 52 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11)) 53 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16)) 54 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \ 55 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \ 56 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus)) 57 58 /* MediaTek specific configuration registers */ 59 #define PCIE_FTS_NUM 0x70c 60 #define PCIE_FTS_NUM_MASK GENMASK(15, 8) 61 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8) 62 63 #define PCIE_FC_CREDIT 0x73c 64 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16)) 65 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16) 66 67 /* PCIe V2 share registers */ 68 #define PCIE_SYS_CFG_V2 0x0 69 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8) 70 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8) 71 72 /* PCIe V2 per-port registers */ 73 #define PCIE_MSI_VECTOR 0x0c0 74 75 #define PCIE_CONF_VEND_ID 0x100 76 #define PCIE_CONF_DEVICE_ID 0x102 77 #define PCIE_CONF_CLASS_ID 0x106 78 79 #define PCIE_INT_MASK 0x420 80 #define INTX_MASK GENMASK(19, 16) 81 #define INTX_SHIFT 16 82 #define PCIE_INT_STATUS 0x424 83 #define MSI_STATUS BIT(23) 84 #define PCIE_IMSI_STATUS 0x42c 85 #define PCIE_IMSI_ADDR 0x430 86 #define MSI_MASK BIT(23) 87 #define MTK_MSI_IRQS_NUM 32 88 89 #define PCIE_AHB_TRANS_BASE0_L 0x438 90 #define PCIE_AHB_TRANS_BASE0_H 0x43c 91 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0)) 92 #define PCIE_AXI_WINDOW0 0x448 93 #define WIN_ENABLE BIT(7) 94 /* 95 * Define PCIe to AHB window size as 2^33 to support max 8GB address space 96 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM 97 * start from 0x40000000). 98 */ 99 #define PCIE2AHB_SIZE 0x21 100 101 /* PCIe V2 configuration transaction header */ 102 #define PCIE_CFG_HEADER0 0x460 103 #define PCIE_CFG_HEADER1 0x464 104 #define PCIE_CFG_HEADER2 0x468 105 #define PCIE_CFG_WDATA 0x470 106 #define PCIE_APP_TLP_REQ 0x488 107 #define PCIE_CFG_RDATA 0x48c 108 #define APP_CFG_REQ BIT(0) 109 #define APP_CPL_STATUS GENMASK(7, 5) 110 111 #define CFG_WRRD_TYPE_0 4 112 #define CFG_WR_FMT 2 113 #define CFG_RD_FMT 0 114 115 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0)) 116 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24)) 117 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29)) 118 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2)) 119 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16)) 120 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19)) 121 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24)) 122 #define CFG_HEADER_DW0(type, fmt) \ 123 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt)) 124 #define CFG_HEADER_DW1(where, size) \ 125 (GENMASK(((size) - 1), 0) << ((where) & 0x3)) 126 #define CFG_HEADER_DW2(regn, fun, dev, bus) \ 127 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \ 128 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus)) 129 130 #define PCIE_RST_CTRL 0x510 131 #define PCIE_PHY_RSTB BIT(0) 132 #define PCIE_PIPE_SRSTB BIT(1) 133 #define PCIE_MAC_SRSTB BIT(2) 134 #define PCIE_CRSTB BIT(3) 135 #define PCIE_PERSTB BIT(8) 136 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13) 137 #define PCIE_LINK_STATUS_V2 0x804 138 #define PCIE_PORT_LINKUP_V2 BIT(10) 139 140 struct mtk_pcie_port; 141 142 /** 143 * struct mtk_pcie_soc - differentiate between host generations 144 * @need_fix_class_id: whether this host's class ID needed to be fixed or not 145 * @need_fix_device_id: whether this host's device ID needed to be fixed or not 146 * @device_id: device ID which this host need to be fixed 147 * @ops: pointer to configuration access functions 148 * @startup: pointer to controller setting functions 149 * @setup_irq: pointer to initialize IRQ functions 150 */ 151 struct mtk_pcie_soc { 152 bool need_fix_class_id; 153 bool need_fix_device_id; 154 unsigned int device_id; 155 struct pci_ops *ops; 156 int (*startup)(struct mtk_pcie_port *port); 157 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); 158 }; 159 160 /** 161 * struct mtk_pcie_port - PCIe port information 162 * @base: IO mapped register base 163 * @list: port list 164 * @pcie: pointer to PCIe host info 165 * @reset: pointer to port reset control 166 * @sys_ck: pointer to transaction/data link layer clock 167 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access 168 * and RC initiated MMIO access 169 * @axi_ck: pointer to application layer MMIO channel operating clock 170 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock 171 * when pcie_mac_ck/pcie_pipe_ck is turned off 172 * @obff_ck: pointer to OBFF functional block operating clock 173 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock 174 * @phy: pointer to PHY control block 175 * @slot: port slot 176 * @irq: GIC irq 177 * @irq_domain: legacy INTx IRQ domain 178 * @inner_domain: inner IRQ domain 179 * @msi_domain: MSI IRQ domain 180 * @lock: protect the msi_irq_in_use bitmap 181 * @msi_irq_in_use: bit map for assigned MSI IRQ 182 */ 183 struct mtk_pcie_port { 184 void __iomem *base; 185 struct list_head list; 186 struct mtk_pcie *pcie; 187 struct reset_control *reset; 188 struct clk *sys_ck; 189 struct clk *ahb_ck; 190 struct clk *axi_ck; 191 struct clk *aux_ck; 192 struct clk *obff_ck; 193 struct clk *pipe_ck; 194 struct phy *phy; 195 u32 slot; 196 int irq; 197 struct irq_domain *irq_domain; 198 struct irq_domain *inner_domain; 199 struct irq_domain *msi_domain; 200 struct mutex lock; 201 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM); 202 }; 203 204 /** 205 * struct mtk_pcie - PCIe host information 206 * @dev: pointer to PCIe device 207 * @base: IO mapped register base 208 * @free_ck: free-run reference clock 209 * @mem: non-prefetchable memory resource 210 * @ports: pointer to PCIe port information 211 * @soc: pointer to SoC-dependent operations 212 * @busnr: root bus number 213 */ 214 struct mtk_pcie { 215 struct device *dev; 216 void __iomem *base; 217 struct clk *free_ck; 218 219 struct list_head ports; 220 const struct mtk_pcie_soc *soc; 221 unsigned int busnr; 222 }; 223 224 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie) 225 { 226 struct device *dev = pcie->dev; 227 228 clk_disable_unprepare(pcie->free_ck); 229 230 pm_runtime_put_sync(dev); 231 pm_runtime_disable(dev); 232 } 233 234 static void mtk_pcie_port_free(struct mtk_pcie_port *port) 235 { 236 struct mtk_pcie *pcie = port->pcie; 237 struct device *dev = pcie->dev; 238 239 devm_iounmap(dev, port->base); 240 list_del(&port->list); 241 devm_kfree(dev, port); 242 } 243 244 static void mtk_pcie_put_resources(struct mtk_pcie *pcie) 245 { 246 struct mtk_pcie_port *port, *tmp; 247 248 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 249 phy_power_off(port->phy); 250 phy_exit(port->phy); 251 clk_disable_unprepare(port->pipe_ck); 252 clk_disable_unprepare(port->obff_ck); 253 clk_disable_unprepare(port->axi_ck); 254 clk_disable_unprepare(port->aux_ck); 255 clk_disable_unprepare(port->ahb_ck); 256 clk_disable_unprepare(port->sys_ck); 257 mtk_pcie_port_free(port); 258 } 259 260 mtk_pcie_subsys_powerdown(pcie); 261 } 262 263 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port) 264 { 265 u32 val; 266 int err; 267 268 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val, 269 !(val & APP_CFG_REQ), 10, 270 100 * USEC_PER_MSEC); 271 if (err) 272 return PCIBIOS_SET_FAILED; 273 274 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS) 275 return PCIBIOS_SET_FAILED; 276 277 return PCIBIOS_SUCCESSFUL; 278 } 279 280 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, 281 int where, int size, u32 *val) 282 { 283 u32 tmp; 284 285 /* Write PCIe configuration transaction header for Cfgrd */ 286 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT), 287 port->base + PCIE_CFG_HEADER0); 288 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 289 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus), 290 port->base + PCIE_CFG_HEADER2); 291 292 /* Trigger h/w to transmit Cfgrd TLP */ 293 tmp = readl(port->base + PCIE_APP_TLP_REQ); 294 tmp |= APP_CFG_REQ; 295 writel(tmp, port->base + PCIE_APP_TLP_REQ); 296 297 /* Check completion status */ 298 if (mtk_pcie_check_cfg_cpld(port)) 299 return PCIBIOS_SET_FAILED; 300 301 /* Read cpld payload of Cfgrd */ 302 *val = readl(port->base + PCIE_CFG_RDATA); 303 304 if (size == 1) 305 *val = (*val >> (8 * (where & 3))) & 0xff; 306 else if (size == 2) 307 *val = (*val >> (8 * (where & 3))) & 0xffff; 308 309 return PCIBIOS_SUCCESSFUL; 310 } 311 312 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, 313 int where, int size, u32 val) 314 { 315 /* Write PCIe configuration transaction header for Cfgwr */ 316 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT), 317 port->base + PCIE_CFG_HEADER0); 318 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 319 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus), 320 port->base + PCIE_CFG_HEADER2); 321 322 /* Write Cfgwr data */ 323 val = val << 8 * (where & 3); 324 writel(val, port->base + PCIE_CFG_WDATA); 325 326 /* Trigger h/w to transmit Cfgwr TLP */ 327 val = readl(port->base + PCIE_APP_TLP_REQ); 328 val |= APP_CFG_REQ; 329 writel(val, port->base + PCIE_APP_TLP_REQ); 330 331 /* Check completion status */ 332 return mtk_pcie_check_cfg_cpld(port); 333 } 334 335 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus, 336 unsigned int devfn) 337 { 338 struct mtk_pcie *pcie = bus->sysdata; 339 struct mtk_pcie_port *port; 340 struct pci_dev *dev = NULL; 341 342 /* 343 * Walk the bus hierarchy to get the devfn value 344 * of the port in the root bus. 345 */ 346 while (bus && bus->number) { 347 dev = bus->self; 348 bus = dev->bus; 349 devfn = dev->devfn; 350 } 351 352 list_for_each_entry(port, &pcie->ports, list) 353 if (port->slot == PCI_SLOT(devfn)) 354 return port; 355 356 return NULL; 357 } 358 359 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 360 int where, int size, u32 *val) 361 { 362 struct mtk_pcie_port *port; 363 u32 bn = bus->number; 364 int ret; 365 366 port = mtk_pcie_find_port(bus, devfn); 367 if (!port) { 368 *val = ~0; 369 return PCIBIOS_DEVICE_NOT_FOUND; 370 } 371 372 ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val); 373 if (ret) 374 *val = ~0; 375 376 return ret; 377 } 378 379 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 380 int where, int size, u32 val) 381 { 382 struct mtk_pcie_port *port; 383 u32 bn = bus->number; 384 385 port = mtk_pcie_find_port(bus, devfn); 386 if (!port) 387 return PCIBIOS_DEVICE_NOT_FOUND; 388 389 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val); 390 } 391 392 static struct pci_ops mtk_pcie_ops_v2 = { 393 .read = mtk_pcie_config_read, 394 .write = mtk_pcie_config_write, 395 }; 396 397 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 398 { 399 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); 400 phys_addr_t addr; 401 402 /* MT2712/MT7622 only support 32-bit MSI addresses */ 403 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); 404 msg->address_hi = 0; 405 msg->address_lo = lower_32_bits(addr); 406 407 msg->data = data->hwirq; 408 409 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n", 410 (int)data->hwirq, msg->address_hi, msg->address_lo); 411 } 412 413 static int mtk_msi_set_affinity(struct irq_data *irq_data, 414 const struct cpumask *mask, bool force) 415 { 416 return -EINVAL; 417 } 418 419 static void mtk_msi_ack_irq(struct irq_data *data) 420 { 421 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); 422 u32 hwirq = data->hwirq; 423 424 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS); 425 } 426 427 static struct irq_chip mtk_msi_bottom_irq_chip = { 428 .name = "MTK MSI", 429 .irq_compose_msi_msg = mtk_compose_msi_msg, 430 .irq_set_affinity = mtk_msi_set_affinity, 431 .irq_ack = mtk_msi_ack_irq, 432 }; 433 434 static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 435 unsigned int nr_irqs, void *args) 436 { 437 struct mtk_pcie_port *port = domain->host_data; 438 unsigned long bit; 439 440 WARN_ON(nr_irqs != 1); 441 mutex_lock(&port->lock); 442 443 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM); 444 if (bit >= MTK_MSI_IRQS_NUM) { 445 mutex_unlock(&port->lock); 446 return -ENOSPC; 447 } 448 449 __set_bit(bit, port->msi_irq_in_use); 450 451 mutex_unlock(&port->lock); 452 453 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip, 454 domain->host_data, handle_edge_irq, 455 NULL, NULL); 456 457 return 0; 458 } 459 460 static void mtk_pcie_irq_domain_free(struct irq_domain *domain, 461 unsigned int virq, unsigned int nr_irqs) 462 { 463 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 464 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d); 465 466 mutex_lock(&port->lock); 467 468 if (!test_bit(d->hwirq, port->msi_irq_in_use)) 469 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n", 470 d->hwirq); 471 else 472 __clear_bit(d->hwirq, port->msi_irq_in_use); 473 474 mutex_unlock(&port->lock); 475 476 irq_domain_free_irqs_parent(domain, virq, nr_irqs); 477 } 478 479 static const struct irq_domain_ops msi_domain_ops = { 480 .alloc = mtk_pcie_irq_domain_alloc, 481 .free = mtk_pcie_irq_domain_free, 482 }; 483 484 static struct irq_chip mtk_msi_irq_chip = { 485 .name = "MTK PCIe MSI", 486 .irq_ack = irq_chip_ack_parent, 487 .irq_mask = pci_msi_mask_irq, 488 .irq_unmask = pci_msi_unmask_irq, 489 }; 490 491 static struct msi_domain_info mtk_msi_domain_info = { 492 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 493 MSI_FLAG_PCI_MSIX), 494 .chip = &mtk_msi_irq_chip, 495 }; 496 497 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) 498 { 499 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node); 500 501 mutex_init(&port->lock); 502 503 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM, 504 &msi_domain_ops, port); 505 if (!port->inner_domain) { 506 dev_err(port->pcie->dev, "failed to create IRQ domain\n"); 507 return -ENOMEM; 508 } 509 510 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info, 511 port->inner_domain); 512 if (!port->msi_domain) { 513 dev_err(port->pcie->dev, "failed to create MSI domain\n"); 514 irq_domain_remove(port->inner_domain); 515 return -ENOMEM; 516 } 517 518 return 0; 519 } 520 521 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) 522 { 523 u32 val; 524 phys_addr_t msg_addr; 525 526 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); 527 val = lower_32_bits(msg_addr); 528 writel(val, port->base + PCIE_IMSI_ADDR); 529 530 val = readl(port->base + PCIE_INT_MASK); 531 val &= ~MSI_MASK; 532 writel(val, port->base + PCIE_INT_MASK); 533 } 534 535 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie) 536 { 537 struct mtk_pcie_port *port, *tmp; 538 539 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 540 irq_set_chained_handler_and_data(port->irq, NULL, NULL); 541 542 if (port->irq_domain) 543 irq_domain_remove(port->irq_domain); 544 545 if (IS_ENABLED(CONFIG_PCI_MSI)) { 546 if (port->msi_domain) 547 irq_domain_remove(port->msi_domain); 548 if (port->inner_domain) 549 irq_domain_remove(port->inner_domain); 550 } 551 552 irq_dispose_mapping(port->irq); 553 } 554 } 555 556 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 557 irq_hw_number_t hwirq) 558 { 559 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 560 irq_set_chip_data(irq, domain->host_data); 561 562 return 0; 563 } 564 565 static const struct irq_domain_ops intx_domain_ops = { 566 .map = mtk_pcie_intx_map, 567 }; 568 569 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, 570 struct device_node *node) 571 { 572 struct device *dev = port->pcie->dev; 573 struct device_node *pcie_intc_node; 574 int ret; 575 576 /* Setup INTx */ 577 pcie_intc_node = of_get_next_child(node, NULL); 578 if (!pcie_intc_node) { 579 dev_err(dev, "no PCIe Intc node found\n"); 580 return -ENODEV; 581 } 582 583 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 584 &intx_domain_ops, port); 585 of_node_put(pcie_intc_node); 586 if (!port->irq_domain) { 587 dev_err(dev, "failed to get INTx IRQ domain\n"); 588 return -ENODEV; 589 } 590 591 if (IS_ENABLED(CONFIG_PCI_MSI)) { 592 ret = mtk_pcie_allocate_msi_domains(port); 593 if (ret) 594 return ret; 595 } 596 597 return 0; 598 } 599 600 static void mtk_pcie_intr_handler(struct irq_desc *desc) 601 { 602 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc); 603 struct irq_chip *irqchip = irq_desc_get_chip(desc); 604 unsigned long status; 605 u32 virq; 606 u32 bit = INTX_SHIFT; 607 608 chained_irq_enter(irqchip, desc); 609 610 status = readl(port->base + PCIE_INT_STATUS); 611 if (status & INTX_MASK) { 612 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { 613 /* Clear the INTx */ 614 writel(1 << bit, port->base + PCIE_INT_STATUS); 615 virq = irq_find_mapping(port->irq_domain, 616 bit - INTX_SHIFT); 617 generic_handle_irq(virq); 618 } 619 } 620 621 if (IS_ENABLED(CONFIG_PCI_MSI)) { 622 if (status & MSI_STATUS){ 623 unsigned long imsi_status; 624 625 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { 626 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) { 627 virq = irq_find_mapping(port->inner_domain, bit); 628 generic_handle_irq(virq); 629 } 630 } 631 /* Clear MSI interrupt status */ 632 writel(MSI_STATUS, port->base + PCIE_INT_STATUS); 633 } 634 } 635 636 chained_irq_exit(irqchip, desc); 637 } 638 639 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, 640 struct device_node *node) 641 { 642 struct mtk_pcie *pcie = port->pcie; 643 struct device *dev = pcie->dev; 644 struct platform_device *pdev = to_platform_device(dev); 645 int err; 646 647 err = mtk_pcie_init_irq_domain(port, node); 648 if (err) { 649 dev_err(dev, "failed to init PCIe IRQ domain\n"); 650 return err; 651 } 652 653 port->irq = platform_get_irq(pdev, port->slot); 654 irq_set_chained_handler_and_data(port->irq, 655 mtk_pcie_intr_handler, port); 656 657 return 0; 658 } 659 660 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) 661 { 662 struct mtk_pcie *pcie = port->pcie; 663 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 664 struct resource *mem = NULL; 665 struct resource_entry *entry; 666 const struct mtk_pcie_soc *soc = port->pcie->soc; 667 u32 val; 668 int err; 669 670 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); 671 if (entry) 672 mem = entry->res; 673 if (!mem) 674 return -EINVAL; 675 676 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ 677 if (pcie->base) { 678 val = readl(pcie->base + PCIE_SYS_CFG_V2); 679 val |= PCIE_CSR_LTSSM_EN(port->slot) | 680 PCIE_CSR_ASPM_L1_EN(port->slot); 681 writel(val, pcie->base + PCIE_SYS_CFG_V2); 682 } 683 684 /* Assert all reset signals */ 685 writel(0, port->base + PCIE_RST_CTRL); 686 687 /* 688 * Enable PCIe link down reset, if link status changed from link up to 689 * link down, this will reset MAC control registers and configuration 690 * space. 691 */ 692 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); 693 694 /* De-assert PHY, PE, PIPE, MAC and configuration reset */ 695 val = readl(port->base + PCIE_RST_CTRL); 696 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | 697 PCIE_MAC_SRSTB | PCIE_CRSTB; 698 writel(val, port->base + PCIE_RST_CTRL); 699 700 /* Set up vendor ID and class code */ 701 if (soc->need_fix_class_id) { 702 val = PCI_VENDOR_ID_MEDIATEK; 703 writew(val, port->base + PCIE_CONF_VEND_ID); 704 705 val = PCI_CLASS_BRIDGE_PCI; 706 writew(val, port->base + PCIE_CONF_CLASS_ID); 707 } 708 709 if (soc->need_fix_device_id) 710 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID); 711 712 /* 100ms timeout value should be enough for Gen1/2 training */ 713 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, 714 !!(val & PCIE_PORT_LINKUP_V2), 20, 715 100 * USEC_PER_MSEC); 716 if (err) 717 return -ETIMEDOUT; 718 719 /* Set INTx mask */ 720 val = readl(port->base + PCIE_INT_MASK); 721 val &= ~INTX_MASK; 722 writel(val, port->base + PCIE_INT_MASK); 723 724 if (IS_ENABLED(CONFIG_PCI_MSI)) 725 mtk_pcie_enable_msi(port); 726 727 /* Set AHB to PCIe translation windows */ 728 val = lower_32_bits(mem->start) | 729 AHB2PCIE_SIZE(fls(resource_size(mem))); 730 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); 731 732 val = upper_32_bits(mem->start); 733 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); 734 735 /* Set PCIe to AXI translation memory space.*/ 736 val = PCIE2AHB_SIZE | WIN_ENABLE; 737 writel(val, port->base + PCIE_AXI_WINDOW0); 738 739 return 0; 740 } 741 742 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, 743 unsigned int devfn, int where) 744 { 745 struct mtk_pcie *pcie = bus->sysdata; 746 747 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn), 748 bus->number), pcie->base + PCIE_CFG_ADDR); 749 750 return pcie->base + PCIE_CFG_DATA + (where & 3); 751 } 752 753 static struct pci_ops mtk_pcie_ops = { 754 .map_bus = mtk_pcie_map_bus, 755 .read = pci_generic_config_read, 756 .write = pci_generic_config_write, 757 }; 758 759 static int mtk_pcie_startup_port(struct mtk_pcie_port *port) 760 { 761 struct mtk_pcie *pcie = port->pcie; 762 u32 func = PCI_FUNC(port->slot << 3); 763 u32 slot = PCI_SLOT(port->slot << 3); 764 u32 val; 765 int err; 766 767 /* assert port PERST_N */ 768 val = readl(pcie->base + PCIE_SYS_CFG); 769 val |= PCIE_PORT_PERST(port->slot); 770 writel(val, pcie->base + PCIE_SYS_CFG); 771 772 /* de-assert port PERST_N */ 773 val = readl(pcie->base + PCIE_SYS_CFG); 774 val &= ~PCIE_PORT_PERST(port->slot); 775 writel(val, pcie->base + PCIE_SYS_CFG); 776 777 /* 100ms timeout value should be enough for Gen1/2 training */ 778 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, 779 !!(val & PCIE_PORT_LINKUP), 20, 780 100 * USEC_PER_MSEC); 781 if (err) 782 return -ETIMEDOUT; 783 784 /* enable interrupt */ 785 val = readl(pcie->base + PCIE_INT_ENABLE); 786 val |= PCIE_PORT_INT_EN(port->slot); 787 writel(val, pcie->base + PCIE_INT_ENABLE); 788 789 /* map to all DDR region. We need to set it before cfg operation. */ 790 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, 791 port->base + PCIE_BAR0_SETUP); 792 793 /* configure class code and revision ID */ 794 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); 795 796 /* configure FC credit */ 797 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0), 798 pcie->base + PCIE_CFG_ADDR); 799 val = readl(pcie->base + PCIE_CFG_DATA); 800 val &= ~PCIE_FC_CREDIT_MASK; 801 val |= PCIE_FC_CREDIT_VAL(0x806c); 802 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0), 803 pcie->base + PCIE_CFG_ADDR); 804 writel(val, pcie->base + PCIE_CFG_DATA); 805 806 /* configure RC FTS number to 250 when it leaves L0s */ 807 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0), 808 pcie->base + PCIE_CFG_ADDR); 809 val = readl(pcie->base + PCIE_CFG_DATA); 810 val &= ~PCIE_FTS_NUM_MASK; 811 val |= PCIE_FTS_NUM_L0(0x50); 812 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0), 813 pcie->base + PCIE_CFG_ADDR); 814 writel(val, pcie->base + PCIE_CFG_DATA); 815 816 return 0; 817 } 818 819 static void mtk_pcie_enable_port(struct mtk_pcie_port *port) 820 { 821 struct mtk_pcie *pcie = port->pcie; 822 struct device *dev = pcie->dev; 823 int err; 824 825 err = clk_prepare_enable(port->sys_ck); 826 if (err) { 827 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot); 828 goto err_sys_clk; 829 } 830 831 err = clk_prepare_enable(port->ahb_ck); 832 if (err) { 833 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot); 834 goto err_ahb_clk; 835 } 836 837 err = clk_prepare_enable(port->aux_ck); 838 if (err) { 839 dev_err(dev, "failed to enable aux_ck%d\n", port->slot); 840 goto err_aux_clk; 841 } 842 843 err = clk_prepare_enable(port->axi_ck); 844 if (err) { 845 dev_err(dev, "failed to enable axi_ck%d\n", port->slot); 846 goto err_axi_clk; 847 } 848 849 err = clk_prepare_enable(port->obff_ck); 850 if (err) { 851 dev_err(dev, "failed to enable obff_ck%d\n", port->slot); 852 goto err_obff_clk; 853 } 854 855 err = clk_prepare_enable(port->pipe_ck); 856 if (err) { 857 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot); 858 goto err_pipe_clk; 859 } 860 861 reset_control_assert(port->reset); 862 reset_control_deassert(port->reset); 863 864 err = phy_init(port->phy); 865 if (err) { 866 dev_err(dev, "failed to initialize port%d phy\n", port->slot); 867 goto err_phy_init; 868 } 869 870 err = phy_power_on(port->phy); 871 if (err) { 872 dev_err(dev, "failed to power on port%d phy\n", port->slot); 873 goto err_phy_on; 874 } 875 876 if (!pcie->soc->startup(port)) 877 return; 878 879 dev_info(dev, "Port%d link down\n", port->slot); 880 881 phy_power_off(port->phy); 882 err_phy_on: 883 phy_exit(port->phy); 884 err_phy_init: 885 clk_disable_unprepare(port->pipe_ck); 886 err_pipe_clk: 887 clk_disable_unprepare(port->obff_ck); 888 err_obff_clk: 889 clk_disable_unprepare(port->axi_ck); 890 err_axi_clk: 891 clk_disable_unprepare(port->aux_ck); 892 err_aux_clk: 893 clk_disable_unprepare(port->ahb_ck); 894 err_ahb_clk: 895 clk_disable_unprepare(port->sys_ck); 896 err_sys_clk: 897 mtk_pcie_port_free(port); 898 } 899 900 static int mtk_pcie_parse_port(struct mtk_pcie *pcie, 901 struct device_node *node, 902 int slot) 903 { 904 struct mtk_pcie_port *port; 905 struct resource *regs; 906 struct device *dev = pcie->dev; 907 struct platform_device *pdev = to_platform_device(dev); 908 char name[10]; 909 int err; 910 911 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 912 if (!port) 913 return -ENOMEM; 914 915 snprintf(name, sizeof(name), "port%d", slot); 916 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 917 port->base = devm_ioremap_resource(dev, regs); 918 if (IS_ERR(port->base)) { 919 dev_err(dev, "failed to map port%d base\n", slot); 920 return PTR_ERR(port->base); 921 } 922 923 snprintf(name, sizeof(name), "sys_ck%d", slot); 924 port->sys_ck = devm_clk_get(dev, name); 925 if (IS_ERR(port->sys_ck)) { 926 dev_err(dev, "failed to get sys_ck%d clock\n", slot); 927 return PTR_ERR(port->sys_ck); 928 } 929 930 /* sys_ck might be divided into the following parts in some chips */ 931 snprintf(name, sizeof(name), "ahb_ck%d", slot); 932 port->ahb_ck = devm_clk_get_optional(dev, name); 933 if (IS_ERR(port->ahb_ck)) 934 return PTR_ERR(port->ahb_ck); 935 936 snprintf(name, sizeof(name), "axi_ck%d", slot); 937 port->axi_ck = devm_clk_get_optional(dev, name); 938 if (IS_ERR(port->axi_ck)) 939 return PTR_ERR(port->axi_ck); 940 941 snprintf(name, sizeof(name), "aux_ck%d", slot); 942 port->aux_ck = devm_clk_get_optional(dev, name); 943 if (IS_ERR(port->aux_ck)) 944 return PTR_ERR(port->aux_ck); 945 946 snprintf(name, sizeof(name), "obff_ck%d", slot); 947 port->obff_ck = devm_clk_get_optional(dev, name); 948 if (IS_ERR(port->obff_ck)) 949 return PTR_ERR(port->obff_ck); 950 951 snprintf(name, sizeof(name), "pipe_ck%d", slot); 952 port->pipe_ck = devm_clk_get_optional(dev, name); 953 if (IS_ERR(port->pipe_ck)) 954 return PTR_ERR(port->pipe_ck); 955 956 snprintf(name, sizeof(name), "pcie-rst%d", slot); 957 port->reset = devm_reset_control_get_optional_exclusive(dev, name); 958 if (PTR_ERR(port->reset) == -EPROBE_DEFER) 959 return PTR_ERR(port->reset); 960 961 /* some platforms may use default PHY setting */ 962 snprintf(name, sizeof(name), "pcie-phy%d", slot); 963 port->phy = devm_phy_optional_get(dev, name); 964 if (IS_ERR(port->phy)) 965 return PTR_ERR(port->phy); 966 967 port->slot = slot; 968 port->pcie = pcie; 969 970 if (pcie->soc->setup_irq) { 971 err = pcie->soc->setup_irq(port, node); 972 if (err) 973 return err; 974 } 975 976 INIT_LIST_HEAD(&port->list); 977 list_add_tail(&port->list, &pcie->ports); 978 979 return 0; 980 } 981 982 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) 983 { 984 struct device *dev = pcie->dev; 985 struct platform_device *pdev = to_platform_device(dev); 986 struct resource *regs; 987 int err; 988 989 /* get shared registers, which are optional */ 990 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys"); 991 if (regs) { 992 pcie->base = devm_ioremap_resource(dev, regs); 993 if (IS_ERR(pcie->base)) { 994 dev_err(dev, "failed to map shared register\n"); 995 return PTR_ERR(pcie->base); 996 } 997 } 998 999 pcie->free_ck = devm_clk_get(dev, "free_ck"); 1000 if (IS_ERR(pcie->free_ck)) { 1001 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) 1002 return -EPROBE_DEFER; 1003 1004 pcie->free_ck = NULL; 1005 } 1006 1007 pm_runtime_enable(dev); 1008 pm_runtime_get_sync(dev); 1009 1010 /* enable top level clock */ 1011 err = clk_prepare_enable(pcie->free_ck); 1012 if (err) { 1013 dev_err(dev, "failed to enable free_ck\n"); 1014 goto err_free_ck; 1015 } 1016 1017 return 0; 1018 1019 err_free_ck: 1020 pm_runtime_put_sync(dev); 1021 pm_runtime_disable(dev); 1022 1023 return err; 1024 } 1025 1026 static int mtk_pcie_setup(struct mtk_pcie *pcie) 1027 { 1028 struct device *dev = pcie->dev; 1029 struct device_node *node = dev->of_node, *child; 1030 struct mtk_pcie_port *port, *tmp; 1031 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1032 struct list_head *windows = &host->windows; 1033 struct resource *bus; 1034 int err; 1035 1036 err = pci_parse_request_of_pci_ranges(dev, windows, 1037 &host->dma_ranges, &bus); 1038 if (err) 1039 return err; 1040 1041 pcie->busnr = bus->start; 1042 1043 for_each_available_child_of_node(node, child) { 1044 int slot; 1045 1046 err = of_pci_get_devfn(child); 1047 if (err < 0) { 1048 dev_err(dev, "failed to parse devfn: %d\n", err); 1049 return err; 1050 } 1051 1052 slot = PCI_SLOT(err); 1053 1054 err = mtk_pcie_parse_port(pcie, child, slot); 1055 if (err) 1056 return err; 1057 } 1058 1059 err = mtk_pcie_subsys_powerup(pcie); 1060 if (err) 1061 return err; 1062 1063 /* enable each port, and then check link status */ 1064 list_for_each_entry_safe(port, tmp, &pcie->ports, list) 1065 mtk_pcie_enable_port(port); 1066 1067 /* power down PCIe subsys if slots are all empty (link down) */ 1068 if (list_empty(&pcie->ports)) 1069 mtk_pcie_subsys_powerdown(pcie); 1070 1071 return 0; 1072 } 1073 1074 static int mtk_pcie_probe(struct platform_device *pdev) 1075 { 1076 struct device *dev = &pdev->dev; 1077 struct mtk_pcie *pcie; 1078 struct pci_host_bridge *host; 1079 int err; 1080 1081 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 1082 if (!host) 1083 return -ENOMEM; 1084 1085 pcie = pci_host_bridge_priv(host); 1086 1087 pcie->dev = dev; 1088 pcie->soc = of_device_get_match_data(dev); 1089 platform_set_drvdata(pdev, pcie); 1090 INIT_LIST_HEAD(&pcie->ports); 1091 1092 err = mtk_pcie_setup(pcie); 1093 if (err) 1094 return err; 1095 1096 host->busnr = pcie->busnr; 1097 host->dev.parent = pcie->dev; 1098 host->ops = pcie->soc->ops; 1099 host->map_irq = of_irq_parse_and_map_pci; 1100 host->swizzle_irq = pci_common_swizzle; 1101 host->sysdata = pcie; 1102 1103 err = pci_host_probe(host); 1104 if (err) 1105 goto put_resources; 1106 1107 return 0; 1108 1109 put_resources: 1110 if (!list_empty(&pcie->ports)) 1111 mtk_pcie_put_resources(pcie); 1112 1113 return err; 1114 } 1115 1116 1117 static void mtk_pcie_free_resources(struct mtk_pcie *pcie) 1118 { 1119 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1120 struct list_head *windows = &host->windows; 1121 1122 pci_free_resource_list(windows); 1123 } 1124 1125 static int mtk_pcie_remove(struct platform_device *pdev) 1126 { 1127 struct mtk_pcie *pcie = platform_get_drvdata(pdev); 1128 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1129 1130 pci_stop_root_bus(host->bus); 1131 pci_remove_root_bus(host->bus); 1132 mtk_pcie_free_resources(pcie); 1133 1134 mtk_pcie_irq_teardown(pcie); 1135 1136 mtk_pcie_put_resources(pcie); 1137 1138 return 0; 1139 } 1140 1141 static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev) 1142 { 1143 struct mtk_pcie *pcie = dev_get_drvdata(dev); 1144 struct mtk_pcie_port *port; 1145 1146 if (list_empty(&pcie->ports)) 1147 return 0; 1148 1149 list_for_each_entry(port, &pcie->ports, list) { 1150 clk_disable_unprepare(port->pipe_ck); 1151 clk_disable_unprepare(port->obff_ck); 1152 clk_disable_unprepare(port->axi_ck); 1153 clk_disable_unprepare(port->aux_ck); 1154 clk_disable_unprepare(port->ahb_ck); 1155 clk_disable_unprepare(port->sys_ck); 1156 phy_power_off(port->phy); 1157 phy_exit(port->phy); 1158 } 1159 1160 clk_disable_unprepare(pcie->free_ck); 1161 1162 return 0; 1163 } 1164 1165 static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev) 1166 { 1167 struct mtk_pcie *pcie = dev_get_drvdata(dev); 1168 struct mtk_pcie_port *port, *tmp; 1169 1170 if (list_empty(&pcie->ports)) 1171 return 0; 1172 1173 clk_prepare_enable(pcie->free_ck); 1174 1175 list_for_each_entry_safe(port, tmp, &pcie->ports, list) 1176 mtk_pcie_enable_port(port); 1177 1178 /* In case of EP was removed while system suspend. */ 1179 if (list_empty(&pcie->ports)) 1180 clk_disable_unprepare(pcie->free_ck); 1181 1182 return 0; 1183 } 1184 1185 static const struct dev_pm_ops mtk_pcie_pm_ops = { 1186 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq, 1187 mtk_pcie_resume_noirq) 1188 }; 1189 1190 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = { 1191 .ops = &mtk_pcie_ops, 1192 .startup = mtk_pcie_startup_port, 1193 }; 1194 1195 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = { 1196 .ops = &mtk_pcie_ops_v2, 1197 .startup = mtk_pcie_startup_port_v2, 1198 .setup_irq = mtk_pcie_setup_irq, 1199 }; 1200 1201 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = { 1202 .need_fix_class_id = true, 1203 .ops = &mtk_pcie_ops_v2, 1204 .startup = mtk_pcie_startup_port_v2, 1205 .setup_irq = mtk_pcie_setup_irq, 1206 }; 1207 1208 static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = { 1209 .need_fix_class_id = true, 1210 .need_fix_device_id = true, 1211 .device_id = PCI_DEVICE_ID_MEDIATEK_7629, 1212 .ops = &mtk_pcie_ops_v2, 1213 .startup = mtk_pcie_startup_port_v2, 1214 .setup_irq = mtk_pcie_setup_irq, 1215 }; 1216 1217 static const struct of_device_id mtk_pcie_ids[] = { 1218 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 }, 1219 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 }, 1220 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, 1221 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 }, 1222 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 }, 1223 {}, 1224 }; 1225 1226 static struct platform_driver mtk_pcie_driver = { 1227 .probe = mtk_pcie_probe, 1228 .remove = mtk_pcie_remove, 1229 .driver = { 1230 .name = "mtk-pcie", 1231 .of_match_table = mtk_pcie_ids, 1232 .suppress_bind_attrs = true, 1233 .pm = &mtk_pcie_pm_ops, 1234 }, 1235 }; 1236 module_platform_driver(mtk_pcie_driver); 1237 MODULE_LICENSE("GPL v2"); 1238