1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Marvell 4 * 5 * Authors: 6 * Evan Wang <xswang@marvell.com> 7 * Miquèl Raynal <miquel.raynal@bootlin.com> 8 * Pali Rohár <pali@kernel.org> 9 * Marek Behún <kabel@kernel.org> 10 * 11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart. 12 * Comphy code from ARM Trusted Firmware ported by Pali Rohár <pali@kernel.org> 13 * and Marek Behún <kabel@kernel.org>. 14 */ 15 16 #include <linux/bitfield.h> 17 #include <linux/clk.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/module.h> 22 #include <linux/phy.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/spinlock.h> 26 27 #define PLL_SET_DELAY_US 600 28 #define COMPHY_PLL_SLEEP 1000 29 #define COMPHY_PLL_TIMEOUT 150000 30 31 /* Comphy lane2 indirect access register offset */ 32 #define COMPHY_LANE2_INDIR_ADDR 0x0 33 #define COMPHY_LANE2_INDIR_DATA 0x4 34 35 /* SATA and USB3 PHY offset compared to SATA PHY */ 36 #define COMPHY_LANE2_REGS_BASE 0x200 37 38 /* 39 * When accessing common PHY lane registers directly, we need to shift by 1, 40 * since the registers are 16-bit. 41 */ 42 #define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1) 43 44 /* COMPHY registers */ 45 #define COMPHY_POWER_PLL_CTRL 0x01 46 #define PU_IVREF_BIT BIT(15) 47 #define PU_PLL_BIT BIT(14) 48 #define PU_RX_BIT BIT(13) 49 #define PU_TX_BIT BIT(12) 50 #define PU_TX_INTP_BIT BIT(11) 51 #define PU_DFE_BIT BIT(10) 52 #define RESET_DTL_RX_BIT BIT(9) 53 #define PLL_LOCK_BIT BIT(8) 54 #define REF_FREF_SEL_MASK GENMASK(4, 0) 55 #define REF_FREF_SEL_SERDES_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x1) 56 #define REF_FREF_SEL_SERDES_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3) 57 #define REF_FREF_SEL_SERDES_50MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x4) 58 #define REF_FREF_SEL_PCIE_USB3_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x2) 59 #define REF_FREF_SEL_PCIE_USB3_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3) 60 #define COMPHY_MODE_MASK GENMASK(7, 5) 61 #define COMPHY_MODE_SATA FIELD_PREP(COMPHY_MODE_MASK, 0x0) 62 #define COMPHY_MODE_PCIE FIELD_PREP(COMPHY_MODE_MASK, 0x3) 63 #define COMPHY_MODE_SERDES FIELD_PREP(COMPHY_MODE_MASK, 0x4) 64 #define COMPHY_MODE_USB3 FIELD_PREP(COMPHY_MODE_MASK, 0x5) 65 66 #define COMPHY_KVCO_CAL_CTRL 0x02 67 #define USE_MAX_PLL_RATE_BIT BIT(12) 68 #define SPEED_PLL_MASK GENMASK(7, 2) 69 #define SPEED_PLL_VALUE_16 FIELD_PREP(SPEED_PLL_MASK, 0x10) 70 71 #define COMPHY_DIG_LOOPBACK_EN 0x23 72 #define SEL_DATA_WIDTH_MASK GENMASK(11, 10) 73 #define DATA_WIDTH_10BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x0) 74 #define DATA_WIDTH_20BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x1) 75 #define DATA_WIDTH_40BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x2) 76 #define PLL_READY_TX_BIT BIT(4) 77 78 #define COMPHY_SYNC_PATTERN 0x24 79 #define TXD_INVERT_BIT BIT(10) 80 #define RXD_INVERT_BIT BIT(11) 81 82 #define COMPHY_SYNC_MASK_GEN 0x25 83 #define PHY_GEN_MAX_MASK GENMASK(11, 10) 84 #define PHY_GEN_MAX_USB3_5G FIELD_PREP(PHY_GEN_MAX_MASK, 0x1) 85 86 #define COMPHY_ISOLATION_CTRL 0x26 87 #define PHY_ISOLATE_MODE BIT(15) 88 89 #define COMPHY_GEN2_SET2 0x3e 90 #define GS2_TX_SSC_AMP_MASK GENMASK(15, 9) 91 #define GS2_TX_SSC_AMP_4128 FIELD_PREP(GS2_TX_SSC_AMP_MASK, 0x20) 92 #define GS2_VREG_RXTX_MAS_ISET_MASK GENMASK(8, 7) 93 #define GS2_VREG_RXTX_MAS_ISET_60U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ 94 0x0) 95 #define GS2_VREG_RXTX_MAS_ISET_80U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ 96 0x1) 97 #define GS2_VREG_RXTX_MAS_ISET_100U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ 98 0x2) 99 #define GS2_VREG_RXTX_MAS_ISET_120U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ 100 0x3) 101 #define GS2_RSVD_6_0_MASK GENMASK(6, 0) 102 103 #define COMPHY_GEN3_SET2 0x3f 104 105 #define COMPHY_IDLE_SYNC_EN 0x48 106 #define IDLE_SYNC_EN BIT(12) 107 108 #define COMPHY_MISC_CTRL0 0x4F 109 #define CLK100M_125M_EN BIT(4) 110 #define TXDCLK_2X_SEL BIT(6) 111 #define CLK500M_EN BIT(7) 112 #define PHY_REF_CLK_SEL BIT(10) 113 114 #define COMPHY_SFT_RESET 0x52 115 #define SFT_RST BIT(9) 116 #define SFT_RST_NO_REG BIT(10) 117 118 #define COMPHY_MISC_CTRL1 0x73 119 #define SEL_BITS_PCIE_FORCE BIT(15) 120 121 #define COMPHY_GEN2_SET3 0x112 122 #define GS3_FFE_CAP_SEL_MASK GENMASK(3, 0) 123 #define GS3_FFE_CAP_SEL_VALUE FIELD_PREP(GS3_FFE_CAP_SEL_MASK, 0xF) 124 125 /* PIPE registers */ 126 #define COMPHY_PIPE_LANE_CFG0 0x180 127 #define PRD_TXDEEMPH0_MASK BIT(0) 128 #define PRD_TXMARGIN_MASK GENMASK(3, 1) 129 #define PRD_TXSWING_MASK BIT(4) 130 #define CFG_TX_ALIGN_POS_MASK GENMASK(8, 5) 131 132 #define COMPHY_PIPE_LANE_CFG1 0x181 133 #define PRD_TXDEEMPH1_MASK BIT(15) 134 #define USE_MAX_PLL_RATE_EN BIT(9) 135 #define TX_DET_RX_MODE BIT(6) 136 #define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3) 137 #define GEN2_TX_DATA_DLY_DEFT FIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2) 138 #define TX_ELEC_IDLE_MODE_EN BIT(0) 139 140 #define COMPHY_PIPE_LANE_STAT1 0x183 141 #define TXDCLK_PCLK_EN BIT(0) 142 143 #define COMPHY_PIPE_LANE_CFG4 0x188 144 #define SPREAD_SPECTRUM_CLK_EN BIT(7) 145 146 #define COMPHY_PIPE_RST_CLK_CTRL 0x1C1 147 #define PIPE_SOFT_RESET BIT(0) 148 #define PIPE_REG_RESET BIT(1) 149 #define MODE_CORE_CLK_FREQ_SEL BIT(9) 150 #define MODE_PIPE_WIDTH_32 BIT(3) 151 #define MODE_REFDIV_MASK GENMASK(5, 4) 152 #define MODE_REFDIV_BY_4 FIELD_PREP(MODE_REFDIV_MASK, 0x2) 153 154 #define COMPHY_PIPE_TEST_MODE_CTRL 0x1C2 155 #define MODE_MARGIN_OVERRIDE BIT(2) 156 157 #define COMPHY_PIPE_CLK_SRC_LO 0x1C3 158 #define MODE_CLK_SRC BIT(0) 159 #define BUNDLE_PERIOD_SEL BIT(1) 160 #define BUNDLE_PERIOD_SCALE_MASK GENMASK(3, 2) 161 #define BUNDLE_SAMPLE_CTRL BIT(4) 162 #define PLL_READY_DLY_MASK GENMASK(7, 5) 163 #define CFG_SEL_20B BIT(15) 164 165 #define COMPHY_PIPE_PWR_MGM_TIM1 0x1D0 166 #define CFG_PM_OSCCLK_WAIT_MASK GENMASK(15, 12) 167 #define CFG_PM_RXDEN_WAIT_MASK GENMASK(11, 8) 168 #define CFG_PM_RXDEN_WAIT_1_UNIT FIELD_PREP(CFG_PM_RXDEN_WAIT_MASK, 0x1) 169 #define CFG_PM_RXDLOZ_WAIT_MASK GENMASK(7, 0) 170 #define CFG_PM_RXDLOZ_WAIT_7_UNIT FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0x7) 171 #define CFG_PM_RXDLOZ_WAIT_12_UNIT FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0xC) 172 173 /* 174 * This register is not from PHY lane register space. It only exists in the 175 * indirect register space, before the actual PHY lane 2 registers. So the 176 * offset is absolute, not relative to COMPHY_LANE2_REGS_BASE. 177 * It is used only for SATA PHY initialization. 178 */ 179 #define COMPHY_RESERVED_REG 0x0E 180 #define PHYCTRL_FRM_PIN_BIT BIT(13) 181 182 /* South Bridge PHY Configuration Registers */ 183 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) 184 185 /* 186 * lane0: USB3/GbE1 PHY Configuration 1 187 * lane1: PCIe/GbE0 PHY Configuration 1 188 * (used only by SGMII code) 189 */ 190 #define COMPHY_PHY_CFG1 0x0 191 #define PIN_PU_IVREF_BIT BIT(1) 192 #define PIN_RESET_CORE_BIT BIT(11) 193 #define PIN_RESET_COMPHY_BIT BIT(12) 194 #define PIN_PU_PLL_BIT BIT(16) 195 #define PIN_PU_RX_BIT BIT(17) 196 #define PIN_PU_TX_BIT BIT(18) 197 #define PIN_TX_IDLE_BIT BIT(19) 198 #define GEN_RX_SEL_MASK GENMASK(25, 22) 199 #define GEN_RX_SEL_VALUE(val) FIELD_PREP(GEN_RX_SEL_MASK, (val)) 200 #define GEN_TX_SEL_MASK GENMASK(29, 26) 201 #define GEN_TX_SEL_VALUE(val) FIELD_PREP(GEN_TX_SEL_MASK, (val)) 202 #define SERDES_SPEED_1_25_G 0x6 203 #define SERDES_SPEED_3_125_G 0x8 204 #define PHY_RX_INIT_BIT BIT(30) 205 206 /* 207 * lane0: USB3/GbE1 PHY Status 1 208 * lane1: PCIe/GbE0 PHY Status 1 209 * (used only by SGMII code) 210 */ 211 #define COMPHY_PHY_STAT1 0x18 212 #define PHY_RX_INIT_DONE_BIT BIT(0) 213 #define PHY_PLL_READY_RX_BIT BIT(2) 214 #define PHY_PLL_READY_TX_BIT BIT(3) 215 216 /* PHY Selector */ 217 #define COMPHY_SELECTOR_PHY_REG 0xFC 218 /* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */ 219 #define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0) 220 /* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */ 221 #define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4) 222 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */ 223 #define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8) 224 225 struct mvebu_a3700_comphy_conf { 226 unsigned int lane; 227 enum phy_mode mode; 228 int submode; 229 }; 230 231 #define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode) \ 232 { \ 233 .lane = _lane, \ 234 .mode = _mode, \ 235 .submode = _smode, \ 236 } 237 238 #define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode) \ 239 MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA) 240 241 #define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode) \ 242 MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode) 243 244 static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = { 245 /* lane 0 */ 246 MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS), 247 MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII), 248 MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_1000BASEX), 249 MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX), 250 /* lane 1 */ 251 MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE), 252 MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII), 253 MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_1000BASEX), 254 MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX), 255 /* lane 2 */ 256 MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA), 257 MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS), 258 }; 259 260 struct mvebu_a3700_comphy_priv { 261 void __iomem *comphy_regs; 262 void __iomem *lane0_phy_regs; /* USB3 and GbE1 */ 263 void __iomem *lane1_phy_regs; /* PCIe and GbE0 */ 264 void __iomem *lane2_phy_indirect; /* SATA and USB3 */ 265 spinlock_t lock; /* for PHY selector access */ 266 bool xtal_is_40m; 267 }; 268 269 struct mvebu_a3700_comphy_lane { 270 struct mvebu_a3700_comphy_priv *priv; 271 struct device *dev; 272 unsigned int id; 273 enum phy_mode mode; 274 int submode; 275 bool invert_tx; 276 bool invert_rx; 277 }; 278 279 struct gbe_phy_init_data_fix { 280 u16 addr; 281 u16 value; 282 }; 283 284 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ 285 static struct gbe_phy_init_data_fix gbe_phy_init_fix[] = { 286 { 0x005, 0x07CC }, { 0x015, 0x0000 }, { 0x01B, 0x0000 }, 287 { 0x01D, 0x0000 }, { 0x01E, 0x0000 }, { 0x01F, 0x0000 }, 288 { 0x020, 0x0000 }, { 0x021, 0x0030 }, { 0x026, 0x0888 }, 289 { 0x04D, 0x0152 }, { 0x04F, 0xA020 }, { 0x050, 0x07CC }, 290 { 0x053, 0xE9CA }, { 0x055, 0xBD97 }, { 0x071, 0x3015 }, 291 { 0x076, 0x03AA }, { 0x07C, 0x0FDF }, { 0x0C2, 0x3030 }, 292 { 0x0C3, 0x8000 }, { 0x0E2, 0x5550 }, { 0x0E3, 0x12A4 }, 293 { 0x0E4, 0x7D00 }, { 0x0E6, 0x0C83 }, { 0x101, 0xFCC0 }, 294 { 0x104, 0x0C10 } 295 }; 296 297 /* 40M1G25 mode init data */ 298 static u16 gbe_phy_init[512] = { 299 /* 0 1 2 3 4 5 6 7 */ 300 /*-----------------------------------------------------------*/ 301 /* 8 9 A B C D E F */ 302 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ 303 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ 304 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ 305 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ 306 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ 307 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ 308 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 309 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ 310 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ 311 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ 312 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ 313 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ 314 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ 315 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ 316 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ 317 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ 318 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ 319 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ 320 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ 321 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ 322 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ 323 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ 324 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ 325 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ 326 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ 327 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ 328 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ 329 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ 330 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ 331 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ 332 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ 333 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ 334 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ 335 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ 336 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ 337 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ 338 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ 339 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ 340 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ 341 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ 342 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ 343 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ 344 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ 345 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ 346 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ 347 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ 348 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ 349 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ 350 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ 351 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ 352 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ 353 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ 354 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ 355 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ 356 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ 357 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ 358 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ 359 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ 360 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ 361 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ 362 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ 363 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ 364 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ 365 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ 366 }; 367 368 static inline void comphy_reg_set(void __iomem *addr, u32 data, u32 mask) 369 { 370 u32 val; 371 372 val = readl(addr); 373 val = (val & ~mask) | (data & mask); 374 writel(val, addr); 375 } 376 377 static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask) 378 { 379 u16 val; 380 381 val = readw(addr); 382 val = (val & ~mask) | (data & mask); 383 writew(val, addr); 384 } 385 386 /* Used for accessing lane 2 registers (SATA/USB3 PHY) */ 387 static void comphy_set_indirect(struct mvebu_a3700_comphy_priv *priv, 388 u32 offset, u16 data, u16 mask) 389 { 390 writel(offset, 391 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); 392 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, 393 data, mask); 394 } 395 396 static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane, 397 u16 reg, u16 data, u16 mask) 398 { 399 if (lane->id == 2) { 400 /* lane 2 PHY registers are accessed indirectly */ 401 comphy_set_indirect(lane->priv, 402 reg + COMPHY_LANE2_REGS_BASE, 403 data, mask); 404 } else { 405 void __iomem *base = lane->id == 1 ? 406 lane->priv->lane1_phy_regs : 407 lane->priv->lane0_phy_regs; 408 409 comphy_reg_set16(base + COMPHY_LANE_REG_DIRECT(reg), 410 data, mask); 411 } 412 } 413 414 static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane, 415 u16 reg, u16 bits, 416 ulong sleep_us, ulong timeout_us) 417 { 418 int ret; 419 420 if (lane->id == 2) { 421 u32 data; 422 423 /* lane 2 PHY registers are accessed indirectly */ 424 writel(reg + COMPHY_LANE2_REGS_BASE, 425 lane->priv->lane2_phy_indirect + 426 COMPHY_LANE2_INDIR_ADDR); 427 428 ret = readl_poll_timeout(lane->priv->lane2_phy_indirect + 429 COMPHY_LANE2_INDIR_DATA, 430 data, (data & bits) == bits, 431 sleep_us, timeout_us); 432 } else { 433 void __iomem *base = lane->id == 1 ? 434 lane->priv->lane1_phy_regs : 435 lane->priv->lane0_phy_regs; 436 u16 data; 437 438 ret = readw_poll_timeout(base + COMPHY_LANE_REG_DIRECT(reg), 439 data, (data & bits) == bits, 440 sleep_us, timeout_us); 441 } 442 443 return ret; 444 } 445 446 static void comphy_periph_reg_set(struct mvebu_a3700_comphy_lane *lane, 447 u8 reg, u32 data, u32 mask) 448 { 449 comphy_reg_set(lane->priv->comphy_regs + COMPHY_PHY_REG(lane->id, reg), 450 data, mask); 451 } 452 453 static int comphy_periph_reg_poll(struct mvebu_a3700_comphy_lane *lane, 454 u8 reg, u32 bits, 455 ulong sleep_us, ulong timeout_us) 456 { 457 u32 data; 458 459 return readl_poll_timeout(lane->priv->comphy_regs + 460 COMPHY_PHY_REG(lane->id, reg), 461 data, (data & bits) == bits, 462 sleep_us, timeout_us); 463 } 464 465 /* PHY selector configures with corresponding modes */ 466 static int 467 mvebu_a3700_comphy_set_phy_selector(struct mvebu_a3700_comphy_lane *lane) 468 { 469 u32 old, new, clr = 0, set = 0; 470 unsigned long flags; 471 472 switch (lane->mode) { 473 case PHY_MODE_SATA: 474 /* SATA must be in Lane2 */ 475 if (lane->id == 2) 476 clr = COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 477 else 478 goto error; 479 break; 480 481 case PHY_MODE_ETHERNET: 482 if (lane->id == 0) 483 clr = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 484 else if (lane->id == 1) 485 clr = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 486 else 487 goto error; 488 break; 489 490 case PHY_MODE_USB_HOST_SS: 491 if (lane->id == 2) 492 set = COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 493 else if (lane->id == 0) 494 set = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 495 else 496 goto error; 497 break; 498 499 case PHY_MODE_PCIE: 500 /* PCIE must be in Lane1 */ 501 if (lane->id == 1) 502 set = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 503 else 504 goto error; 505 break; 506 507 default: 508 goto error; 509 } 510 511 spin_lock_irqsave(&lane->priv->lock, flags); 512 513 old = readl(lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG); 514 new = (old & ~clr) | set; 515 writel(new, lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG); 516 517 spin_unlock_irqrestore(&lane->priv->lock, flags); 518 519 dev_dbg(lane->dev, 520 "COMPHY[%d] mode[%d] changed PHY selector 0x%08x -> 0x%08x\n", 521 lane->id, lane->mode, old, new); 522 523 return 0; 524 error: 525 dev_err(lane->dev, "COMPHY[%d] mode[%d] is invalid\n", lane->id, 526 lane->mode); 527 return -EINVAL; 528 } 529 530 static int 531 mvebu_a3700_comphy_sata_power_on(struct mvebu_a3700_comphy_lane *lane) 532 { 533 u32 mask, data, ref_clk; 534 int ret; 535 536 /* Configure phy selector for SATA */ 537 ret = mvebu_a3700_comphy_set_phy_selector(lane); 538 if (ret) 539 return ret; 540 541 /* Clear phy isolation mode to make it work in normal mode */ 542 comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL, 543 0x0, PHY_ISOLATE_MODE); 544 545 /* 0. Check the Polarity invert bits */ 546 data = 0x0; 547 if (lane->invert_tx) 548 data |= TXD_INVERT_BIT; 549 if (lane->invert_rx) 550 data |= RXD_INVERT_BIT; 551 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 552 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); 553 554 /* 1. Select 40-bit data width */ 555 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, 556 DATA_WIDTH_40BIT, SEL_DATA_WIDTH_MASK); 557 558 /* 2. Select reference clock(25M) and PHY mode (SATA) */ 559 if (lane->priv->xtal_is_40m) 560 ref_clk = REF_FREF_SEL_SERDES_40MHZ; 561 else 562 ref_clk = REF_FREF_SEL_SERDES_25MHZ; 563 564 data = ref_clk | COMPHY_MODE_SATA; 565 mask = REF_FREF_SEL_MASK | COMPHY_MODE_MASK; 566 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 567 568 /* 3. Use maximum PLL rate (no power save) */ 569 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, 570 USE_MAX_PLL_RATE_BIT, USE_MAX_PLL_RATE_BIT); 571 572 /* 4. Reset reserved bit */ 573 comphy_set_indirect(lane->priv, COMPHY_RESERVED_REG, 574 0x0, PHYCTRL_FRM_PIN_BIT); 575 576 /* 5. Set vendor-specific configuration (It is done in sata driver) */ 577 /* XXX: in U-Boot below sequence was executed in this place, in Linux 578 * not. Now it is done only in U-Boot before this comphy 579 * initialization - tests shows that it works ok, but in case of any 580 * future problem it is left for reference. 581 * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff); 582 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); 583 */ 584 585 /* Wait for > 55 us to allow PLL be enabled */ 586 udelay(PLL_SET_DELAY_US); 587 588 /* Polling status */ 589 ret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN, 590 PLL_READY_TX_BIT, COMPHY_PLL_SLEEP, 591 COMPHY_PLL_TIMEOUT); 592 if (ret) 593 dev_err(lane->dev, "Failed to lock SATA PLL\n"); 594 595 return ret; 596 } 597 598 static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane, 599 bool is_1gbps) 600 { 601 int addr, fix_idx; 602 u16 val; 603 604 fix_idx = 0; 605 for (addr = 0; addr < 512; addr++) { 606 /* 607 * All PHY register values are defined in full for 3.125Gbps 608 * SERDES speed. The values required for 1.25 Gbps are almost 609 * the same and only few registers should be "fixed" in 610 * comparison to 3.125 Gbps values. These register values are 611 * stored in "gbe_phy_init_fix" array. 612 */ 613 if (!is_1gbps && gbe_phy_init_fix[fix_idx].addr == addr) { 614 /* Use new value */ 615 val = gbe_phy_init_fix[fix_idx].value; 616 if (fix_idx < ARRAY_SIZE(gbe_phy_init_fix)) 617 fix_idx++; 618 } else { 619 val = gbe_phy_init[addr]; 620 } 621 622 comphy_lane_reg_set(lane, addr, val, 0xFFFF); 623 } 624 } 625 626 static int 627 mvebu_a3700_comphy_ethernet_power_on(struct mvebu_a3700_comphy_lane *lane) 628 { 629 u32 mask, data, speed_sel; 630 int ret; 631 632 /* Set selector */ 633 ret = mvebu_a3700_comphy_set_phy_selector(lane); 634 if (ret) 635 return ret; 636 637 /* 638 * 1. Reset PHY by setting PHY input port PIN_RESET=1. 639 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep 640 * PHY TXP/TXN output to idle state during PHY initialization 641 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. 642 */ 643 data = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; 644 mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | 645 PIN_PU_TX_BIT | PHY_RX_INIT_BIT; 646 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 647 648 /* 4. Release reset to the PHY by setting PIN_RESET=0. */ 649 data = 0x0; 650 mask = PIN_RESET_COMPHY_BIT; 651 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 652 653 /* 654 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY 655 * bit rate 656 */ 657 switch (lane->submode) { 658 case PHY_INTERFACE_MODE_SGMII: 659 case PHY_INTERFACE_MODE_1000BASEX: 660 /* SGMII 1G, SerDes speed 1.25G */ 661 speed_sel = SERDES_SPEED_1_25_G; 662 break; 663 case PHY_INTERFACE_MODE_2500BASEX: 664 /* 2500Base-X, SerDes speed 3.125G */ 665 speed_sel = SERDES_SPEED_3_125_G; 666 break; 667 default: 668 /* Other rates are not supported */ 669 dev_err(lane->dev, 670 "unsupported phy speed %d on comphy lane%d\n", 671 lane->submode, lane->id); 672 return -EINVAL; 673 } 674 data = GEN_RX_SEL_VALUE(speed_sel) | GEN_TX_SEL_VALUE(speed_sel); 675 mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK; 676 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 677 678 /* 679 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then 680 * start SW programming. 681 */ 682 mdelay(10); 683 684 /* 7. Program COMPHY register PHY_MODE */ 685 data = COMPHY_MODE_SERDES; 686 mask = COMPHY_MODE_MASK; 687 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 688 689 /* 690 * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK 691 * source 692 */ 693 data = 0x0; 694 mask = PHY_REF_CLK_SEL; 695 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask); 696 697 /* 698 * 9. Set correct reference clock frequency in COMPHY register 699 * REF_FREF_SEL. 700 */ 701 if (lane->priv->xtal_is_40m) 702 data = REF_FREF_SEL_SERDES_50MHZ; 703 else 704 data = REF_FREF_SEL_SERDES_25MHZ; 705 706 mask = REF_FREF_SEL_MASK; 707 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 708 709 /* 710 * 10. Program COMPHY register PHY_GEN_MAX[1:0] 711 * This step is mentioned in the flow received from verification team. 712 * However the PHY_GEN_MAX value is only meaningful for other interfaces 713 * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or 714 * PCIe speed 2.5/5 Gbps 715 */ 716 717 /* 718 * 11. Program COMPHY register SEL_BITS to set correct parallel data 719 * bus width 720 */ 721 data = DATA_WIDTH_10BIT; 722 mask = SEL_DATA_WIDTH_MASK; 723 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask); 724 725 /* 726 * 12. As long as DFE function needs to be enabled in any mode, 727 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F 728 * for real chip during COMPHY power on. 729 * The value of the DFE_UPDATE_EN already is 0x3F, because it is the 730 * default value after reset of the PHY. 731 */ 732 733 /* 734 * 13. Program COMPHY GEN registers. 735 * These registers should be programmed based on the lab testing result 736 * to achieve optimal performance. Please contact the CEA group to get 737 * the related GEN table during real chip bring-up. We only required to 738 * run though the entire registers programming flow defined by 739 * "comphy_gbe_phy_init" when the REF clock is 40 MHz. For REF clock 740 * 25 MHz the default values stored in PHY registers are OK. 741 */ 742 dev_dbg(lane->dev, "Running C-DPI phy init %s mode\n", 743 lane->submode == PHY_INTERFACE_MODE_2500BASEX ? "2G5" : "1G"); 744 if (lane->priv->xtal_is_40m) 745 comphy_gbe_phy_init(lane, 746 lane->submode != PHY_INTERFACE_MODE_2500BASEX); 747 748 /* 749 * 14. Check the PHY Polarity invert bit 750 */ 751 data = 0x0; 752 if (lane->invert_tx) 753 data |= TXD_INVERT_BIT; 754 if (lane->invert_rx) 755 data |= RXD_INVERT_BIT; 756 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 757 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); 758 759 /* 760 * 15. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to 761 * start PHY power up sequence. All the PHY register programming should 762 * be done before PIN_PU_PLL=1. There should be no register programming 763 * for normal PHY operation from this point. 764 */ 765 data = PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT; 766 mask = data; 767 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 768 769 /* 770 * 16. Wait for PHY power up sequence to finish by checking output ports 771 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. 772 */ 773 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, 774 PHY_PLL_READY_TX_BIT | 775 PHY_PLL_READY_RX_BIT, 776 COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 777 if (ret) { 778 dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n", 779 lane->id); 780 return ret; 781 } 782 783 /* 784 * 17. Set COMPHY input port PIN_TX_IDLE=0 785 */ 786 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT); 787 788 /* 789 * 18. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To 790 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the 791 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to 792 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please 793 * refer to RX initialization part for details. 794 */ 795 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 796 PHY_RX_INIT_BIT, PHY_RX_INIT_BIT); 797 798 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, 799 PHY_PLL_READY_TX_BIT | 800 PHY_PLL_READY_RX_BIT, 801 COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 802 if (ret) { 803 dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n", 804 lane->id); 805 return ret; 806 } 807 808 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, 809 PHY_RX_INIT_DONE_BIT, 810 COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 811 if (ret) 812 dev_err(lane->dev, "Failed to init RX of SERDES PHY %d\n", 813 lane->id); 814 815 return ret; 816 } 817 818 static int 819 mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane *lane) 820 { 821 u32 mask, data, cfg, ref_clk; 822 int ret; 823 824 /* Set phy seclector */ 825 ret = mvebu_a3700_comphy_set_phy_selector(lane); 826 if (ret) 827 return ret; 828 829 /* 830 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The 831 * register belong to UTMI module, so it is set in UTMI phy driver. 832 */ 833 834 /* 835 * 1. Set PRD_TXDEEMPH (3.5db de-emph) 836 */ 837 data = PRD_TXDEEMPH0_MASK; 838 mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK | 839 CFG_TX_ALIGN_POS_MASK; 840 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask); 841 842 /* 843 * 2. Set BIT0: enable transmitter in high impedance mode 844 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency 845 * Set BIT6: Tx detect Rx at HiZ mode 846 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db 847 * together with bit 0 of COMPHY_PIPE_LANE_CFG0 register 848 */ 849 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN; 850 mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK | 851 TX_ELEC_IDLE_MODE_EN; 852 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask); 853 854 /* 855 * 3. Set Spread Spectrum Clock Enabled 856 */ 857 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG4, 858 SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN); 859 860 /* 861 * 4. Set Override Margining Controls From the MAC: 862 * Use margining signals from lane configuration 863 */ 864 comphy_lane_reg_set(lane, COMPHY_PIPE_TEST_MODE_CTRL, 865 MODE_MARGIN_OVERRIDE, 0xFFFF); 866 867 /* 868 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles 869 * set Mode Clock Source = PCLK is generated from REFCLK 870 */ 871 data = 0x0; 872 mask = MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE_MASK | 873 BUNDLE_SAMPLE_CTRL | PLL_READY_DLY_MASK; 874 comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask); 875 876 /* 877 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K 878 */ 879 comphy_lane_reg_set(lane, COMPHY_GEN2_SET2, 880 GS2_TX_SSC_AMP_4128, GS2_TX_SSC_AMP_MASK); 881 882 /* 883 * 7. Unset G3 Spread Spectrum Clock Amplitude 884 * set G3 TX and RX Register Master Current Select 885 */ 886 data = GS2_VREG_RXTX_MAS_ISET_60U; 887 mask = GS2_TX_SSC_AMP_MASK | GS2_VREG_RXTX_MAS_ISET_MASK | 888 GS2_RSVD_6_0_MASK; 889 comphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask); 890 891 /* 892 * 8. Check crystal jumper setting and program the Power and PLL Control 893 * accordingly Change RX wait 894 */ 895 if (lane->priv->xtal_is_40m) { 896 ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; 897 cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT; 898 } else { 899 ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; 900 cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT; 901 } 902 903 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 904 PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_USB3 | ref_clk; 905 mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 906 PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | COMPHY_MODE_MASK | 907 REF_FREF_SEL_MASK; 908 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 909 910 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg; 911 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 912 CFG_PM_RXDLOZ_WAIT_MASK; 913 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask); 914 915 /* 916 * 9. Enable idle sync 917 */ 918 comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN, 919 IDLE_SYNC_EN, IDLE_SYNC_EN); 920 921 /* 922 * 10. Enable the output of 500M clock 923 */ 924 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, CLK500M_EN, CLK500M_EN); 925 926 /* 927 * 11. Set 20-bit data width 928 */ 929 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, 930 DATA_WIDTH_20BIT, 0xFFFF); 931 932 /* 933 * 12. Override Speed_PLL value and use MAC PLL 934 */ 935 data = SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT; 936 mask = 0xFFFF; 937 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask); 938 939 /* 940 * 13. Check the Polarity invert bit 941 */ 942 data = 0x0; 943 if (lane->invert_tx) 944 data |= TXD_INVERT_BIT; 945 if (lane->invert_rx) 946 data |= RXD_INVERT_BIT; 947 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 948 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); 949 950 /* 951 * 14. Set max speed generation to USB3.0 5Gbps 952 */ 953 comphy_lane_reg_set(lane, COMPHY_SYNC_MASK_GEN, 954 PHY_GEN_MAX_USB3_5G, PHY_GEN_MAX_MASK); 955 956 /* 957 * 15. Set capacitor value for FFE gain peaking to 0xF 958 */ 959 comphy_lane_reg_set(lane, COMPHY_GEN2_SET3, 960 GS3_FFE_CAP_SEL_VALUE, GS3_FFE_CAP_SEL_MASK); 961 962 /* 963 * 16. Release SW reset 964 */ 965 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; 966 mask = 0xFFFF; 967 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); 968 969 /* Wait for > 55 us to allow PCLK be enabled */ 970 udelay(PLL_SET_DELAY_US); 971 972 ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, 973 COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 974 if (ret) 975 dev_err(lane->dev, "Failed to lock USB3 PLL\n"); 976 977 return ret; 978 } 979 980 static int 981 mvebu_a3700_comphy_pcie_power_on(struct mvebu_a3700_comphy_lane *lane) 982 { 983 u32 mask, data, ref_clk; 984 int ret; 985 986 /* Configure phy selector for PCIe */ 987 ret = mvebu_a3700_comphy_set_phy_selector(lane); 988 if (ret) 989 return ret; 990 991 /* 1. Enable max PLL. */ 992 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, 993 USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN); 994 995 /* 2. Select 20 bit SERDES interface. */ 996 comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, 997 CFG_SEL_20B, CFG_SEL_20B); 998 999 /* 3. Force to use reg setting for PCIe mode */ 1000 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL1, 1001 SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE); 1002 1003 /* 4. Change RX wait */ 1004 data = CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT; 1005 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 1006 CFG_PM_RXDLOZ_WAIT_MASK; 1007 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask); 1008 1009 /* 5. Enable idle sync */ 1010 comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN, 1011 IDLE_SYNC_EN, IDLE_SYNC_EN); 1012 1013 /* 6. Enable the output of 100M/125M/500M clock */ 1014 data = CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN; 1015 mask = data; 1016 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask); 1017 1018 /* 1019 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in 1020 * PCI-E driver 1021 */ 1022 1023 /* 1024 * 8. Check crystal jumper setting and program the Power and PLL 1025 * Control accordingly 1026 */ 1027 1028 if (lane->priv->xtal_is_40m) 1029 ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; 1030 else 1031 ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; 1032 1033 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 1034 PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_PCIE | ref_clk; 1035 mask = 0xFFFF; 1036 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 1037 1038 /* 9. Override Speed_PLL value and use MAC PLL */ 1039 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, 1040 SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, 1041 0xFFFF); 1042 1043 /* 10. Check the Polarity invert bit */ 1044 data = 0x0; 1045 if (lane->invert_tx) 1046 data |= TXD_INVERT_BIT; 1047 if (lane->invert_rx) 1048 data |= RXD_INVERT_BIT; 1049 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 1050 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); 1051 1052 /* 11. Release SW reset */ 1053 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32; 1054 mask = data | PIPE_SOFT_RESET | MODE_REFDIV_MASK; 1055 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); 1056 1057 /* Wait for > 55 us to allow PCLK be enabled */ 1058 udelay(PLL_SET_DELAY_US); 1059 1060 ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, 1061 COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 1062 if (ret) 1063 dev_err(lane->dev, "Failed to lock PCIE PLL\n"); 1064 1065 return ret; 1066 } 1067 1068 static void 1069 mvebu_a3700_comphy_sata_power_off(struct mvebu_a3700_comphy_lane *lane) 1070 { 1071 /* Set phy isolation mode */ 1072 comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL, 1073 PHY_ISOLATE_MODE, PHY_ISOLATE_MODE); 1074 1075 /* Power off PLL, Tx, Rx */ 1076 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, 1077 0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); 1078 } 1079 1080 static void 1081 mvebu_a3700_comphy_ethernet_power_off(struct mvebu_a3700_comphy_lane *lane) 1082 { 1083 u32 mask, data; 1084 1085 data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT | PIN_PU_IVREF_BIT | 1086 PHY_RX_INIT_BIT; 1087 mask = data; 1088 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 1089 } 1090 1091 static void 1092 mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane *lane) 1093 { 1094 /* Power off PLL, Tx, Rx */ 1095 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, 1096 0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); 1097 } 1098 1099 static void mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane) 1100 { 1101 /* 1102 * The USB3 MAC sets the USB3 PHY to low state, so we do not 1103 * need to power off USB3 PHY again. 1104 */ 1105 } 1106 1107 static bool mvebu_a3700_comphy_check_mode(int lane, 1108 enum phy_mode mode, 1109 int submode) 1110 { 1111 int i, n = ARRAY_SIZE(mvebu_a3700_comphy_modes); 1112 1113 /* Unused PHY mux value is 0x0 */ 1114 if (mode == PHY_MODE_INVALID) 1115 return false; 1116 1117 for (i = 0; i < n; i++) { 1118 if (mvebu_a3700_comphy_modes[i].lane == lane && 1119 mvebu_a3700_comphy_modes[i].mode == mode && 1120 mvebu_a3700_comphy_modes[i].submode == submode) 1121 break; 1122 } 1123 1124 if (i == n) 1125 return false; 1126 1127 return true; 1128 } 1129 1130 static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode, 1131 int submode) 1132 { 1133 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); 1134 1135 if (!mvebu_a3700_comphy_check_mode(lane->id, mode, submode)) { 1136 dev_err(lane->dev, "invalid COMPHY mode\n"); 1137 return -EINVAL; 1138 } 1139 1140 /* Mode cannot be changed while the PHY is powered on */ 1141 if (phy->power_count && 1142 (lane->mode != mode || lane->submode != submode)) 1143 return -EBUSY; 1144 1145 /* Just remember the mode, ->power_on() will do the real setup */ 1146 lane->mode = mode; 1147 lane->submode = submode; 1148 1149 return 0; 1150 } 1151 1152 static int mvebu_a3700_comphy_power_on(struct phy *phy) 1153 { 1154 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); 1155 1156 if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode, 1157 lane->submode)) { 1158 dev_err(lane->dev, "invalid COMPHY mode\n"); 1159 return -EINVAL; 1160 } 1161 1162 switch (lane->mode) { 1163 case PHY_MODE_USB_HOST_SS: 1164 dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id); 1165 return mvebu_a3700_comphy_usb3_power_on(lane); 1166 case PHY_MODE_SATA: 1167 dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id); 1168 return mvebu_a3700_comphy_sata_power_on(lane); 1169 case PHY_MODE_ETHERNET: 1170 dev_dbg(lane->dev, "set lane %d to Ethernet mode\n", lane->id); 1171 return mvebu_a3700_comphy_ethernet_power_on(lane); 1172 case PHY_MODE_PCIE: 1173 dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id); 1174 return mvebu_a3700_comphy_pcie_power_on(lane); 1175 default: 1176 dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode); 1177 return -EOPNOTSUPP; 1178 } 1179 } 1180 1181 static int mvebu_a3700_comphy_power_off(struct phy *phy) 1182 { 1183 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); 1184 1185 switch (lane->id) { 1186 case 0: 1187 mvebu_a3700_comphy_usb3_power_off(lane); 1188 mvebu_a3700_comphy_ethernet_power_off(lane); 1189 return 0; 1190 case 1: 1191 mvebu_a3700_comphy_pcie_power_off(lane); 1192 mvebu_a3700_comphy_ethernet_power_off(lane); 1193 return 0; 1194 case 2: 1195 mvebu_a3700_comphy_usb3_power_off(lane); 1196 mvebu_a3700_comphy_sata_power_off(lane); 1197 return 0; 1198 default: 1199 dev_err(lane->dev, "invalid COMPHY mode\n"); 1200 return -EINVAL; 1201 } 1202 } 1203 1204 static const struct phy_ops mvebu_a3700_comphy_ops = { 1205 .power_on = mvebu_a3700_comphy_power_on, 1206 .power_off = mvebu_a3700_comphy_power_off, 1207 .set_mode = mvebu_a3700_comphy_set_mode, 1208 .owner = THIS_MODULE, 1209 }; 1210 1211 static struct phy *mvebu_a3700_comphy_xlate(struct device *dev, 1212 struct of_phandle_args *args) 1213 { 1214 struct mvebu_a3700_comphy_lane *lane; 1215 unsigned int port; 1216 struct phy *phy; 1217 1218 phy = of_phy_simple_xlate(dev, args); 1219 if (IS_ERR(phy)) 1220 return phy; 1221 1222 lane = phy_get_drvdata(phy); 1223 1224 port = args->args[0]; 1225 if (port != 0 && (port != 1 || lane->id != 0)) { 1226 dev_err(lane->dev, "invalid port number %u\n", port); 1227 return ERR_PTR(-EINVAL); 1228 } 1229 1230 lane->invert_tx = args->args[1] & BIT(0); 1231 lane->invert_rx = args->args[1] & BIT(1); 1232 1233 return phy; 1234 } 1235 1236 static int mvebu_a3700_comphy_probe(struct platform_device *pdev) 1237 { 1238 struct mvebu_a3700_comphy_priv *priv; 1239 struct phy_provider *provider; 1240 struct device_node *child; 1241 struct resource *res; 1242 struct clk *clk; 1243 int ret; 1244 1245 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1246 if (!priv) 1247 return -ENOMEM; 1248 1249 spin_lock_init(&priv->lock); 1250 1251 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "comphy"); 1252 priv->comphy_regs = devm_ioremap_resource(&pdev->dev, res); 1253 if (IS_ERR(priv->comphy_regs)) 1254 return PTR_ERR(priv->comphy_regs); 1255 1256 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1257 "lane1_pcie_gbe"); 1258 priv->lane1_phy_regs = devm_ioremap_resource(&pdev->dev, res); 1259 if (IS_ERR(priv->lane1_phy_regs)) 1260 return PTR_ERR(priv->lane1_phy_regs); 1261 1262 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1263 "lane0_usb3_gbe"); 1264 priv->lane0_phy_regs = devm_ioremap_resource(&pdev->dev, res); 1265 if (IS_ERR(priv->lane0_phy_regs)) 1266 return PTR_ERR(priv->lane0_phy_regs); 1267 1268 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1269 "lane2_sata_usb3"); 1270 priv->lane2_phy_indirect = devm_ioremap_resource(&pdev->dev, res); 1271 if (IS_ERR(priv->lane2_phy_indirect)) 1272 return PTR_ERR(priv->lane2_phy_indirect); 1273 1274 /* 1275 * Driver needs to know if reference xtal clock is 40MHz or 25MHz. 1276 * Old DT bindings do not have xtal clk present. So do not fail here 1277 * and expects that default 25MHz reference clock is used. 1278 */ 1279 clk = clk_get(&pdev->dev, "xtal"); 1280 if (IS_ERR(clk)) { 1281 if (PTR_ERR(clk) == -EPROBE_DEFER) 1282 return -EPROBE_DEFER; 1283 dev_warn(&pdev->dev, "missing 'xtal' clk (%ld)\n", 1284 PTR_ERR(clk)); 1285 } else { 1286 ret = clk_prepare_enable(clk); 1287 if (ret) { 1288 dev_warn(&pdev->dev, "enabling xtal clk failed (%d)\n", 1289 ret); 1290 } else { 1291 if (clk_get_rate(clk) == 40000000) 1292 priv->xtal_is_40m = true; 1293 clk_disable_unprepare(clk); 1294 } 1295 clk_put(clk); 1296 } 1297 1298 dev_set_drvdata(&pdev->dev, priv); 1299 1300 for_each_available_child_of_node(pdev->dev.of_node, child) { 1301 struct mvebu_a3700_comphy_lane *lane; 1302 struct phy *phy; 1303 int ret; 1304 u32 lane_id; 1305 1306 ret = of_property_read_u32(child, "reg", &lane_id); 1307 if (ret < 0) { 1308 dev_err(&pdev->dev, "missing 'reg' property (%d)\n", 1309 ret); 1310 continue; 1311 } 1312 1313 if (lane_id >= 3) { 1314 dev_err(&pdev->dev, "invalid 'reg' property\n"); 1315 continue; 1316 } 1317 1318 lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); 1319 if (!lane) { 1320 of_node_put(child); 1321 return -ENOMEM; 1322 } 1323 1324 phy = devm_phy_create(&pdev->dev, child, 1325 &mvebu_a3700_comphy_ops); 1326 if (IS_ERR(phy)) { 1327 of_node_put(child); 1328 return PTR_ERR(phy); 1329 } 1330 1331 lane->priv = priv; 1332 lane->dev = &pdev->dev; 1333 lane->mode = PHY_MODE_INVALID; 1334 lane->submode = PHY_INTERFACE_MODE_NA; 1335 lane->id = lane_id; 1336 lane->invert_tx = false; 1337 lane->invert_rx = false; 1338 phy_set_drvdata(phy, lane); 1339 1340 /* 1341 * To avoid relying on the bootloader/firmware configuration, 1342 * power off all comphys. 1343 */ 1344 mvebu_a3700_comphy_power_off(phy); 1345 } 1346 1347 provider = devm_of_phy_provider_register(&pdev->dev, 1348 mvebu_a3700_comphy_xlate); 1349 1350 return PTR_ERR_OR_ZERO(provider); 1351 } 1352 1353 static const struct of_device_id mvebu_a3700_comphy_of_match_table[] = { 1354 { .compatible = "marvell,comphy-a3700" }, 1355 { }, 1356 }; 1357 MODULE_DEVICE_TABLE(of, mvebu_a3700_comphy_of_match_table); 1358 1359 static struct platform_driver mvebu_a3700_comphy_driver = { 1360 .probe = mvebu_a3700_comphy_probe, 1361 .driver = { 1362 .name = "mvebu-a3700-comphy", 1363 .of_match_table = mvebu_a3700_comphy_of_match_table, 1364 }, 1365 }; 1366 module_platform_driver(mvebu_a3700_comphy_driver); 1367 1368 MODULE_AUTHOR("Miquèl Raynal <miquel.raynal@bootlin.com>"); 1369 MODULE_AUTHOR("Pali Rohár <pali@kernel.org>"); 1370 MODULE_AUTHOR("Marek Behún <kabel@kernel.org>"); 1371 MODULE_DESCRIPTION("Common PHY driver for A3700"); 1372 MODULE_LICENSE("GPL v2"); 1373