1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy.h> 24 25 #include "phy-qcom-qmp.h" 26 27 /* QPHY_SW_RESET bit */ 28 #define SW_RESET BIT(0) 29 /* QPHY_POWER_DOWN_CONTROL */ 30 #define SW_PWRDN BIT(0) 31 #define REFCLK_DRV_DSBL BIT(1) 32 /* QPHY_START_CONTROL bits */ 33 #define SERDES_START BIT(0) 34 #define PCS_START BIT(1) 35 #define PLL_READY_GATE_EN BIT(3) 36 /* QPHY_PCS_STATUS bit */ 37 #define PHYSTATUS BIT(6) 38 #define PHYSTATUS_4_20 BIT(7) 39 /* QPHY_COM_PCS_READY_STATUS bit */ 40 #define PCS_READY BIT(0) 41 42 #define PHY_INIT_COMPLETE_TIMEOUT 10000 43 #define POWER_DOWN_DELAY_US_MIN 10 44 #define POWER_DOWN_DELAY_US_MAX 11 45 46 struct qmp_phy_init_tbl { 47 unsigned int offset; 48 unsigned int val; 49 /* 50 * register part of layout ? 51 * if yes, then offset gives index in the reg-layout 52 */ 53 bool in_layout; 54 /* 55 * mask of lanes for which this register is written 56 * for cases when second lane needs different values 57 */ 58 u8 lane_mask; 59 }; 60 61 #define QMP_PHY_INIT_CFG(o, v) \ 62 { \ 63 .offset = o, \ 64 .val = v, \ 65 .lane_mask = 0xff, \ 66 } 67 68 #define QMP_PHY_INIT_CFG_L(o, v) \ 69 { \ 70 .offset = o, \ 71 .val = v, \ 72 .in_layout = true, \ 73 .lane_mask = 0xff, \ 74 } 75 76 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 77 { \ 78 .offset = o, \ 79 .val = v, \ 80 .lane_mask = l, \ 81 } 82 83 /* set of registers with offsets different per-PHY */ 84 enum qphy_reg_layout { 85 /* Common block control registers */ 86 QPHY_COM_SW_RESET, 87 QPHY_COM_POWER_DOWN_CONTROL, 88 QPHY_COM_START_CONTROL, 89 QPHY_COM_PCS_READY_STATUS, 90 /* PCS registers */ 91 QPHY_SW_RESET, 92 QPHY_START_CTRL, 93 QPHY_PCS_STATUS, 94 QPHY_PCS_POWER_DOWN_CONTROL, 95 /* Keep last to ensure regs_layout arrays are properly initialized */ 96 QPHY_LAYOUT_SIZE 97 }; 98 99 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 100 [QPHY_COM_SW_RESET] = 0x400, 101 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, 102 [QPHY_COM_START_CONTROL] = 0x408, 103 [QPHY_COM_PCS_READY_STATUS] = 0x448, 104 [QPHY_SW_RESET] = 0x00, 105 [QPHY_START_CTRL] = 0x08, 106 [QPHY_PCS_STATUS] = 0x174, 107 }; 108 109 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { 110 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 111 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 112 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 113 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 114 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), 115 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 116 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 117 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 118 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), 119 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 120 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 121 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 122 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), 123 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 124 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 125 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 126 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 127 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 128 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), 129 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), 130 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 131 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), 132 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 133 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), 134 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 135 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 136 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 137 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 138 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 139 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 140 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 141 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 142 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), 143 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 144 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 145 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 146 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), 147 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 148 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 149 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 150 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 151 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 152 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), 153 }; 154 155 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { 156 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 157 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 158 }; 159 160 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { 161 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 162 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), 163 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), 164 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 165 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), 166 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 167 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), 168 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 169 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 170 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), 171 }; 172 173 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { 174 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL, 0x4c), 175 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), 176 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 177 178 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x05), 179 180 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05), 181 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02), 182 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG4, 0x00), 183 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG1, 0xa3), 184 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 185 }; 186 187 /* struct qmp_phy_cfg - per-PHY initialization config */ 188 struct qmp_phy_cfg { 189 /* number of PHYs provided by this block */ 190 int num_phys; 191 192 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 193 const struct qmp_phy_init_tbl *serdes_tbl; 194 int serdes_tbl_num; 195 const struct qmp_phy_init_tbl *tx_tbl; 196 int tx_tbl_num; 197 const struct qmp_phy_init_tbl *rx_tbl; 198 int rx_tbl_num; 199 const struct qmp_phy_init_tbl *pcs_tbl; 200 int pcs_tbl_num; 201 202 /* clock ids to be requested */ 203 const char * const *clk_list; 204 int num_clks; 205 /* resets to be requested */ 206 const char * const *reset_list; 207 int num_resets; 208 /* regulators to be requested */ 209 const char * const *vreg_list; 210 int num_vregs; 211 212 /* array of registers with different offsets */ 213 const unsigned int *regs; 214 215 unsigned int start_ctrl; 216 unsigned int pwrdn_ctrl; 217 unsigned int mask_com_pcs_ready; 218 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 219 unsigned int phy_status; 220 221 /* true, if PHY needs delay after POWER_DOWN */ 222 bool has_pwrdn_delay; 223 /* power_down delay in usec */ 224 int pwrdn_delay_min; 225 int pwrdn_delay_max; 226 }; 227 228 /** 229 * struct qmp_phy - per-lane phy descriptor 230 * 231 * @phy: generic phy 232 * @cfg: phy specific configuration 233 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 234 * @tx: iomapped memory space for lane's tx 235 * @rx: iomapped memory space for lane's rx 236 * @pcs: iomapped memory space for lane's pcs 237 * @pipe_clk: pipe clock 238 * @index: lane index 239 * @qmp: QMP phy to which this lane belongs 240 * @lane_rst: lane's reset controller 241 */ 242 struct qmp_phy { 243 struct phy *phy; 244 const struct qmp_phy_cfg *cfg; 245 void __iomem *serdes; 246 void __iomem *tx; 247 void __iomem *rx; 248 void __iomem *pcs; 249 struct clk *pipe_clk; 250 unsigned int index; 251 struct qcom_qmp *qmp; 252 struct reset_control *lane_rst; 253 }; 254 255 /** 256 * struct qcom_qmp - structure holding QMP phy block attributes 257 * 258 * @dev: device 259 * 260 * @clks: array of clocks required by phy 261 * @resets: array of resets required by phy 262 * @vregs: regulator supplies bulk data 263 * 264 * @phys: array of per-lane phy descriptors 265 * @phy_mutex: mutex lock for PHY common block initialization 266 * @init_count: phy common block initialization count 267 */ 268 struct qcom_qmp { 269 struct device *dev; 270 271 struct clk_bulk_data *clks; 272 struct reset_control_bulk_data *resets; 273 struct regulator_bulk_data *vregs; 274 275 struct qmp_phy **phys; 276 277 struct mutex phy_mutex; 278 int init_count; 279 }; 280 281 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 282 { 283 u32 reg; 284 285 reg = readl(base + offset); 286 reg |= val; 287 writel(reg, base + offset); 288 289 /* ensure that above write is through */ 290 readl(base + offset); 291 } 292 293 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 294 { 295 u32 reg; 296 297 reg = readl(base + offset); 298 reg &= ~val; 299 writel(reg, base + offset); 300 301 /* ensure that above write is through */ 302 readl(base + offset); 303 } 304 305 /* list of clocks required by phy */ 306 static const char * const msm8996_phy_clk_l[] = { 307 "aux", "cfg_ahb", "ref", 308 }; 309 310 /* list of resets */ 311 static const char * const msm8996_pciephy_reset_l[] = { 312 "phy", "common", "cfg", 313 }; 314 315 /* list of regulators */ 316 static const char * const qmp_phy_vreg_l[] = { 317 "vdda-phy", "vdda-pll", 318 }; 319 320 static const struct qmp_phy_cfg msm8996_pciephy_cfg = { 321 .num_phys = 3, 322 323 .serdes_tbl = msm8996_pcie_serdes_tbl, 324 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), 325 .tx_tbl = msm8996_pcie_tx_tbl, 326 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), 327 .rx_tbl = msm8996_pcie_rx_tbl, 328 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), 329 .pcs_tbl = msm8996_pcie_pcs_tbl, 330 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), 331 .clk_list = msm8996_phy_clk_l, 332 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 333 .reset_list = msm8996_pciephy_reset_l, 334 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), 335 .vreg_list = qmp_phy_vreg_l, 336 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 337 .regs = pciephy_regs_layout, 338 339 .start_ctrl = PCS_START | PLL_READY_GATE_EN, 340 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 341 .mask_com_pcs_ready = PCS_READY, 342 .phy_status = PHYSTATUS, 343 344 .has_pwrdn_delay = true, 345 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 346 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 347 }; 348 349 static void qmp_pcie_msm8996_configure_lane(void __iomem *base, 350 const unsigned int *regs, 351 const struct qmp_phy_init_tbl tbl[], 352 int num, 353 u8 lane_mask) 354 { 355 int i; 356 const struct qmp_phy_init_tbl *t = tbl; 357 358 if (!t) 359 return; 360 361 for (i = 0; i < num; i++, t++) { 362 if (!(t->lane_mask & lane_mask)) 363 continue; 364 365 if (t->in_layout) 366 writel(t->val, base + regs[t->offset]); 367 else 368 writel(t->val, base + t->offset); 369 } 370 } 371 372 static void qmp_pcie_msm8996_configure(void __iomem *base, 373 const unsigned int *regs, 374 const struct qmp_phy_init_tbl tbl[], 375 int num) 376 { 377 qmp_pcie_msm8996_configure_lane(base, regs, tbl, num, 0xff); 378 } 379 380 static int qmp_pcie_msm8996_serdes_init(struct qmp_phy *qphy) 381 { 382 struct qcom_qmp *qmp = qphy->qmp; 383 const struct qmp_phy_cfg *cfg = qphy->cfg; 384 void __iomem *serdes = qphy->serdes; 385 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 386 int serdes_tbl_num = cfg->serdes_tbl_num; 387 void __iomem *status; 388 unsigned int mask, val; 389 int ret; 390 391 qmp_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 392 393 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); 394 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 395 SERDES_START | PCS_START); 396 397 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; 398 mask = cfg->mask_com_pcs_ready; 399 400 ret = readl_poll_timeout(status, val, (val & mask), 10, 401 PHY_INIT_COMPLETE_TIMEOUT); 402 if (ret) { 403 dev_err(qmp->dev, 404 "phy common block init timed-out\n"); 405 return ret; 406 } 407 408 return 0; 409 } 410 411 static int qmp_pcie_msm8996_com_init(struct qmp_phy *qphy) 412 { 413 struct qcom_qmp *qmp = qphy->qmp; 414 const struct qmp_phy_cfg *cfg = qphy->cfg; 415 void __iomem *serdes = qphy->serdes; 416 int ret; 417 418 mutex_lock(&qmp->phy_mutex); 419 if (qmp->init_count++) { 420 mutex_unlock(&qmp->phy_mutex); 421 return 0; 422 } 423 424 /* turn on regulator supplies */ 425 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 426 if (ret) { 427 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 428 goto err_unlock; 429 } 430 431 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 432 if (ret) { 433 dev_err(qmp->dev, "reset assert failed\n"); 434 goto err_disable_regulators; 435 } 436 437 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 438 if (ret) { 439 dev_err(qmp->dev, "reset deassert failed\n"); 440 goto err_disable_regulators; 441 } 442 443 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 444 if (ret) 445 goto err_assert_reset; 446 447 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 448 SW_PWRDN); 449 450 mutex_unlock(&qmp->phy_mutex); 451 452 return 0; 453 454 err_assert_reset: 455 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 456 err_disable_regulators: 457 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 458 err_unlock: 459 mutex_unlock(&qmp->phy_mutex); 460 461 return ret; 462 } 463 464 static int qmp_pcie_msm8996_com_exit(struct qmp_phy *qphy) 465 { 466 struct qcom_qmp *qmp = qphy->qmp; 467 const struct qmp_phy_cfg *cfg = qphy->cfg; 468 void __iomem *serdes = qphy->serdes; 469 470 mutex_lock(&qmp->phy_mutex); 471 if (--qmp->init_count) { 472 mutex_unlock(&qmp->phy_mutex); 473 return 0; 474 } 475 476 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 477 SERDES_START | PCS_START); 478 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], 479 SW_RESET); 480 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 481 SW_PWRDN); 482 483 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 484 485 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 486 487 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 488 489 mutex_unlock(&qmp->phy_mutex); 490 491 return 0; 492 } 493 494 static int qmp_pcie_msm8996_init(struct phy *phy) 495 { 496 struct qmp_phy *qphy = phy_get_drvdata(phy); 497 struct qcom_qmp *qmp = qphy->qmp; 498 int ret; 499 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 500 501 ret = qmp_pcie_msm8996_com_init(qphy); 502 if (ret) 503 return ret; 504 505 return 0; 506 } 507 508 static int qmp_pcie_msm8996_power_on(struct phy *phy) 509 { 510 struct qmp_phy *qphy = phy_get_drvdata(phy); 511 struct qcom_qmp *qmp = qphy->qmp; 512 const struct qmp_phy_cfg *cfg = qphy->cfg; 513 void __iomem *tx = qphy->tx; 514 void __iomem *rx = qphy->rx; 515 void __iomem *pcs = qphy->pcs; 516 void __iomem *status; 517 unsigned int mask, val, ready; 518 int ret; 519 520 qmp_pcie_msm8996_serdes_init(qphy); 521 522 ret = reset_control_deassert(qphy->lane_rst); 523 if (ret) { 524 dev_err(qmp->dev, "lane%d reset deassert failed\n", 525 qphy->index); 526 return ret; 527 } 528 529 ret = clk_prepare_enable(qphy->pipe_clk); 530 if (ret) { 531 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 532 goto err_reset_lane; 533 } 534 535 /* Tx, Rx, and PCS configurations */ 536 qmp_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl, 537 cfg->tx_tbl_num, 1); 538 539 qmp_pcie_msm8996_configure_lane(rx, cfg->regs, cfg->rx_tbl, 540 cfg->rx_tbl_num, 1); 541 542 qmp_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 543 544 /* 545 * Pull out PHY from POWER DOWN state. 546 * This is active low enable signal to power-down PHY. 547 */ 548 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 549 550 if (cfg->has_pwrdn_delay) 551 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 552 553 /* Pull PHY out of reset state */ 554 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 555 556 /* start SerDes and Phy-Coding-Sublayer */ 557 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 558 559 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 560 mask = cfg->phy_status; 561 ready = 0; 562 563 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 564 PHY_INIT_COMPLETE_TIMEOUT); 565 if (ret) { 566 dev_err(qmp->dev, "phy initialization timed-out\n"); 567 goto err_disable_pipe_clk; 568 } 569 570 return 0; 571 572 err_disable_pipe_clk: 573 clk_disable_unprepare(qphy->pipe_clk); 574 err_reset_lane: 575 reset_control_assert(qphy->lane_rst); 576 577 return ret; 578 } 579 580 static int qmp_pcie_msm8996_power_off(struct phy *phy) 581 { 582 struct qmp_phy *qphy = phy_get_drvdata(phy); 583 const struct qmp_phy_cfg *cfg = qphy->cfg; 584 585 clk_disable_unprepare(qphy->pipe_clk); 586 587 /* PHY reset */ 588 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 589 590 /* stop SerDes and Phy-Coding-Sublayer */ 591 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 592 593 /* Put PHY into POWER DOWN state: active low */ 594 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 595 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 596 cfg->pwrdn_ctrl); 597 } else { 598 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 599 cfg->pwrdn_ctrl); 600 } 601 602 return 0; 603 } 604 605 static int qmp_pcie_msm8996_exit(struct phy *phy) 606 { 607 struct qmp_phy *qphy = phy_get_drvdata(phy); 608 609 reset_control_assert(qphy->lane_rst); 610 611 qmp_pcie_msm8996_com_exit(qphy); 612 613 return 0; 614 } 615 616 static int qmp_pcie_msm8996_enable(struct phy *phy) 617 { 618 int ret; 619 620 ret = qmp_pcie_msm8996_init(phy); 621 if (ret) 622 return ret; 623 624 ret = qmp_pcie_msm8996_power_on(phy); 625 if (ret) 626 qmp_pcie_msm8996_exit(phy); 627 628 return ret; 629 } 630 631 static int qmp_pcie_msm8996_disable(struct phy *phy) 632 { 633 int ret; 634 635 ret = qmp_pcie_msm8996_power_off(phy); 636 if (ret) 637 return ret; 638 return qmp_pcie_msm8996_exit(phy); 639 } 640 641 static int qmp_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 642 { 643 struct qcom_qmp *qmp = dev_get_drvdata(dev); 644 int num = cfg->num_vregs; 645 int i; 646 647 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 648 if (!qmp->vregs) 649 return -ENOMEM; 650 651 for (i = 0; i < num; i++) 652 qmp->vregs[i].supply = cfg->vreg_list[i]; 653 654 return devm_regulator_bulk_get(dev, num, qmp->vregs); 655 } 656 657 static int qmp_pcie_msm8996_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 658 { 659 struct qcom_qmp *qmp = dev_get_drvdata(dev); 660 int i; 661 int ret; 662 663 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 664 sizeof(*qmp->resets), GFP_KERNEL); 665 if (!qmp->resets) 666 return -ENOMEM; 667 668 for (i = 0; i < cfg->num_resets; i++) 669 qmp->resets[i].id = cfg->reset_list[i]; 670 671 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 672 if (ret) 673 return dev_err_probe(dev, ret, "failed to get resets\n"); 674 675 return 0; 676 } 677 678 static int qmp_pcie_msm8996_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 679 { 680 struct qcom_qmp *qmp = dev_get_drvdata(dev); 681 int num = cfg->num_clks; 682 int i; 683 684 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 685 if (!qmp->clks) 686 return -ENOMEM; 687 688 for (i = 0; i < num; i++) 689 qmp->clks[i].id = cfg->clk_list[i]; 690 691 return devm_clk_bulk_get(dev, num, qmp->clks); 692 } 693 694 static void phy_clk_release_provider(void *res) 695 { 696 of_clk_del_provider(res); 697 } 698 699 /* 700 * Register a fixed rate pipe clock. 701 * 702 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 703 * controls it. The <s>_pipe_clk coming out of the GCC is requested 704 * by the PHY driver for its operations. 705 * We register the <s>_pipe_clksrc here. The gcc driver takes care 706 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 707 * Below picture shows this relationship. 708 * 709 * +---------------+ 710 * | PHY block |<<---------------------------------------+ 711 * | | | 712 * | +-------+ | +-----+ | 713 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 714 * clk | +-------+ | +-----+ 715 * +---------------+ 716 */ 717 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 718 { 719 struct clk_fixed_rate *fixed; 720 struct clk_init_data init = { }; 721 int ret; 722 723 ret = of_property_read_string(np, "clock-output-names", &init.name); 724 if (ret) { 725 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 726 return ret; 727 } 728 729 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 730 if (!fixed) 731 return -ENOMEM; 732 733 init.ops = &clk_fixed_rate_ops; 734 735 /* controllers using QMP phys use 125MHz pipe clock interface */ 736 fixed->fixed_rate = 125000000; 737 fixed->hw.init = &init; 738 739 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 740 if (ret) 741 return ret; 742 743 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 744 if (ret) 745 return ret; 746 747 /* 748 * Roll a devm action because the clock provider is the child node, but 749 * the child node is not actually a device. 750 */ 751 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 752 } 753 754 static const struct phy_ops qmp_pcie_msm8996_ops = { 755 .power_on = qmp_pcie_msm8996_enable, 756 .power_off = qmp_pcie_msm8996_disable, 757 .owner = THIS_MODULE, 758 }; 759 760 static void qcom_qmp_reset_control_put(void *data) 761 { 762 reset_control_put(data); 763 } 764 765 static int qmp_pcie_msm8996_create(struct device *dev, struct device_node *np, int id, 766 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 767 { 768 struct qcom_qmp *qmp = dev_get_drvdata(dev); 769 struct phy *generic_phy; 770 struct qmp_phy *qphy; 771 int ret; 772 773 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 774 if (!qphy) 775 return -ENOMEM; 776 777 qphy->cfg = cfg; 778 qphy->serdes = serdes; 779 /* 780 * Get memory resources for each phy lane: 781 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 782 */ 783 qphy->tx = devm_of_iomap(dev, np, 0, NULL); 784 if (IS_ERR(qphy->tx)) 785 return PTR_ERR(qphy->tx); 786 787 qphy->rx = devm_of_iomap(dev, np, 1, NULL); 788 if (IS_ERR(qphy->rx)) 789 return PTR_ERR(qphy->rx); 790 791 qphy->pcs = devm_of_iomap(dev, np, 2, NULL); 792 if (IS_ERR(qphy->pcs)) 793 return PTR_ERR(qphy->pcs); 794 795 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 796 if (IS_ERR(qphy->pipe_clk)) { 797 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 798 "failed to get lane%d pipe clock\n", id); 799 } 800 801 qphy->lane_rst = of_reset_control_get_exclusive_by_index(np, 0); 802 if (IS_ERR(qphy->lane_rst)) { 803 dev_err(dev, "failed to get lane%d reset\n", id); 804 return PTR_ERR(qphy->lane_rst); 805 } 806 ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, 807 qphy->lane_rst); 808 if (ret) 809 return ret; 810 811 generic_phy = devm_phy_create(dev, np, &qmp_pcie_msm8996_ops); 812 if (IS_ERR(generic_phy)) { 813 ret = PTR_ERR(generic_phy); 814 dev_err(dev, "failed to create qphy %d\n", ret); 815 return ret; 816 } 817 818 qphy->phy = generic_phy; 819 qphy->index = id; 820 qphy->qmp = qmp; 821 qmp->phys[id] = qphy; 822 phy_set_drvdata(generic_phy, qphy); 823 824 return 0; 825 } 826 827 static const struct of_device_id qmp_pcie_msm8996_of_match_table[] = { 828 { 829 .compatible = "qcom,msm8996-qmp-pcie-phy", 830 .data = &msm8996_pciephy_cfg, 831 }, 832 { }, 833 }; 834 MODULE_DEVICE_TABLE(of, qmp_pcie_msm8996_of_match_table); 835 836 static int qmp_pcie_msm8996_probe(struct platform_device *pdev) 837 { 838 struct qcom_qmp *qmp; 839 struct device *dev = &pdev->dev; 840 struct device_node *child; 841 struct phy_provider *phy_provider; 842 void __iomem *serdes; 843 const struct qmp_phy_cfg *cfg = NULL; 844 int num, id, expected_phys; 845 int ret; 846 847 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 848 if (!qmp) 849 return -ENOMEM; 850 851 qmp->dev = dev; 852 dev_set_drvdata(dev, qmp); 853 854 /* Get the specific init parameters of QMP phy */ 855 cfg = of_device_get_match_data(dev); 856 if (!cfg) 857 return -EINVAL; 858 859 /* per PHY serdes; usually located at base address */ 860 serdes = devm_platform_ioremap_resource(pdev, 0); 861 if (IS_ERR(serdes)) 862 return PTR_ERR(serdes); 863 864 expected_phys = cfg->num_phys; 865 866 mutex_init(&qmp->phy_mutex); 867 868 ret = qmp_pcie_msm8996_clk_init(dev, cfg); 869 if (ret) 870 return ret; 871 872 ret = qmp_pcie_msm8996_reset_init(dev, cfg); 873 if (ret) 874 return ret; 875 876 ret = qmp_pcie_msm8996_vreg_init(dev, cfg); 877 if (ret) 878 return dev_err_probe(dev, ret, 879 "failed to get regulator supplies\n"); 880 881 num = of_get_available_child_count(dev->of_node); 882 /* do we have a rogue child node ? */ 883 if (num > expected_phys) 884 return -EINVAL; 885 886 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 887 if (!qmp->phys) 888 return -ENOMEM; 889 890 id = 0; 891 for_each_available_child_of_node(dev->of_node, child) { 892 /* Create per-lane phy */ 893 ret = qmp_pcie_msm8996_create(dev, child, id, serdes, cfg); 894 if (ret) { 895 dev_err(dev, "failed to create lane%d phy, %d\n", 896 id, ret); 897 goto err_node_put; 898 } 899 900 /* 901 * Register the pipe clock provided by phy. 902 * See function description to see details of this pipe clock. 903 */ 904 ret = phy_pipe_clk_register(qmp, child); 905 if (ret) { 906 dev_err(qmp->dev, 907 "failed to register pipe clock source\n"); 908 goto err_node_put; 909 } 910 911 id++; 912 } 913 914 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 915 916 return PTR_ERR_OR_ZERO(phy_provider); 917 918 err_node_put: 919 of_node_put(child); 920 return ret; 921 } 922 923 static struct platform_driver qmp_pcie_msm8996_driver = { 924 .probe = qmp_pcie_msm8996_probe, 925 .driver = { 926 .name = "qcom-qmp-msm8996-pcie-phy", 927 .of_match_table = qmp_pcie_msm8996_of_match_table, 928 }, 929 }; 930 931 module_platform_driver(qmp_pcie_msm8996_driver); 932 933 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 934 MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver"); 935 MODULE_LICENSE("GPL v2"); 936