1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_ 7 #define QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_ 8 9 #define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX 0x30 10 #define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX 0x34 11 #define QSERDES_V6_N4_TX_LANE_MODE_1 0x78 12 #define QSERDES_V6_N4_TX_LANE_MODE_2 0x7c 13 #define QSERDES_V6_N4_TX_LANE_MODE_3 0x80 14 15 #define QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2 0x8 16 #define QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2 0x18 17 #define QSERDES_V6_N4_RX_UCDR_PI_CONTROLS 0x20 18 #define QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE 0x94 19 #define QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2 0x9c 20 #define QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET 0xa0 21 #define QSERDES_V6_N4_RX_DFE_3 0xb4 22 #define QSERDES_V6_N4_RX_VGA_CAL_CNTRL1 0xe0 23 #define QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL 0xe8 24 #define QSERDES_V6_N4_RX_GM_CAL 0x10c 25 #define QSERDES_V6_N4_RX_SIGDET_ENABLES 0x148 26 #define QSERDES_V6_N4_RX_SIGDET_CNTRL 0x14c 27 #define QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL 0x154 28 #define QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET 0x194 29 #define QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc 30 #define QSERDES_V6_N4_RX_UCDR_PI_CTRL1 0x23c 31 #define QSERDES_V6_N4_RX_UCDR_PI_CTRL2 0x240 32 #define QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2 0x27c 33 #define QSERDES_V6_N4_RX_DFE_DAC_ENABLE1 0x298 34 #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B0 0x2b8 35 #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B1 0x2bc 36 #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B2 0x2c0 37 #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B3 0x2c4 38 #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B4 0x2c8 39 #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B5 0x2cc 40 #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B6 0x2d0 41 #define QSERDES_V6_N4_RX_MODE_RATE2_B0 0x2d4 42 #define QSERDES_V6_N4_RX_MODE_RATE2_B1 0x2d8 43 #define QSERDES_V6_N4_RX_MODE_RATE2_B2 0x2dc 44 #define QSERDES_V6_N4_RX_MODE_RATE2_B3 0x2e0 45 #define QSERDES_V6_N4_RX_MODE_RATE2_B4 0x2e4 46 #define QSERDES_V6_N4_RX_MODE_RATE2_B5 0x2e8 47 #define QSERDES_V6_N4_RX_MODE_RATE2_B6 0x2ec 48 #define QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE 0x30c 49 #define QSERDES_V6_N4_RX_RX_BKUP_CTRL1 0x310 50 51 #endif 52