1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <ufs/unipro.h> 24 #include "phy-qcom-qmp.h" 25 #include "phy-qcom-qmp-pcs-ufs-v2.h" 26 #include "phy-qcom-qmp-pcs-ufs-v3.h" 27 #include "phy-qcom-qmp-pcs-ufs-v4.h" 28 #include "phy-qcom-qmp-pcs-ufs-v5.h" 29 #include "phy-qcom-qmp-pcs-ufs-v6.h" 30 31 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h" 32 33 /* QPHY_SW_RESET bit */ 34 #define SW_RESET BIT(0) 35 /* QPHY_POWER_DOWN_CONTROL */ 36 #define SW_PWRDN BIT(0) 37 /* QPHY_START_CONTROL bits */ 38 #define SERDES_START BIT(0) 39 #define PCS_START BIT(1) 40 /* QPHY_PCS_READY_STATUS bit */ 41 #define PCS_READY BIT(0) 42 43 #define PHY_INIT_COMPLETE_TIMEOUT 10000 44 45 struct qmp_phy_init_tbl { 46 unsigned int offset; 47 unsigned int val; 48 /* 49 * mask of lanes for which this register is written 50 * for cases when second lane needs different values 51 */ 52 u8 lane_mask; 53 }; 54 55 #define QMP_PHY_INIT_CFG(o, v) \ 56 { \ 57 .offset = o, \ 58 .val = v, \ 59 .lane_mask = 0xff, \ 60 } 61 62 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 63 { \ 64 .offset = o, \ 65 .val = v, \ 66 .lane_mask = l, \ 67 } 68 69 /* set of registers with offsets different per-PHY */ 70 enum qphy_reg_layout { 71 /* PCS registers */ 72 QPHY_SW_RESET, 73 QPHY_START_CTRL, 74 QPHY_PCS_READY_STATUS, 75 QPHY_PCS_POWER_DOWN_CONTROL, 76 /* Keep last to ensure regs_layout arrays are properly initialized */ 77 QPHY_LAYOUT_SIZE 78 }; 79 80 static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { 81 [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, 82 [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, 83 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, 84 }; 85 86 static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { 87 [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START, 88 [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS, 89 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL, 90 }; 91 92 static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { 93 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, 94 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, 95 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, 96 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, 97 }; 98 99 static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 100 [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START, 101 [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS, 102 [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET, 103 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL, 104 }; 105 106 static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { 107 [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START, 108 [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS, 109 [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET, 110 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL, 111 }; 112 113 static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = { 114 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), 115 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), 116 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 117 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 118 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 119 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 120 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), 121 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 122 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), 123 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), 124 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), 125 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 126 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 127 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 128 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 129 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), 130 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), 131 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), 132 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 133 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 134 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), 135 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), 136 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 137 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 138 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 139 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 140 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 141 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), 142 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), 143 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), 144 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), 145 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 146 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), 147 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), 148 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), 149 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), 150 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), 151 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), 152 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), 153 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), 154 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 155 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), 156 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), 157 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), 158 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), 159 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), 160 }; 161 162 static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = { 163 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 164 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), 165 }; 166 167 static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = { 168 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), 169 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), 170 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), 171 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), 172 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), 173 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), 174 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), 175 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), 176 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), 177 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), 178 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), 179 }; 180 181 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = { 182 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), 183 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 184 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 185 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), 186 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 187 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 188 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 189 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 190 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), 191 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), 192 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 193 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 194 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 195 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 196 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 197 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), 198 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), 199 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), 200 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 201 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 202 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), 203 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), 204 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 205 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 206 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 207 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 208 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 209 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), 210 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), 211 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), 212 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), 213 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 214 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), 215 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), 216 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), 217 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), 218 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), 219 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), 220 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), 221 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), 222 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 223 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), 224 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), 225 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), 226 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), 227 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), 228 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 229 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 230 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), 231 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), 232 }; 233 234 static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = { 235 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), 236 }; 237 238 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = { 239 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 240 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 241 }; 242 243 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = { 244 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), 245 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), 246 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), 247 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), 248 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), 249 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), 250 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), 251 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), 252 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), 253 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), 254 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), 255 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 256 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 257 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), 258 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), 259 }; 260 261 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = { 262 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15), 263 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 264 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 265 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 266 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), 267 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 268 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12), 269 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), 270 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ 271 }; 272 273 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = { 274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 279 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), 280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 285 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 286 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), 287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), 288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), 289 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), 290 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 291 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), 297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), 299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), 300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), 301 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), 302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), 303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), 304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), 307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), 308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), 309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), 310 }; 311 312 static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = { 313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), 314 }; 315 316 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = { 317 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 318 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), 319 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 320 }; 321 322 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = { 323 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), 324 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), 325 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 326 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 327 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 328 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), 329 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 330 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 331 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 332 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 333 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 334 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), 335 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 336 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), 337 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 338 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 339 }; 340 341 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = { 342 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), 343 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 344 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 345 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 346 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 347 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f), 348 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), 349 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 350 }; 351 352 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = { 353 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), 354 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), 355 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 356 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), 357 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 358 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 359 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), 360 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 361 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 362 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 363 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 364 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 365 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), 366 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), 367 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), 368 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 369 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), 370 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 371 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 372 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 373 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), 374 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), 375 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 376 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 377 }; 378 379 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = { 380 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), 381 }; 382 383 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = { 384 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 385 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 386 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 387 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 388 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), 389 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), 390 }; 391 392 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = { 393 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), 394 }; 395 396 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { 397 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 398 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 399 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 400 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 401 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 402 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 403 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 404 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 405 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), 406 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 407 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 408 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), 409 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 410 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 411 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), 412 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 413 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), 414 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 415 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 416 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), 417 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), 418 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), 419 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), 420 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), 421 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), 422 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), 423 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 424 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 425 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 426 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 427 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 428 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 429 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 430 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 431 }; 432 433 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = { 434 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 435 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 436 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 437 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 438 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 439 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 440 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 441 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 442 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 443 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 444 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 445 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), 446 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 447 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 450 }; 451 452 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { 453 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 454 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 455 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 456 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 457 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 458 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 459 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 460 }; 461 462 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = { 463 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), 464 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), 465 }; 466 467 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = { 468 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), 469 }; 470 471 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = { 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 478 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), 479 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 480 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 481 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 482 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 483 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 484 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 485 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 486 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 487 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 488 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), 489 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 490 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 491 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 492 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 493 }; 494 495 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { 496 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), 497 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), 498 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 499 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 500 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 501 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 502 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 503 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 504 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 505 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), 506 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), 507 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), 508 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 509 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), 510 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), 511 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 512 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), 513 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), 514 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), 515 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), 516 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), 517 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), 518 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 519 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 520 }; 521 522 static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = { 523 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), 524 }; 525 526 static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = { 527 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 528 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 529 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 530 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 531 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), 532 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 533 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), 534 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 535 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), 536 }; 537 538 static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = { 539 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), 540 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), 541 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 542 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), 543 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 544 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 545 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), 546 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 547 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), 548 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), 549 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), 550 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), 551 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 552 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 553 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 554 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 555 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 556 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 557 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), 558 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 559 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 560 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), 561 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), 562 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), 563 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), 564 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), 565 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), 566 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), 567 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), 568 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), 569 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), 570 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), 571 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), 572 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), 573 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), 574 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), 575 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 576 }; 577 578 static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = { 579 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 580 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 581 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 582 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 583 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 584 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 585 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), 586 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 587 }; 588 589 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = { 590 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), 591 }; 592 593 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = { 594 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), 595 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), 596 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 597 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 598 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 599 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), 600 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), 601 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 602 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), 603 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), 604 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 605 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), 606 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), 607 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), 608 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), 609 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), 610 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), 611 }; 612 613 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { 614 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), 615 }; 616 617 static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { 618 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 619 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 620 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 621 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 622 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 623 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 624 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 625 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 626 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 627 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), 628 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 629 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 630 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 631 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 632 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c), 633 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), 634 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 635 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 636 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99), 637 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 638 }; 639 640 static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { 641 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05), 642 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 643 }; 644 645 static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { 646 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c), 647 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f), 648 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), 649 650 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), 651 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), 652 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), 653 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), 654 655 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), 656 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), 657 658 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), 659 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), 660 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), 661 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), 662 }; 663 664 static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { 665 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), 666 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 667 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 668 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), 669 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 670 }; 671 672 struct qmp_ufs_offsets { 673 u16 serdes; 674 u16 pcs; 675 u16 tx; 676 u16 rx; 677 u16 tx2; 678 u16 rx2; 679 }; 680 681 struct qmp_phy_cfg_tbls { 682 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 683 const struct qmp_phy_init_tbl *serdes; 684 int serdes_num; 685 const struct qmp_phy_init_tbl *tx; 686 int tx_num; 687 const struct qmp_phy_init_tbl *rx; 688 int rx_num; 689 const struct qmp_phy_init_tbl *pcs; 690 int pcs_num; 691 }; 692 693 /* struct qmp_phy_cfg - per-PHY initialization config */ 694 struct qmp_phy_cfg { 695 int lanes; 696 697 const struct qmp_ufs_offsets *offsets; 698 699 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 700 const struct qmp_phy_cfg_tbls tbls; 701 /* Additional sequence for HS Series B */ 702 const struct qmp_phy_cfg_tbls tbls_hs_b; 703 /* Additional sequence for HS G4 */ 704 const struct qmp_phy_cfg_tbls tbls_hs_g4; 705 706 /* clock ids to be requested */ 707 const char * const *clk_list; 708 int num_clks; 709 /* regulators to be requested */ 710 const char * const *vreg_list; 711 int num_vregs; 712 713 /* array of registers with different offsets */ 714 const unsigned int *regs; 715 716 /* true, if PCS block has no separate SW_RESET register */ 717 bool no_pcs_sw_reset; 718 }; 719 720 struct qmp_ufs { 721 struct device *dev; 722 723 const struct qmp_phy_cfg *cfg; 724 725 void __iomem *serdes; 726 void __iomem *pcs; 727 void __iomem *pcs_misc; 728 void __iomem *tx; 729 void __iomem *rx; 730 void __iomem *tx2; 731 void __iomem *rx2; 732 733 struct clk_bulk_data *clks; 734 struct regulator_bulk_data *vregs; 735 struct reset_control *ufs_reset; 736 737 struct phy *phy; 738 u32 mode; 739 u32 submode; 740 }; 741 742 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 743 { 744 u32 reg; 745 746 reg = readl(base + offset); 747 reg |= val; 748 writel(reg, base + offset); 749 750 /* ensure that above write is through */ 751 readl(base + offset); 752 } 753 754 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 755 { 756 u32 reg; 757 758 reg = readl(base + offset); 759 reg &= ~val; 760 writel(reg, base + offset); 761 762 /* ensure that above write is through */ 763 readl(base + offset); 764 } 765 766 /* list of clocks required by phy */ 767 static const char * const msm8996_ufs_phy_clk_l[] = { 768 "ref", 769 }; 770 771 /* the primary usb3 phy on sm8250 doesn't have a ref clock */ 772 static const char * const sm8450_ufs_phy_clk_l[] = { 773 "qref", "ref", "ref_aux", 774 }; 775 776 static const char * const sdm845_ufs_phy_clk_l[] = { 777 "ref", "ref_aux", 778 }; 779 780 /* list of regulators */ 781 static const char * const qmp_phy_vreg_l[] = { 782 "vdda-phy", "vdda-pll", 783 }; 784 785 static const struct qmp_ufs_offsets qmp_ufs_offsets = { 786 .serdes = 0, 787 .pcs = 0xc00, 788 .tx = 0x400, 789 .rx = 0x600, 790 .tx2 = 0x800, 791 .rx2 = 0xa00, 792 }; 793 794 static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = { 795 .serdes = 0, 796 .pcs = 0x0400, 797 .tx = 0x1000, 798 .rx = 0x1200, 799 .tx2 = 0x1800, 800 .rx2 = 0x1a00, 801 }; 802 803 static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { 804 .lanes = 1, 805 806 .tbls = { 807 .serdes = msm8996_ufsphy_serdes, 808 .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes), 809 .tx = msm8996_ufsphy_tx, 810 .tx_num = ARRAY_SIZE(msm8996_ufsphy_tx), 811 .rx = msm8996_ufsphy_rx, 812 .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx), 813 }, 814 815 .clk_list = msm8996_ufs_phy_clk_l, 816 .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), 817 818 .vreg_list = qmp_phy_vreg_l, 819 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 820 821 .regs = ufsphy_v2_regs_layout, 822 823 .no_pcs_sw_reset = true, 824 }; 825 826 static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { 827 .lanes = 2, 828 829 .offsets = &qmp_ufs_offsets, 830 831 .tbls = { 832 .serdes = sm8350_ufsphy_serdes, 833 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 834 .tx = sm8350_ufsphy_tx, 835 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 836 .rx = sm8350_ufsphy_rx, 837 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 838 .pcs = sm8350_ufsphy_pcs, 839 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 840 }, 841 .tbls_hs_b = { 842 .serdes = sm8350_ufsphy_hs_b_serdes, 843 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 844 }, 845 .tbls_hs_g4 = { 846 .tx = sm8350_ufsphy_g4_tx, 847 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 848 .rx = sm8350_ufsphy_g4_rx, 849 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 850 .pcs = sm8350_ufsphy_g4_pcs, 851 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 852 }, 853 .clk_list = sdm845_ufs_phy_clk_l, 854 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 855 .vreg_list = qmp_phy_vreg_l, 856 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 857 .regs = ufsphy_v5_regs_layout, 858 }; 859 860 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { 861 .lanes = 2, 862 863 .tbls = { 864 .serdes = sdm845_ufsphy_serdes, 865 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes), 866 .tx = sdm845_ufsphy_tx, 867 .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx), 868 .rx = sdm845_ufsphy_rx, 869 .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx), 870 .pcs = sdm845_ufsphy_pcs, 871 .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs), 872 }, 873 .tbls_hs_b = { 874 .serdes = sdm845_ufsphy_hs_b_serdes, 875 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), 876 }, 877 .clk_list = sdm845_ufs_phy_clk_l, 878 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 879 .vreg_list = qmp_phy_vreg_l, 880 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 881 .regs = ufsphy_v3_regs_layout, 882 883 .no_pcs_sw_reset = true, 884 }; 885 886 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { 887 .lanes = 1, 888 889 .offsets = &qmp_ufs_offsets, 890 891 .tbls = { 892 .serdes = sm6115_ufsphy_serdes, 893 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes), 894 .tx = sm6115_ufsphy_tx, 895 .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx), 896 .rx = sm6115_ufsphy_rx, 897 .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx), 898 .pcs = sm6115_ufsphy_pcs, 899 .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs), 900 }, 901 .tbls_hs_b = { 902 .serdes = sm6115_ufsphy_hs_b_serdes, 903 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), 904 }, 905 .clk_list = sdm845_ufs_phy_clk_l, 906 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 907 .vreg_list = qmp_phy_vreg_l, 908 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 909 .regs = ufsphy_v2_regs_layout, 910 911 .no_pcs_sw_reset = true, 912 }; 913 914 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { 915 .lanes = 2, 916 917 .tbls = { 918 .serdes = sm8150_ufsphy_serdes, 919 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 920 .tx = sm8150_ufsphy_tx, 921 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), 922 .rx = sm8150_ufsphy_rx, 923 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), 924 .pcs = sm8150_ufsphy_pcs, 925 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), 926 }, 927 .tbls_hs_b = { 928 .serdes = sm8150_ufsphy_hs_b_serdes, 929 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 930 }, 931 .tbls_hs_g4 = { 932 .tx = sm8150_ufsphy_hs_g4_tx, 933 .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), 934 .rx = sm8150_ufsphy_hs_g4_rx, 935 .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), 936 .pcs = sm8150_ufsphy_hs_g4_pcs, 937 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 938 }, 939 .clk_list = sdm845_ufs_phy_clk_l, 940 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 941 .vreg_list = qmp_phy_vreg_l, 942 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 943 .regs = ufsphy_v4_regs_layout, 944 }; 945 946 static const struct qmp_phy_cfg sm8250_ufsphy_cfg = { 947 .lanes = 2, 948 949 .tbls = { 950 .serdes = sm8150_ufsphy_serdes, 951 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 952 .tx = sm8150_ufsphy_tx, 953 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), 954 .rx = sm8150_ufsphy_rx, 955 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), 956 .pcs = sm8150_ufsphy_pcs, 957 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), 958 }, 959 .tbls_hs_b = { 960 .serdes = sm8150_ufsphy_hs_b_serdes, 961 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 962 }, 963 .tbls_hs_g4 = { 964 .tx = sm8250_ufsphy_hs_g4_tx, 965 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), 966 .rx = sm8250_ufsphy_hs_g4_rx, 967 .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx), 968 .pcs = sm8150_ufsphy_hs_g4_pcs, 969 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 970 }, 971 .clk_list = sdm845_ufs_phy_clk_l, 972 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 973 .vreg_list = qmp_phy_vreg_l, 974 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 975 .regs = ufsphy_v4_regs_layout, 976 }; 977 978 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { 979 .lanes = 2, 980 981 .tbls = { 982 .serdes = sm8350_ufsphy_serdes, 983 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 984 .tx = sm8350_ufsphy_tx, 985 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 986 .rx = sm8350_ufsphy_rx, 987 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 988 .pcs = sm8350_ufsphy_pcs, 989 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 990 }, 991 .tbls_hs_b = { 992 .serdes = sm8350_ufsphy_hs_b_serdes, 993 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 994 }, 995 .tbls_hs_g4 = { 996 .tx = sm8350_ufsphy_g4_tx, 997 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 998 .rx = sm8350_ufsphy_g4_rx, 999 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1000 .pcs = sm8350_ufsphy_g4_pcs, 1001 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1002 }, 1003 .clk_list = sdm845_ufs_phy_clk_l, 1004 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1005 .vreg_list = qmp_phy_vreg_l, 1006 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1007 .regs = ufsphy_v5_regs_layout, 1008 }; 1009 1010 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { 1011 .lanes = 2, 1012 1013 .tbls = { 1014 .serdes = sm8350_ufsphy_serdes, 1015 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1016 .tx = sm8350_ufsphy_tx, 1017 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1018 .rx = sm8350_ufsphy_rx, 1019 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1020 .pcs = sm8350_ufsphy_pcs, 1021 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1022 }, 1023 .tbls_hs_b = { 1024 .serdes = sm8350_ufsphy_hs_b_serdes, 1025 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1026 }, 1027 .tbls_hs_g4 = { 1028 .tx = sm8350_ufsphy_g4_tx, 1029 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1030 .rx = sm8350_ufsphy_g4_rx, 1031 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1032 .pcs = sm8350_ufsphy_g4_pcs, 1033 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1034 }, 1035 .clk_list = sm8450_ufs_phy_clk_l, 1036 .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), 1037 .vreg_list = qmp_phy_vreg_l, 1038 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1039 .regs = ufsphy_v5_regs_layout, 1040 }; 1041 1042 static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { 1043 .lanes = 2, 1044 1045 .offsets = &qmp_ufs_offsets_v6, 1046 1047 .tbls = { 1048 .serdes = sm8550_ufsphy_serdes, 1049 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes), 1050 .tx = sm8550_ufsphy_tx, 1051 .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx), 1052 .rx = sm8550_ufsphy_rx, 1053 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), 1054 .pcs = sm8550_ufsphy_pcs, 1055 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), 1056 }, 1057 .clk_list = sdm845_ufs_phy_clk_l, 1058 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1059 .vreg_list = qmp_phy_vreg_l, 1060 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1061 .regs = ufsphy_v6_regs_layout, 1062 }; 1063 1064 static void qmp_ufs_configure_lane(void __iomem *base, 1065 const struct qmp_phy_init_tbl tbl[], 1066 int num, 1067 u8 lane_mask) 1068 { 1069 int i; 1070 const struct qmp_phy_init_tbl *t = tbl; 1071 1072 if (!t) 1073 return; 1074 1075 for (i = 0; i < num; i++, t++) { 1076 if (!(t->lane_mask & lane_mask)) 1077 continue; 1078 1079 writel(t->val, base + t->offset); 1080 } 1081 } 1082 1083 static void qmp_ufs_configure(void __iomem *base, 1084 const struct qmp_phy_init_tbl tbl[], 1085 int num) 1086 { 1087 qmp_ufs_configure_lane(base, tbl, num, 0xff); 1088 } 1089 1090 static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1091 { 1092 void __iomem *serdes = qmp->serdes; 1093 1094 qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num); 1095 } 1096 1097 static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1098 { 1099 const struct qmp_phy_cfg *cfg = qmp->cfg; 1100 void __iomem *tx = qmp->tx; 1101 void __iomem *rx = qmp->rx; 1102 1103 qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1); 1104 qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1); 1105 1106 if (cfg->lanes >= 2) { 1107 qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2); 1108 qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2); 1109 } 1110 } 1111 1112 static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1113 { 1114 void __iomem *pcs = qmp->pcs; 1115 1116 qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num); 1117 } 1118 1119 static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) 1120 { 1121 qmp_ufs_serdes_init(qmp, &cfg->tbls); 1122 if (qmp->mode == PHY_MODE_UFS_HS_B) 1123 qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b); 1124 qmp_ufs_lanes_init(qmp, &cfg->tbls); 1125 if (qmp->submode == UFS_HS_G4) 1126 qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4); 1127 qmp_ufs_pcs_init(qmp, &cfg->tbls); 1128 if (qmp->submode == UFS_HS_G4) 1129 qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4); 1130 } 1131 1132 static int qmp_ufs_com_init(struct qmp_ufs *qmp) 1133 { 1134 const struct qmp_phy_cfg *cfg = qmp->cfg; 1135 void __iomem *pcs = qmp->pcs; 1136 int ret; 1137 1138 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1139 if (ret) { 1140 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1141 return ret; 1142 } 1143 1144 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1145 if (ret) 1146 goto err_disable_regulators; 1147 1148 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 1149 1150 return 0; 1151 1152 err_disable_regulators: 1153 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1154 1155 return ret; 1156 } 1157 1158 static int qmp_ufs_com_exit(struct qmp_ufs *qmp) 1159 { 1160 const struct qmp_phy_cfg *cfg = qmp->cfg; 1161 1162 reset_control_assert(qmp->ufs_reset); 1163 1164 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1165 1166 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1167 1168 return 0; 1169 } 1170 1171 static int qmp_ufs_init(struct phy *phy) 1172 { 1173 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1174 const struct qmp_phy_cfg *cfg = qmp->cfg; 1175 int ret; 1176 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 1177 1178 if (cfg->no_pcs_sw_reset) { 1179 /* 1180 * Get UFS reset, which is delayed until now to avoid a 1181 * circular dependency where UFS needs its PHY, but the PHY 1182 * needs this UFS reset. 1183 */ 1184 if (!qmp->ufs_reset) { 1185 qmp->ufs_reset = 1186 devm_reset_control_get_exclusive(qmp->dev, 1187 "ufsphy"); 1188 1189 if (IS_ERR(qmp->ufs_reset)) { 1190 ret = PTR_ERR(qmp->ufs_reset); 1191 dev_err(qmp->dev, 1192 "failed to get UFS reset: %d\n", 1193 ret); 1194 1195 qmp->ufs_reset = NULL; 1196 return ret; 1197 } 1198 } 1199 1200 ret = reset_control_assert(qmp->ufs_reset); 1201 if (ret) 1202 return ret; 1203 } 1204 1205 ret = qmp_ufs_com_init(qmp); 1206 if (ret) 1207 return ret; 1208 1209 return 0; 1210 } 1211 1212 static int qmp_ufs_power_on(struct phy *phy) 1213 { 1214 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1215 const struct qmp_phy_cfg *cfg = qmp->cfg; 1216 void __iomem *pcs = qmp->pcs; 1217 void __iomem *status; 1218 unsigned int val; 1219 int ret; 1220 1221 qmp_ufs_init_registers(qmp, cfg); 1222 1223 ret = reset_control_deassert(qmp->ufs_reset); 1224 if (ret) 1225 return ret; 1226 1227 /* Pull PHY out of reset state */ 1228 if (!cfg->no_pcs_sw_reset) 1229 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1230 1231 /* start SerDes */ 1232 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); 1233 1234 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; 1235 ret = readl_poll_timeout(status, val, (val & PCS_READY), 200, 1236 PHY_INIT_COMPLETE_TIMEOUT); 1237 if (ret) { 1238 dev_err(qmp->dev, "phy initialization timed-out\n"); 1239 return ret; 1240 } 1241 1242 return 0; 1243 } 1244 1245 static int qmp_ufs_power_off(struct phy *phy) 1246 { 1247 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1248 const struct qmp_phy_cfg *cfg = qmp->cfg; 1249 1250 /* PHY reset */ 1251 if (!cfg->no_pcs_sw_reset) 1252 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1253 1254 /* stop SerDes */ 1255 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); 1256 1257 /* Put PHY into POWER DOWN state: active low */ 1258 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1259 SW_PWRDN); 1260 1261 return 0; 1262 } 1263 1264 static int qmp_ufs_exit(struct phy *phy) 1265 { 1266 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1267 1268 qmp_ufs_com_exit(qmp); 1269 1270 return 0; 1271 } 1272 1273 static int qmp_ufs_enable(struct phy *phy) 1274 { 1275 int ret; 1276 1277 ret = qmp_ufs_init(phy); 1278 if (ret) 1279 return ret; 1280 1281 ret = qmp_ufs_power_on(phy); 1282 if (ret) 1283 qmp_ufs_exit(phy); 1284 1285 return ret; 1286 } 1287 1288 static int qmp_ufs_disable(struct phy *phy) 1289 { 1290 int ret; 1291 1292 ret = qmp_ufs_power_off(phy); 1293 if (ret) 1294 return ret; 1295 return qmp_ufs_exit(phy); 1296 } 1297 1298 static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) 1299 { 1300 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1301 1302 qmp->mode = mode; 1303 qmp->submode = submode; 1304 1305 return 0; 1306 } 1307 1308 static const struct phy_ops qcom_qmp_ufs_phy_ops = { 1309 .power_on = qmp_ufs_enable, 1310 .power_off = qmp_ufs_disable, 1311 .set_mode = qmp_ufs_set_mode, 1312 .owner = THIS_MODULE, 1313 }; 1314 1315 static int qmp_ufs_vreg_init(struct qmp_ufs *qmp) 1316 { 1317 const struct qmp_phy_cfg *cfg = qmp->cfg; 1318 struct device *dev = qmp->dev; 1319 int num = cfg->num_vregs; 1320 int i; 1321 1322 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 1323 if (!qmp->vregs) 1324 return -ENOMEM; 1325 1326 for (i = 0; i < num; i++) 1327 qmp->vregs[i].supply = cfg->vreg_list[i]; 1328 1329 return devm_regulator_bulk_get(dev, num, qmp->vregs); 1330 } 1331 1332 static int qmp_ufs_clk_init(struct qmp_ufs *qmp) 1333 { 1334 const struct qmp_phy_cfg *cfg = qmp->cfg; 1335 struct device *dev = qmp->dev; 1336 int num = cfg->num_clks; 1337 int i; 1338 1339 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 1340 if (!qmp->clks) 1341 return -ENOMEM; 1342 1343 for (i = 0; i < num; i++) 1344 qmp->clks[i].id = cfg->clk_list[i]; 1345 1346 return devm_clk_bulk_get(dev, num, qmp->clks); 1347 } 1348 1349 static void qmp_ufs_clk_release_provider(void *res) 1350 { 1351 of_clk_del_provider(res); 1352 } 1353 1354 #define UFS_SYMBOL_CLOCKS 3 1355 1356 static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np) 1357 { 1358 struct clk_hw_onecell_data *clk_data; 1359 struct clk_hw *hw; 1360 char name[64]; 1361 int ret; 1362 1363 clk_data = devm_kzalloc(qmp->dev, 1364 struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS), 1365 GFP_KERNEL); 1366 if (!clk_data) 1367 return -ENOMEM; 1368 1369 clk_data->num = UFS_SYMBOL_CLOCKS; 1370 1371 snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev)); 1372 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 1373 if (IS_ERR(hw)) 1374 return PTR_ERR(hw); 1375 1376 clk_data->hws[0] = hw; 1377 1378 snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev)); 1379 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 1380 if (IS_ERR(hw)) 1381 return PTR_ERR(hw); 1382 1383 clk_data->hws[1] = hw; 1384 1385 snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev)); 1386 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 1387 if (IS_ERR(hw)) 1388 return PTR_ERR(hw); 1389 1390 clk_data->hws[2] = hw; 1391 1392 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 1393 if (ret) 1394 return ret; 1395 1396 /* 1397 * Roll a devm action because the clock provider can be a child node. 1398 */ 1399 return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np); 1400 } 1401 1402 static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np) 1403 { 1404 struct platform_device *pdev = to_platform_device(qmp->dev); 1405 const struct qmp_phy_cfg *cfg = qmp->cfg; 1406 struct device *dev = qmp->dev; 1407 1408 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 1409 if (IS_ERR(qmp->serdes)) 1410 return PTR_ERR(qmp->serdes); 1411 1412 /* 1413 * Get memory resources for the PHY: 1414 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 1415 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 1416 * For single lane PHYs: pcs_misc (optional) -> 3. 1417 */ 1418 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 1419 if (IS_ERR(qmp->tx)) 1420 return PTR_ERR(qmp->tx); 1421 1422 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 1423 if (IS_ERR(qmp->rx)) 1424 return PTR_ERR(qmp->rx); 1425 1426 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 1427 if (IS_ERR(qmp->pcs)) 1428 return PTR_ERR(qmp->pcs); 1429 1430 if (cfg->lanes >= 2) { 1431 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 1432 if (IS_ERR(qmp->tx2)) 1433 return PTR_ERR(qmp->tx2); 1434 1435 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 1436 if (IS_ERR(qmp->rx2)) 1437 return PTR_ERR(qmp->rx2); 1438 1439 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 1440 } else { 1441 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 1442 } 1443 1444 if (IS_ERR(qmp->pcs_misc)) 1445 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 1446 1447 return 0; 1448 } 1449 1450 static int qmp_ufs_parse_dt(struct qmp_ufs *qmp) 1451 { 1452 struct platform_device *pdev = to_platform_device(qmp->dev); 1453 const struct qmp_phy_cfg *cfg = qmp->cfg; 1454 const struct qmp_ufs_offsets *offs = cfg->offsets; 1455 void __iomem *base; 1456 1457 if (!offs) 1458 return -EINVAL; 1459 1460 base = devm_platform_ioremap_resource(pdev, 0); 1461 if (IS_ERR(base)) 1462 return PTR_ERR(base); 1463 1464 qmp->serdes = base + offs->serdes; 1465 qmp->pcs = base + offs->pcs; 1466 qmp->tx = base + offs->tx; 1467 qmp->rx = base + offs->rx; 1468 1469 if (cfg->lanes >= 2) { 1470 qmp->tx2 = base + offs->tx2; 1471 qmp->rx2 = base + offs->rx2; 1472 } 1473 1474 return 0; 1475 } 1476 1477 static int qmp_ufs_probe(struct platform_device *pdev) 1478 { 1479 struct device *dev = &pdev->dev; 1480 struct phy_provider *phy_provider; 1481 struct device_node *np; 1482 struct qmp_ufs *qmp; 1483 int ret; 1484 1485 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 1486 if (!qmp) 1487 return -ENOMEM; 1488 1489 qmp->dev = dev; 1490 1491 qmp->cfg = of_device_get_match_data(dev); 1492 if (!qmp->cfg) 1493 return -EINVAL; 1494 1495 ret = qmp_ufs_clk_init(qmp); 1496 if (ret) 1497 return ret; 1498 1499 ret = qmp_ufs_vreg_init(qmp); 1500 if (ret) 1501 return ret; 1502 1503 /* Check for legacy binding with child node. */ 1504 np = of_get_next_available_child(dev->of_node, NULL); 1505 if (np) { 1506 ret = qmp_ufs_parse_dt_legacy(qmp, np); 1507 } else { 1508 np = of_node_get(dev->of_node); 1509 ret = qmp_ufs_parse_dt(qmp); 1510 } 1511 if (ret) 1512 goto err_node_put; 1513 1514 ret = qmp_ufs_register_clocks(qmp, np); 1515 if (ret) 1516 goto err_node_put; 1517 1518 qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops); 1519 if (IS_ERR(qmp->phy)) { 1520 ret = PTR_ERR(qmp->phy); 1521 dev_err(dev, "failed to create PHY: %d\n", ret); 1522 goto err_node_put; 1523 } 1524 1525 phy_set_drvdata(qmp->phy, qmp); 1526 1527 of_node_put(np); 1528 1529 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1530 1531 return PTR_ERR_OR_ZERO(phy_provider); 1532 1533 err_node_put: 1534 of_node_put(np); 1535 return ret; 1536 } 1537 1538 static const struct of_device_id qmp_ufs_of_match_table[] = { 1539 { 1540 .compatible = "qcom,msm8996-qmp-ufs-phy", 1541 .data = &msm8996_ufsphy_cfg, 1542 }, { 1543 .compatible = "qcom,msm8998-qmp-ufs-phy", 1544 .data = &sdm845_ufsphy_cfg, 1545 }, { 1546 .compatible = "qcom,sc8180x-qmp-ufs-phy", 1547 .data = &sm8150_ufsphy_cfg, 1548 }, { 1549 .compatible = "qcom,sc8280xp-qmp-ufs-phy", 1550 .data = &sc8280xp_ufsphy_cfg, 1551 }, { 1552 .compatible = "qcom,sdm845-qmp-ufs-phy", 1553 .data = &sdm845_ufsphy_cfg, 1554 }, { 1555 .compatible = "qcom,sm6115-qmp-ufs-phy", 1556 .data = &sm6115_ufsphy_cfg, 1557 }, { 1558 .compatible = "qcom,sm6125-qmp-ufs-phy", 1559 .data = &sm6115_ufsphy_cfg, 1560 }, { 1561 .compatible = "qcom,sm6350-qmp-ufs-phy", 1562 .data = &sdm845_ufsphy_cfg, 1563 }, { 1564 .compatible = "qcom,sm8150-qmp-ufs-phy", 1565 .data = &sm8150_ufsphy_cfg, 1566 }, { 1567 .compatible = "qcom,sm8250-qmp-ufs-phy", 1568 .data = &sm8250_ufsphy_cfg, 1569 }, { 1570 .compatible = "qcom,sm8350-qmp-ufs-phy", 1571 .data = &sm8350_ufsphy_cfg, 1572 }, { 1573 .compatible = "qcom,sm8450-qmp-ufs-phy", 1574 .data = &sm8450_ufsphy_cfg, 1575 }, { 1576 .compatible = "qcom,sm8550-qmp-ufs-phy", 1577 .data = &sm8550_ufsphy_cfg, 1578 }, 1579 { }, 1580 }; 1581 MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table); 1582 1583 static struct platform_driver qmp_ufs_driver = { 1584 .probe = qmp_ufs_probe, 1585 .driver = { 1586 .name = "qcom-qmp-ufs-phy", 1587 .of_match_table = qmp_ufs_of_match_table, 1588 }, 1589 }; 1590 1591 module_platform_driver(qmp_ufs_driver); 1592 1593 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 1594 MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver"); 1595 MODULE_LICENSE("GPL v2"); 1596