1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * P2U (PIPE to UPHY) driver for Tegra T194 SoC 4 * 5 * Copyright (C) 2019-2022 NVIDIA Corporation. 6 * 7 * Author: Vidya Sagar <vidyas@nvidia.com> 8 */ 9 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/phy/phy.h> 16 17 #define P2U_CONTROL_CMN 0x74 18 #define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20) 19 20 #define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0 21 #define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0) 22 #define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1) 23 #define P2U_PERIODIC_EQ_CTRL_GEN4 0xc4 24 #define P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN BIT(1) 25 26 #define P2U_RX_DEBOUNCE_TIME 0xa4 27 #define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK 0xffff 28 #define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL 160 29 30 #define P2U_DIR_SEARCH_CTRL 0xd4 31 #define P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE BIT(18) 32 33 struct tegra_p2u_of_data { 34 bool one_dir_search; 35 }; 36 37 struct tegra_p2u { 38 void __iomem *base; 39 bool skip_sz_protection_en; /* Needed to support two retimers */ 40 struct tegra_p2u_of_data *of_data; 41 }; 42 43 static inline void p2u_writel(struct tegra_p2u *phy, const u32 value, 44 const u32 reg) 45 { 46 writel_relaxed(value, phy->base + reg); 47 } 48 49 static inline u32 p2u_readl(struct tegra_p2u *phy, const u32 reg) 50 { 51 return readl_relaxed(phy->base + reg); 52 } 53 54 static int tegra_p2u_power_on(struct phy *x) 55 { 56 struct tegra_p2u *phy = phy_get_drvdata(x); 57 u32 val; 58 59 if (phy->skip_sz_protection_en) { 60 val = p2u_readl(phy, P2U_CONTROL_CMN); 61 val |= P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN; 62 p2u_writel(phy, val, P2U_CONTROL_CMN); 63 } 64 65 val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3); 66 val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN; 67 val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN; 68 p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN3); 69 70 val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN4); 71 val |= P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN; 72 p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN4); 73 74 val = p2u_readl(phy, P2U_RX_DEBOUNCE_TIME); 75 val &= ~P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK; 76 val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL; 77 p2u_writel(phy, val, P2U_RX_DEBOUNCE_TIME); 78 79 if (phy->of_data->one_dir_search) { 80 val = p2u_readl(phy, P2U_DIR_SEARCH_CTRL); 81 val &= ~P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE; 82 p2u_writel(phy, val, P2U_DIR_SEARCH_CTRL); 83 } 84 85 return 0; 86 } 87 88 static const struct phy_ops ops = { 89 .power_on = tegra_p2u_power_on, 90 .owner = THIS_MODULE, 91 }; 92 93 static int tegra_p2u_probe(struct platform_device *pdev) 94 { 95 struct phy_provider *phy_provider; 96 struct device *dev = &pdev->dev; 97 struct phy *generic_phy; 98 struct tegra_p2u *phy; 99 100 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); 101 if (!phy) 102 return -ENOMEM; 103 104 phy->of_data = 105 (struct tegra_p2u_of_data *)of_device_get_match_data(dev); 106 if (!phy->of_data) 107 return -EINVAL; 108 109 phy->base = devm_platform_ioremap_resource_byname(pdev, "ctl"); 110 if (IS_ERR(phy->base)) 111 return PTR_ERR(phy->base); 112 113 phy->skip_sz_protection_en = 114 of_property_read_bool(dev->of_node, 115 "nvidia,skip-sz-protect-en"); 116 117 platform_set_drvdata(pdev, phy); 118 119 generic_phy = devm_phy_create(dev, NULL, &ops); 120 if (IS_ERR(generic_phy)) 121 return PTR_ERR(generic_phy); 122 123 phy_set_drvdata(generic_phy, phy); 124 125 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 126 if (IS_ERR(phy_provider)) 127 return PTR_ERR(phy_provider); 128 129 return 0; 130 } 131 132 static const struct tegra_p2u_of_data tegra194_p2u_of_data = { 133 .one_dir_search = false, 134 }; 135 136 static const struct tegra_p2u_of_data tegra234_p2u_of_data = { 137 .one_dir_search = true, 138 }; 139 140 static const struct of_device_id tegra_p2u_id_table[] = { 141 { 142 .compatible = "nvidia,tegra194-p2u", 143 .data = &tegra194_p2u_of_data, 144 }, 145 { 146 .compatible = "nvidia,tegra234-p2u", 147 .data = &tegra234_p2u_of_data, 148 }, 149 {} 150 }; 151 MODULE_DEVICE_TABLE(of, tegra_p2u_id_table); 152 153 static struct platform_driver tegra_p2u_driver = { 154 .probe = tegra_p2u_probe, 155 .driver = { 156 .name = "tegra194-p2u", 157 .of_match_table = tegra_p2u_id_table, 158 }, 159 }; 160 module_platform_driver(tegra_p2u_driver); 161 162 MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>"); 163 MODULE_DESCRIPTION("NVIDIA Tegra194 PIPE2UPHY PHY driver"); 164 MODULE_LICENSE("GPL v2"); 165