1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Wrapper driver for SERDES used in J721E 4 * 5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/phy/phy-ti.h> 11 #include <linux/slab.h> 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/gpio.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/mux/consumer.h> 20 #include <linux/of_address.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/reset-controller.h> 26 27 #define REF_CLK_19_2MHZ 19200000 28 #define REF_CLK_25MHZ 25000000 29 #define REF_CLK_100MHZ 100000000 30 #define REF_CLK_156_25MHZ 156250000 31 32 /* SCM offsets */ 33 #define SERDES_SUP_CTRL 0x4400 34 35 /* SERDES offsets */ 36 #define WIZ_SERDES_CTRL 0x404 37 #define WIZ_SERDES_TOP_CTRL 0x408 38 #define WIZ_SERDES_RST 0x40c 39 #define WIZ_SERDES_TYPEC 0x410 40 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) 41 #define WIZ_LANEDIV(n) (0x484 + (0x40 * (n))) 42 43 #define WIZ_MAX_INPUT_CLOCKS 4 44 /* To include mux clocks, divider clocks and gate clocks */ 45 #define WIZ_MAX_OUTPUT_CLOCKS 32 46 47 #define WIZ_MAX_LANES 4 48 #define WIZ_MUX_NUM_CLOCKS 3 49 #define WIZ_DIV_NUM_CLOCKS_16G 2 50 #define WIZ_DIV_NUM_CLOCKS_10G 1 51 52 #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) 53 54 enum wiz_lane_standard_mode { 55 LANE_MODE_GEN1, 56 LANE_MODE_GEN2, 57 LANE_MODE_GEN3, 58 LANE_MODE_GEN4, 59 }; 60 61 /* 62 * List of master lanes used for lane swapping 63 */ 64 enum wiz_typec_master_lane { 65 LANE0 = 0, 66 LANE2 = 2, 67 }; 68 69 enum wiz_refclk_mux_sel { 70 PLL0_REFCLK, 71 PLL1_REFCLK, 72 REFCLK_DIG, 73 }; 74 75 enum wiz_refclk_div_sel { 76 CMN_REFCLK_DIG_DIV, 77 CMN_REFCLK1_DIG_DIV, 78 }; 79 80 enum wiz_clock_input { 81 WIZ_CORE_REFCLK, 82 WIZ_EXT_REFCLK, 83 WIZ_CORE_REFCLK1, 84 WIZ_EXT_REFCLK1, 85 }; 86 87 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); 88 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); 89 static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30); 90 static const struct reg_field pll1_refclk_mux_sel = 91 REG_FIELD(WIZ_SERDES_RST, 29, 29); 92 static const struct reg_field pll1_refclk_mux_sel_2 = 93 REG_FIELD(WIZ_SERDES_RST, 22, 23); 94 static const struct reg_field pll0_refclk_mux_sel = 95 REG_FIELD(WIZ_SERDES_RST, 28, 28); 96 static const struct reg_field pll0_refclk_mux_sel_2 = 97 REG_FIELD(WIZ_SERDES_RST, 28, 29); 98 static const struct reg_field refclk_dig_sel_16g = 99 REG_FIELD(WIZ_SERDES_RST, 24, 25); 100 static const struct reg_field refclk_dig_sel_10g = 101 REG_FIELD(WIZ_SERDES_RST, 24, 24); 102 static const struct reg_field pma_cmn_refclk_int_mode = 103 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); 104 static const struct reg_field pma_cmn_refclk1_int_mode = 105 REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21); 106 static const struct reg_field pma_cmn_refclk_mode = 107 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); 108 static const struct reg_field pma_cmn_refclk_dig_div = 109 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); 110 static const struct reg_field pma_cmn_refclk1_dig_div = 111 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); 112 113 static const struct reg_field sup_pll0_refclk_mux_sel = 114 REG_FIELD(SERDES_SUP_CTRL, 0, 1); 115 static const struct reg_field sup_pll1_refclk_mux_sel = 116 REG_FIELD(SERDES_SUP_CTRL, 2, 3); 117 static const struct reg_field sup_pma_cmn_refclk1_int_mode = 118 REG_FIELD(SERDES_SUP_CTRL, 4, 5); 119 static const struct reg_field sup_refclk_dig_sel_10g = 120 REG_FIELD(SERDES_SUP_CTRL, 6, 7); 121 static const struct reg_field sup_legacy_clk_override = 122 REG_FIELD(SERDES_SUP_CTRL, 8, 8); 123 124 static const char * const output_clk_names[] = { 125 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk", 126 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk", 127 [TI_WIZ_REFCLK_DIG] = "refclk-dig", 128 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk", 129 }; 130 131 static const struct reg_field p_enable[WIZ_MAX_LANES] = { 132 REG_FIELD(WIZ_LANECTL(0), 30, 31), 133 REG_FIELD(WIZ_LANECTL(1), 30, 31), 134 REG_FIELD(WIZ_LANECTL(2), 30, 31), 135 REG_FIELD(WIZ_LANECTL(3), 30, 31), 136 }; 137 138 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 }; 139 140 static const struct reg_field p_align[WIZ_MAX_LANES] = { 141 REG_FIELD(WIZ_LANECTL(0), 29, 29), 142 REG_FIELD(WIZ_LANECTL(1), 29, 29), 143 REG_FIELD(WIZ_LANECTL(2), 29, 29), 144 REG_FIELD(WIZ_LANECTL(3), 29, 29), 145 }; 146 147 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = { 148 REG_FIELD(WIZ_LANECTL(0), 28, 28), 149 REG_FIELD(WIZ_LANECTL(1), 28, 28), 150 REG_FIELD(WIZ_LANECTL(2), 28, 28), 151 REG_FIELD(WIZ_LANECTL(3), 28, 28), 152 }; 153 154 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { 155 REG_FIELD(WIZ_LANECTL(0), 24, 25), 156 REG_FIELD(WIZ_LANECTL(1), 24, 25), 157 REG_FIELD(WIZ_LANECTL(2), 24, 25), 158 REG_FIELD(WIZ_LANECTL(3), 24, 25), 159 }; 160 161 static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = { 162 REG_FIELD(WIZ_LANECTL(0), 22, 23), 163 REG_FIELD(WIZ_LANECTL(1), 22, 23), 164 REG_FIELD(WIZ_LANECTL(2), 22, 23), 165 REG_FIELD(WIZ_LANECTL(3), 22, 23), 166 }; 167 168 static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = { 169 REG_FIELD(WIZ_LANECTL(0), 20, 21), 170 REG_FIELD(WIZ_LANECTL(1), 20, 21), 171 REG_FIELD(WIZ_LANECTL(2), 20, 21), 172 REG_FIELD(WIZ_LANECTL(3), 20, 21), 173 }; 174 175 static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = { 176 REG_FIELD(WIZ_LANECTL(0), 6, 7), 177 REG_FIELD(WIZ_LANECTL(1), 6, 7), 178 REG_FIELD(WIZ_LANECTL(2), 6, 7), 179 REG_FIELD(WIZ_LANECTL(3), 6, 7), 180 }; 181 182 static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = { 183 REG_FIELD(WIZ_LANECTL(0), 18, 19), 184 REG_FIELD(WIZ_LANECTL(1), 18, 19), 185 REG_FIELD(WIZ_LANECTL(2), 18, 19), 186 REG_FIELD(WIZ_LANECTL(3), 18, 19), 187 }; 188 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = { 189 REG_FIELD(WIZ_LANEDIV(0), 16, 22), 190 REG_FIELD(WIZ_LANEDIV(1), 16, 22), 191 REG_FIELD(WIZ_LANEDIV(2), 16, 22), 192 REG_FIELD(WIZ_LANEDIV(3), 16, 22), 193 }; 194 195 static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = { 196 REG_FIELD(WIZ_LANEDIV(0), 0, 8), 197 REG_FIELD(WIZ_LANEDIV(1), 0, 8), 198 REG_FIELD(WIZ_LANEDIV(2), 0, 8), 199 REG_FIELD(WIZ_LANEDIV(3), 0, 8), 200 }; 201 202 static const struct reg_field typec_ln10_swap = 203 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); 204 205 static const struct reg_field typec_ln23_swap = 206 REG_FIELD(WIZ_SERDES_TYPEC, 31, 31); 207 208 struct wiz_clk_mux { 209 struct clk_hw hw; 210 struct regmap_field *field; 211 const u32 *table; 212 struct clk_init_data clk_data; 213 }; 214 215 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw) 216 217 struct wiz_clk_divider { 218 struct clk_hw hw; 219 struct regmap_field *field; 220 const struct clk_div_table *table; 221 struct clk_init_data clk_data; 222 }; 223 224 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw) 225 226 struct wiz_clk_mux_sel { 227 u32 table[WIZ_MAX_INPUT_CLOCKS]; 228 const char *node_name; 229 u32 num_parents; 230 u32 parents[WIZ_MAX_INPUT_CLOCKS]; 231 }; 232 233 struct wiz_clk_div_sel { 234 const struct clk_div_table *table; 235 const char *node_name; 236 }; 237 238 struct wiz_phy_en_refclk { 239 struct clk_hw hw; 240 struct regmap_field *phy_en_refclk; 241 struct clk_init_data clk_data; 242 }; 243 244 #define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw) 245 246 static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = { 247 { 248 /* 249 * Mux value to be configured for each of the input clocks 250 * in the order populated in device tree 251 */ 252 .table = { 1, 0 }, 253 .node_name = "pll0-refclk", 254 }, 255 { 256 .table = { 1, 0 }, 257 .node_name = "pll1-refclk", 258 }, 259 { 260 .table = { 1, 3, 0, 2 }, 261 .node_name = "refclk-dig", 262 }, 263 }; 264 265 static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = { 266 { 267 /* 268 * Mux value to be configured for each of the input clocks 269 * in the order populated in device tree 270 */ 271 .num_parents = 2, 272 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 273 .table = { 1, 0 }, 274 .node_name = "pll0-refclk", 275 }, 276 { 277 .num_parents = 2, 278 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 279 .table = { 1, 0 }, 280 .node_name = "pll1-refclk", 281 }, 282 { 283 .num_parents = 2, 284 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 285 .table = { 1, 0 }, 286 .node_name = "refclk-dig", 287 }, 288 }; 289 290 static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = { 291 { 292 .num_parents = 3, 293 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 294 .table = { 2, 3, 0 }, 295 .node_name = "pll0-refclk", 296 }, 297 { 298 .num_parents = 3, 299 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 300 .table = { 2, 3, 0 }, 301 .node_name = "pll1-refclk", 302 }, 303 { 304 .num_parents = 3, 305 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 306 .table = { 2, 3, 0 }, 307 .node_name = "refclk-dig", 308 }, 309 }; 310 311 static const struct clk_div_table clk_div_table[] = { 312 { .val = 0, .div = 1, }, 313 { .val = 1, .div = 2, }, 314 { .val = 2, .div = 4, }, 315 { .val = 3, .div = 8, }, 316 { /* sentinel */ }, 317 }; 318 319 static const struct wiz_clk_div_sel clk_div_sel[] = { 320 { 321 .table = clk_div_table, 322 .node_name = "cmn-refclk-dig-div", 323 }, 324 { 325 .table = clk_div_table, 326 .node_name = "cmn-refclk1-dig-div", 327 }, 328 }; 329 330 enum wiz_type { 331 J721E_WIZ_16G, 332 J721E_WIZ_10G, /* Also for J7200 SR1.0 */ 333 AM64_WIZ_10G, 334 J7200_WIZ_10G, /* J7200 SR2.0 */ 335 J784S4_WIZ_10G, 336 J721S2_WIZ_10G, 337 }; 338 339 struct wiz_data { 340 enum wiz_type type; 341 const struct reg_field *pll0_refclk_mux_sel; 342 const struct reg_field *pll1_refclk_mux_sel; 343 const struct reg_field *refclk_dig_sel; 344 const struct reg_field *pma_cmn_refclk1_dig_div; 345 const struct reg_field *pma_cmn_refclk1_int_mode; 346 const struct wiz_clk_mux_sel *clk_mux_sel; 347 unsigned int clk_div_sel_num; 348 }; 349 350 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ 351 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 352 353 struct wiz { 354 struct regmap *regmap; 355 struct regmap *scm_regmap; 356 enum wiz_type type; 357 const struct wiz_clk_mux_sel *clk_mux_sel; 358 const struct wiz_clk_div_sel *clk_div_sel; 359 unsigned int clk_div_sel_num; 360 struct regmap_field *por_en; 361 struct regmap_field *phy_reset_n; 362 struct regmap_field *phy_en_refclk; 363 struct regmap_field *p_enable[WIZ_MAX_LANES]; 364 struct regmap_field *p_align[WIZ_MAX_LANES]; 365 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; 366 struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; 367 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES]; 368 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES]; 369 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; 370 struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES]; 371 struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES]; 372 struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES]; 373 struct regmap_field *pma_cmn_refclk_int_mode; 374 struct regmap_field *pma_cmn_refclk1_int_mode; 375 struct regmap_field *pma_cmn_refclk_mode; 376 struct regmap_field *pma_cmn_refclk_dig_div; 377 struct regmap_field *pma_cmn_refclk1_dig_div; 378 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS]; 379 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G]; 380 struct regmap_field *typec_ln10_swap; 381 struct regmap_field *typec_ln23_swap; 382 struct regmap_field *sup_legacy_clk_override; 383 384 struct device *dev; 385 u32 num_lanes; 386 struct platform_device *serdes_pdev; 387 struct reset_controller_dev wiz_phy_reset_dev; 388 struct gpio_desc *gpio_typec_dir; 389 int typec_dir_delay; 390 u32 lane_phy_type[WIZ_MAX_LANES]; 391 u32 master_lane_num[WIZ_MAX_LANES]; 392 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; 393 struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS]; 394 struct clk_onecell_data clk_data; 395 const struct wiz_data *data; 396 }; 397 398 static int wiz_reset(struct wiz *wiz) 399 { 400 int ret; 401 402 ret = regmap_field_write(wiz->por_en, 0x1); 403 if (ret) 404 return ret; 405 406 mdelay(1); 407 408 ret = regmap_field_write(wiz->por_en, 0x0); 409 if (ret) 410 return ret; 411 412 return 0; 413 } 414 415 static int wiz_p_mac_div_sel(struct wiz *wiz) 416 { 417 u32 num_lanes = wiz->num_lanes; 418 int ret; 419 int i; 420 421 for (i = 0; i < num_lanes; i++) { 422 if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII || 423 wiz->lane_phy_type[i] == PHY_TYPE_QSGMII || 424 wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 425 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); 426 if (ret) 427 return ret; 428 429 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2); 430 if (ret) 431 return ret; 432 } 433 } 434 435 return 0; 436 } 437 438 static int wiz_mode_select(struct wiz *wiz) 439 { 440 u32 num_lanes = wiz->num_lanes; 441 enum wiz_lane_standard_mode mode; 442 int ret; 443 int i; 444 445 for (i = 0; i < num_lanes; i++) { 446 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) { 447 mode = LANE_MODE_GEN1; 448 } else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) { 449 mode = LANE_MODE_GEN2; 450 } else if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 451 ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3); 452 ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3); 453 ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3); 454 mode = LANE_MODE_GEN1; 455 } else { 456 continue; 457 } 458 459 ret = regmap_field_write(wiz->p_standard_mode[i], mode); 460 if (ret) 461 return ret; 462 } 463 464 return 0; 465 } 466 467 static int wiz_init_raw_interface(struct wiz *wiz, bool enable) 468 { 469 u32 num_lanes = wiz->num_lanes; 470 int i; 471 int ret; 472 473 for (i = 0; i < num_lanes; i++) { 474 ret = regmap_field_write(wiz->p_align[i], enable); 475 if (ret) 476 return ret; 477 478 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); 479 if (ret) 480 return ret; 481 } 482 483 return 0; 484 } 485 486 static int wiz_init(struct wiz *wiz) 487 { 488 struct device *dev = wiz->dev; 489 int ret; 490 491 ret = wiz_reset(wiz); 492 if (ret) { 493 dev_err(dev, "WIZ reset failed\n"); 494 return ret; 495 } 496 497 ret = wiz_mode_select(wiz); 498 if (ret) { 499 dev_err(dev, "WIZ mode select failed\n"); 500 return ret; 501 } 502 503 ret = wiz_p_mac_div_sel(wiz); 504 if (ret) { 505 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n"); 506 return ret; 507 } 508 509 ret = wiz_init_raw_interface(wiz, true); 510 if (ret) { 511 dev_err(dev, "WIZ interface initialization failed\n"); 512 return ret; 513 } 514 515 return 0; 516 } 517 518 static int wiz_regfield_init(struct wiz *wiz) 519 { 520 struct regmap *regmap = wiz->regmap; 521 struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */ 522 int num_lanes = wiz->num_lanes; 523 struct device *dev = wiz->dev; 524 const struct wiz_data *data = wiz->data; 525 int i; 526 527 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); 528 if (IS_ERR(wiz->por_en)) { 529 dev_err(dev, "POR_EN reg field init failed\n"); 530 return PTR_ERR(wiz->por_en); 531 } 532 533 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, 534 phy_reset_n); 535 if (IS_ERR(wiz->phy_reset_n)) { 536 dev_err(dev, "PHY_RESET_N reg field init failed\n"); 537 return PTR_ERR(wiz->phy_reset_n); 538 } 539 540 wiz->pma_cmn_refclk_int_mode = 541 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode); 542 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { 543 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n"); 544 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); 545 } 546 547 wiz->pma_cmn_refclk_mode = 548 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); 549 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { 550 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n"); 551 return PTR_ERR(wiz->pma_cmn_refclk_mode); 552 } 553 554 wiz->div_sel_field[CMN_REFCLK_DIG_DIV] = 555 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div); 556 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) { 557 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n"); 558 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]); 559 } 560 561 if (data->pma_cmn_refclk1_dig_div) { 562 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] = 563 devm_regmap_field_alloc(dev, regmap, 564 *data->pma_cmn_refclk1_dig_div); 565 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) { 566 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); 567 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]); 568 } 569 } 570 571 if (wiz->scm_regmap) { 572 scm_regmap = wiz->scm_regmap; 573 wiz->sup_legacy_clk_override = 574 devm_regmap_field_alloc(dev, scm_regmap, sup_legacy_clk_override); 575 if (IS_ERR(wiz->sup_legacy_clk_override)) { 576 dev_err(dev, "SUP_LEGACY_CLK_OVERRIDE reg field init failed\n"); 577 return PTR_ERR(wiz->sup_legacy_clk_override); 578 } 579 } 580 581 wiz->mux_sel_field[PLL0_REFCLK] = 582 devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel); 583 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { 584 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); 585 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); 586 } 587 588 wiz->mux_sel_field[PLL1_REFCLK] = 589 devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel); 590 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { 591 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); 592 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); 593 } 594 595 wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap, 596 *data->refclk_dig_sel); 597 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { 598 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); 599 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); 600 } 601 602 if (data->pma_cmn_refclk1_int_mode) { 603 wiz->pma_cmn_refclk1_int_mode = 604 devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mode); 605 if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) { 606 dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n"); 607 return PTR_ERR(wiz->pma_cmn_refclk1_int_mode); 608 } 609 } 610 611 for (i = 0; i < num_lanes; i++) { 612 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, 613 p_enable[i]); 614 if (IS_ERR(wiz->p_enable[i])) { 615 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 616 return PTR_ERR(wiz->p_enable[i]); 617 } 618 619 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, 620 p_align[i]); 621 if (IS_ERR(wiz->p_align[i])) { 622 dev_err(dev, "P%d_ALIGN reg field init failed\n", i); 623 return PTR_ERR(wiz->p_align[i]); 624 } 625 626 wiz->p_raw_auto_start[i] = 627 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]); 628 if (IS_ERR(wiz->p_raw_auto_start[i])) { 629 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n", 630 i); 631 return PTR_ERR(wiz->p_raw_auto_start[i]); 632 } 633 634 wiz->p_standard_mode[i] = 635 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]); 636 if (IS_ERR(wiz->p_standard_mode[i])) { 637 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n", 638 i); 639 return PTR_ERR(wiz->p_standard_mode[i]); 640 } 641 642 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]); 643 if (IS_ERR(wiz->p0_fullrt_div[i])) { 644 dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i); 645 return PTR_ERR(wiz->p0_fullrt_div[i]); 646 } 647 648 wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]); 649 if (IS_ERR(wiz->p0_mac_src_sel[i])) { 650 dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i); 651 return PTR_ERR(wiz->p0_mac_src_sel[i]); 652 } 653 654 wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]); 655 if (IS_ERR(wiz->p0_rxfclk_sel[i])) { 656 dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i); 657 return PTR_ERR(wiz->p0_rxfclk_sel[i]); 658 } 659 660 wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]); 661 if (IS_ERR(wiz->p0_refclk_sel[i])) { 662 dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i); 663 return PTR_ERR(wiz->p0_refclk_sel[i]); 664 } 665 666 wiz->p_mac_div_sel0[i] = 667 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]); 668 if (IS_ERR(wiz->p_mac_div_sel0[i])) { 669 dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n", 670 i); 671 return PTR_ERR(wiz->p_mac_div_sel0[i]); 672 } 673 674 wiz->p_mac_div_sel1[i] = 675 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]); 676 if (IS_ERR(wiz->p_mac_div_sel1[i])) { 677 dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n", 678 i); 679 return PTR_ERR(wiz->p_mac_div_sel1[i]); 680 } 681 } 682 683 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, 684 typec_ln10_swap); 685 if (IS_ERR(wiz->typec_ln10_swap)) { 686 dev_err(dev, "LN10_SWAP reg field init failed\n"); 687 return PTR_ERR(wiz->typec_ln10_swap); 688 } 689 690 wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap, 691 typec_ln23_swap); 692 if (IS_ERR(wiz->typec_ln23_swap)) { 693 dev_err(dev, "LN23_SWAP reg field init failed\n"); 694 return PTR_ERR(wiz->typec_ln23_swap); 695 } 696 697 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk); 698 if (IS_ERR(wiz->phy_en_refclk)) { 699 dev_err(dev, "PHY_EN_REFCLK reg field init failed\n"); 700 return PTR_ERR(wiz->phy_en_refclk); 701 } 702 703 return 0; 704 } 705 706 static int wiz_phy_en_refclk_enable(struct clk_hw *hw) 707 { 708 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 709 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 710 711 regmap_field_write(phy_en_refclk, 1); 712 713 return 0; 714 } 715 716 static void wiz_phy_en_refclk_disable(struct clk_hw *hw) 717 { 718 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 719 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 720 721 regmap_field_write(phy_en_refclk, 0); 722 } 723 724 static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw) 725 { 726 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 727 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 728 int val; 729 730 regmap_field_read(phy_en_refclk, &val); 731 732 return !!val; 733 } 734 735 static const struct clk_ops wiz_phy_en_refclk_ops = { 736 .enable = wiz_phy_en_refclk_enable, 737 .disable = wiz_phy_en_refclk_disable, 738 .is_enabled = wiz_phy_en_refclk_is_enabled, 739 }; 740 741 static int wiz_phy_en_refclk_register(struct wiz *wiz) 742 { 743 struct wiz_phy_en_refclk *wiz_phy_en_refclk; 744 struct device *dev = wiz->dev; 745 struct clk_init_data *init; 746 struct clk *clk; 747 char *clk_name; 748 unsigned int sz; 749 750 wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL); 751 if (!wiz_phy_en_refclk) 752 return -ENOMEM; 753 754 init = &wiz_phy_en_refclk->clk_data; 755 756 init->ops = &wiz_phy_en_refclk_ops; 757 init->flags = 0; 758 759 sz = strlen(dev_name(dev)) + strlen(output_clk_names[TI_WIZ_PHY_EN_REFCLK]) + 2; 760 761 clk_name = kzalloc(sz, GFP_KERNEL); 762 if (!clk_name) 763 return -ENOMEM; 764 765 snprintf(clk_name, sz, "%s_%s", dev_name(dev), output_clk_names[TI_WIZ_PHY_EN_REFCLK]); 766 init->name = clk_name; 767 768 wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk; 769 wiz_phy_en_refclk->hw.init = init; 770 771 clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw); 772 773 kfree(clk_name); 774 775 if (IS_ERR(clk)) 776 return PTR_ERR(clk); 777 778 wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk; 779 780 return 0; 781 } 782 783 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) 784 { 785 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 786 struct regmap_field *field = mux->field; 787 unsigned int val; 788 789 regmap_field_read(field, &val); 790 return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val); 791 } 792 793 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) 794 { 795 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 796 struct regmap_field *field = mux->field; 797 int val; 798 799 val = mux->table[index]; 800 return regmap_field_write(field, val); 801 } 802 803 static const struct clk_ops wiz_clk_mux_ops = { 804 .determine_rate = __clk_mux_determine_rate, 805 .set_parent = wiz_clk_mux_set_parent, 806 .get_parent = wiz_clk_mux_get_parent, 807 }; 808 809 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field, 810 const struct wiz_clk_mux_sel *mux_sel, int clk_index) 811 { 812 struct device *dev = wiz->dev; 813 struct clk_init_data *init; 814 const char **parent_names; 815 unsigned int num_parents; 816 struct wiz_clk_mux *mux; 817 char clk_name[100]; 818 struct clk *clk; 819 int ret = 0, i; 820 821 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 822 if (!mux) 823 return -ENOMEM; 824 825 num_parents = mux_sel->num_parents; 826 827 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); 828 if (!parent_names) 829 return -ENOMEM; 830 831 for (i = 0; i < num_parents; i++) { 832 clk = wiz->input_clks[mux_sel->parents[i]]; 833 if (IS_ERR_OR_NULL(clk)) { 834 dev_err(dev, "Failed to get parent clk for %s\n", 835 output_clk_names[clk_index]); 836 ret = -EINVAL; 837 goto err; 838 } 839 parent_names[i] = __clk_get_name(clk); 840 } 841 842 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]); 843 844 init = &mux->clk_data; 845 846 init->ops = &wiz_clk_mux_ops; 847 init->flags = CLK_SET_RATE_NO_REPARENT; 848 init->parent_names = parent_names; 849 init->num_parents = num_parents; 850 init->name = clk_name; 851 852 mux->field = field; 853 mux->table = mux_sel->table; 854 mux->hw.init = init; 855 856 clk = devm_clk_register(dev, &mux->hw); 857 if (IS_ERR(clk)) { 858 ret = PTR_ERR(clk); 859 goto err; 860 } 861 862 wiz->output_clks[clk_index] = clk; 863 864 err: 865 kfree(parent_names); 866 867 return ret; 868 } 869 870 static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node, 871 struct regmap_field *field, const u32 *table) 872 { 873 struct device *dev = wiz->dev; 874 struct clk_init_data *init; 875 const char **parent_names; 876 unsigned int num_parents; 877 struct wiz_clk_mux *mux; 878 char clk_name[100]; 879 struct clk *clk; 880 int ret; 881 882 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 883 if (!mux) 884 return -ENOMEM; 885 886 num_parents = of_clk_get_parent_count(node); 887 if (num_parents < 2) { 888 dev_err(dev, "SERDES clock must have parents\n"); 889 return -EINVAL; 890 } 891 892 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), 893 GFP_KERNEL); 894 if (!parent_names) 895 return -ENOMEM; 896 897 of_clk_parent_fill(node, parent_names, num_parents); 898 899 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 900 node->name); 901 902 init = &mux->clk_data; 903 904 init->ops = &wiz_clk_mux_ops; 905 init->flags = CLK_SET_RATE_NO_REPARENT; 906 init->parent_names = parent_names; 907 init->num_parents = num_parents; 908 init->name = clk_name; 909 910 mux->field = field; 911 mux->table = table; 912 mux->hw.init = init; 913 914 clk = devm_clk_register(dev, &mux->hw); 915 if (IS_ERR(clk)) 916 return PTR_ERR(clk); 917 918 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 919 if (ret) 920 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 921 922 return ret; 923 } 924 925 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw, 926 unsigned long parent_rate) 927 { 928 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 929 struct regmap_field *field = div->field; 930 int val; 931 932 regmap_field_read(field, &val); 933 934 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); 935 } 936 937 static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, 938 unsigned long *prate) 939 { 940 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 941 942 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); 943 } 944 945 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 946 unsigned long parent_rate) 947 { 948 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 949 struct regmap_field *field = div->field; 950 int val; 951 952 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); 953 if (val < 0) 954 return val; 955 956 return regmap_field_write(field, val); 957 } 958 959 static const struct clk_ops wiz_clk_div_ops = { 960 .recalc_rate = wiz_clk_div_recalc_rate, 961 .round_rate = wiz_clk_div_round_rate, 962 .set_rate = wiz_clk_div_set_rate, 963 }; 964 965 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, 966 struct regmap_field *field, 967 const struct clk_div_table *table) 968 { 969 struct device *dev = wiz->dev; 970 struct wiz_clk_divider *div; 971 struct clk_init_data *init; 972 const char **parent_names; 973 char clk_name[100]; 974 struct clk *clk; 975 int ret; 976 977 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 978 if (!div) 979 return -ENOMEM; 980 981 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 982 node->name); 983 984 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 985 if (!parent_names) 986 return -ENOMEM; 987 988 of_clk_parent_fill(node, parent_names, 1); 989 990 init = &div->clk_data; 991 992 init->ops = &wiz_clk_div_ops; 993 init->flags = 0; 994 init->parent_names = parent_names; 995 init->num_parents = 1; 996 init->name = clk_name; 997 998 div->field = field; 999 div->table = table; 1000 div->hw.init = init; 1001 1002 clk = devm_clk_register(dev, &div->hw); 1003 if (IS_ERR(clk)) 1004 return PTR_ERR(clk); 1005 1006 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 1007 if (ret) 1008 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 1009 1010 return ret; 1011 } 1012 1013 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) 1014 { 1015 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1016 struct device *dev = wiz->dev; 1017 struct device_node *clk_node; 1018 int i; 1019 1020 switch (wiz->type) { 1021 case AM64_WIZ_10G: 1022 case J7200_WIZ_10G: 1023 case J784S4_WIZ_10G: 1024 case J721S2_WIZ_10G: 1025 of_clk_del_provider(dev->of_node); 1026 return; 1027 default: 1028 break; 1029 } 1030 1031 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 1032 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name); 1033 of_clk_del_provider(clk_node); 1034 of_node_put(clk_node); 1035 } 1036 1037 for (i = 0; i < wiz->clk_div_sel_num; i++) { 1038 clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name); 1039 of_clk_del_provider(clk_node); 1040 of_node_put(clk_node); 1041 } 1042 1043 of_clk_del_provider(wiz->dev->of_node); 1044 } 1045 1046 static int wiz_clock_register(struct wiz *wiz) 1047 { 1048 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1049 struct device *dev = wiz->dev; 1050 struct device_node *node = dev->of_node; 1051 int clk_index; 1052 int ret; 1053 int i; 1054 1055 clk_index = TI_WIZ_PLL0_REFCLK; 1056 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) { 1057 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index); 1058 if (ret) { 1059 dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]); 1060 return ret; 1061 } 1062 } 1063 1064 ret = wiz_phy_en_refclk_register(wiz); 1065 if (ret) { 1066 dev_err(dev, "Failed to add phy-en-refclk\n"); 1067 return ret; 1068 } 1069 1070 wiz->clk_data.clks = wiz->output_clks; 1071 wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS; 1072 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data); 1073 if (ret) 1074 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 1075 1076 return ret; 1077 } 1078 1079 static int wiz_clock_init(struct wiz *wiz, struct device_node *node) 1080 { 1081 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1082 struct device *dev = wiz->dev; 1083 struct device_node *clk_node; 1084 const char *node_name; 1085 unsigned long rate; 1086 struct clk *clk; 1087 int ret; 1088 int i; 1089 1090 clk = devm_clk_get(dev, "core_ref_clk"); 1091 if (IS_ERR(clk)) { 1092 dev_err(dev, "core_ref_clk clock not found\n"); 1093 ret = PTR_ERR(clk); 1094 return ret; 1095 } 1096 wiz->input_clks[WIZ_CORE_REFCLK] = clk; 1097 1098 rate = clk_get_rate(clk); 1099 if (rate >= 100000000) 1100 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); 1101 else 1102 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); 1103 1104 switch (wiz->type) { 1105 case AM64_WIZ_10G: 1106 case J7200_WIZ_10G: 1107 switch (rate) { 1108 case REF_CLK_100MHZ: 1109 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2); 1110 break; 1111 case REF_CLK_156_25MHZ: 1112 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3); 1113 break; 1114 default: 1115 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0); 1116 break; 1117 } 1118 break; 1119 default: 1120 break; 1121 } 1122 1123 if (wiz->data->pma_cmn_refclk1_int_mode) { 1124 clk = devm_clk_get(dev, "core_ref1_clk"); 1125 if (IS_ERR(clk)) { 1126 dev_err(dev, "core_ref1_clk clock not found\n"); 1127 ret = PTR_ERR(clk); 1128 return ret; 1129 } 1130 wiz->input_clks[WIZ_CORE_REFCLK1] = clk; 1131 1132 rate = clk_get_rate(clk); 1133 if (rate >= 100000000) 1134 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1); 1135 else 1136 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3); 1137 } 1138 1139 clk = devm_clk_get(dev, "ext_ref_clk"); 1140 if (IS_ERR(clk)) { 1141 dev_err(dev, "ext_ref_clk clock not found\n"); 1142 ret = PTR_ERR(clk); 1143 return ret; 1144 } 1145 wiz->input_clks[WIZ_EXT_REFCLK] = clk; 1146 1147 rate = clk_get_rate(clk); 1148 if (rate >= 100000000) 1149 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); 1150 else 1151 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); 1152 1153 switch (wiz->type) { 1154 case AM64_WIZ_10G: 1155 case J7200_WIZ_10G: 1156 case J784S4_WIZ_10G: 1157 case J721S2_WIZ_10G: 1158 ret = wiz_clock_register(wiz); 1159 if (ret) 1160 dev_err(dev, "Failed to register wiz clocks\n"); 1161 return ret; 1162 default: 1163 break; 1164 } 1165 1166 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 1167 node_name = clk_mux_sel[i].node_name; 1168 clk_node = of_get_child_by_name(node, node_name); 1169 if (!clk_node) { 1170 dev_err(dev, "Unable to get %s node\n", node_name); 1171 ret = -EINVAL; 1172 goto err; 1173 } 1174 1175 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i], 1176 clk_mux_sel[i].table); 1177 if (ret) { 1178 dev_err(dev, "Failed to register %s clock\n", 1179 node_name); 1180 of_node_put(clk_node); 1181 goto err; 1182 } 1183 1184 of_node_put(clk_node); 1185 } 1186 1187 for (i = 0; i < wiz->clk_div_sel_num; i++) { 1188 node_name = clk_div_sel[i].node_name; 1189 clk_node = of_get_child_by_name(node, node_name); 1190 if (!clk_node) { 1191 dev_err(dev, "Unable to get %s node\n", node_name); 1192 ret = -EINVAL; 1193 goto err; 1194 } 1195 1196 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i], 1197 clk_div_sel[i].table); 1198 if (ret) { 1199 dev_err(dev, "Failed to register %s clock\n", 1200 node_name); 1201 of_node_put(clk_node); 1202 goto err; 1203 } 1204 1205 of_node_put(clk_node); 1206 } 1207 1208 return 0; 1209 err: 1210 wiz_clock_cleanup(wiz, node); 1211 1212 return ret; 1213 } 1214 1215 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, 1216 unsigned long id) 1217 { 1218 struct device *dev = rcdev->dev; 1219 struct wiz *wiz = dev_get_drvdata(dev); 1220 int ret = 0; 1221 1222 if (id == 0) { 1223 ret = regmap_field_write(wiz->phy_reset_n, false); 1224 return ret; 1225 } 1226 1227 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); 1228 return ret; 1229 } 1230 1231 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) 1232 { 1233 switch (wiz->type) { 1234 case AM64_WIZ_10G: 1235 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) 1236 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); 1237 break; 1238 1239 case J721E_WIZ_16G: 1240 case J721E_WIZ_10G: 1241 case J7200_WIZ_10G: 1242 case J721S2_WIZ_10G: 1243 case J784S4_WIZ_10G: 1244 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII) 1245 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); 1246 break; 1247 default: 1248 return 0; 1249 } 1250 return 0; 1251 } 1252 1253 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, 1254 unsigned long id) 1255 { 1256 struct device *dev = rcdev->dev; 1257 struct wiz *wiz = dev_get_drvdata(dev); 1258 int ret; 1259 1260 if (id == 0) { 1261 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ 1262 if (wiz->gpio_typec_dir) { 1263 if (wiz->typec_dir_delay) 1264 msleep_interruptible(wiz->typec_dir_delay); 1265 1266 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) 1267 regmap_field_write(wiz->typec_ln10_swap, 1); 1268 else 1269 regmap_field_write(wiz->typec_ln10_swap, 0); 1270 } else { 1271 /* if no typec-dir gpio is specified and PHY type is USB3 1272 * with master lane number is '0' or '2', then set LN10 or 1273 * LN23 SWAP bit to '1' respectively. 1274 */ 1275 u32 num_lanes = wiz->num_lanes; 1276 int i; 1277 1278 for (i = 0; i < num_lanes; i++) { 1279 if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) { 1280 switch (wiz->master_lane_num[i]) { 1281 case LANE0: 1282 regmap_field_write(wiz->typec_ln10_swap, 1); 1283 break; 1284 case LANE2: 1285 regmap_field_write(wiz->typec_ln23_swap, 1); 1286 break; 1287 default: 1288 break; 1289 } 1290 } 1291 } 1292 } 1293 } 1294 1295 if (id == 0) { 1296 ret = regmap_field_write(wiz->phy_reset_n, true); 1297 return ret; 1298 } 1299 1300 ret = wiz_phy_fullrt_div(wiz, id - 1); 1301 if (ret) 1302 return ret; 1303 1304 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) 1305 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); 1306 else 1307 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); 1308 1309 return ret; 1310 } 1311 1312 static const struct reset_control_ops wiz_phy_reset_ops = { 1313 .assert = wiz_phy_reset_assert, 1314 .deassert = wiz_phy_reset_deassert, 1315 }; 1316 1317 static const struct regmap_config wiz_regmap_config = { 1318 .reg_bits = 32, 1319 .val_bits = 32, 1320 .reg_stride = 4, 1321 .fast_io = true, 1322 }; 1323 1324 static struct wiz_data j721e_16g_data = { 1325 .type = J721E_WIZ_16G, 1326 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1327 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1328 .refclk_dig_sel = &refclk_dig_sel_16g, 1329 .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div, 1330 .clk_mux_sel = clk_mux_sel_16g, 1331 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G, 1332 }; 1333 1334 static struct wiz_data j721e_10g_data = { 1335 .type = J721E_WIZ_10G, 1336 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1337 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1338 .refclk_dig_sel = &refclk_dig_sel_10g, 1339 .clk_mux_sel = clk_mux_sel_10g, 1340 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1341 }; 1342 1343 static struct wiz_data am64_10g_data = { 1344 .type = AM64_WIZ_10G, 1345 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1346 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1347 .refclk_dig_sel = &refclk_dig_sel_10g, 1348 .clk_mux_sel = clk_mux_sel_10g, 1349 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1350 }; 1351 1352 static struct wiz_data j7200_pg2_10g_data = { 1353 .type = J7200_WIZ_10G, 1354 .pll0_refclk_mux_sel = &sup_pll0_refclk_mux_sel, 1355 .pll1_refclk_mux_sel = &sup_pll1_refclk_mux_sel, 1356 .refclk_dig_sel = &sup_refclk_dig_sel_10g, 1357 .pma_cmn_refclk1_int_mode = &sup_pma_cmn_refclk1_int_mode, 1358 .clk_mux_sel = clk_mux_sel_10g_2_refclk, 1359 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1360 }; 1361 1362 static struct wiz_data j784s4_10g_data = { 1363 .type = J784S4_WIZ_10G, 1364 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2, 1365 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2, 1366 .refclk_dig_sel = &refclk_dig_sel_16g, 1367 .pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode, 1368 .clk_mux_sel = clk_mux_sel_10g_2_refclk, 1369 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1370 }; 1371 1372 static struct wiz_data j721s2_10g_data = { 1373 .type = J721S2_WIZ_10G, 1374 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1375 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1376 .refclk_dig_sel = &refclk_dig_sel_10g, 1377 .clk_mux_sel = clk_mux_sel_10g, 1378 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1379 }; 1380 1381 static const struct of_device_id wiz_id_table[] = { 1382 { 1383 .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data, 1384 }, 1385 { 1386 .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data, 1387 }, 1388 { 1389 .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data, 1390 }, 1391 { 1392 .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data, 1393 }, 1394 { 1395 .compatible = "ti,j784s4-wiz-10g", .data = &j784s4_10g_data, 1396 }, 1397 { 1398 .compatible = "ti,j721s2-wiz-10g", .data = &j721s2_10g_data, 1399 }, 1400 {} 1401 }; 1402 MODULE_DEVICE_TABLE(of, wiz_id_table); 1403 1404 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) 1405 { 1406 struct device_node *serdes, *subnode; 1407 1408 serdes = of_get_child_by_name(dev->of_node, "serdes"); 1409 if (!serdes) { 1410 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__); 1411 return -EINVAL; 1412 } 1413 1414 for_each_child_of_node(serdes, subnode) { 1415 u32 reg, num_lanes = 1, phy_type = PHY_NONE; 1416 int ret, i; 1417 1418 if (!(of_node_name_eq(subnode, "phy") || 1419 of_node_name_eq(subnode, "link"))) 1420 continue; 1421 1422 ret = of_property_read_u32(subnode, "reg", ®); 1423 if (ret) { 1424 of_node_put(subnode); 1425 dev_err(dev, 1426 "%s: Reading \"reg\" from \"%s\" failed: %d\n", 1427 __func__, subnode->name, ret); 1428 return ret; 1429 } 1430 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); 1431 of_property_read_u32(subnode, "cdns,phy-type", &phy_type); 1432 1433 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, 1434 reg, reg + num_lanes - 1, phy_type); 1435 1436 for (i = reg; i < reg + num_lanes; i++) { 1437 wiz->master_lane_num[i] = reg; 1438 wiz->lane_phy_type[i] = phy_type; 1439 } 1440 } 1441 1442 return 0; 1443 } 1444 1445 static int wiz_probe(struct platform_device *pdev) 1446 { 1447 struct reset_controller_dev *phy_reset_dev; 1448 struct device *dev = &pdev->dev; 1449 struct device_node *node = dev->of_node; 1450 struct platform_device *serdes_pdev; 1451 bool already_configured = false; 1452 struct device_node *child_node; 1453 struct regmap *regmap; 1454 struct resource res; 1455 void __iomem *base; 1456 struct wiz *wiz; 1457 int ret, val, i; 1458 u32 num_lanes; 1459 const struct wiz_data *data; 1460 1461 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); 1462 if (!wiz) 1463 return -ENOMEM; 1464 1465 data = of_device_get_match_data(dev); 1466 if (!data) { 1467 dev_err(dev, "NULL device data\n"); 1468 return -EINVAL; 1469 } 1470 1471 wiz->data = data; 1472 wiz->type = data->type; 1473 1474 child_node = of_get_child_by_name(node, "serdes"); 1475 if (!child_node) { 1476 dev_err(dev, "Failed to get SERDES child DT node\n"); 1477 return -ENODEV; 1478 } 1479 1480 ret = of_address_to_resource(child_node, 0, &res); 1481 if (ret) { 1482 dev_err(dev, "Failed to get memory resource\n"); 1483 goto err_addr_to_resource; 1484 } 1485 1486 base = devm_ioremap(dev, res.start, resource_size(&res)); 1487 if (!base) { 1488 ret = -ENOMEM; 1489 goto err_addr_to_resource; 1490 } 1491 1492 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config); 1493 if (IS_ERR(regmap)) { 1494 dev_err(dev, "Failed to initialize regmap\n"); 1495 ret = PTR_ERR(regmap); 1496 goto err_addr_to_resource; 1497 } 1498 1499 wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm"); 1500 if (IS_ERR(wiz->scm_regmap)) { 1501 if (wiz->type == J7200_WIZ_10G) { 1502 dev_err(dev, "Couldn't get ti,scm regmap\n"); 1503 ret = -ENODEV; 1504 goto err_addr_to_resource; 1505 } 1506 1507 wiz->scm_regmap = NULL; 1508 } 1509 1510 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 1511 if (ret) { 1512 dev_err(dev, "Failed to read num-lanes property\n"); 1513 goto err_addr_to_resource; 1514 } 1515 1516 if (num_lanes > WIZ_MAX_LANES) { 1517 dev_err(dev, "Cannot support %d lanes\n", num_lanes); 1518 ret = -ENODEV; 1519 goto err_addr_to_resource; 1520 } 1521 1522 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", 1523 GPIOD_IN); 1524 if (IS_ERR(wiz->gpio_typec_dir)) { 1525 ret = PTR_ERR(wiz->gpio_typec_dir); 1526 if (ret != -EPROBE_DEFER) 1527 dev_err(dev, "Failed to request typec-dir gpio: %d\n", 1528 ret); 1529 goto err_addr_to_resource; 1530 } 1531 1532 if (wiz->gpio_typec_dir) { 1533 ret = of_property_read_u32(node, "typec-dir-debounce-ms", 1534 &wiz->typec_dir_delay); 1535 if (ret && ret != -EINVAL) { 1536 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1537 goto err_addr_to_resource; 1538 } 1539 1540 /* use min. debounce from Type-C spec if not provided in DT */ 1541 if (ret == -EINVAL) 1542 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; 1543 1544 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || 1545 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { 1546 ret = -EINVAL; 1547 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1548 goto err_addr_to_resource; 1549 } 1550 } 1551 1552 ret = wiz_get_lane_phy_types(dev, wiz); 1553 if (ret) 1554 goto err_addr_to_resource; 1555 1556 wiz->dev = dev; 1557 wiz->regmap = regmap; 1558 wiz->num_lanes = num_lanes; 1559 wiz->clk_mux_sel = data->clk_mux_sel; 1560 wiz->clk_div_sel = clk_div_sel; 1561 wiz->clk_div_sel_num = data->clk_div_sel_num; 1562 1563 platform_set_drvdata(pdev, wiz); 1564 1565 ret = wiz_regfield_init(wiz); 1566 if (ret) { 1567 dev_err(dev, "Failed to initialize regfields\n"); 1568 goto err_addr_to_resource; 1569 } 1570 1571 /* Enable supplemental Control override if available */ 1572 if (wiz->scm_regmap) 1573 regmap_field_write(wiz->sup_legacy_clk_override, 1); 1574 1575 phy_reset_dev = &wiz->wiz_phy_reset_dev; 1576 phy_reset_dev->dev = dev; 1577 phy_reset_dev->ops = &wiz_phy_reset_ops, 1578 phy_reset_dev->owner = THIS_MODULE, 1579 phy_reset_dev->of_node = node; 1580 /* Reset for each of the lane and one for the entire SERDES */ 1581 phy_reset_dev->nr_resets = num_lanes + 1; 1582 1583 ret = devm_reset_controller_register(dev, phy_reset_dev); 1584 if (ret < 0) { 1585 dev_warn(dev, "Failed to register reset controller\n"); 1586 goto err_addr_to_resource; 1587 } 1588 1589 pm_runtime_enable(dev); 1590 ret = pm_runtime_get_sync(dev); 1591 if (ret < 0) { 1592 dev_err(dev, "pm_runtime_get_sync failed\n"); 1593 goto err_get_sync; 1594 } 1595 1596 ret = wiz_clock_init(wiz, node); 1597 if (ret < 0) { 1598 dev_warn(dev, "Failed to initialize clocks\n"); 1599 goto err_get_sync; 1600 } 1601 1602 for (i = 0; i < wiz->num_lanes; i++) { 1603 regmap_field_read(wiz->p_enable[i], &val); 1604 if (val & (P_ENABLE | P_ENABLE_FORCE)) { 1605 already_configured = true; 1606 break; 1607 } 1608 } 1609 1610 if (!already_configured) { 1611 ret = wiz_init(wiz); 1612 if (ret) { 1613 dev_err(dev, "WIZ initialization failed\n"); 1614 goto err_wiz_init; 1615 } 1616 } 1617 1618 serdes_pdev = of_platform_device_create(child_node, NULL, dev); 1619 if (!serdes_pdev) { 1620 dev_WARN(dev, "Unable to create SERDES platform device\n"); 1621 ret = -ENOMEM; 1622 goto err_wiz_init; 1623 } 1624 wiz->serdes_pdev = serdes_pdev; 1625 1626 of_node_put(child_node); 1627 return 0; 1628 1629 err_wiz_init: 1630 wiz_clock_cleanup(wiz, node); 1631 1632 err_get_sync: 1633 pm_runtime_put(dev); 1634 pm_runtime_disable(dev); 1635 1636 err_addr_to_resource: 1637 of_node_put(child_node); 1638 1639 return ret; 1640 } 1641 1642 static void wiz_remove(struct platform_device *pdev) 1643 { 1644 struct device *dev = &pdev->dev; 1645 struct device_node *node = dev->of_node; 1646 struct platform_device *serdes_pdev; 1647 struct wiz *wiz; 1648 1649 wiz = dev_get_drvdata(dev); 1650 serdes_pdev = wiz->serdes_pdev; 1651 1652 of_platform_device_destroy(&serdes_pdev->dev, NULL); 1653 wiz_clock_cleanup(wiz, node); 1654 pm_runtime_put(dev); 1655 pm_runtime_disable(dev); 1656 } 1657 1658 static struct platform_driver wiz_driver = { 1659 .probe = wiz_probe, 1660 .remove_new = wiz_remove, 1661 .driver = { 1662 .name = "wiz", 1663 .of_match_table = wiz_id_table, 1664 }, 1665 }; 1666 module_platform_driver(wiz_driver); 1667 1668 MODULE_AUTHOR("Texas Instruments Inc."); 1669 MODULE_DESCRIPTION("TI J721E WIZ driver"); 1670 MODULE_LICENSE("GPL v2"); 1671