12242ddfbSManivannan Sadhasivam // SPDX-License-Identifier: GPL-2.0+ 22242ddfbSManivannan Sadhasivam /* 32242ddfbSManivannan Sadhasivam * OWL SoC's Pinctrl definitions 42242ddfbSManivannan Sadhasivam * 52242ddfbSManivannan Sadhasivam * Copyright (c) 2014 Actions Semi Inc. 62242ddfbSManivannan Sadhasivam * Author: David Liu <liuwei@actions-semi.com> 72242ddfbSManivannan Sadhasivam * 82242ddfbSManivannan Sadhasivam * Copyright (c) 2018 Linaro Ltd. 92242ddfbSManivannan Sadhasivam * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 102242ddfbSManivannan Sadhasivam */ 112242ddfbSManivannan Sadhasivam 122242ddfbSManivannan Sadhasivam #ifndef __PINCTRL_OWL_H__ 132242ddfbSManivannan Sadhasivam #define __PINCTRL_OWL_H__ 142242ddfbSManivannan Sadhasivam 152242ddfbSManivannan Sadhasivam #define OWL_PINCONF_SLEW_SLOW 0 162242ddfbSManivannan Sadhasivam #define OWL_PINCONF_SLEW_FAST 1 172242ddfbSManivannan Sadhasivam 180a98bf52SSaravanan Sekar #define MUX_PG(group_name, reg, shift, width) \ 190a98bf52SSaravanan Sekar { \ 200a98bf52SSaravanan Sekar .name = #group_name, \ 210a98bf52SSaravanan Sekar .pads = group_name##_pads, \ 220a98bf52SSaravanan Sekar .npads = ARRAY_SIZE(group_name##_pads), \ 230a98bf52SSaravanan Sekar .funcs = group_name##_funcs, \ 240a98bf52SSaravanan Sekar .nfuncs = ARRAY_SIZE(group_name##_funcs), \ 250a98bf52SSaravanan Sekar .mfpctl_reg = MFCTL##reg, \ 260a98bf52SSaravanan Sekar .mfpctl_shift = shift, \ 270a98bf52SSaravanan Sekar .mfpctl_width = width, \ 280a98bf52SSaravanan Sekar .drv_reg = -1, \ 290a98bf52SSaravanan Sekar .drv_shift = -1, \ 300a98bf52SSaravanan Sekar .drv_width = -1, \ 310a98bf52SSaravanan Sekar .sr_reg = -1, \ 320a98bf52SSaravanan Sekar .sr_shift = -1, \ 330a98bf52SSaravanan Sekar .sr_width = -1, \ 340a98bf52SSaravanan Sekar } 350a98bf52SSaravanan Sekar 360a98bf52SSaravanan Sekar #define DRV_PG(group_name, reg, shift, width) \ 370a98bf52SSaravanan Sekar { \ 380a98bf52SSaravanan Sekar .name = #group_name, \ 390a98bf52SSaravanan Sekar .pads = group_name##_pads, \ 400a98bf52SSaravanan Sekar .npads = ARRAY_SIZE(group_name##_pads), \ 410a98bf52SSaravanan Sekar .mfpctl_reg = -1, \ 420a98bf52SSaravanan Sekar .mfpctl_shift = -1, \ 430a98bf52SSaravanan Sekar .mfpctl_width = -1, \ 440a98bf52SSaravanan Sekar .drv_reg = PAD_DRV##reg, \ 450a98bf52SSaravanan Sekar .drv_shift = shift, \ 460a98bf52SSaravanan Sekar .drv_width = width, \ 470a98bf52SSaravanan Sekar .sr_reg = -1, \ 480a98bf52SSaravanan Sekar .sr_shift = -1, \ 490a98bf52SSaravanan Sekar .sr_width = -1, \ 500a98bf52SSaravanan Sekar } 510a98bf52SSaravanan Sekar 520a98bf52SSaravanan Sekar #define SR_PG(group_name, reg, shift, width) \ 530a98bf52SSaravanan Sekar { \ 540a98bf52SSaravanan Sekar .name = #group_name, \ 550a98bf52SSaravanan Sekar .pads = group_name##_pads, \ 560a98bf52SSaravanan Sekar .npads = ARRAY_SIZE(group_name##_pads), \ 570a98bf52SSaravanan Sekar .mfpctl_reg = -1, \ 580a98bf52SSaravanan Sekar .mfpctl_shift = -1, \ 590a98bf52SSaravanan Sekar .mfpctl_width = -1, \ 600a98bf52SSaravanan Sekar .drv_reg = -1, \ 610a98bf52SSaravanan Sekar .drv_shift = -1, \ 620a98bf52SSaravanan Sekar .drv_width = -1, \ 630a98bf52SSaravanan Sekar .sr_reg = PAD_SR##reg, \ 640a98bf52SSaravanan Sekar .sr_shift = shift, \ 650a98bf52SSaravanan Sekar .sr_width = width, \ 660a98bf52SSaravanan Sekar } 670a98bf52SSaravanan Sekar 680a98bf52SSaravanan Sekar #define FUNCTION(fname) \ 690a98bf52SSaravanan Sekar { \ 700a98bf52SSaravanan Sekar .name = #fname, \ 710a98bf52SSaravanan Sekar .groups = fname##_groups, \ 720a98bf52SSaravanan Sekar .ngroups = ARRAY_SIZE(fname##_groups), \ 730a98bf52SSaravanan Sekar } 740a98bf52SSaravanan Sekar 750a98bf52SSaravanan Sekar /* PAD PULL UP/DOWN CONFIGURES */ 760a98bf52SSaravanan Sekar #define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \ 770a98bf52SSaravanan Sekar { \ 780a98bf52SSaravanan Sekar .reg = PAD_PULLCTL##pull_reg, \ 790a98bf52SSaravanan Sekar .shift = pull_sft, \ 800a98bf52SSaravanan Sekar .width = pull_wdt, \ 810a98bf52SSaravanan Sekar } 820a98bf52SSaravanan Sekar 830a98bf52SSaravanan Sekar #define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \ 840a98bf52SSaravanan Sekar struct owl_pullctl pad_name##_pullctl_conf \ 850a98bf52SSaravanan Sekar = PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) 860a98bf52SSaravanan Sekar 870a98bf52SSaravanan Sekar #define ST_CONF(st_reg, st_sft, st_wdt) \ 880a98bf52SSaravanan Sekar { \ 890a98bf52SSaravanan Sekar .reg = PAD_ST##st_reg, \ 900a98bf52SSaravanan Sekar .shift = st_sft, \ 910a98bf52SSaravanan Sekar .width = st_wdt, \ 920a98bf52SSaravanan Sekar } 930a98bf52SSaravanan Sekar 940a98bf52SSaravanan Sekar #define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \ 950a98bf52SSaravanan Sekar struct owl_st pad_name##_st_conf \ 960a98bf52SSaravanan Sekar = ST_CONF(st_reg, st_sft, st_wdt) 970a98bf52SSaravanan Sekar 980a98bf52SSaravanan Sekar #define PAD_INFO(name) \ 990a98bf52SSaravanan Sekar { \ 1000a98bf52SSaravanan Sekar .pad = name, \ 1010a98bf52SSaravanan Sekar .pullctl = NULL, \ 1020a98bf52SSaravanan Sekar .st = NULL, \ 1030a98bf52SSaravanan Sekar } 1040a98bf52SSaravanan Sekar 1050a98bf52SSaravanan Sekar #define PAD_INFO_ST(name) \ 1060a98bf52SSaravanan Sekar { \ 1070a98bf52SSaravanan Sekar .pad = name, \ 1080a98bf52SSaravanan Sekar .pullctl = NULL, \ 1090a98bf52SSaravanan Sekar .st = &name##_st_conf, \ 1100a98bf52SSaravanan Sekar } 1110a98bf52SSaravanan Sekar 1120a98bf52SSaravanan Sekar #define PAD_INFO_PULLCTL(name) \ 1130a98bf52SSaravanan Sekar { \ 1140a98bf52SSaravanan Sekar .pad = name, \ 1150a98bf52SSaravanan Sekar .pullctl = &name##_pullctl_conf, \ 1160a98bf52SSaravanan Sekar .st = NULL, \ 1170a98bf52SSaravanan Sekar } 1180a98bf52SSaravanan Sekar 1190a98bf52SSaravanan Sekar #define PAD_INFO_PULLCTL_ST(name) \ 1200a98bf52SSaravanan Sekar { \ 1210a98bf52SSaravanan Sekar .pad = name, \ 1220a98bf52SSaravanan Sekar .pullctl = &name##_pullctl_conf, \ 1230a98bf52SSaravanan Sekar .st = &name##_st_conf, \ 1240a98bf52SSaravanan Sekar } 1250a98bf52SSaravanan Sekar 1260a98bf52SSaravanan Sekar #define OWL_GPIO_PORT_A 0 1270a98bf52SSaravanan Sekar #define OWL_GPIO_PORT_B 1 1280a98bf52SSaravanan Sekar #define OWL_GPIO_PORT_C 2 1290a98bf52SSaravanan Sekar #define OWL_GPIO_PORT_D 3 1300a98bf52SSaravanan Sekar #define OWL_GPIO_PORT_E 4 1310a98bf52SSaravanan Sekar #define OWL_GPIO_PORT_F 5 1320a98bf52SSaravanan Sekar 1330a98bf52SSaravanan Sekar #define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, _intc_ctl,\ 1340a98bf52SSaravanan Sekar _intc_pd, _intc_msk, _intc_type, _share) \ 1350a98bf52SSaravanan Sekar [OWL_GPIO_PORT_##port] = { \ 1360a98bf52SSaravanan Sekar .offset = base, \ 1370a98bf52SSaravanan Sekar .pins = count, \ 1380a98bf52SSaravanan Sekar .outen = _outen, \ 1390a98bf52SSaravanan Sekar .inen = _inen, \ 1400a98bf52SSaravanan Sekar .dat = _dat, \ 1410a98bf52SSaravanan Sekar .intc_ctl = _intc_ctl, \ 1420a98bf52SSaravanan Sekar .intc_pd = _intc_pd, \ 1430a98bf52SSaravanan Sekar .intc_msk = _intc_msk, \ 1440a98bf52SSaravanan Sekar .intc_type = _intc_type, \ 1450a98bf52SSaravanan Sekar .shared_ctl_offset = _share, \ 1460a98bf52SSaravanan Sekar } 1470a98bf52SSaravanan Sekar 1482242ddfbSManivannan Sadhasivam enum owl_pinconf_drv { 1492242ddfbSManivannan Sadhasivam OWL_PINCONF_DRV_2MA, 1502242ddfbSManivannan Sadhasivam OWL_PINCONF_DRV_4MA, 1512242ddfbSManivannan Sadhasivam OWL_PINCONF_DRV_8MA, 1522242ddfbSManivannan Sadhasivam OWL_PINCONF_DRV_12MA, 1532242ddfbSManivannan Sadhasivam }; 1542242ddfbSManivannan Sadhasivam 1556c5d0736SManivannan Sadhasivam /* GPIO CTRL Bit Definition */ 1566c5d0736SManivannan Sadhasivam #define OWL_GPIO_CTLR_PENDING 0 1576c5d0736SManivannan Sadhasivam #define OWL_GPIO_CTLR_ENABLE 1 1586c5d0736SManivannan Sadhasivam #define OWL_GPIO_CTLR_SAMPLE_CLK_24M 2 1596c5d0736SManivannan Sadhasivam 1606c5d0736SManivannan Sadhasivam /* GPIO TYPE Bit Definition */ 1616c5d0736SManivannan Sadhasivam #define OWL_GPIO_INT_LEVEL_HIGH 0 1626c5d0736SManivannan Sadhasivam #define OWL_GPIO_INT_LEVEL_LOW 1 1636c5d0736SManivannan Sadhasivam #define OWL_GPIO_INT_EDGE_RISING 2 1646c5d0736SManivannan Sadhasivam #define OWL_GPIO_INT_EDGE_FALLING 3 1656c5d0736SManivannan Sadhasivam #define OWL_GPIO_INT_MASK 3 1666c5d0736SManivannan Sadhasivam 1672242ddfbSManivannan Sadhasivam /** 1682242ddfbSManivannan Sadhasivam * struct owl_pullctl - Actions pad pull control register 1692242ddfbSManivannan Sadhasivam * @reg: offset to the pull control register 1702242ddfbSManivannan Sadhasivam * @shift: shift value of the register 1712242ddfbSManivannan Sadhasivam * @width: width of the register 1722242ddfbSManivannan Sadhasivam */ 1732242ddfbSManivannan Sadhasivam struct owl_pullctl { 1742242ddfbSManivannan Sadhasivam int reg; 1752242ddfbSManivannan Sadhasivam unsigned int shift; 1762242ddfbSManivannan Sadhasivam unsigned int width; 1772242ddfbSManivannan Sadhasivam }; 1782242ddfbSManivannan Sadhasivam 1792242ddfbSManivannan Sadhasivam /** 1802242ddfbSManivannan Sadhasivam * struct owl_st - Actions pad schmitt trigger enable register 1812242ddfbSManivannan Sadhasivam * @reg: offset to the schmitt trigger enable register 1822242ddfbSManivannan Sadhasivam * @shift: shift value of the register 1832242ddfbSManivannan Sadhasivam * @width: width of the register 1842242ddfbSManivannan Sadhasivam */ 1852242ddfbSManivannan Sadhasivam struct owl_st { 1862242ddfbSManivannan Sadhasivam int reg; 1872242ddfbSManivannan Sadhasivam unsigned int shift; 1882242ddfbSManivannan Sadhasivam unsigned int width; 1892242ddfbSManivannan Sadhasivam }; 1902242ddfbSManivannan Sadhasivam 1912242ddfbSManivannan Sadhasivam /** 1922242ddfbSManivannan Sadhasivam * struct owl_pingroup - Actions pingroup definition 1932242ddfbSManivannan Sadhasivam * @name: name of the pin group 1942242ddfbSManivannan Sadhasivam * @pads: list of pins assigned to this pingroup 1952242ddfbSManivannan Sadhasivam * @npads: size of @pads array 1962242ddfbSManivannan Sadhasivam * @funcs: list of pinmux functions for this pingroup 1972242ddfbSManivannan Sadhasivam * @nfuncs: size of @funcs array 1982242ddfbSManivannan Sadhasivam * @mfpctl_reg: multiplexing control register offset 1992242ddfbSManivannan Sadhasivam * @mfpctl_shift: multiplexing control register bit mask 2002242ddfbSManivannan Sadhasivam * @mfpctl_width: multiplexing control register width 2012242ddfbSManivannan Sadhasivam * @drv_reg: drive control register offset 2022242ddfbSManivannan Sadhasivam * @drv_shift: drive control register bit mask 2032242ddfbSManivannan Sadhasivam * @drv_width: driver control register width 2042242ddfbSManivannan Sadhasivam * @sr_reg: slew rate control register offset 2052242ddfbSManivannan Sadhasivam * @sr_shift: slew rate control register bit mask 2062242ddfbSManivannan Sadhasivam * @sr_width: slew rate control register width 2072242ddfbSManivannan Sadhasivam */ 2082242ddfbSManivannan Sadhasivam struct owl_pingroup { 2092242ddfbSManivannan Sadhasivam const char *name; 2102242ddfbSManivannan Sadhasivam unsigned int *pads; 2112242ddfbSManivannan Sadhasivam unsigned int npads; 2122242ddfbSManivannan Sadhasivam unsigned int *funcs; 2132242ddfbSManivannan Sadhasivam unsigned int nfuncs; 2142242ddfbSManivannan Sadhasivam 2152242ddfbSManivannan Sadhasivam int mfpctl_reg; 2162242ddfbSManivannan Sadhasivam unsigned int mfpctl_shift; 2172242ddfbSManivannan Sadhasivam unsigned int mfpctl_width; 2182242ddfbSManivannan Sadhasivam 2192242ddfbSManivannan Sadhasivam int drv_reg; 2202242ddfbSManivannan Sadhasivam unsigned int drv_shift; 2212242ddfbSManivannan Sadhasivam unsigned int drv_width; 2222242ddfbSManivannan Sadhasivam 2232242ddfbSManivannan Sadhasivam int sr_reg; 2242242ddfbSManivannan Sadhasivam unsigned int sr_shift; 2252242ddfbSManivannan Sadhasivam unsigned int sr_width; 2262242ddfbSManivannan Sadhasivam }; 2272242ddfbSManivannan Sadhasivam 2282242ddfbSManivannan Sadhasivam /** 2292242ddfbSManivannan Sadhasivam * struct owl_padinfo - Actions pinctrl pad info 2302242ddfbSManivannan Sadhasivam * @pad: pad name of the SoC 2312242ddfbSManivannan Sadhasivam * @pullctl: pull control register info 2322242ddfbSManivannan Sadhasivam * @st: schmitt trigger register info 2332242ddfbSManivannan Sadhasivam */ 2342242ddfbSManivannan Sadhasivam struct owl_padinfo { 2352242ddfbSManivannan Sadhasivam int pad; 2362242ddfbSManivannan Sadhasivam struct owl_pullctl *pullctl; 2372242ddfbSManivannan Sadhasivam struct owl_st *st; 2382242ddfbSManivannan Sadhasivam }; 2392242ddfbSManivannan Sadhasivam 2402242ddfbSManivannan Sadhasivam /** 2412242ddfbSManivannan Sadhasivam * struct owl_pinmux_func - Actions pinctrl mux functions 2422242ddfbSManivannan Sadhasivam * @name: name of the pinmux function. 2432242ddfbSManivannan Sadhasivam * @groups: array of pin groups that may select this function. 2442242ddfbSManivannan Sadhasivam * @ngroups: number of entries in @groups. 2452242ddfbSManivannan Sadhasivam */ 2462242ddfbSManivannan Sadhasivam struct owl_pinmux_func { 2472242ddfbSManivannan Sadhasivam const char *name; 2482242ddfbSManivannan Sadhasivam const char * const *groups; 2492242ddfbSManivannan Sadhasivam unsigned int ngroups; 2502242ddfbSManivannan Sadhasivam }; 2512242ddfbSManivannan Sadhasivam 2522242ddfbSManivannan Sadhasivam /** 25333257f86SManivannan Sadhasivam * struct owl_gpio_port - Actions GPIO port info 25433257f86SManivannan Sadhasivam * @offset: offset of the GPIO port. 25533257f86SManivannan Sadhasivam * @pins: number of pins belongs to the GPIO port. 25633257f86SManivannan Sadhasivam * @outen: offset of the output enable register. 25733257f86SManivannan Sadhasivam * @inen: offset of the input enable register. 25833257f86SManivannan Sadhasivam * @dat: offset of the data register. 2596c5d0736SManivannan Sadhasivam * @intc_ctl: offset of the interrupt control register. 2606c5d0736SManivannan Sadhasivam * @intc_pd: offset of the interrupt pending register. 2616c5d0736SManivannan Sadhasivam * @intc_msk: offset of the interrupt mask register. 2626c5d0736SManivannan Sadhasivam * @intc_type: offset of the interrupt type register. 26333257f86SManivannan Sadhasivam */ 26433257f86SManivannan Sadhasivam struct owl_gpio_port { 26533257f86SManivannan Sadhasivam unsigned int offset; 26633257f86SManivannan Sadhasivam unsigned int pins; 26733257f86SManivannan Sadhasivam unsigned int outen; 26833257f86SManivannan Sadhasivam unsigned int inen; 26933257f86SManivannan Sadhasivam unsigned int dat; 2706c5d0736SManivannan Sadhasivam unsigned int intc_ctl; 2716c5d0736SManivannan Sadhasivam unsigned int intc_pd; 2726c5d0736SManivannan Sadhasivam unsigned int intc_msk; 2736c5d0736SManivannan Sadhasivam unsigned int intc_type; 2740a98bf52SSaravanan Sekar u8 shared_ctl_offset; 27533257f86SManivannan Sadhasivam }; 27633257f86SManivannan Sadhasivam 27733257f86SManivannan Sadhasivam /** 2782242ddfbSManivannan Sadhasivam * struct owl_pinctrl_soc_data - Actions pin controller driver configuration 2792242ddfbSManivannan Sadhasivam * @pins: array describing all pins of the pin controller. 2802242ddfbSManivannan Sadhasivam * @npins: number of entries in @pins. 2812242ddfbSManivannan Sadhasivam * @functions: array describing all mux functions of this SoC. 2822242ddfbSManivannan Sadhasivam * @nfunction: number of entries in @functions. 2832242ddfbSManivannan Sadhasivam * @groups: array describing all pin groups of this SoC. 2842242ddfbSManivannan Sadhasivam * @ngroups: number of entries in @groups. 2852242ddfbSManivannan Sadhasivam * @padinfo: array describing the pad info of this SoC. 2862242ddfbSManivannan Sadhasivam * @ngpios: number of pingroups the driver should expose as GPIOs. 2876c5d0736SManivannan Sadhasivam * @ports: array describing all GPIO ports of this SoC. 28833257f86SManivannan Sadhasivam * @nports: number of GPIO ports in this SoC. 2892242ddfbSManivannan Sadhasivam */ 2902242ddfbSManivannan Sadhasivam struct owl_pinctrl_soc_data { 2912242ddfbSManivannan Sadhasivam const struct pinctrl_pin_desc *pins; 2922242ddfbSManivannan Sadhasivam unsigned int npins; 2932242ddfbSManivannan Sadhasivam const struct owl_pinmux_func *functions; 2942242ddfbSManivannan Sadhasivam unsigned int nfunctions; 2952242ddfbSManivannan Sadhasivam const struct owl_pingroup *groups; 2962242ddfbSManivannan Sadhasivam unsigned int ngroups; 2972242ddfbSManivannan Sadhasivam const struct owl_padinfo *padinfo; 2982242ddfbSManivannan Sadhasivam unsigned int ngpios; 29933257f86SManivannan Sadhasivam const struct owl_gpio_port *ports; 30033257f86SManivannan Sadhasivam unsigned int nports; 301*f3f7af95SSaravanan Sekar int (*padctl_val2arg)(const struct owl_padinfo *padinfo, 302*f3f7af95SSaravanan Sekar unsigned int param, 303*f3f7af95SSaravanan Sekar u32 *arg); 304*f3f7af95SSaravanan Sekar int (*padctl_arg2val)(const struct owl_padinfo *info, 305*f3f7af95SSaravanan Sekar unsigned int param, 306*f3f7af95SSaravanan Sekar u32 *arg); 3072242ddfbSManivannan Sadhasivam }; 3082242ddfbSManivannan Sadhasivam 3092242ddfbSManivannan Sadhasivam int owl_pinctrl_probe(struct platform_device *pdev, 3102242ddfbSManivannan Sadhasivam struct owl_pinctrl_soc_data *soc_data); 3112242ddfbSManivannan Sadhasivam 3122242ddfbSManivannan Sadhasivam #endif /* __PINCTRL_OWL_H__ */ 313