1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 IBM Corp. 4 */ 5 #include <linux/bitops.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/mutex.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/pinctrl/pinctrl.h> 13 #include <linux/pinctrl/pinmux.h> 14 #include <linux/pinctrl/pinconf.h> 15 #include <linux/pinctrl/pinconf-generic.h> 16 #include <linux/string.h> 17 #include <linux/types.h> 18 19 #include "../core.h" 20 #include "../pinctrl-utils.h" 21 #include "pinmux-aspeed.h" 22 #include "pinctrl-aspeed.h" 23 24 /* 25 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet 26 * references registers by the device/offset mnemonic. The register macros 27 * below are named the same way to ease transcription and verification (as 28 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions 29 * reference registers beyond those dedicated to pinmux, such as the system 30 * reset control and MAC clock configuration registers. 31 */ 32 #define SCU2C 0x2C /* Misc. Control Register */ 33 #define SCU3C 0x3C /* System Reset Control/Status Register */ 34 #define SCU48 0x48 /* MAC Interface Clock Delay Setting */ 35 #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */ 36 #define HW_REVISION_ID 0x7C /* Silicon revision ID register */ 37 #define SCU80 0x80 /* Multi-function Pin Control #1 */ 38 #define SCU84 0x84 /* Multi-function Pin Control #2 */ 39 #define SCU88 0x88 /* Multi-function Pin Control #3 */ 40 #define SCU8C 0x8C /* Multi-function Pin Control #4 */ 41 #define SCU90 0x90 /* Multi-function Pin Control #5 */ 42 #define SCU94 0x94 /* Multi-function Pin Control #6 */ 43 #define SCUA0 0xA0 /* Multi-function Pin Control #7 */ 44 #define SCUA4 0xA4 /* Multi-function Pin Control #8 */ 45 #define SCUA8 0xA8 /* Multi-function Pin Control #9 */ 46 #define SCUAC 0xAC /* Multi-function Pin Control #10 */ 47 #define HW_STRAP2 0xD0 /* Strapping */ 48 49 /* 50 * Uses undefined macros for symbol naming and references, eg GPIOA0, MAC1LINK, 51 * TIMER3 etc. 52 * 53 * Pins are defined in GPIO bank order: 54 * 55 * GPIOA0: 0 56 * ... 57 * GPIOA7: 7 58 * GPIOB0: 8 59 * ... 60 * GPIOZ7: 207 61 * GPIOAA0: 208 62 * ... 63 * GPIOAB3: 219 64 * 65 * Not all pins have their signals defined (yet). 66 */ 67 68 #define D6 0 69 SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); 70 71 #define B5 1 72 SSSF_PIN_DECL(B5, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1)); 73 74 #define A4 2 75 SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2)); 76 77 #define E6 3 78 SSSF_PIN_DECL(E6, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); 79 80 #define I2C9_DESC SIG_DESC_SET(SCU90, 22) 81 82 #define C5 4 83 SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC); 84 SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4)); 85 MS_PIN_DECL(C5, GPIOA4, SCL9, TIMER5); 86 87 FUNC_GROUP_DECL(TIMER5, C5); 88 89 #define B4 5 90 SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC); 91 SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5)); 92 MS_PIN_DECL(B4, GPIOA5, SDA9, TIMER6); 93 94 FUNC_GROUP_DECL(TIMER6, B4); 95 FUNC_GROUP_DECL(I2C9, C5, B4); 96 97 #define MDIO2_DESC SIG_DESC_SET(SCU90, 2) 98 99 #define A3 6 100 SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC); 101 SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6)); 102 MS_PIN_DECL(A3, GPIOA6, MDC2, TIMER7); 103 104 FUNC_GROUP_DECL(TIMER7, A3); 105 106 #define D5 7 107 SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC); 108 SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7)); 109 MS_PIN_DECL(D5, GPIOA7, MDIO2, TIMER8); 110 111 FUNC_GROUP_DECL(TIMER8, D5); 112 FUNC_GROUP_DECL(MDIO2, A3, D5); 113 114 #define J21 8 115 SSSF_PIN_DECL(J21, GPIOB0, SALT1, SIG_DESC_SET(SCU80, 8)); 116 117 #define J20 9 118 SSSF_PIN_DECL(J20, GPIOB1, SALT2, SIG_DESC_SET(SCU80, 9)); 119 120 #define H18 10 121 SSSF_PIN_DECL(H18, GPIOB2, SALT3, SIG_DESC_SET(SCU80, 10)); 122 123 #define F18 11 124 SSSF_PIN_DECL(F18, GPIOB3, SALT4, SIG_DESC_SET(SCU80, 11)); 125 126 #define E19 12 127 SIG_EXPR_DECL(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12)); 128 SIG_EXPR_DECL(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14)); 129 SIG_EXPR_LIST_DECL_DUAL(LPCRST, LPCRST, LPCRSTS); 130 SS_PIN_DECL(E19, GPIOB4, LPCRST); 131 132 FUNC_GROUP_DECL(LPCRST, E19); 133 134 #define H19 13 135 #define H19_DESC SIG_DESC_SET(SCU80, 13) 136 SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H19_DESC); 137 SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H19_DESC); 138 MS_PIN_DECL(H19, GPIOB5, LPCPD, LPCSMI); 139 140 FUNC_GROUP_DECL(LPCPD, H19); 141 FUNC_GROUP_DECL(LPCSMI, H19); 142 143 #define H20 14 144 SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14)); 145 146 #define E18 15 147 SIG_EXPR_LIST_DECL_SINGLE(EXTRST, EXTRST, 148 SIG_DESC_SET(SCU80, 15), 149 SIG_DESC_BIT(SCU90, 31, 0), 150 SIG_DESC_SET(SCU3C, 3)); 151 SIG_EXPR_LIST_DECL_SINGLE(SPICS1, SPICS1, 152 SIG_DESC_SET(SCU80, 15), 153 SIG_DESC_SET(SCU90, 31)); 154 MS_PIN_DECL(E18, GPIOB7, EXTRST, SPICS1); 155 156 FUNC_GROUP_DECL(EXTRST, E18); 157 FUNC_GROUP_DECL(SPICS1, E18); 158 159 #define SD1_DESC SIG_DESC_SET(SCU90, 0) 160 #define I2C10_DESC SIG_DESC_SET(SCU90, 23) 161 162 #define C4 16 163 SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC); 164 SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC); 165 MS_PIN_DECL(C4, GPIOC0, SD1CLK, SCL10); 166 167 #define B3 17 168 SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC); 169 SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC); 170 MS_PIN_DECL(B3, GPIOC1, SD1CMD, SDA10); 171 172 FUNC_GROUP_DECL(I2C10, C4, B3); 173 174 #define I2C11_DESC SIG_DESC_SET(SCU90, 24) 175 176 #define A2 18 177 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC); 178 SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC); 179 MS_PIN_DECL(A2, GPIOC2, SD1DAT0, SCL11); 180 181 #define E5 19 182 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC); 183 SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC); 184 MS_PIN_DECL(E5, GPIOC3, SD1DAT1, SDA11); 185 186 FUNC_GROUP_DECL(I2C11, A2, E5); 187 188 #define I2C12_DESC SIG_DESC_SET(SCU90, 25) 189 190 #define D4 20 191 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC); 192 SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC); 193 MS_PIN_DECL(D4, GPIOC4, SD1DAT2, SCL12); 194 195 #define C3 21 196 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC); 197 SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC); 198 MS_PIN_DECL(C3, GPIOC5, SD1DAT3, SDA12); 199 200 FUNC_GROUP_DECL(I2C12, D4, C3); 201 202 #define I2C13_DESC SIG_DESC_SET(SCU90, 26) 203 204 #define B2 22 205 SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC); 206 SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC); 207 MS_PIN_DECL(B2, GPIOC6, SD1CD, SCL13); 208 209 #define A1 23 210 SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC); 211 SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC); 212 MS_PIN_DECL(A1, GPIOC7, SD1WP, SDA13); 213 214 FUNC_GROUP_DECL(I2C13, B2, A1); 215 FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1); 216 217 #define SD2_DESC SIG_DESC_SET(SCU90, 1) 218 #define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21) 219 #define GPID0_DESC SIG_DESC_SET(SCU8C, 8) 220 221 #define A18 24 222 SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC); 223 SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC); 224 SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC); 225 SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID); 226 MS_PIN_DECL(A18, GPIOD0, SD2CLK, GPID0IN); 227 228 #define D16 25 229 SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC); 230 SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC); 231 SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC); 232 SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID); 233 MS_PIN_DECL(D16, GPIOD1, SD2CMD, GPID0OUT); 234 235 FUNC_GROUP_DECL(GPID0, A18, D16); 236 237 #define GPID2_DESC SIG_DESC_SET(SCU8C, 9) 238 239 #define B17 26 240 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC); 241 SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC); 242 SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC); 243 SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID); 244 MS_PIN_DECL(B17, GPIOD2, SD2DAT0, GPID2IN); 245 246 #define A17 27 247 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC); 248 SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC); 249 SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC); 250 SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID); 251 MS_PIN_DECL(A17, GPIOD3, SD2DAT1, GPID2OUT); 252 253 FUNC_GROUP_DECL(GPID2, B17, A17); 254 255 #define GPID4_DESC SIG_DESC_SET(SCU8C, 10) 256 257 #define C16 28 258 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC); 259 SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC); 260 SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC); 261 SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID); 262 MS_PIN_DECL(C16, GPIOD4, SD2DAT2, GPID4IN); 263 264 #define B16 29 265 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC); 266 SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC); 267 SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC); 268 SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID); 269 MS_PIN_DECL(B16, GPIOD5, SD2DAT3, GPID4OUT); 270 271 FUNC_GROUP_DECL(GPID4, C16, B16); 272 273 #define GPID6_DESC SIG_DESC_SET(SCU8C, 11) 274 275 #define A16 30 276 SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC); 277 SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC); 278 SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC); 279 SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID); 280 MS_PIN_DECL(A16, GPIOD6, SD2CD, GPID6IN); 281 282 #define E15 31 283 SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC); 284 SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC); 285 SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC); 286 SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID); 287 MS_PIN_DECL(E15, GPIOD7, SD2WP, GPID6OUT); 288 289 FUNC_GROUP_DECL(GPID6, A16, E15); 290 FUNC_GROUP_DECL(SD2, A18, D16, B17, A17, C16, B16, A16, E15); 291 FUNC_GROUP_DECL(GPID, A18, D16, B17, A17, C16, B16, A16, E15); 292 293 #define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22) 294 #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) 295 #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) 296 #define GPIE4_DESC SIG_DESC_SET(SCU8C, 14) 297 #define GPIE6_DESC SIG_DESC_SET(SCU8C, 15) 298 299 #define D15 32 300 SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); 301 SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); 302 SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); 303 SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); 304 MS_PIN_DECL(D15, GPIOE0, NCTS3, GPIE0IN); 305 306 FUNC_GROUP_DECL(NCTS3, D15); 307 308 #define C15 33 309 SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); 310 SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); 311 SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); 312 SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); 313 MS_PIN_DECL(C15, GPIOE1, NDCD3, GPIE0OUT); 314 315 FUNC_GROUP_DECL(NDCD3, C15); 316 FUNC_GROUP_DECL(GPIE0, D15, C15); 317 318 #define B15 34 319 SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); 320 SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC); 321 SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC); 322 SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE); 323 MS_PIN_DECL(B15, GPIOE2, NDSR3, GPIE2IN); 324 325 FUNC_GROUP_DECL(NDSR3, B15); 326 327 #define A15 35 328 SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); 329 SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC); 330 SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC); 331 SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE); 332 MS_PIN_DECL(A15, GPIOE3, NRI3, GPIE2OUT); 333 334 FUNC_GROUP_DECL(NRI3, A15); 335 FUNC_GROUP_DECL(GPIE2, B15, A15); 336 337 #define E14 36 338 SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); 339 SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC); 340 SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC); 341 SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE); 342 MS_PIN_DECL(E14, GPIOE4, NDTR3, GPIE4IN); 343 344 FUNC_GROUP_DECL(NDTR3, E14); 345 346 #define D14 37 347 SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); 348 SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC); 349 SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC); 350 SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE); 351 MS_PIN_DECL(D14, GPIOE5, NRTS3, GPIE4OUT); 352 353 FUNC_GROUP_DECL(NRTS3, D14); 354 FUNC_GROUP_DECL(GPIE4, E14, D14); 355 356 #define C14 38 357 SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); 358 SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC); 359 SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC); 360 SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE); 361 MS_PIN_DECL(C14, GPIOE6, TXD3, GPIE6IN); 362 363 FUNC_GROUP_DECL(TXD3, C14); 364 365 #define B14 39 366 SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); 367 SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC); 368 SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC); 369 SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE); 370 MS_PIN_DECL(B14, GPIOE7, RXD3, GPIE6OUT); 371 372 FUNC_GROUP_DECL(RXD3, B14); 373 FUNC_GROUP_DECL(GPIE6, C14, B14); 374 375 #define D18 40 376 SSSF_PIN_DECL(D18, GPIOF0, NCTS4, SIG_DESC_SET(SCU80, 24)); 377 378 #define ACPI_DESC SIG_DESC_BIT(HW_STRAP1, 19, 0) 379 380 #define B19 41 381 SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); 382 SIG_EXPR_DECL(SIOPBI, SIOPBI, SIG_DESC_SET(SCUA4, 12)); 383 SIG_EXPR_DECL(SIOPBI, ACPI, ACPI_DESC); 384 SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI); 385 MS_PIN_DECL(B19, GPIOF1, NDCD4, SIOPBI); 386 FUNC_GROUP_DECL(NDCD4, B19); 387 FUNC_GROUP_DECL(SIOPBI, B19); 388 389 #define A20 42 390 SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); 391 SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, SIG_DESC_SET(SCUA4, 12)); 392 SIG_EXPR_DECL(SIOPWRGD, ACPI, ACPI_DESC); 393 SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI); 394 MS_PIN_DECL(A20, GPIOF2, NDSR4, SIOPWRGD); 395 FUNC_GROUP_DECL(NDSR4, A20); 396 FUNC_GROUP_DECL(SIOPWRGD, A20); 397 398 #define D17 43 399 SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); 400 SIG_EXPR_DECL(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14)); 401 SIG_EXPR_DECL(SIOPBO, ACPI, ACPI_DESC); 402 SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI); 403 MS_PIN_DECL(D17, GPIOF3, NRI4, SIOPBO); 404 FUNC_GROUP_DECL(NRI4, D17); 405 FUNC_GROUP_DECL(SIOPBO, D17); 406 407 #define B18 44 408 SSSF_PIN_DECL(B18, GPIOF4, NDTR4, SIG_DESC_SET(SCU80, 28)); 409 410 #define A19 45 411 SIG_EXPR_LIST_DECL_SINGLE(NDTS4, NDTS4, SIG_DESC_SET(SCU80, 29)); 412 SIG_EXPR_DECL(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15)); 413 SIG_EXPR_DECL(SIOSCI, ACPI, ACPI_DESC); 414 SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI); 415 MS_PIN_DECL(A19, GPIOF5, NDTS4, SIOSCI); 416 FUNC_GROUP_DECL(NDTS4, A19); 417 FUNC_GROUP_DECL(SIOSCI, A19); 418 419 #define E16 46 420 SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30)); 421 422 #define C17 47 423 SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31)); 424 425 #define A14 48 426 SSSF_PIN_DECL(A14, GPIOG0, SGPSCK, SIG_DESC_SET(SCU84, 0)); 427 428 #define E13 49 429 SSSF_PIN_DECL(E13, GPIOG1, SGPSLD, SIG_DESC_SET(SCU84, 1)); 430 431 #define D13 50 432 SSSF_PIN_DECL(D13, GPIOG2, SGPSI0, SIG_DESC_SET(SCU84, 2)); 433 434 #define C13 51 435 SSSF_PIN_DECL(C13, GPIOG3, SGPSI1, SIG_DESC_SET(SCU84, 3)); 436 437 #define B13 52 438 SIG_EXPR_LIST_DECL_SINGLE(OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1)); 439 SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, SIG_DESC_SET(SCU84, 4)); 440 MS_PIN_DECL(B13, GPIOG4, OSCCLK, WDTRST1); 441 442 FUNC_GROUP_DECL(OSCCLK, B13); 443 FUNC_GROUP_DECL(WDTRST1, B13); 444 445 #define Y21 53 446 SIG_EXPR_LIST_DECL_SINGLE(USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); 447 SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, SIG_DESC_SET(SCU84, 5)); 448 MS_PIN_DECL(Y21, GPIOG5, USBCKI, WDTRST2); 449 450 FUNC_GROUP_DECL(USBCKI, Y21); 451 FUNC_GROUP_DECL(WDTRST2, Y21); 452 453 #define AA22 54 454 SSSF_PIN_DECL(AA22, GPIOG6, FLBUSY, SIG_DESC_SET(SCU84, 6)); 455 456 #define U18 55 457 SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7)); 458 459 #define UART6_DESC SIG_DESC_SET(SCU90, 7) 460 #define ROM16_DESC SIG_DESC_SET(SCU90, 6) 461 #define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4) 462 #define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 } 463 464 #define A8 56 465 SIG_EXPR_DECL(ROMD8, ROM16, ROM16_DESC); 466 SIG_EXPR_DECL(ROMD8, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 467 SIG_EXPR_LIST_DECL_DUAL(ROMD8, ROM16, ROM16S); 468 SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, UART6_DESC); 469 MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6); 470 471 #define C7 57 472 SIG_EXPR_DECL(ROMD9, ROM16, ROM16_DESC); 473 SIG_EXPR_DECL(ROMD9, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 474 SIG_EXPR_LIST_DECL_DUAL(ROMD9, ROM16, ROM16S); 475 SIG_EXPR_LIST_DECL_SINGLE(NDCD6, NDCD6, UART6_DESC); 476 MS_PIN_DECL(C7, GPIOH1, ROMD9, NDCD6); 477 478 #define B7 58 479 SIG_EXPR_DECL(ROMD10, ROM16, ROM16_DESC); 480 SIG_EXPR_DECL(ROMD10, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 481 SIG_EXPR_LIST_DECL_DUAL(ROMD10, ROM16, ROM16S); 482 SIG_EXPR_LIST_DECL_SINGLE(NDSR6, NDSR6, UART6_DESC); 483 MS_PIN_DECL(B7, GPIOH2, ROMD10, NDSR6); 484 485 #define A7 59 486 SIG_EXPR_DECL(ROMD11, ROM16, ROM16_DESC); 487 SIG_EXPR_DECL(ROMD11, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 488 SIG_EXPR_LIST_DECL_DUAL(ROMD11, ROM16, ROM16S); 489 SIG_EXPR_LIST_DECL_SINGLE(NRI6, NRI6, UART6_DESC); 490 MS_PIN_DECL(A7, GPIOH3, ROMD11, NRI6); 491 492 #define D7 60 493 SIG_EXPR_DECL(ROMD12, ROM16, ROM16_DESC); 494 SIG_EXPR_DECL(ROMD12, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 495 SIG_EXPR_LIST_DECL_DUAL(ROMD12, ROM16, ROM16S); 496 SIG_EXPR_LIST_DECL_SINGLE(NDTR6, NDTR6, UART6_DESC); 497 MS_PIN_DECL(D7, GPIOH4, ROMD12, NDTR6); 498 499 #define B6 61 500 SIG_EXPR_DECL(ROMD13, ROM16, ROM16_DESC); 501 SIG_EXPR_DECL(ROMD13, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 502 SIG_EXPR_LIST_DECL_DUAL(ROMD13, ROM16, ROM16S); 503 SIG_EXPR_LIST_DECL_SINGLE(NRTS6, NRTS6, UART6_DESC); 504 MS_PIN_DECL(B6, GPIOH5, ROMD13, NRTS6); 505 506 #define A6 62 507 SIG_EXPR_DECL(ROMD14, ROM16, ROM16_DESC); 508 SIG_EXPR_DECL(ROMD14, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 509 SIG_EXPR_LIST_DECL_DUAL(ROMD14, ROM16, ROM16S); 510 SIG_EXPR_LIST_DECL_SINGLE(TXD6, TXD6, UART6_DESC); 511 MS_PIN_DECL(A6, GPIOH6, ROMD14, TXD6); 512 513 #define E7 63 514 SIG_EXPR_DECL(ROMD15, ROM16, ROM16_DESC); 515 SIG_EXPR_DECL(ROMD15, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 516 SIG_EXPR_LIST_DECL_DUAL(ROMD15, ROM16, ROM16S); 517 SIG_EXPR_LIST_DECL_SINGLE(RXD6, RXD6, UART6_DESC); 518 MS_PIN_DECL(E7, GPIOH7, ROMD15, RXD6); 519 520 FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7); 521 522 #define SPI1_DESC \ 523 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 } 524 #define SPI1DEBUG_DESC \ 525 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 } 526 #define SPI1PASSTHRU_DESC \ 527 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 } 528 529 #define C22 64 530 SIG_EXPR_DECL(SYSCS, SPI1DEBUG, SPI1DEBUG_DESC); 531 SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 532 SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU); 533 SS_PIN_DECL(C22, GPIOI0, SYSCS); 534 535 #define G18 65 536 SIG_EXPR_DECL(SYSCK, SPI1DEBUG, SPI1DEBUG_DESC); 537 SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 538 SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU); 539 SS_PIN_DECL(G18, GPIOI1, SYSCK); 540 541 #define D19 66 542 SIG_EXPR_DECL(SYSDO, SPI1DEBUG, SPI1DEBUG_DESC); 543 SIG_EXPR_DECL(SYSDO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 544 SIG_EXPR_LIST_DECL_DUAL(SYSDO, SPI1DEBUG, SPI1PASSTHRU); 545 SS_PIN_DECL(D19, GPIOI2, SYSDO); 546 547 #define C20 67 548 SIG_EXPR_DECL(SYSDI, SPI1DEBUG, SPI1DEBUG_DESC); 549 SIG_EXPR_DECL(SYSDI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 550 SIG_EXPR_LIST_DECL_DUAL(SYSDI, SPI1DEBUG, SPI1PASSTHRU); 551 SS_PIN_DECL(C20, GPIOI3, SYSDI); 552 553 #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5) 554 555 #define B22 68 556 SIG_EXPR_DECL(SPI1CS0, SPI1, SPI1_DESC); 557 SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, SPI1DEBUG_DESC); 558 SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 559 SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1), 560 SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG), 561 SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU)); 562 SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOS_ROM, VB_DESC); 563 MS_PIN_DECL(B22, GPIOI4, SPI1CS0, VBCS); 564 565 #define G19 69 566 SIG_EXPR_DECL(SPI1CK, SPI1, SPI1_DESC); 567 SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, SPI1DEBUG_DESC); 568 SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 569 SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1), 570 SIG_EXPR_PTR(SPI1CK, SPI1DEBUG), 571 SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU)); 572 SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOS_ROM, VB_DESC); 573 MS_PIN_DECL(G19, GPIOI5, SPI1CK, VBCK); 574 575 #define C18 70 576 SIG_EXPR_DECL(SPI1DO, SPI1, SPI1_DESC); 577 SIG_EXPR_DECL(SPI1DO, SPI1DEBUG, SPI1DEBUG_DESC); 578 SIG_EXPR_DECL(SPI1DO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 579 SIG_EXPR_LIST_DECL(SPI1DO, SIG_EXPR_PTR(SPI1DO, SPI1), 580 SIG_EXPR_PTR(SPI1DO, SPI1DEBUG), 581 SIG_EXPR_PTR(SPI1DO, SPI1PASSTHRU)); 582 SIG_EXPR_LIST_DECL_SINGLE(VBDO, VGABIOS_ROM, VB_DESC); 583 MS_PIN_DECL(C18, GPIOI6, SPI1DO, VBDO); 584 585 #define E20 71 586 SIG_EXPR_DECL(SPI1DI, SPI1, SPI1_DESC); 587 SIG_EXPR_DECL(SPI1DI, SPI1DEBUG, SPI1DEBUG_DESC); 588 SIG_EXPR_DECL(SPI1DI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 589 SIG_EXPR_LIST_DECL(SPI1DI, SIG_EXPR_PTR(SPI1DI, SPI1), 590 SIG_EXPR_PTR(SPI1DI, SPI1DEBUG), 591 SIG_EXPR_PTR(SPI1DI, SPI1PASSTHRU)); 592 SIG_EXPR_LIST_DECL_SINGLE(VBDI, VGABIOS_ROM, VB_DESC); 593 MS_PIN_DECL(E20, GPIOI7, SPI1DI, VBDI); 594 595 FUNC_GROUP_DECL(SPI1, B22, G19, C18, E20); 596 FUNC_GROUP_DECL(SPI1DEBUG, C22, G18, D19, C20, B22, G19, C18, E20); 597 FUNC_GROUP_DECL(SPI1PASSTHRU, C22, G18, D19, C20, B22, G19, C18, E20); 598 FUNC_GROUP_DECL(VGABIOS_ROM, B22, G19, C18, E20); 599 600 #define J5 72 601 SSSF_PIN_DECL(J5, GPIOJ0, SGPMCK, SIG_DESC_SET(SCU84, 8)); 602 603 #define J4 73 604 SSSF_PIN_DECL(J4, GPIOJ1, SGPMLD, SIG_DESC_SET(SCU84, 9)); 605 606 #define K5 74 607 SSSF_PIN_DECL(K5, GPIOJ2, SGPMO, SIG_DESC_SET(SCU84, 10)); 608 609 #define J3 75 610 SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11)); 611 612 #define T4 76 613 SSSF_PIN_DECL(T4, GPIOJ4, VGAHS, SIG_DESC_SET(SCU84, 12)); 614 615 #define U2 77 616 SSSF_PIN_DECL(U2, GPIOJ5, VGAVS, SIG_DESC_SET(SCU84, 13)); 617 618 #define T2 78 619 SSSF_PIN_DECL(T2, GPIOJ6, DDCCLK, SIG_DESC_SET(SCU84, 14)); 620 621 #define T1 79 622 SSSF_PIN_DECL(T1, GPIOJ7, DDCDAT, SIG_DESC_SET(SCU84, 15)); 623 624 #define I2C5_DESC SIG_DESC_SET(SCU90, 18) 625 626 #define E3 80 627 SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); 628 SS_PIN_DECL(E3, GPIOK0, SCL5); 629 630 #define D2 81 631 SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC); 632 SS_PIN_DECL(D2, GPIOK1, SDA5); 633 634 FUNC_GROUP_DECL(I2C5, E3, D2); 635 636 #define I2C6_DESC SIG_DESC_SET(SCU90, 19) 637 638 #define C1 82 639 SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC); 640 SS_PIN_DECL(C1, GPIOK2, SCL6); 641 642 #define F4 83 643 SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC); 644 SS_PIN_DECL(F4, GPIOK3, SDA6); 645 646 FUNC_GROUP_DECL(I2C6, C1, F4); 647 648 #define I2C7_DESC SIG_DESC_SET(SCU90, 20) 649 650 #define E2 84 651 SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC); 652 SS_PIN_DECL(E2, GPIOK4, SCL7); 653 654 #define D1 85 655 SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC); 656 SS_PIN_DECL(D1, GPIOK5, SDA7); 657 658 FUNC_GROUP_DECL(I2C7, E2, D1); 659 660 #define I2C8_DESC SIG_DESC_SET(SCU90, 21) 661 662 #define G5 86 663 SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC); 664 SS_PIN_DECL(G5, GPIOK6, SCL8); 665 666 #define F3 87 667 SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC); 668 SS_PIN_DECL(F3, GPIOK7, SDA8); 669 670 FUNC_GROUP_DECL(I2C8, G5, F3); 671 672 #define U1 88 673 SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); 674 675 #define VPI18_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 } 676 #define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 } 677 #define VPI30_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 } 678 679 #define T5 89 680 #define T5_DESC SIG_DESC_SET(SCU84, 17) 681 SIG_EXPR_DECL(VPIDE, VPI18, VPI18_DESC, T5_DESC); 682 SIG_EXPR_DECL(VPIDE, VPI24, VPI24_DESC, T5_DESC); 683 SIG_EXPR_DECL(VPIDE, VPI30, VPI30_DESC, T5_DESC); 684 SIG_EXPR_LIST_DECL(VPIDE, SIG_EXPR_PTR(VPIDE, VPI18), 685 SIG_EXPR_PTR(VPIDE, VPI24), 686 SIG_EXPR_PTR(VPIDE, VPI30)); 687 SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T5_DESC); 688 MS_PIN_DECL(T5, GPIOL1, VPIDE, NDCD1); 689 FUNC_GROUP_DECL(NDCD1, T5); 690 691 #define U3 90 692 #define U3_DESC SIG_DESC_SET(SCU84, 18) 693 SIG_EXPR_DECL(VPIODD, VPI18, VPI18_DESC, U3_DESC); 694 SIG_EXPR_DECL(VPIODD, VPI24, VPI24_DESC, U3_DESC); 695 SIG_EXPR_DECL(VPIODD, VPI30, VPI30_DESC, U3_DESC); 696 SIG_EXPR_LIST_DECL(VPIODD, SIG_EXPR_PTR(VPIODD, VPI18), 697 SIG_EXPR_PTR(VPIODD, VPI24), 698 SIG_EXPR_PTR(VPIODD, VPI30)); 699 SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U3_DESC); 700 MS_PIN_DECL(U3, GPIOL2, VPIODD, NDSR1); 701 FUNC_GROUP_DECL(NDSR1, U3); 702 703 #define V1 91 704 #define V1_DESC SIG_DESC_SET(SCU84, 19) 705 SIG_EXPR_DECL(VPIHS, VPI18, VPI18_DESC, V1_DESC); 706 SIG_EXPR_DECL(VPIHS, VPI24, VPI24_DESC, V1_DESC); 707 SIG_EXPR_DECL(VPIHS, VPI30, VPI30_DESC, V1_DESC); 708 SIG_EXPR_LIST_DECL(VPIHS, SIG_EXPR_PTR(VPIHS, VPI18), 709 SIG_EXPR_PTR(VPIHS, VPI24), 710 SIG_EXPR_PTR(VPIHS, VPI30)); 711 SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, V1_DESC); 712 MS_PIN_DECL(V1, GPIOL3, VPIHS, NRI1); 713 FUNC_GROUP_DECL(NRI1, V1); 714 715 #define U4 92 716 #define U4_DESC SIG_DESC_SET(SCU84, 20) 717 SIG_EXPR_DECL(VPIVS, VPI18, VPI18_DESC, U4_DESC); 718 SIG_EXPR_DECL(VPIVS, VPI24, VPI24_DESC, U4_DESC); 719 SIG_EXPR_DECL(VPIVS, VPI30, VPI30_DESC, U4_DESC); 720 SIG_EXPR_LIST_DECL(VPIVS, SIG_EXPR_PTR(VPIVS, VPI18), 721 SIG_EXPR_PTR(VPIVS, VPI24), 722 SIG_EXPR_PTR(VPIVS, VPI30)); 723 SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, U4_DESC); 724 MS_PIN_DECL(U4, GPIOL4, VPIVS, NDTR1); 725 FUNC_GROUP_DECL(NDTR1, U4); 726 727 #define V2 93 728 #define V2_DESC SIG_DESC_SET(SCU84, 21) 729 SIG_EXPR_DECL(VPICLK, VPI18, VPI18_DESC, V2_DESC); 730 SIG_EXPR_DECL(VPICLK, VPI24, VPI24_DESC, V2_DESC); 731 SIG_EXPR_DECL(VPICLK, VPI30, VPI30_DESC, V2_DESC); 732 SIG_EXPR_LIST_DECL(VPICLK, SIG_EXPR_PTR(VPICLK, VPI18), 733 SIG_EXPR_PTR(VPICLK, VPI24), 734 SIG_EXPR_PTR(VPICLK, VPI30)); 735 SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, V2_DESC); 736 MS_PIN_DECL(V2, GPIOL5, VPICLK, NRTS1); 737 FUNC_GROUP_DECL(NRTS1, V2); 738 739 #define W1 94 740 #define W1_DESC SIG_DESC_SET(SCU84, 22) 741 SIG_EXPR_LIST_DECL_SINGLE(VPIB0, VPI30, VPI30_DESC, W1_DESC); 742 SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, W1_DESC); 743 MS_PIN_DECL(W1, GPIOL6, VPIB0, TXD1); 744 FUNC_GROUP_DECL(TXD1, W1); 745 746 #define U5 95 747 #define U5_DESC SIG_DESC_SET(SCU84, 23) 748 SIG_EXPR_LIST_DECL_SINGLE(VPIB1, VPI30, VPI30_DESC, U5_DESC); 749 SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, U5_DESC); 750 MS_PIN_DECL(U5, GPIOL7, VPIB1, RXD1); 751 FUNC_GROUP_DECL(RXD1, U5); 752 753 #define V3 96 754 #define V3_DESC SIG_DESC_SET(SCU84, 24) 755 SIG_EXPR_DECL(VPIOB2, VPI18, VPI18_DESC, V3_DESC); 756 SIG_EXPR_DECL(VPIOB2, VPI24, VPI24_DESC, V3_DESC); 757 SIG_EXPR_DECL(VPIOB2, VPI30, VPI30_DESC, V3_DESC); 758 SIG_EXPR_LIST_DECL(VPIOB2, SIG_EXPR_PTR(VPIOB2, VPI18), 759 SIG_EXPR_PTR(VPIOB2, VPI24), 760 SIG_EXPR_PTR(VPIOB2, VPI30)); 761 SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, V3_DESC); 762 MS_PIN_DECL(V3, GPIOM0, VPIOB2, NCTS2); 763 FUNC_GROUP_DECL(NCTS2, V3); 764 765 #define W2 97 766 #define W2_DESC SIG_DESC_SET(SCU84, 25) 767 SIG_EXPR_DECL(VPIOB3, VPI18, VPI18_DESC, W2_DESC); 768 SIG_EXPR_DECL(VPIOB3, VPI24, VPI24_DESC, W2_DESC); 769 SIG_EXPR_DECL(VPIOB3, VPI30, VPI30_DESC, W2_DESC); 770 SIG_EXPR_LIST_DECL(VPIOB3, SIG_EXPR_PTR(VPIOB3, VPI18), 771 SIG_EXPR_PTR(VPIOB3, VPI24), 772 SIG_EXPR_PTR(VPIOB3, VPI30)); 773 SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, W2_DESC); 774 MS_PIN_DECL(W2, GPIOM1, VPIOB3, NDCD2); 775 FUNC_GROUP_DECL(NDCD2, W2); 776 777 #define Y1 98 778 #define Y1_DESC SIG_DESC_SET(SCU84, 26) 779 SIG_EXPR_DECL(VPIOB4, VPI18, VPI18_DESC, Y1_DESC); 780 SIG_EXPR_DECL(VPIOB4, VPI24, VPI24_DESC, Y1_DESC); 781 SIG_EXPR_DECL(VPIOB4, VPI30, VPI30_DESC, Y1_DESC); 782 SIG_EXPR_LIST_DECL(VPIOB4, SIG_EXPR_PTR(VPIOB4, VPI18), 783 SIG_EXPR_PTR(VPIOB4, VPI24), 784 SIG_EXPR_PTR(VPIOB4, VPI30)); 785 SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, Y1_DESC); 786 MS_PIN_DECL(Y1, GPIOM2, VPIOB4, NDSR2); 787 FUNC_GROUP_DECL(NDSR2, Y1); 788 789 #define V4 99 790 #define V4_DESC SIG_DESC_SET(SCU84, 27) 791 SIG_EXPR_DECL(VPIOB5, VPI18, VPI18_DESC, V4_DESC); 792 SIG_EXPR_DECL(VPIOB5, VPI24, VPI24_DESC, V4_DESC); 793 SIG_EXPR_DECL(VPIOB5, VPI30, VPI30_DESC, V4_DESC); 794 SIG_EXPR_LIST_DECL(VPIOB5, SIG_EXPR_PTR(VPIOB5, VPI18), 795 SIG_EXPR_PTR(VPIOB5, VPI24), 796 SIG_EXPR_PTR(VPIOB5, VPI30)); 797 SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, V4_DESC); 798 MS_PIN_DECL(V4, GPIOM3, VPIOB5, NRI2); 799 FUNC_GROUP_DECL(NRI2, V4); 800 801 #define W3 100 802 #define W3_DESC SIG_DESC_SET(SCU84, 28) 803 SIG_EXPR_DECL(VPIOB6, VPI18, VPI18_DESC, W3_DESC); 804 SIG_EXPR_DECL(VPIOB6, VPI24, VPI24_DESC, W3_DESC); 805 SIG_EXPR_DECL(VPIOB6, VPI30, VPI30_DESC, W3_DESC); 806 SIG_EXPR_LIST_DECL(VPIOB6, SIG_EXPR_PTR(VPIOB6, VPI18), 807 SIG_EXPR_PTR(VPIOB6, VPI24), 808 SIG_EXPR_PTR(VPIOB6, VPI30)); 809 SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, W3_DESC); 810 MS_PIN_DECL(W3, GPIOM4, VPIOB6, NDTR2); 811 FUNC_GROUP_DECL(NDTR2, W3); 812 813 #define Y2 101 814 #define Y2_DESC SIG_DESC_SET(SCU84, 29) 815 SIG_EXPR_DECL(VPIOB7, VPI18, VPI18_DESC, Y2_DESC); 816 SIG_EXPR_DECL(VPIOB7, VPI24, VPI24_DESC, Y2_DESC); 817 SIG_EXPR_DECL(VPIOB7, VPI30, VPI30_DESC, Y2_DESC); 818 SIG_EXPR_LIST_DECL(VPIOB7, SIG_EXPR_PTR(VPIOB7, VPI18), 819 SIG_EXPR_PTR(VPIOB7, VPI24), 820 SIG_EXPR_PTR(VPIOB7, VPI30)); 821 SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, Y2_DESC); 822 MS_PIN_DECL(Y2, GPIOM5, VPIOB7, NRTS2); 823 FUNC_GROUP_DECL(NRTS2, Y2); 824 825 #define AA1 102 826 #define AA1_DESC SIG_DESC_SET(SCU84, 30) 827 SIG_EXPR_DECL(VPIOB8, VPI18, VPI18_DESC, AA1_DESC); 828 SIG_EXPR_DECL(VPIOB8, VPI24, VPI24_DESC, AA1_DESC); 829 SIG_EXPR_DECL(VPIOB8, VPI30, VPI30_DESC, AA1_DESC); 830 SIG_EXPR_LIST_DECL(VPIOB8, SIG_EXPR_PTR(VPIOB8, VPI18), 831 SIG_EXPR_PTR(VPIOB8, VPI24), 832 SIG_EXPR_PTR(VPIOB8, VPI30)); 833 SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, AA1_DESC); 834 MS_PIN_DECL(AA1, GPIOM6, VPIOB8, TXD2); 835 FUNC_GROUP_DECL(TXD2, AA1); 836 837 #define V5 103 838 #define V5_DESC SIG_DESC_SET(SCU84, 31) 839 SIG_EXPR_DECL(VPIOB9, VPI18, VPI18_DESC, V5_DESC); 840 SIG_EXPR_DECL(VPIOB9, VPI24, VPI24_DESC, V5_DESC); 841 SIG_EXPR_DECL(VPIOB9, VPI30, VPI30_DESC, V5_DESC); 842 SIG_EXPR_LIST_DECL(VPIOB9, SIG_EXPR_PTR(VPIOB9, VPI18), 843 SIG_EXPR_PTR(VPIOB9, VPI24), 844 SIG_EXPR_PTR(VPIOB9, VPI30)); 845 SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, V5_DESC); 846 MS_PIN_DECL(V5, GPIOM7, VPIOB9, RXD2); 847 FUNC_GROUP_DECL(RXD2, V5); 848 849 #define W4 104 850 #define W4_DESC SIG_DESC_SET(SCU88, 0) 851 SIG_EXPR_LIST_DECL_SINGLE(VPIG0, VPI30, VPI30_DESC, W4_DESC); 852 SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, W4_DESC); 853 MS_PIN_DECL(W4, GPION0, VPIG0, PWM0); 854 FUNC_GROUP_DECL(PWM0, W4); 855 856 #define Y3 105 857 #define Y3_DESC SIG_DESC_SET(SCU88, 1) 858 SIG_EXPR_LIST_DECL_SINGLE(VPIG1, VPI30, VPI30_DESC, Y3_DESC); 859 SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, Y3_DESC); 860 MS_PIN_DECL(Y3, GPION1, VPIG1, PWM1); 861 FUNC_GROUP_DECL(PWM1, Y3); 862 863 #define AA2 106 864 #define AA2_DESC SIG_DESC_SET(SCU88, 2) 865 SIG_EXPR_DECL(VPIG2, VPI18, VPI18_DESC, AA2_DESC); 866 SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, AA2_DESC); 867 SIG_EXPR_DECL(VPIG2, VPI30, VPI30_DESC, AA2_DESC); 868 SIG_EXPR_LIST_DECL(VPIG2, SIG_EXPR_PTR(VPIG2, VPI18), 869 SIG_EXPR_PTR(VPIG2, VPI24), 870 SIG_EXPR_PTR(VPIG2, VPI30)); 871 SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, AA2_DESC); 872 MS_PIN_DECL(AA2, GPION2, VPIG2, PWM2); 873 FUNC_GROUP_DECL(PWM2, AA2); 874 875 #define AB1 107 876 #define AB1_DESC SIG_DESC_SET(SCU88, 3) 877 SIG_EXPR_DECL(VPIG3, VPI18, VPI18_DESC, AB1_DESC); 878 SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, AB1_DESC); 879 SIG_EXPR_DECL(VPIG3, VPI30, VPI30_DESC, AB1_DESC); 880 SIG_EXPR_LIST_DECL(VPIG3, SIG_EXPR_PTR(VPIG3, VPI18), 881 SIG_EXPR_PTR(VPIG3, VPI24), 882 SIG_EXPR_PTR(VPIG3, VPI30)); 883 SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, AB1_DESC); 884 MS_PIN_DECL(AB1, GPION3, VPIG3, PWM3); 885 FUNC_GROUP_DECL(PWM3, AB1); 886 887 #define W5 108 888 #define W5_DESC SIG_DESC_SET(SCU88, 4) 889 SIG_EXPR_DECL(VPIG4, VPI18, VPI18_DESC, W5_DESC); 890 SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W5_DESC); 891 SIG_EXPR_DECL(VPIG4, VPI30, VPI30_DESC, W5_DESC); 892 SIG_EXPR_LIST_DECL(VPIG4, SIG_EXPR_PTR(VPIG4, VPI18), 893 SIG_EXPR_PTR(VPIG4, VPI24), 894 SIG_EXPR_PTR(VPIG4, VPI30)); 895 SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W5_DESC); 896 MS_PIN_DECL(W5, GPION4, VPIG4, PWM4); 897 FUNC_GROUP_DECL(PWM4, W5); 898 899 #define Y4 109 900 #define Y4_DESC SIG_DESC_SET(SCU88, 5) 901 SIG_EXPR_DECL(VPIG5, VPI18, VPI18_DESC, Y4_DESC); 902 SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, Y4_DESC); 903 SIG_EXPR_DECL(VPIG5, VPI30, VPI30_DESC, Y4_DESC); 904 SIG_EXPR_LIST_DECL(VPIG5, SIG_EXPR_PTR(VPIG5, VPI18), 905 SIG_EXPR_PTR(VPIG5, VPI24), 906 SIG_EXPR_PTR(VPIG5, VPI30)); 907 SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, Y4_DESC); 908 MS_PIN_DECL(Y4, GPION5, VPIG5, PWM5); 909 FUNC_GROUP_DECL(PWM5, Y4); 910 911 #define AA3 110 912 #define AA3_DESC SIG_DESC_SET(SCU88, 6) 913 SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI30, VPI30_DESC, AA3_DESC); 914 SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, AA3_DESC); 915 MS_PIN_DECL(AA3, GPION6, VPIG6, PWM6); 916 FUNC_GROUP_DECL(PWM6, AA3); 917 918 #define AB2 111 919 #define AB2_DESC SIG_DESC_SET(SCU88, 7) 920 SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI30, VPI30_DESC, AB2_DESC); 921 SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, AB2_DESC); 922 MS_PIN_DECL(AB2, GPION7, VPIG7, PWM7); 923 FUNC_GROUP_DECL(PWM7, AB2); 924 925 #define V6 112 926 SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8)); 927 SS_PIN_DECL(V6, GPIOO0, VPIG8); 928 929 #define Y5 113 930 SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9)); 931 SS_PIN_DECL(Y5, GPIOO1, VPIG9); 932 933 #define AA4 114 934 SIG_EXPR_LIST_DECL_SINGLE(VPIR0, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 10)); 935 SS_PIN_DECL(AA4, GPIOO2, VPIR0); 936 937 #define AB3 115 938 SIG_EXPR_LIST_DECL_SINGLE(VPIR1, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 11)); 939 SS_PIN_DECL(AB3, GPIOO3, VPIR1); 940 941 #define W6 116 942 SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12)); 943 SS_PIN_DECL(W6, GPIOO4, VPIR2); 944 945 #define AA5 117 946 SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13)); 947 SS_PIN_DECL(AA5, GPIOO5, VPIR3); 948 949 #define AB4 118 950 SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14)); 951 SS_PIN_DECL(AB4, GPIOO6, VPIR4); 952 953 #define V7 119 954 SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15)); 955 SS_PIN_DECL(V7, GPIOO7, VPIR5); 956 957 #define Y6 120 958 SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16)); 959 SS_PIN_DECL(Y6, GPIOP0, VPIR6); 960 961 #define AB5 121 962 SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17)); 963 SS_PIN_DECL(AB5, GPIOP1, VPIR7); 964 965 #define W7 122 966 SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18)); 967 SS_PIN_DECL(W7, GPIOP2, VPIR8); 968 969 #define AA6 123 970 SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19)); 971 SS_PIN_DECL(AA6, GPIOP3, VPIR9); 972 973 FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5, 974 AA22, W5, Y4, AA3, AB2); 975 FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5, 976 AA22, W5, Y4, AA3, AB2, V6, Y5, W6, AA5, AB4, V7, Y6, AB5, W7, 977 AA6); 978 FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1, 979 V5, W4, Y3, AA22, W5, Y4, AA3, AB2, AA4, AB3); 980 981 #define AB6 124 982 SIG_EXPR_LIST_DECL_SINGLE(GPIOP4, GPIOP4); 983 MS_PIN_DECL_(AB6, SIG_EXPR_LIST_PTR(GPIOP4)); 984 985 #define Y7 125 986 SIG_EXPR_LIST_DECL_SINGLE(GPIOP5, GPIOP5); 987 MS_PIN_DECL_(Y7, SIG_EXPR_LIST_PTR(GPIOP5)); 988 989 #define AA7 126 990 SSSF_PIN_DECL(AA7, GPIOP6, BMCINT, SIG_DESC_SET(SCU88, 22)); 991 992 #define AB7 127 993 SSSF_PIN_DECL(AB7, GPIOP7, FLACK, SIG_DESC_SET(SCU88, 23)); 994 995 #define I2C3_DESC SIG_DESC_SET(SCU90, 16) 996 997 #define D3 128 998 SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC); 999 SS_PIN_DECL(D3, GPIOQ0, SCL3); 1000 1001 #define C2 129 1002 SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC); 1003 SS_PIN_DECL(C2, GPIOQ1, SDA3); 1004 1005 FUNC_GROUP_DECL(I2C3, D3, C2); 1006 1007 #define I2C4_DESC SIG_DESC_SET(SCU90, 17) 1008 1009 #define B1 130 1010 SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC); 1011 SS_PIN_DECL(B1, GPIOQ2, SCL4); 1012 1013 #define F5 131 1014 SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC); 1015 SS_PIN_DECL(F5, GPIOQ3, SDA4); 1016 1017 FUNC_GROUP_DECL(I2C4, B1, F5); 1018 1019 #define I2C14_DESC SIG_DESC_SET(SCU90, 27) 1020 1021 #define H4 132 1022 SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC); 1023 SS_PIN_DECL(H4, GPIOQ4, SCL14); 1024 1025 #define H3 133 1026 SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC); 1027 SS_PIN_DECL(H3, GPIOQ5, SDA14); 1028 1029 FUNC_GROUP_DECL(I2C14, H4, H3); 1030 1031 /* 1032 * There are several opportunities to document USB port 4 in the datasheet, but 1033 * it is only mentioned in one location. Particularly, the Multi-function Pins 1034 * Mapping and Control table in the datasheet elides the signal names, 1035 * suggesting that port 4 may not actually be functional. As such we define the 1036 * signal names and control bit, but don't export the capability's function or 1037 * group. 1038 */ 1039 #define USB11H3_DESC SIG_DESC_SET(SCU90, 28) 1040 1041 #define H2 134 1042 SIG_EXPR_LIST_DECL_SINGLE(USB11HDP3, USB11H3, USB11H3_DESC); 1043 SS_PIN_DECL(H2, GPIOQ6, USB11HDP3); 1044 1045 #define H1 135 1046 SIG_EXPR_LIST_DECL_SINGLE(USB11HDN3, USB11H3, USB11H3_DESC); 1047 SS_PIN_DECL(H1, GPIOQ7, USB11HDN3); 1048 1049 #define V20 136 1050 SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24)); 1051 1052 #define W21 137 1053 SSSF_PIN_DECL(W21, GPIOR1, ROMCS2, SIG_DESC_SET(SCU88, 25)); 1054 1055 #define Y22 138 1056 SSSF_PIN_DECL(Y22, GPIOR2, ROMCS3, SIG_DESC_SET(SCU88, 26)); 1057 1058 #define U19 139 1059 SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27)); 1060 1061 #define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } 1062 #define VPO12_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 } 1063 #define VPO24_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 } 1064 #define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 } 1065 #define VPO_OFF_12 { ASPEED_IP_SCU, SCU94, 0x2, 0, 0 } 1066 #define VPO_24_OFF SIG_DESC_SET(SCU94, 1) 1067 1068 #define V21 140 1069 #define V21_DESC SIG_DESC_SET(SCU88, 28) 1070 SIG_EXPR_DECL(ROMA24, ROM8, V21_DESC, VPO_OFF_12); 1071 SIG_EXPR_DECL(ROMA24, ROM16, V21_DESC, VPO_OFF_12); 1072 SIG_EXPR_DECL(ROMA24, ROM16S, V21_DESC, VPO_OFF_12); 1073 SIG_EXPR_LIST_DECL(ROMA24, SIG_EXPR_PTR(ROMA24, ROM8), 1074 SIG_EXPR_PTR(ROMA24, ROM16), 1075 SIG_EXPR_PTR(ROMA24, ROM16S)); 1076 SIG_EXPR_LIST_DECL_SINGLE(VPOR6, VPO24, V21_DESC, VPO_24_OFF); 1077 MS_PIN_DECL(V21, GPIOR4, ROMA24, VPOR6); 1078 1079 #define W22 141 1080 #define W22_DESC SIG_DESC_SET(SCU88, 29) 1081 SIG_EXPR_DECL(ROMA25, ROM8, W22_DESC, VPO_OFF_12); 1082 SIG_EXPR_DECL(ROMA25, ROM16, W22_DESC, VPO_OFF_12); 1083 SIG_EXPR_DECL(ROMA25, ROM16S, W22_DESC, VPO_OFF_12); 1084 SIG_EXPR_LIST_DECL(ROMA25, SIG_EXPR_PTR(ROMA25, ROM8), 1085 SIG_EXPR_PTR(ROMA25, ROM16), 1086 SIG_EXPR_PTR(ROMA25, ROM16S)); 1087 SIG_EXPR_LIST_DECL_SINGLE(VPOR7, VPO24, W22_DESC, VPO_24_OFF); 1088 MS_PIN_DECL(W22, GPIOR5, ROMA25, VPOR7); 1089 1090 #define C6 142 1091 SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); 1092 SS_PIN_DECL(C6, GPIOR6, MDC1); 1093 1094 #define A5 143 1095 SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); 1096 SS_PIN_DECL(A5, GPIOR7, MDIO1); 1097 1098 FUNC_GROUP_DECL(MDIO1, C6, A5); 1099 1100 #define U21 144 1101 #define U21_DESC SIG_DESC_SET(SCU8C, 0) 1102 SIG_EXPR_DECL(ROMD4, ROM8, U21_DESC, VPOOFF0_DESC); 1103 SIG_EXPR_DECL(ROMD4, ROM16, U21_DESC, VPOOFF0_DESC); 1104 SIG_EXPR_DECL(ROMD4, ROM16S, U21_DESC, VPOOFF0_DESC); 1105 SIG_EXPR_LIST_DECL(ROMD4, SIG_EXPR_PTR(ROMD4, ROM8), 1106 SIG_EXPR_PTR(ROMD4, ROM16), 1107 SIG_EXPR_PTR(ROMD4, ROM16S)); 1108 SIG_EXPR_DECL(VPODE, VPO12, U21_DESC, VPO12_DESC); 1109 SIG_EXPR_DECL(VPODE, VPO24, U21_DESC, VPO12_DESC); 1110 SIG_EXPR_LIST_DECL_DUAL(VPODE, VPO12, VPO24); 1111 MS_PIN_DECL(U21, GPIOS0, ROMD4, VPODE); 1112 1113 #define T19 145 1114 #define T19_DESC SIG_DESC_SET(SCU8C, 1) 1115 SIG_EXPR_DECL(ROMD5, ROM8, T19_DESC, VPOOFF0_DESC); 1116 SIG_EXPR_DECL(ROMD5, ROM16, T19_DESC, VPOOFF0_DESC); 1117 SIG_EXPR_DECL(ROMD5, ROM16S, T19_DESC, VPOOFF0_DESC); 1118 SIG_EXPR_LIST_DECL(ROMD5, SIG_EXPR_PTR(ROMD5, ROM8), 1119 SIG_EXPR_PTR(ROMD5, ROM16), 1120 SIG_EXPR_PTR(ROMD5, ROM16S)); 1121 SIG_EXPR_DECL(VPOHS, VPO12, T19_DESC, VPO12_DESC); 1122 SIG_EXPR_DECL(VPOHS, VPO24, T19_DESC, VPO24_DESC); 1123 SIG_EXPR_LIST_DECL_DUAL(VPOHS, VPO12, VPO24); 1124 MS_PIN_DECL(T19, GPIOS1, ROMD5, VPOHS); 1125 1126 #define V22 146 1127 #define V22_DESC SIG_DESC_SET(SCU8C, 2) 1128 SIG_EXPR_DECL(ROMD6, ROM8, V22_DESC, VPOOFF0_DESC); 1129 SIG_EXPR_DECL(ROMD6, ROM16, V22_DESC, VPOOFF0_DESC); 1130 SIG_EXPR_DECL(ROMD6, ROM16S, V22_DESC, VPOOFF0_DESC); 1131 SIG_EXPR_LIST_DECL(ROMD6, SIG_EXPR_PTR(ROMD6, ROM8), 1132 SIG_EXPR_PTR(ROMD6, ROM16), 1133 SIG_EXPR_PTR(ROMD6, ROM16S)); 1134 SIG_EXPR_DECL(VPOVS, VPO12, V22_DESC, VPO12_DESC); 1135 SIG_EXPR_DECL(VPOVS, VPO24, V22_DESC, VPO24_DESC); 1136 SIG_EXPR_LIST_DECL_DUAL(VPOVS, VPO12, VPO24); 1137 MS_PIN_DECL(V22, GPIOS2, ROMD6, VPOVS); 1138 1139 #define U20 147 1140 #define U20_DESC SIG_DESC_SET(SCU8C, 3) 1141 SIG_EXPR_DECL(ROMD7, ROM8, U20_DESC, VPOOFF0_DESC); 1142 SIG_EXPR_DECL(ROMD7, ROM16, U20_DESC, VPOOFF0_DESC); 1143 SIG_EXPR_DECL(ROMD7, ROM16S, U20_DESC, VPOOFF0_DESC); 1144 SIG_EXPR_LIST_DECL(ROMD7, SIG_EXPR_PTR(ROMD7, ROM8), 1145 SIG_EXPR_PTR(ROMD7, ROM16), 1146 SIG_EXPR_PTR(ROMD7, ROM16S)); 1147 SIG_EXPR_DECL(VPOCLK, VPO12, U20_DESC, VPO12_DESC); 1148 SIG_EXPR_DECL(VPOCLK, VPO24, U20_DESC, VPO24_DESC); 1149 SIG_EXPR_LIST_DECL_DUAL(VPOCLK, VPO12, VPO24); 1150 MS_PIN_DECL(U20, GPIOS3, ROMD7, VPOCLK); 1151 1152 #define R18 148 1153 #define ROMOE_DESC SIG_DESC_SET(SCU8C, 4) 1154 SIG_EXPR_LIST_DECL_SINGLE(GPIOS4, GPIOS4); 1155 SIG_EXPR_DECL(ROMOE, ROM8, ROMOE_DESC); 1156 SIG_EXPR_DECL(ROMOE, ROM16, ROMOE_DESC); 1157 SIG_EXPR_DECL(ROMOE, ROM16S, ROMOE_DESC); 1158 SIG_EXPR_LIST_DECL(ROMOE, SIG_EXPR_PTR(ROMOE, ROM8), 1159 SIG_EXPR_PTR(ROMOE, ROM16), 1160 SIG_EXPR_PTR(ROMOE, ROM16S)); 1161 MS_PIN_DECL_(R18, SIG_EXPR_LIST_PTR(ROMOE), SIG_EXPR_LIST_PTR(GPIOS4)); 1162 1163 #define N21 149 1164 #define ROMWE_DESC SIG_DESC_SET(SCU8C, 5) 1165 SIG_EXPR_LIST_DECL_SINGLE(GPIOS5, GPIOS5); 1166 SIG_EXPR_DECL(ROMWE, ROM8, ROMWE_DESC); 1167 SIG_EXPR_DECL(ROMWE, ROM16, ROMWE_DESC); 1168 SIG_EXPR_DECL(ROMWE, ROM16S, ROMWE_DESC); 1169 SIG_EXPR_LIST_DECL(ROMWE, SIG_EXPR_PTR(ROMWE, ROM8), 1170 SIG_EXPR_PTR(ROMWE, ROM16), 1171 SIG_EXPR_PTR(ROMWE, ROM16S)); 1172 MS_PIN_DECL_(N21, SIG_EXPR_LIST_PTR(ROMWE), SIG_EXPR_LIST_PTR(GPIOS5)); 1173 1174 #define L22 150 1175 #define L22_DESC SIG_DESC_SET(SCU8C, 6) 1176 SIG_EXPR_DECL(ROMA22, ROM8, L22_DESC, VPO_OFF_12); 1177 SIG_EXPR_DECL(ROMA22, ROM16, L22_DESC, VPO_OFF_12); 1178 SIG_EXPR_DECL(ROMA22, ROM16S, L22_DESC, VPO_OFF_12); 1179 SIG_EXPR_LIST_DECL(ROMA22, SIG_EXPR_PTR(ROMA22, ROM8), 1180 SIG_EXPR_PTR(ROMA22, ROM16), 1181 SIG_EXPR_PTR(ROMA22, ROM16S)); 1182 SIG_EXPR_LIST_DECL_SINGLE(VPOR4, VPO24, L22_DESC, VPO_24_OFF); 1183 MS_PIN_DECL(L22, GPIOS6, ROMA22, VPOR4); 1184 1185 #define K18 151 1186 #define K18_DESC SIG_DESC_SET(SCU8C, 7) 1187 SIG_EXPR_DECL(ROMA23, ROM8, K18_DESC, VPO_OFF_12); 1188 SIG_EXPR_DECL(ROMA23, ROM16, K18_DESC, VPO_OFF_12); 1189 SIG_EXPR_DECL(ROMA23, ROM16S, K18_DESC, VPO_OFF_12); 1190 SIG_EXPR_LIST_DECL(ROMA23, SIG_EXPR_PTR(ROMA23, ROM8), 1191 SIG_EXPR_PTR(ROMA23, ROM16), 1192 SIG_EXPR_PTR(ROMA23, ROM16S)); 1193 SIG_EXPR_LIST_DECL_SINGLE(VPOR5, VPO24, K18_DESC, VPO_24_OFF); 1194 MS_PIN_DECL(K18, GPIOS7, ROMA23, VPOR5); 1195 1196 #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0) 1197 1198 #define A12 152 1199 SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); 1200 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC); 1201 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1); 1202 MS_PIN_DECL_(A12, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1TXEN), 1203 SIG_EXPR_LIST_PTR(RGMII1TXCK)); 1204 1205 #define B12 153 1206 SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); 1207 SIG_EXPR_LIST_DECL_SINGLE(DASHB12, RMII1, RMII1_DESC); 1208 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1); 1209 MS_PIN_DECL_(B12, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(DASHB12), 1210 SIG_EXPR_LIST_PTR(RGMII1TXCTL)); 1211 1212 #define C12 154 1213 SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); 1214 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC); 1215 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1); 1216 MS_PIN_DECL_(C12, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0), 1217 SIG_EXPR_LIST_PTR(RGMII1TXD0)); 1218 1219 #define D12 155 1220 SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); 1221 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC); 1222 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1); 1223 MS_PIN_DECL_(D12, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1), 1224 SIG_EXPR_LIST_PTR(RGMII1TXD1)); 1225 1226 #define E12 156 1227 SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); 1228 SIG_EXPR_LIST_DECL_SINGLE(DASHE12, RMII1, RMII1_DESC); 1229 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1); 1230 MS_PIN_DECL_(E12, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(DASHE12), 1231 SIG_EXPR_LIST_PTR(RGMII1TXD2)); 1232 1233 #define A13 157 1234 SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); 1235 SIG_EXPR_LIST_DECL_SINGLE(DASHA13, RMII1, RMII1_DESC); 1236 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1); 1237 MS_PIN_DECL_(A13, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(DASHA13), 1238 SIG_EXPR_LIST_PTR(RGMII1TXD3)); 1239 1240 #define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0) 1241 1242 #define D9 158 1243 SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); 1244 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC); 1245 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2); 1246 MS_PIN_DECL_(D9, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2TXEN), 1247 SIG_EXPR_LIST_PTR(RGMII2TXCK)); 1248 1249 #define E9 159 1250 SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); 1251 SIG_EXPR_LIST_DECL_SINGLE(DASHE9, RMII2, RMII2_DESC); 1252 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2); 1253 MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(DASHE9), 1254 SIG_EXPR_LIST_PTR(RGMII2TXCTL)); 1255 1256 #define A10 160 1257 SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); 1258 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC); 1259 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2); 1260 MS_PIN_DECL_(A10, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0), 1261 SIG_EXPR_LIST_PTR(RGMII2TXD0)); 1262 1263 #define B10 161 1264 SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); 1265 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC); 1266 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2); 1267 MS_PIN_DECL_(B10, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1), 1268 SIG_EXPR_LIST_PTR(RGMII2TXD1)); 1269 1270 #define C10 162 1271 SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); 1272 SIG_EXPR_LIST_DECL_SINGLE(DASHC10, RMII2, RMII2_DESC); 1273 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2); 1274 MS_PIN_DECL_(C10, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(DASHC10), 1275 SIG_EXPR_LIST_PTR(RGMII2TXD2)); 1276 1277 #define D10 163 1278 SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); 1279 SIG_EXPR_LIST_DECL_SINGLE(DASHD10, RMII2, RMII2_DESC); 1280 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2); 1281 MS_PIN_DECL_(D10, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(DASHD10), 1282 SIG_EXPR_LIST_PTR(RGMII2TXD3)); 1283 1284 #define E11 164 1285 SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); 1286 SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLK, RMII1, RMII1_DESC); 1287 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1); 1288 MS_PIN_DECL_(E11, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLK), 1289 SIG_EXPR_LIST_PTR(RGMII1RXCK)); 1290 1291 #define D11 165 1292 SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); 1293 SIG_EXPR_LIST_DECL_SINGLE(DASHD11, RMII1, RMII1_DESC); 1294 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1); 1295 MS_PIN_DECL_(D11, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(DASHD11), 1296 SIG_EXPR_LIST_PTR(RGMII1RXCTL)); 1297 1298 #define C11 166 1299 SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); 1300 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC); 1301 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1); 1302 MS_PIN_DECL_(C11, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0), 1303 SIG_EXPR_LIST_PTR(RGMII1RXD0)); 1304 1305 #define B11 167 1306 SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); 1307 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC); 1308 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1); 1309 MS_PIN_DECL_(B11, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1), 1310 SIG_EXPR_LIST_PTR(RGMII1RXD1)); 1311 1312 #define A11 168 1313 SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); 1314 SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC); 1315 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1); 1316 MS_PIN_DECL_(A11, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV), 1317 SIG_EXPR_LIST_PTR(RGMII1RXD2)); 1318 1319 #define E10 169 1320 SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); 1321 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC); 1322 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1); 1323 MS_PIN_DECL_(E10, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER), 1324 SIG_EXPR_LIST_PTR(RGMII1RXD3)); 1325 1326 #define C9 170 1327 SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); 1328 SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLK, RMII2, RMII2_DESC); 1329 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2); 1330 MS_PIN_DECL_(C9, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLK), 1331 SIG_EXPR_LIST_PTR(RGMII2RXCK)); 1332 1333 #define B9 171 1334 SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); 1335 SIG_EXPR_LIST_DECL_SINGLE(DASHB9, RMII2, RMII2_DESC); 1336 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2); 1337 MS_PIN_DECL_(B9, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(DASHB9), 1338 SIG_EXPR_LIST_PTR(RGMII2RXCTL)); 1339 1340 #define A9 172 1341 SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); 1342 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC); 1343 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2); 1344 MS_PIN_DECL_(A9, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0), 1345 SIG_EXPR_LIST_PTR(RGMII2RXD0)); 1346 1347 #define E8 173 1348 SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); 1349 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC); 1350 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2); 1351 MS_PIN_DECL_(E8, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1), 1352 SIG_EXPR_LIST_PTR(RGMII2RXD1)); 1353 1354 #define D8 174 1355 SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); 1356 SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC); 1357 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2); 1358 MS_PIN_DECL_(D8, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV), 1359 SIG_EXPR_LIST_PTR(RGMII2RXD2)); 1360 1361 #define C8 175 1362 SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); 1363 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC); 1364 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2); 1365 MS_PIN_DECL_(C8, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER), 1366 SIG_EXPR_LIST_PTR(RGMII2RXD3)); 1367 1368 FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, 1369 E10); 1370 FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, 1371 E10); 1372 1373 FUNC_GROUP_DECL(RMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8); 1374 FUNC_GROUP_DECL(RGMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8); 1375 1376 #define L5 176 1377 SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); 1378 SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0); 1379 MS_PIN_DECL_(L5, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0)); 1380 FUNC_GROUP_DECL(ADC0, L5); 1381 1382 #define L4 177 1383 SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); 1384 SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1); 1385 MS_PIN_DECL_(L4, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1)); 1386 FUNC_GROUP_DECL(ADC1, L4); 1387 1388 #define L3 178 1389 SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); 1390 SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2); 1391 MS_PIN_DECL_(L3, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2)); 1392 FUNC_GROUP_DECL(ADC2, L3); 1393 1394 #define L2 179 1395 SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); 1396 SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3); 1397 MS_PIN_DECL_(L2, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3)); 1398 FUNC_GROUP_DECL(ADC3, L2); 1399 1400 #define L1 180 1401 SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); 1402 SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4); 1403 MS_PIN_DECL_(L1, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4)); 1404 FUNC_GROUP_DECL(ADC4, L1); 1405 1406 #define M5 181 1407 SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); 1408 SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5); 1409 MS_PIN_DECL_(M5, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5)); 1410 FUNC_GROUP_DECL(ADC5, M5); 1411 1412 #define M4 182 1413 SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); 1414 SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6); 1415 MS_PIN_DECL_(M4, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6)); 1416 FUNC_GROUP_DECL(ADC6, M4); 1417 1418 #define M3 183 1419 SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); 1420 SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7); 1421 MS_PIN_DECL_(M3, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7)); 1422 FUNC_GROUP_DECL(ADC7, M3); 1423 1424 #define M2 184 1425 SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); 1426 SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8); 1427 MS_PIN_DECL_(M2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8)); 1428 FUNC_GROUP_DECL(ADC8, M2); 1429 1430 #define M1 185 1431 SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); 1432 SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9); 1433 MS_PIN_DECL_(M1, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9)); 1434 FUNC_GROUP_DECL(ADC9, M1); 1435 1436 #define N5 186 1437 SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); 1438 SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10); 1439 MS_PIN_DECL_(N5, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10)); 1440 FUNC_GROUP_DECL(ADC10, N5); 1441 1442 #define N4 187 1443 SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); 1444 SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11); 1445 MS_PIN_DECL_(N4, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11)); 1446 FUNC_GROUP_DECL(ADC11, N4); 1447 1448 #define N3 188 1449 SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); 1450 SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12); 1451 MS_PIN_DECL_(N3, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12)); 1452 FUNC_GROUP_DECL(ADC12, N3); 1453 1454 #define N2 189 1455 SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); 1456 SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13); 1457 MS_PIN_DECL_(N2, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13)); 1458 FUNC_GROUP_DECL(ADC13, N2); 1459 1460 #define N1 190 1461 SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); 1462 SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14); 1463 MS_PIN_DECL_(N1, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14)); 1464 FUNC_GROUP_DECL(ADC14, N1); 1465 1466 #define P5 191 1467 SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); 1468 SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15); 1469 MS_PIN_DECL_(P5, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15)); 1470 FUNC_GROUP_DECL(ADC15, P5); 1471 1472 #define C21 192 1473 SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); 1474 SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC); 1475 SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI); 1476 SS_PIN_DECL(C21, GPIOY0, SIOS3); 1477 FUNC_GROUP_DECL(SIOS3, C21); 1478 1479 #define F20 193 1480 SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); 1481 SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC); 1482 SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI); 1483 SS_PIN_DECL(F20, GPIOY1, SIOS5); 1484 FUNC_GROUP_DECL(SIOS5, F20); 1485 1486 #define G20 194 1487 SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); 1488 SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC); 1489 SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI); 1490 SS_PIN_DECL(G20, GPIOY2, SIOPWREQ); 1491 FUNC_GROUP_DECL(SIOPWREQ, G20); 1492 1493 #define K20 195 1494 SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); 1495 SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC); 1496 SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI); 1497 SS_PIN_DECL(K20, GPIOY3, SIOONCTRL); 1498 FUNC_GROUP_DECL(SIOONCTRL, K20); 1499 1500 FUNC_GROUP_DECL(ACPI, B19, A20, D17, A19, C21, F20, G20, K20); 1501 1502 #define R22 200 1503 #define R22_DESC SIG_DESC_SET(SCUA4, 16) 1504 SIG_EXPR_DECL(ROMA2, ROM8, R22_DESC, VPOOFF0_DESC); 1505 SIG_EXPR_DECL(ROMA2, ROM16, R22_DESC, VPOOFF0_DESC); 1506 SIG_EXPR_LIST_DECL_DUAL(ROMA2, ROM8, ROM16); 1507 SIG_EXPR_DECL(VPOB0, VPO12, R22_DESC, VPO12_DESC); 1508 SIG_EXPR_DECL(VPOB0, VPO24, R22_DESC, VPO24_DESC); 1509 SIG_EXPR_DECL(VPOB0, VPOOFF1, R22_DESC, VPOOFF1_DESC); 1510 SIG_EXPR_LIST_DECL(VPOB0, SIG_EXPR_PTR(VPOB0, VPO12), 1511 SIG_EXPR_PTR(VPOB0, VPO24), SIG_EXPR_PTR(VPOB0, VPOOFF1)); 1512 MS_PIN_DECL(R22, GPIOZ0, ROMA2, VPOB0); 1513 1514 #define P18 201 1515 #define P18_DESC SIG_DESC_SET(SCUA4, 17) 1516 SIG_EXPR_DECL(ROMA3, ROM8, P18_DESC, VPOOFF0_DESC); 1517 SIG_EXPR_DECL(ROMA3, ROM16, P18_DESC, VPOOFF0_DESC); 1518 SIG_EXPR_LIST_DECL_DUAL(ROMA3, ROM8, ROM16); 1519 SIG_EXPR_DECL(VPOB1, VPO12, P18_DESC, VPO12_DESC); 1520 SIG_EXPR_DECL(VPOB1, VPO24, P18_DESC, VPO24_DESC); 1521 SIG_EXPR_DECL(VPOB1, VPOOFF1, P18_DESC, VPOOFF1_DESC); 1522 SIG_EXPR_LIST_DECL(VPOB1, SIG_EXPR_PTR(VPOB1, VPO12), 1523 SIG_EXPR_PTR(VPOB1, VPO24), SIG_EXPR_PTR(VPOB1, VPOOFF1)); 1524 MS_PIN_DECL(P18, GPIOZ1, ROMA3, VPOB1); 1525 1526 #define P19 202 1527 #define P19_DESC SIG_DESC_SET(SCUA4, 18) 1528 SIG_EXPR_DECL(ROMA4, ROM8, P19_DESC, VPOOFF0_DESC); 1529 SIG_EXPR_DECL(ROMA4, ROM16, P19_DESC, VPOOFF0_DESC); 1530 SIG_EXPR_LIST_DECL_DUAL(ROMA4, ROM8, ROM16); 1531 SIG_EXPR_DECL(VPOB2, VPO12, P19_DESC, VPO12_DESC); 1532 SIG_EXPR_DECL(VPOB2, VPO24, P19_DESC, VPO24_DESC); 1533 SIG_EXPR_DECL(VPOB2, VPOOFF1, P19_DESC, VPOOFF1_DESC); 1534 SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO12), 1535 SIG_EXPR_PTR(VPOB2, VPO24), SIG_EXPR_PTR(VPOB2, VPOOFF1)); 1536 MS_PIN_DECL(P19, GPIOZ2, ROMA4, VPOB2); 1537 1538 #define P20 203 1539 #define P20_DESC SIG_DESC_SET(SCUA4, 19) 1540 SIG_EXPR_DECL(ROMA5, ROM8, P20_DESC, VPOOFF0_DESC); 1541 SIG_EXPR_DECL(ROMA5, ROM16, P20_DESC, VPOOFF0_DESC); 1542 SIG_EXPR_LIST_DECL_DUAL(ROMA5, ROM8, ROM16); 1543 SIG_EXPR_DECL(VPOB3, VPO12, P20_DESC, VPO12_DESC); 1544 SIG_EXPR_DECL(VPOB3, VPO24, P20_DESC, VPO24_DESC); 1545 SIG_EXPR_DECL(VPOB3, VPOOFF1, P20_DESC, VPOOFF1_DESC); 1546 SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO12), 1547 SIG_EXPR_PTR(VPOB3, VPO24), SIG_EXPR_PTR(VPOB3, VPOOFF1)); 1548 MS_PIN_DECL(P20, GPIOZ3, ROMA5, VPOB3); 1549 1550 #define P21 204 1551 #define P21_DESC SIG_DESC_SET(SCUA4, 20) 1552 SIG_EXPR_DECL(ROMA6, ROM8, P21_DESC, VPOOFF0_DESC); 1553 SIG_EXPR_DECL(ROMA6, ROM16, P21_DESC, VPOOFF0_DESC); 1554 SIG_EXPR_LIST_DECL_DUAL(ROMA6, ROM8, ROM16); 1555 SIG_EXPR_DECL(VPOB4, VPO12, P21_DESC, VPO12_DESC); 1556 SIG_EXPR_DECL(VPOB4, VPO24, P21_DESC, VPO24_DESC); 1557 SIG_EXPR_DECL(VPOB4, VPOOFF1, P21_DESC, VPOOFF1_DESC); 1558 SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO12), 1559 SIG_EXPR_PTR(VPOB4, VPO24), SIG_EXPR_PTR(VPOB4, VPOOFF1)); 1560 MS_PIN_DECL(P21, GPIOZ4, ROMA6, VPOB4); 1561 1562 #define P22 205 1563 #define P22_DESC SIG_DESC_SET(SCUA4, 21) 1564 SIG_EXPR_DECL(ROMA7, ROM8, P22_DESC, VPOOFF0_DESC); 1565 SIG_EXPR_DECL(ROMA7, ROM16, P22_DESC, VPOOFF0_DESC); 1566 SIG_EXPR_LIST_DECL_DUAL(ROMA7, ROM8, ROM16); 1567 SIG_EXPR_DECL(VPOB5, VPO12, P22_DESC, VPO12_DESC); 1568 SIG_EXPR_DECL(VPOB5, VPO24, P22_DESC, VPO24_DESC); 1569 SIG_EXPR_DECL(VPOB5, VPOOFF1, P22_DESC, VPOOFF1_DESC); 1570 SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO12), 1571 SIG_EXPR_PTR(VPOB5, VPO24), SIG_EXPR_PTR(VPOB5, VPOOFF1)); 1572 MS_PIN_DECL(P22, GPIOZ5, ROMA7, VPOB5); 1573 1574 #define M19 206 1575 #define M19_DESC SIG_DESC_SET(SCUA4, 22) 1576 SIG_EXPR_DECL(ROMA8, ROM8, M19_DESC, VPOOFF0_DESC); 1577 SIG_EXPR_DECL(ROMA8, ROM16, M19_DESC, VPOOFF0_DESC); 1578 SIG_EXPR_LIST_DECL_DUAL(ROMA8, ROM8, ROM16); 1579 SIG_EXPR_DECL(VPOB6, VPO12, M19_DESC, VPO12_DESC); 1580 SIG_EXPR_DECL(VPOB6, VPO24, M19_DESC, VPO24_DESC); 1581 SIG_EXPR_DECL(VPOB6, VPOOFF1, M19_DESC, VPOOFF1_DESC); 1582 SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO12), 1583 SIG_EXPR_PTR(VPOB6, VPO24), SIG_EXPR_PTR(VPOB6, VPOOFF1)); 1584 MS_PIN_DECL(M19, GPIOZ6, ROMA8, VPOB6); 1585 1586 #define M20 207 1587 #define M20_DESC SIG_DESC_SET(SCUA4, 23) 1588 SIG_EXPR_DECL(ROMA9, ROM8, M20_DESC, VPOOFF0_DESC); 1589 SIG_EXPR_DECL(ROMA9, ROM16, M20_DESC, VPOOFF0_DESC); 1590 SIG_EXPR_LIST_DECL_DUAL(ROMA9, ROM8, ROM16); 1591 SIG_EXPR_DECL(VPOB7, VPO12, M20_DESC, VPO12_DESC); 1592 SIG_EXPR_DECL(VPOB7, VPO24, M20_DESC, VPO24_DESC); 1593 SIG_EXPR_DECL(VPOB7, VPOOFF1, M20_DESC, VPOOFF1_DESC); 1594 SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO12), 1595 SIG_EXPR_PTR(VPOB7, VPO24), SIG_EXPR_PTR(VPOB7, VPOOFF1)); 1596 MS_PIN_DECL(M20, GPIOZ7, ROMA9, VPOB7); 1597 1598 #define M21 208 1599 #define M21_DESC SIG_DESC_SET(SCUA4, 24) 1600 SIG_EXPR_DECL(ROMA10, ROM8, M21_DESC, VPOOFF0_DESC); 1601 SIG_EXPR_DECL(ROMA10, ROM16, M21_DESC, VPOOFF0_DESC); 1602 SIG_EXPR_LIST_DECL_DUAL(ROMA10, ROM8, ROM16); 1603 SIG_EXPR_DECL(VPOG0, VPO12, M21_DESC, VPO12_DESC); 1604 SIG_EXPR_DECL(VPOG0, VPO24, M21_DESC, VPO24_DESC); 1605 SIG_EXPR_DECL(VPOG0, VPOOFF1, M21_DESC, VPOOFF1_DESC); 1606 SIG_EXPR_LIST_DECL(VPOG0, SIG_EXPR_PTR(VPOG0, VPO12), 1607 SIG_EXPR_PTR(VPOG0, VPO24), SIG_EXPR_PTR(VPOG0, VPOOFF1)); 1608 MS_PIN_DECL(M21, GPIOAA0, ROMA10, VPOG0); 1609 1610 #define M22 209 1611 #define M22_DESC SIG_DESC_SET(SCUA4, 25) 1612 SIG_EXPR_DECL(ROMA11, ROM8, M22_DESC, VPOOFF0_DESC); 1613 SIG_EXPR_DECL(ROMA11, ROM16, M22_DESC, VPOOFF0_DESC); 1614 SIG_EXPR_LIST_DECL_DUAL(ROMA11, ROM8, ROM16); 1615 SIG_EXPR_DECL(VPOG1, VPO12, M22_DESC, VPO12_DESC); 1616 SIG_EXPR_DECL(VPOG1, VPO24, M22_DESC, VPO24_DESC); 1617 SIG_EXPR_DECL(VPOG1, VPOOFF1, M22_DESC, VPOOFF1_DESC); 1618 SIG_EXPR_LIST_DECL(VPOG1, SIG_EXPR_PTR(VPOG1, VPO12), 1619 SIG_EXPR_PTR(VPOG1, VPO24), SIG_EXPR_PTR(VPOG1, VPOOFF1)); 1620 MS_PIN_DECL(M22, GPIOAA1, ROMA11, VPOG1); 1621 1622 #define L18 210 1623 #define L18_DESC SIG_DESC_SET(SCUA4, 26) 1624 SIG_EXPR_DECL(ROMA12, ROM8, L18_DESC, VPOOFF0_DESC); 1625 SIG_EXPR_DECL(ROMA12, ROM16, L18_DESC, VPOOFF0_DESC); 1626 SIG_EXPR_LIST_DECL_DUAL(ROMA12, ROM8, ROM16); 1627 SIG_EXPR_DECL(VPOG2, VPO12, L18_DESC, VPO12_DESC); 1628 SIG_EXPR_DECL(VPOG2, VPO24, L18_DESC, VPO24_DESC); 1629 SIG_EXPR_DECL(VPOG2, VPOOFF1, L18_DESC, VPOOFF1_DESC); 1630 SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO12), 1631 SIG_EXPR_PTR(VPOG2, VPO24), SIG_EXPR_PTR(VPOG2, VPOOFF1)); 1632 MS_PIN_DECL(L18, GPIOAA2, ROMA12, VPOG2); 1633 1634 #define L19 211 1635 #define L19_DESC SIG_DESC_SET(SCUA4, 27) 1636 SIG_EXPR_DECL(ROMA13, ROM8, L19_DESC, VPOOFF0_DESC); 1637 SIG_EXPR_DECL(ROMA13, ROM16, L19_DESC, VPOOFF0_DESC); 1638 SIG_EXPR_LIST_DECL_DUAL(ROMA13, ROM8, ROM16); 1639 SIG_EXPR_DECL(VPOG3, VPO12, L19_DESC, VPO12_DESC); 1640 SIG_EXPR_DECL(VPOG3, VPO24, L19_DESC, VPO24_DESC); 1641 SIG_EXPR_DECL(VPOG3, VPOOFF1, L19_DESC, VPOOFF1_DESC); 1642 SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO12), 1643 SIG_EXPR_PTR(VPOG3, VPO24), SIG_EXPR_PTR(VPOG3, VPOOFF1)); 1644 MS_PIN_DECL(L19, GPIOAA3, ROMA13, VPOG3); 1645 1646 #define L20 212 1647 #define L20_DESC SIG_DESC_SET(SCUA4, 28) 1648 SIG_EXPR_DECL(ROMA14, ROM8, L20_DESC, VPO_OFF_12); 1649 SIG_EXPR_DECL(ROMA14, ROM16, L20_DESC, VPO_OFF_12); 1650 SIG_EXPR_LIST_DECL_DUAL(ROMA14, ROM8, ROM16); 1651 SIG_EXPR_DECL(VPOG4, VPO24, L20_DESC, VPO24_DESC); 1652 SIG_EXPR_DECL(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC); 1653 SIG_EXPR_LIST_DECL_DUAL(VPOG4, VPO24, VPOOFF1); 1654 MS_PIN_DECL(L20, GPIOAA4, ROMA14, VPOG4); 1655 1656 #define L21 213 1657 #define L21_DESC SIG_DESC_SET(SCUA4, 29) 1658 SIG_EXPR_DECL(ROMA15, ROM8, L21_DESC, VPO_OFF_12); 1659 SIG_EXPR_DECL(ROMA15, ROM16, L21_DESC, VPO_OFF_12); 1660 SIG_EXPR_LIST_DECL_DUAL(ROMA15, ROM8, ROM16); 1661 SIG_EXPR_DECL(VPOG5, VPO24, L21_DESC, VPO24_DESC); 1662 SIG_EXPR_DECL(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC); 1663 SIG_EXPR_LIST_DECL_DUAL(VPOG5, VPO24, VPOOFF1); 1664 MS_PIN_DECL(L21, GPIOAA5, ROMA15, VPOG5); 1665 1666 #define T18 214 1667 #define T18_DESC SIG_DESC_SET(SCUA4, 30) 1668 SIG_EXPR_DECL(ROMA16, ROM8, T18_DESC, VPO_OFF_12); 1669 SIG_EXPR_DECL(ROMA16, ROM16, T18_DESC, VPO_OFF_12); 1670 SIG_EXPR_LIST_DECL_DUAL(ROMA16, ROM8, ROM16); 1671 SIG_EXPR_DECL(VPOG6, VPO24, T18_DESC, VPO24_DESC); 1672 SIG_EXPR_DECL(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC); 1673 SIG_EXPR_LIST_DECL_DUAL(VPOG6, VPO24, VPOOFF1); 1674 MS_PIN_DECL(T18, GPIOAA6, ROMA16, VPOG6); 1675 1676 #define N18 215 1677 #define N18_DESC SIG_DESC_SET(SCUA4, 31) 1678 SIG_EXPR_DECL(ROMA17, ROM8, N18_DESC, VPO_OFF_12); 1679 SIG_EXPR_DECL(ROMA17, ROM16, N18_DESC, VPO_OFF_12); 1680 SIG_EXPR_LIST_DECL_DUAL(ROMA17, ROM8, ROM16); 1681 SIG_EXPR_DECL(VPOG7, VPO24, N18_DESC, VPO24_DESC); 1682 SIG_EXPR_DECL(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC); 1683 SIG_EXPR_LIST_DECL_DUAL(VPOG7, VPO24, VPOOFF1); 1684 MS_PIN_DECL(N18, GPIOAA7, ROMA17, VPOG7); 1685 1686 #define N19 216 1687 #define N19_DESC SIG_DESC_SET(SCUA8, 0) 1688 SIG_EXPR_DECL(ROMA18, ROM8, N19_DESC, VPO_OFF_12); 1689 SIG_EXPR_DECL(ROMA18, ROM16, N19_DESC, VPO_OFF_12); 1690 SIG_EXPR_LIST_DECL_DUAL(ROMA18, ROM8, ROM16); 1691 SIG_EXPR_DECL(VPOR0, VPO24, N19_DESC, VPO24_DESC); 1692 SIG_EXPR_DECL(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC); 1693 SIG_EXPR_LIST_DECL_DUAL(VPOR0, VPO24, VPOOFF1); 1694 MS_PIN_DECL(N19, GPIOAB0, ROMA18, VPOR0); 1695 1696 #define M18 217 1697 #define M18_DESC SIG_DESC_SET(SCUA8, 1) 1698 SIG_EXPR_DECL(ROMA19, ROM8, M18_DESC, VPO_OFF_12); 1699 SIG_EXPR_DECL(ROMA19, ROM16, M18_DESC, VPO_OFF_12); 1700 SIG_EXPR_LIST_DECL_DUAL(ROMA19, ROM8, ROM16); 1701 SIG_EXPR_DECL(VPOR1, VPO24, M18_DESC, VPO24_DESC); 1702 SIG_EXPR_DECL(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC); 1703 SIG_EXPR_LIST_DECL_DUAL(VPOR1, VPO24, VPOOFF1); 1704 MS_PIN_DECL(M18, GPIOAB1, ROMA19, VPOR1); 1705 1706 #define N22 218 1707 #define N22_DESC SIG_DESC_SET(SCUA8, 2) 1708 SIG_EXPR_DECL(ROMA20, ROM8, N22_DESC, VPO_OFF_12); 1709 SIG_EXPR_DECL(ROMA20, ROM16, N22_DESC, VPO_OFF_12); 1710 SIG_EXPR_LIST_DECL_DUAL(ROMA20, ROM8, ROM16); 1711 SIG_EXPR_DECL(VPOR2, VPO24, N22_DESC, VPO24_DESC); 1712 SIG_EXPR_DECL(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC); 1713 SIG_EXPR_LIST_DECL_DUAL(VPOR2, VPO24, VPOOFF1); 1714 MS_PIN_DECL(N22, GPIOAB2, ROMA20, VPOR2); 1715 1716 #define N20 219 1717 #define N20_DESC SIG_DESC_SET(SCUA8, 3) 1718 SIG_EXPR_DECL(ROMA21, ROM8, N20_DESC, VPO_OFF_12); 1719 SIG_EXPR_DECL(ROMA21, ROM16, N20_DESC, VPO_OFF_12); 1720 SIG_EXPR_LIST_DECL_DUAL(ROMA21, ROM8, ROM16); 1721 SIG_EXPR_DECL(VPOR3, VPO24, N20_DESC, VPO24_DESC); 1722 SIG_EXPR_DECL(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC); 1723 SIG_EXPR_LIST_DECL_DUAL(VPOR3, VPO24, VPOOFF1); 1724 MS_PIN_DECL(N20, GPIOAB3, ROMA21, VPOR3); 1725 1726 FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22, 1727 U19, R22, P18, P19, P20, P21, P22, M19, M20, M21, M22, L18, 1728 L19, L20, L21, T18, N18, N19, M18, N22, N20); 1729 FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18, 1730 A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19, R22, P18, P19, 1731 P20, P21, P22, M19, M20, M21, M22, L18, L19, L20, L21, T18, 1732 N18, N19, M18, N22, N20); 1733 FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19, 1734 M20, M21, M22, L18, L19, L20, L21, T18, N18, N19, M18, N22, 1735 N20); 1736 FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19, 1737 P20, P21, P22, M19, M20, M21, M22, L18, L19); 1738 1739 #define USB11H2_DESC SIG_DESC_SET(SCU90, 3) 1740 #define USB11D1_DESC SIG_DESC_BIT(SCU90, 3, 0) 1741 1742 #define K4 220 1743 SIG_EXPR_LIST_DECL_SINGLE(USB11HDP2, USB11H2, USB11H2_DESC); 1744 SIG_EXPR_LIST_DECL_SINGLE(USB11DP1, USB11D1, USB11D1_DESC); 1745 MS_PIN_DECL_(K4, SIG_EXPR_LIST_PTR(USB11HDP2), SIG_EXPR_LIST_PTR(USB11DP1)); 1746 1747 #define K3 221 1748 SIG_EXPR_LIST_DECL_SINGLE(USB11HDN1, USB11H2, USB11H2_DESC); 1749 SIG_EXPR_LIST_DECL_SINGLE(USB11DDN1, USB11D1, USB11D1_DESC); 1750 MS_PIN_DECL_(K3, SIG_EXPR_LIST_PTR(USB11HDN1), SIG_EXPR_LIST_PTR(USB11DDN1)); 1751 1752 FUNC_GROUP_DECL(USB11H2, K4, K3); 1753 FUNC_GROUP_DECL(USB11D1, K4, K3); 1754 1755 #define USB2H1_DESC SIG_DESC_SET(SCU90, 29) 1756 #define USB2D1_DESC SIG_DESC_BIT(SCU90, 29, 0) 1757 1758 #define AB21 222 1759 SIG_EXPR_LIST_DECL_SINGLE(USB2HDP1, USB2H1, USB2H1_DESC); 1760 SIG_EXPR_LIST_DECL_SINGLE(USB2DDP1, USB2D1, USB2D1_DESC); 1761 MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(USB2HDP1), SIG_EXPR_LIST_PTR(USB2DDP1)); 1762 1763 #define AB20 223 1764 SIG_EXPR_LIST_DECL_SINGLE(USB2HDN1, USB2H1, USB2H1_DESC); 1765 SIG_EXPR_LIST_DECL_SINGLE(USB2DDN1, USB2D1, USB2D1_DESC); 1766 MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(USB2HDN1), SIG_EXPR_LIST_PTR(USB2DDN1)); 1767 1768 FUNC_GROUP_DECL(USB2H1, AB21, AB20); 1769 FUNC_GROUP_DECL(USB2D1, AB21, AB20); 1770 1771 /* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216 1772 * pins becomes 220. Four additional non-GPIO-capable pins are present for USB. 1773 */ 1774 #define ASPEED_G4_NR_PINS 224 1775 1776 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ 1777 1778 static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = { 1779 ASPEED_PINCTRL_PIN(A1), 1780 ASPEED_PINCTRL_PIN(A10), 1781 ASPEED_PINCTRL_PIN(A11), 1782 ASPEED_PINCTRL_PIN(A12), 1783 ASPEED_PINCTRL_PIN(A13), 1784 ASPEED_PINCTRL_PIN(A14), 1785 ASPEED_PINCTRL_PIN(A15), 1786 ASPEED_PINCTRL_PIN(A16), 1787 ASPEED_PINCTRL_PIN(A17), 1788 ASPEED_PINCTRL_PIN(A18), 1789 ASPEED_PINCTRL_PIN(A19), 1790 ASPEED_PINCTRL_PIN(A2), 1791 ASPEED_PINCTRL_PIN(A20), 1792 ASPEED_PINCTRL_PIN(A3), 1793 ASPEED_PINCTRL_PIN(A4), 1794 ASPEED_PINCTRL_PIN(A5), 1795 ASPEED_PINCTRL_PIN(A6), 1796 ASPEED_PINCTRL_PIN(A7), 1797 ASPEED_PINCTRL_PIN(A8), 1798 ASPEED_PINCTRL_PIN(A9), 1799 ASPEED_PINCTRL_PIN(AA1), 1800 ASPEED_PINCTRL_PIN(AA2), 1801 ASPEED_PINCTRL_PIN(AA22), 1802 ASPEED_PINCTRL_PIN(AA3), 1803 ASPEED_PINCTRL_PIN(AA4), 1804 ASPEED_PINCTRL_PIN(AA5), 1805 ASPEED_PINCTRL_PIN(AA6), 1806 ASPEED_PINCTRL_PIN(AA7), 1807 ASPEED_PINCTRL_PIN(AB1), 1808 ASPEED_PINCTRL_PIN(AB2), 1809 ASPEED_PINCTRL_PIN(AB3), 1810 ASPEED_PINCTRL_PIN(AB4), 1811 ASPEED_PINCTRL_PIN(AB5), 1812 ASPEED_PINCTRL_PIN(AB6), 1813 ASPEED_PINCTRL_PIN(AB7), 1814 ASPEED_PINCTRL_PIN(AB20), 1815 ASPEED_PINCTRL_PIN(AB21), 1816 ASPEED_PINCTRL_PIN(B1), 1817 ASPEED_PINCTRL_PIN(B10), 1818 ASPEED_PINCTRL_PIN(B11), 1819 ASPEED_PINCTRL_PIN(B12), 1820 ASPEED_PINCTRL_PIN(B13), 1821 ASPEED_PINCTRL_PIN(B14), 1822 ASPEED_PINCTRL_PIN(B15), 1823 ASPEED_PINCTRL_PIN(B16), 1824 ASPEED_PINCTRL_PIN(B17), 1825 ASPEED_PINCTRL_PIN(B18), 1826 ASPEED_PINCTRL_PIN(B19), 1827 ASPEED_PINCTRL_PIN(B2), 1828 ASPEED_PINCTRL_PIN(B22), 1829 ASPEED_PINCTRL_PIN(B3), 1830 ASPEED_PINCTRL_PIN(B4), 1831 ASPEED_PINCTRL_PIN(B5), 1832 ASPEED_PINCTRL_PIN(B6), 1833 ASPEED_PINCTRL_PIN(B7), 1834 ASPEED_PINCTRL_PIN(B9), 1835 ASPEED_PINCTRL_PIN(C1), 1836 ASPEED_PINCTRL_PIN(C10), 1837 ASPEED_PINCTRL_PIN(C11), 1838 ASPEED_PINCTRL_PIN(C12), 1839 ASPEED_PINCTRL_PIN(C13), 1840 ASPEED_PINCTRL_PIN(C14), 1841 ASPEED_PINCTRL_PIN(C15), 1842 ASPEED_PINCTRL_PIN(C16), 1843 ASPEED_PINCTRL_PIN(C17), 1844 ASPEED_PINCTRL_PIN(C18), 1845 ASPEED_PINCTRL_PIN(C2), 1846 ASPEED_PINCTRL_PIN(C20), 1847 ASPEED_PINCTRL_PIN(C21), 1848 ASPEED_PINCTRL_PIN(C22), 1849 ASPEED_PINCTRL_PIN(C3), 1850 ASPEED_PINCTRL_PIN(C4), 1851 ASPEED_PINCTRL_PIN(C5), 1852 ASPEED_PINCTRL_PIN(C6), 1853 ASPEED_PINCTRL_PIN(C7), 1854 ASPEED_PINCTRL_PIN(C8), 1855 ASPEED_PINCTRL_PIN(C9), 1856 ASPEED_PINCTRL_PIN(D1), 1857 ASPEED_PINCTRL_PIN(D10), 1858 ASPEED_PINCTRL_PIN(D11), 1859 ASPEED_PINCTRL_PIN(D12), 1860 ASPEED_PINCTRL_PIN(D13), 1861 ASPEED_PINCTRL_PIN(D14), 1862 ASPEED_PINCTRL_PIN(D15), 1863 ASPEED_PINCTRL_PIN(D16), 1864 ASPEED_PINCTRL_PIN(D17), 1865 ASPEED_PINCTRL_PIN(D18), 1866 ASPEED_PINCTRL_PIN(D19), 1867 ASPEED_PINCTRL_PIN(D2), 1868 ASPEED_PINCTRL_PIN(D3), 1869 ASPEED_PINCTRL_PIN(D4), 1870 ASPEED_PINCTRL_PIN(D5), 1871 ASPEED_PINCTRL_PIN(D6), 1872 ASPEED_PINCTRL_PIN(D7), 1873 ASPEED_PINCTRL_PIN(D8), 1874 ASPEED_PINCTRL_PIN(D9), 1875 ASPEED_PINCTRL_PIN(E10), 1876 ASPEED_PINCTRL_PIN(E11), 1877 ASPEED_PINCTRL_PIN(E12), 1878 ASPEED_PINCTRL_PIN(E13), 1879 ASPEED_PINCTRL_PIN(E14), 1880 ASPEED_PINCTRL_PIN(E15), 1881 ASPEED_PINCTRL_PIN(E16), 1882 ASPEED_PINCTRL_PIN(E18), 1883 ASPEED_PINCTRL_PIN(E19), 1884 ASPEED_PINCTRL_PIN(E2), 1885 ASPEED_PINCTRL_PIN(E20), 1886 ASPEED_PINCTRL_PIN(E3), 1887 ASPEED_PINCTRL_PIN(E5), 1888 ASPEED_PINCTRL_PIN(E6), 1889 ASPEED_PINCTRL_PIN(E7), 1890 ASPEED_PINCTRL_PIN(E8), 1891 ASPEED_PINCTRL_PIN(E9), 1892 ASPEED_PINCTRL_PIN(F18), 1893 ASPEED_PINCTRL_PIN(F20), 1894 ASPEED_PINCTRL_PIN(F3), 1895 ASPEED_PINCTRL_PIN(F4), 1896 ASPEED_PINCTRL_PIN(F5), 1897 ASPEED_PINCTRL_PIN(G18), 1898 ASPEED_PINCTRL_PIN(G19), 1899 ASPEED_PINCTRL_PIN(G20), 1900 ASPEED_PINCTRL_PIN(G5), 1901 ASPEED_PINCTRL_PIN(H1), 1902 ASPEED_PINCTRL_PIN(H18), 1903 ASPEED_PINCTRL_PIN(H19), 1904 ASPEED_PINCTRL_PIN(H2), 1905 ASPEED_PINCTRL_PIN(H20), 1906 ASPEED_PINCTRL_PIN(H3), 1907 ASPEED_PINCTRL_PIN(H4), 1908 ASPEED_PINCTRL_PIN(J20), 1909 ASPEED_PINCTRL_PIN(J21), 1910 ASPEED_PINCTRL_PIN(J3), 1911 ASPEED_PINCTRL_PIN(J4), 1912 ASPEED_PINCTRL_PIN(J5), 1913 ASPEED_PINCTRL_PIN(K18), 1914 ASPEED_PINCTRL_PIN(K20), 1915 ASPEED_PINCTRL_PIN(K3), 1916 ASPEED_PINCTRL_PIN(K4), 1917 ASPEED_PINCTRL_PIN(K5), 1918 ASPEED_PINCTRL_PIN(L1), 1919 ASPEED_PINCTRL_PIN(L18), 1920 ASPEED_PINCTRL_PIN(L19), 1921 ASPEED_PINCTRL_PIN(L2), 1922 ASPEED_PINCTRL_PIN(L20), 1923 ASPEED_PINCTRL_PIN(L21), 1924 ASPEED_PINCTRL_PIN(L22), 1925 ASPEED_PINCTRL_PIN(L3), 1926 ASPEED_PINCTRL_PIN(L4), 1927 ASPEED_PINCTRL_PIN(L5), 1928 ASPEED_PINCTRL_PIN(M1), 1929 ASPEED_PINCTRL_PIN(M18), 1930 ASPEED_PINCTRL_PIN(M19), 1931 ASPEED_PINCTRL_PIN(M2), 1932 ASPEED_PINCTRL_PIN(M20), 1933 ASPEED_PINCTRL_PIN(M21), 1934 ASPEED_PINCTRL_PIN(M22), 1935 ASPEED_PINCTRL_PIN(M3), 1936 ASPEED_PINCTRL_PIN(M4), 1937 ASPEED_PINCTRL_PIN(M5), 1938 ASPEED_PINCTRL_PIN(N1), 1939 ASPEED_PINCTRL_PIN(N18), 1940 ASPEED_PINCTRL_PIN(N19), 1941 ASPEED_PINCTRL_PIN(N2), 1942 ASPEED_PINCTRL_PIN(N20), 1943 ASPEED_PINCTRL_PIN(N21), 1944 ASPEED_PINCTRL_PIN(N22), 1945 ASPEED_PINCTRL_PIN(N3), 1946 ASPEED_PINCTRL_PIN(N4), 1947 ASPEED_PINCTRL_PIN(N5), 1948 ASPEED_PINCTRL_PIN(P18), 1949 ASPEED_PINCTRL_PIN(P19), 1950 ASPEED_PINCTRL_PIN(P20), 1951 ASPEED_PINCTRL_PIN(P21), 1952 ASPEED_PINCTRL_PIN(P22), 1953 ASPEED_PINCTRL_PIN(P5), 1954 ASPEED_PINCTRL_PIN(R18), 1955 ASPEED_PINCTRL_PIN(R22), 1956 ASPEED_PINCTRL_PIN(T1), 1957 ASPEED_PINCTRL_PIN(T18), 1958 ASPEED_PINCTRL_PIN(T19), 1959 ASPEED_PINCTRL_PIN(T2), 1960 ASPEED_PINCTRL_PIN(T4), 1961 ASPEED_PINCTRL_PIN(T5), 1962 ASPEED_PINCTRL_PIN(U1), 1963 ASPEED_PINCTRL_PIN(U18), 1964 ASPEED_PINCTRL_PIN(U19), 1965 ASPEED_PINCTRL_PIN(U2), 1966 ASPEED_PINCTRL_PIN(U20), 1967 ASPEED_PINCTRL_PIN(U21), 1968 ASPEED_PINCTRL_PIN(U3), 1969 ASPEED_PINCTRL_PIN(U4), 1970 ASPEED_PINCTRL_PIN(U5), 1971 ASPEED_PINCTRL_PIN(V1), 1972 ASPEED_PINCTRL_PIN(V2), 1973 ASPEED_PINCTRL_PIN(V20), 1974 ASPEED_PINCTRL_PIN(V21), 1975 ASPEED_PINCTRL_PIN(V22), 1976 ASPEED_PINCTRL_PIN(V3), 1977 ASPEED_PINCTRL_PIN(V4), 1978 ASPEED_PINCTRL_PIN(V5), 1979 ASPEED_PINCTRL_PIN(V6), 1980 ASPEED_PINCTRL_PIN(V7), 1981 ASPEED_PINCTRL_PIN(W1), 1982 ASPEED_PINCTRL_PIN(W2), 1983 ASPEED_PINCTRL_PIN(W21), 1984 ASPEED_PINCTRL_PIN(W22), 1985 ASPEED_PINCTRL_PIN(W3), 1986 ASPEED_PINCTRL_PIN(W4), 1987 ASPEED_PINCTRL_PIN(W5), 1988 ASPEED_PINCTRL_PIN(W6), 1989 ASPEED_PINCTRL_PIN(W7), 1990 ASPEED_PINCTRL_PIN(Y1), 1991 ASPEED_PINCTRL_PIN(Y2), 1992 ASPEED_PINCTRL_PIN(Y21), 1993 ASPEED_PINCTRL_PIN(Y22), 1994 ASPEED_PINCTRL_PIN(Y3), 1995 ASPEED_PINCTRL_PIN(Y4), 1996 ASPEED_PINCTRL_PIN(Y5), 1997 ASPEED_PINCTRL_PIN(Y6), 1998 ASPEED_PINCTRL_PIN(Y7), 1999 }; 2000 2001 static const struct aspeed_pin_group aspeed_g4_groups[] = { 2002 ASPEED_PINCTRL_GROUP(ACPI), 2003 ASPEED_PINCTRL_GROUP(ADC0), 2004 ASPEED_PINCTRL_GROUP(ADC1), 2005 ASPEED_PINCTRL_GROUP(ADC10), 2006 ASPEED_PINCTRL_GROUP(ADC11), 2007 ASPEED_PINCTRL_GROUP(ADC12), 2008 ASPEED_PINCTRL_GROUP(ADC13), 2009 ASPEED_PINCTRL_GROUP(ADC14), 2010 ASPEED_PINCTRL_GROUP(ADC15), 2011 ASPEED_PINCTRL_GROUP(ADC2), 2012 ASPEED_PINCTRL_GROUP(ADC3), 2013 ASPEED_PINCTRL_GROUP(ADC4), 2014 ASPEED_PINCTRL_GROUP(ADC5), 2015 ASPEED_PINCTRL_GROUP(ADC6), 2016 ASPEED_PINCTRL_GROUP(ADC7), 2017 ASPEED_PINCTRL_GROUP(ADC8), 2018 ASPEED_PINCTRL_GROUP(ADC9), 2019 ASPEED_PINCTRL_GROUP(BMCINT), 2020 ASPEED_PINCTRL_GROUP(DDCCLK), 2021 ASPEED_PINCTRL_GROUP(DDCDAT), 2022 ASPEED_PINCTRL_GROUP(EXTRST), 2023 ASPEED_PINCTRL_GROUP(FLACK), 2024 ASPEED_PINCTRL_GROUP(FLBUSY), 2025 ASPEED_PINCTRL_GROUP(FLWP), 2026 ASPEED_PINCTRL_GROUP(GPID), 2027 ASPEED_PINCTRL_GROUP(GPID0), 2028 ASPEED_PINCTRL_GROUP(GPID2), 2029 ASPEED_PINCTRL_GROUP(GPID4), 2030 ASPEED_PINCTRL_GROUP(GPID6), 2031 ASPEED_PINCTRL_GROUP(GPIE0), 2032 ASPEED_PINCTRL_GROUP(GPIE2), 2033 ASPEED_PINCTRL_GROUP(GPIE4), 2034 ASPEED_PINCTRL_GROUP(GPIE6), 2035 ASPEED_PINCTRL_GROUP(I2C10), 2036 ASPEED_PINCTRL_GROUP(I2C11), 2037 ASPEED_PINCTRL_GROUP(I2C12), 2038 ASPEED_PINCTRL_GROUP(I2C13), 2039 ASPEED_PINCTRL_GROUP(I2C14), 2040 ASPEED_PINCTRL_GROUP(I2C3), 2041 ASPEED_PINCTRL_GROUP(I2C4), 2042 ASPEED_PINCTRL_GROUP(I2C5), 2043 ASPEED_PINCTRL_GROUP(I2C6), 2044 ASPEED_PINCTRL_GROUP(I2C7), 2045 ASPEED_PINCTRL_GROUP(I2C8), 2046 ASPEED_PINCTRL_GROUP(I2C9), 2047 ASPEED_PINCTRL_GROUP(LPCPD), 2048 ASPEED_PINCTRL_GROUP(LPCPME), 2049 ASPEED_PINCTRL_GROUP(LPCRST), 2050 ASPEED_PINCTRL_GROUP(LPCSMI), 2051 ASPEED_PINCTRL_GROUP(MAC1LINK), 2052 ASPEED_PINCTRL_GROUP(MAC2LINK), 2053 ASPEED_PINCTRL_GROUP(MDIO1), 2054 ASPEED_PINCTRL_GROUP(MDIO2), 2055 ASPEED_PINCTRL_GROUP(NCTS1), 2056 ASPEED_PINCTRL_GROUP(NCTS2), 2057 ASPEED_PINCTRL_GROUP(NCTS3), 2058 ASPEED_PINCTRL_GROUP(NCTS4), 2059 ASPEED_PINCTRL_GROUP(NDCD1), 2060 ASPEED_PINCTRL_GROUP(NDCD2), 2061 ASPEED_PINCTRL_GROUP(NDCD3), 2062 ASPEED_PINCTRL_GROUP(NDCD4), 2063 ASPEED_PINCTRL_GROUP(NDSR1), 2064 ASPEED_PINCTRL_GROUP(NDSR2), 2065 ASPEED_PINCTRL_GROUP(NDSR3), 2066 ASPEED_PINCTRL_GROUP(NDSR4), 2067 ASPEED_PINCTRL_GROUP(NDTR1), 2068 ASPEED_PINCTRL_GROUP(NDTR2), 2069 ASPEED_PINCTRL_GROUP(NDTR3), 2070 ASPEED_PINCTRL_GROUP(NDTR4), 2071 ASPEED_PINCTRL_GROUP(NDTS4), 2072 ASPEED_PINCTRL_GROUP(NRI1), 2073 ASPEED_PINCTRL_GROUP(NRI2), 2074 ASPEED_PINCTRL_GROUP(NRI3), 2075 ASPEED_PINCTRL_GROUP(NRI4), 2076 ASPEED_PINCTRL_GROUP(NRTS1), 2077 ASPEED_PINCTRL_GROUP(NRTS2), 2078 ASPEED_PINCTRL_GROUP(NRTS3), 2079 ASPEED_PINCTRL_GROUP(OSCCLK), 2080 ASPEED_PINCTRL_GROUP(PWM0), 2081 ASPEED_PINCTRL_GROUP(PWM1), 2082 ASPEED_PINCTRL_GROUP(PWM2), 2083 ASPEED_PINCTRL_GROUP(PWM3), 2084 ASPEED_PINCTRL_GROUP(PWM4), 2085 ASPEED_PINCTRL_GROUP(PWM5), 2086 ASPEED_PINCTRL_GROUP(PWM6), 2087 ASPEED_PINCTRL_GROUP(PWM7), 2088 ASPEED_PINCTRL_GROUP(RGMII1), 2089 ASPEED_PINCTRL_GROUP(RGMII2), 2090 ASPEED_PINCTRL_GROUP(RMII1), 2091 ASPEED_PINCTRL_GROUP(RMII2), 2092 ASPEED_PINCTRL_GROUP(ROM16), 2093 ASPEED_PINCTRL_GROUP(ROM8), 2094 ASPEED_PINCTRL_GROUP(ROMCS1), 2095 ASPEED_PINCTRL_GROUP(ROMCS2), 2096 ASPEED_PINCTRL_GROUP(ROMCS3), 2097 ASPEED_PINCTRL_GROUP(ROMCS4), 2098 ASPEED_PINCTRL_GROUP(RXD1), 2099 ASPEED_PINCTRL_GROUP(RXD2), 2100 ASPEED_PINCTRL_GROUP(RXD3), 2101 ASPEED_PINCTRL_GROUP(RXD4), 2102 ASPEED_PINCTRL_GROUP(SALT1), 2103 ASPEED_PINCTRL_GROUP(SALT2), 2104 ASPEED_PINCTRL_GROUP(SALT3), 2105 ASPEED_PINCTRL_GROUP(SALT4), 2106 ASPEED_PINCTRL_GROUP(SD1), 2107 ASPEED_PINCTRL_GROUP(SD2), 2108 ASPEED_PINCTRL_GROUP(SGPMCK), 2109 ASPEED_PINCTRL_GROUP(SGPMI), 2110 ASPEED_PINCTRL_GROUP(SGPMLD), 2111 ASPEED_PINCTRL_GROUP(SGPMO), 2112 ASPEED_PINCTRL_GROUP(SGPSCK), 2113 ASPEED_PINCTRL_GROUP(SGPSI0), 2114 ASPEED_PINCTRL_GROUP(SGPSI1), 2115 ASPEED_PINCTRL_GROUP(SGPSLD), 2116 ASPEED_PINCTRL_GROUP(SIOONCTRL), 2117 ASPEED_PINCTRL_GROUP(SIOPBI), 2118 ASPEED_PINCTRL_GROUP(SIOPBO), 2119 ASPEED_PINCTRL_GROUP(SIOPWREQ), 2120 ASPEED_PINCTRL_GROUP(SIOPWRGD), 2121 ASPEED_PINCTRL_GROUP(SIOS3), 2122 ASPEED_PINCTRL_GROUP(SIOS5), 2123 ASPEED_PINCTRL_GROUP(SIOSCI), 2124 ASPEED_PINCTRL_GROUP(SPI1), 2125 ASPEED_PINCTRL_GROUP(SPI1DEBUG), 2126 ASPEED_PINCTRL_GROUP(SPI1PASSTHRU), 2127 ASPEED_PINCTRL_GROUP(SPICS1), 2128 ASPEED_PINCTRL_GROUP(TIMER3), 2129 ASPEED_PINCTRL_GROUP(TIMER4), 2130 ASPEED_PINCTRL_GROUP(TIMER5), 2131 ASPEED_PINCTRL_GROUP(TIMER6), 2132 ASPEED_PINCTRL_GROUP(TIMER7), 2133 ASPEED_PINCTRL_GROUP(TIMER8), 2134 ASPEED_PINCTRL_GROUP(TXD1), 2135 ASPEED_PINCTRL_GROUP(TXD2), 2136 ASPEED_PINCTRL_GROUP(TXD3), 2137 ASPEED_PINCTRL_GROUP(TXD4), 2138 ASPEED_PINCTRL_GROUP(UART6), 2139 ASPEED_PINCTRL_GROUP(USB11D1), 2140 ASPEED_PINCTRL_GROUP(USB11H2), 2141 ASPEED_PINCTRL_GROUP(USB2D1), 2142 ASPEED_PINCTRL_GROUP(USB2H1), 2143 ASPEED_PINCTRL_GROUP(USBCKI), 2144 ASPEED_PINCTRL_GROUP(VGABIOS_ROM), 2145 ASPEED_PINCTRL_GROUP(VGAHS), 2146 ASPEED_PINCTRL_GROUP(VGAVS), 2147 ASPEED_PINCTRL_GROUP(VPI18), 2148 ASPEED_PINCTRL_GROUP(VPI24), 2149 ASPEED_PINCTRL_GROUP(VPI30), 2150 ASPEED_PINCTRL_GROUP(VPO12), 2151 ASPEED_PINCTRL_GROUP(VPO24), 2152 ASPEED_PINCTRL_GROUP(WDTRST1), 2153 ASPEED_PINCTRL_GROUP(WDTRST2), 2154 }; 2155 2156 static const struct aspeed_pin_function aspeed_g4_functions[] = { 2157 ASPEED_PINCTRL_FUNC(ACPI), 2158 ASPEED_PINCTRL_FUNC(ADC0), 2159 ASPEED_PINCTRL_FUNC(ADC1), 2160 ASPEED_PINCTRL_FUNC(ADC10), 2161 ASPEED_PINCTRL_FUNC(ADC11), 2162 ASPEED_PINCTRL_FUNC(ADC12), 2163 ASPEED_PINCTRL_FUNC(ADC13), 2164 ASPEED_PINCTRL_FUNC(ADC14), 2165 ASPEED_PINCTRL_FUNC(ADC15), 2166 ASPEED_PINCTRL_FUNC(ADC2), 2167 ASPEED_PINCTRL_FUNC(ADC3), 2168 ASPEED_PINCTRL_FUNC(ADC4), 2169 ASPEED_PINCTRL_FUNC(ADC5), 2170 ASPEED_PINCTRL_FUNC(ADC6), 2171 ASPEED_PINCTRL_FUNC(ADC7), 2172 ASPEED_PINCTRL_FUNC(ADC8), 2173 ASPEED_PINCTRL_FUNC(ADC9), 2174 ASPEED_PINCTRL_FUNC(BMCINT), 2175 ASPEED_PINCTRL_FUNC(DDCCLK), 2176 ASPEED_PINCTRL_FUNC(DDCDAT), 2177 ASPEED_PINCTRL_FUNC(EXTRST), 2178 ASPEED_PINCTRL_FUNC(FLACK), 2179 ASPEED_PINCTRL_FUNC(FLBUSY), 2180 ASPEED_PINCTRL_FUNC(FLWP), 2181 ASPEED_PINCTRL_FUNC(GPID), 2182 ASPEED_PINCTRL_FUNC(GPID0), 2183 ASPEED_PINCTRL_FUNC(GPID2), 2184 ASPEED_PINCTRL_FUNC(GPID4), 2185 ASPEED_PINCTRL_FUNC(GPID6), 2186 ASPEED_PINCTRL_FUNC(GPIE0), 2187 ASPEED_PINCTRL_FUNC(GPIE2), 2188 ASPEED_PINCTRL_FUNC(GPIE4), 2189 ASPEED_PINCTRL_FUNC(GPIE6), 2190 ASPEED_PINCTRL_FUNC(I2C10), 2191 ASPEED_PINCTRL_FUNC(I2C11), 2192 ASPEED_PINCTRL_FUNC(I2C12), 2193 ASPEED_PINCTRL_FUNC(I2C13), 2194 ASPEED_PINCTRL_FUNC(I2C14), 2195 ASPEED_PINCTRL_FUNC(I2C3), 2196 ASPEED_PINCTRL_FUNC(I2C4), 2197 ASPEED_PINCTRL_FUNC(I2C5), 2198 ASPEED_PINCTRL_FUNC(I2C6), 2199 ASPEED_PINCTRL_FUNC(I2C7), 2200 ASPEED_PINCTRL_FUNC(I2C8), 2201 ASPEED_PINCTRL_FUNC(I2C9), 2202 ASPEED_PINCTRL_FUNC(LPCPD), 2203 ASPEED_PINCTRL_FUNC(LPCPME), 2204 ASPEED_PINCTRL_FUNC(LPCRST), 2205 ASPEED_PINCTRL_FUNC(LPCSMI), 2206 ASPEED_PINCTRL_FUNC(MAC1LINK), 2207 ASPEED_PINCTRL_FUNC(MAC2LINK), 2208 ASPEED_PINCTRL_FUNC(MDIO1), 2209 ASPEED_PINCTRL_FUNC(MDIO2), 2210 ASPEED_PINCTRL_FUNC(NCTS1), 2211 ASPEED_PINCTRL_FUNC(NCTS2), 2212 ASPEED_PINCTRL_FUNC(NCTS3), 2213 ASPEED_PINCTRL_FUNC(NCTS4), 2214 ASPEED_PINCTRL_FUNC(NDCD1), 2215 ASPEED_PINCTRL_FUNC(NDCD2), 2216 ASPEED_PINCTRL_FUNC(NDCD3), 2217 ASPEED_PINCTRL_FUNC(NDCD4), 2218 ASPEED_PINCTRL_FUNC(NDSR1), 2219 ASPEED_PINCTRL_FUNC(NDSR2), 2220 ASPEED_PINCTRL_FUNC(NDSR3), 2221 ASPEED_PINCTRL_FUNC(NDSR4), 2222 ASPEED_PINCTRL_FUNC(NDTR1), 2223 ASPEED_PINCTRL_FUNC(NDTR2), 2224 ASPEED_PINCTRL_FUNC(NDTR3), 2225 ASPEED_PINCTRL_FUNC(NDTR4), 2226 ASPEED_PINCTRL_FUNC(NDTS4), 2227 ASPEED_PINCTRL_FUNC(NRI1), 2228 ASPEED_PINCTRL_FUNC(NRI2), 2229 ASPEED_PINCTRL_FUNC(NRI3), 2230 ASPEED_PINCTRL_FUNC(NRI4), 2231 ASPEED_PINCTRL_FUNC(NRTS1), 2232 ASPEED_PINCTRL_FUNC(NRTS2), 2233 ASPEED_PINCTRL_FUNC(NRTS3), 2234 ASPEED_PINCTRL_FUNC(OSCCLK), 2235 ASPEED_PINCTRL_FUNC(PWM0), 2236 ASPEED_PINCTRL_FUNC(PWM1), 2237 ASPEED_PINCTRL_FUNC(PWM2), 2238 ASPEED_PINCTRL_FUNC(PWM3), 2239 ASPEED_PINCTRL_FUNC(PWM4), 2240 ASPEED_PINCTRL_FUNC(PWM5), 2241 ASPEED_PINCTRL_FUNC(PWM6), 2242 ASPEED_PINCTRL_FUNC(PWM7), 2243 ASPEED_PINCTRL_FUNC(RGMII1), 2244 ASPEED_PINCTRL_FUNC(RGMII2), 2245 ASPEED_PINCTRL_FUNC(RMII1), 2246 ASPEED_PINCTRL_FUNC(RMII2), 2247 ASPEED_PINCTRL_FUNC(ROM16), 2248 ASPEED_PINCTRL_FUNC(ROM8), 2249 ASPEED_PINCTRL_FUNC(ROMCS1), 2250 ASPEED_PINCTRL_FUNC(ROMCS2), 2251 ASPEED_PINCTRL_FUNC(ROMCS3), 2252 ASPEED_PINCTRL_FUNC(ROMCS4), 2253 ASPEED_PINCTRL_FUNC(RXD1), 2254 ASPEED_PINCTRL_FUNC(RXD2), 2255 ASPEED_PINCTRL_FUNC(RXD3), 2256 ASPEED_PINCTRL_FUNC(RXD4), 2257 ASPEED_PINCTRL_FUNC(SALT1), 2258 ASPEED_PINCTRL_FUNC(SALT2), 2259 ASPEED_PINCTRL_FUNC(SALT3), 2260 ASPEED_PINCTRL_FUNC(SALT4), 2261 ASPEED_PINCTRL_FUNC(SD1), 2262 ASPEED_PINCTRL_FUNC(SD2), 2263 ASPEED_PINCTRL_FUNC(SGPMCK), 2264 ASPEED_PINCTRL_FUNC(SGPMI), 2265 ASPEED_PINCTRL_FUNC(SGPMLD), 2266 ASPEED_PINCTRL_FUNC(SGPMO), 2267 ASPEED_PINCTRL_FUNC(SGPSCK), 2268 ASPEED_PINCTRL_FUNC(SGPSI0), 2269 ASPEED_PINCTRL_FUNC(SGPSI1), 2270 ASPEED_PINCTRL_FUNC(SGPSLD), 2271 ASPEED_PINCTRL_FUNC(SIOONCTRL), 2272 ASPEED_PINCTRL_FUNC(SIOPBI), 2273 ASPEED_PINCTRL_FUNC(SIOPBO), 2274 ASPEED_PINCTRL_FUNC(SIOPWREQ), 2275 ASPEED_PINCTRL_FUNC(SIOPWRGD), 2276 ASPEED_PINCTRL_FUNC(SIOS3), 2277 ASPEED_PINCTRL_FUNC(SIOS5), 2278 ASPEED_PINCTRL_FUNC(SIOSCI), 2279 ASPEED_PINCTRL_FUNC(SPI1), 2280 ASPEED_PINCTRL_FUNC(SPI1DEBUG), 2281 ASPEED_PINCTRL_FUNC(SPI1PASSTHRU), 2282 ASPEED_PINCTRL_FUNC(SPICS1), 2283 ASPEED_PINCTRL_FUNC(TIMER3), 2284 ASPEED_PINCTRL_FUNC(TIMER4), 2285 ASPEED_PINCTRL_FUNC(TIMER5), 2286 ASPEED_PINCTRL_FUNC(TIMER6), 2287 ASPEED_PINCTRL_FUNC(TIMER7), 2288 ASPEED_PINCTRL_FUNC(TIMER8), 2289 ASPEED_PINCTRL_FUNC(TXD1), 2290 ASPEED_PINCTRL_FUNC(TXD2), 2291 ASPEED_PINCTRL_FUNC(TXD3), 2292 ASPEED_PINCTRL_FUNC(TXD4), 2293 ASPEED_PINCTRL_FUNC(UART6), 2294 ASPEED_PINCTRL_FUNC(USB11D1), 2295 ASPEED_PINCTRL_FUNC(USB11H2), 2296 ASPEED_PINCTRL_FUNC(USB2D1), 2297 ASPEED_PINCTRL_FUNC(USB2H1), 2298 ASPEED_PINCTRL_FUNC(USBCKI), 2299 ASPEED_PINCTRL_FUNC(VGABIOS_ROM), 2300 ASPEED_PINCTRL_FUNC(VGAHS), 2301 ASPEED_PINCTRL_FUNC(VGAVS), 2302 ASPEED_PINCTRL_FUNC(VPI18), 2303 ASPEED_PINCTRL_FUNC(VPI24), 2304 ASPEED_PINCTRL_FUNC(VPI30), 2305 ASPEED_PINCTRL_FUNC(VPO12), 2306 ASPEED_PINCTRL_FUNC(VPO24), 2307 ASPEED_PINCTRL_FUNC(WDTRST1), 2308 ASPEED_PINCTRL_FUNC(WDTRST2), 2309 }; 2310 2311 static const struct aspeed_pin_config aspeed_g4_configs[] = { 2312 /* GPIO banks ranges [A, B], [D, J], [M, R] */ 2313 { PIN_CONFIG_BIAS_PULL_DOWN, { D6, D5 }, SCU8C, 16 }, 2314 { PIN_CONFIG_BIAS_DISABLE, { D6, D5 }, SCU8C, 16 }, 2315 { PIN_CONFIG_BIAS_PULL_DOWN, { J21, E18 }, SCU8C, 17 }, 2316 { PIN_CONFIG_BIAS_DISABLE, { J21, E18 }, SCU8C, 17 }, 2317 { PIN_CONFIG_BIAS_PULL_DOWN, { A18, E15 }, SCU8C, 19 }, 2318 { PIN_CONFIG_BIAS_DISABLE, { A18, E15 }, SCU8C, 19 }, 2319 { PIN_CONFIG_BIAS_PULL_DOWN, { D15, B14 }, SCU8C, 20 }, 2320 { PIN_CONFIG_BIAS_DISABLE, { D15, B14 }, SCU8C, 20 }, 2321 { PIN_CONFIG_BIAS_PULL_DOWN, { D18, C17 }, SCU8C, 21 }, 2322 { PIN_CONFIG_BIAS_DISABLE, { D18, C17 }, SCU8C, 21 }, 2323 { PIN_CONFIG_BIAS_PULL_DOWN, { A14, U18 }, SCU8C, 22 }, 2324 { PIN_CONFIG_BIAS_DISABLE, { A14, U18 }, SCU8C, 22 }, 2325 { PIN_CONFIG_BIAS_PULL_DOWN, { A8, E7 }, SCU8C, 23 }, 2326 { PIN_CONFIG_BIAS_DISABLE, { A8, E7 }, SCU8C, 23 }, 2327 { PIN_CONFIG_BIAS_PULL_DOWN, { C22, E20 }, SCU8C, 24 }, 2328 { PIN_CONFIG_BIAS_DISABLE, { C22, E20 }, SCU8C, 24 }, 2329 { PIN_CONFIG_BIAS_PULL_DOWN, { J5, T1 }, SCU8C, 25 }, 2330 { PIN_CONFIG_BIAS_DISABLE, { J5, T1 }, SCU8C, 25 }, 2331 { PIN_CONFIG_BIAS_PULL_DOWN, { U1, U5 }, SCU8C, 26 }, 2332 { PIN_CONFIG_BIAS_DISABLE, { U1, U5 }, SCU8C, 26 }, 2333 { PIN_CONFIG_BIAS_PULL_DOWN, { V3, V5 }, SCU8C, 27 }, 2334 { PIN_CONFIG_BIAS_DISABLE, { V3, V5 }, SCU8C, 27 }, 2335 { PIN_CONFIG_BIAS_PULL_DOWN, { W4, AB2 }, SCU8C, 28 }, 2336 { PIN_CONFIG_BIAS_DISABLE, { W4, AB2 }, SCU8C, 28 }, 2337 { PIN_CONFIG_BIAS_PULL_DOWN, { V6, V7 }, SCU8C, 29 }, 2338 { PIN_CONFIG_BIAS_DISABLE, { V6, V7 }, SCU8C, 29 }, 2339 { PIN_CONFIG_BIAS_PULL_DOWN, { Y6, AB7 }, SCU8C, 30 }, 2340 { PIN_CONFIG_BIAS_DISABLE, { Y6, AB7 }, SCU8C, 30 }, 2341 { PIN_CONFIG_BIAS_PULL_DOWN, { V20, A5 }, SCU8C, 31 }, 2342 { PIN_CONFIG_BIAS_DISABLE, { V20, A5 }, SCU8C, 31 }, 2343 2344 /* GPIOs T[0-5] (RGMII1 Tx pins) */ 2345 { PIN_CONFIG_DRIVE_STRENGTH, { A12, A13 }, SCU90, 9 }, 2346 { PIN_CONFIG_BIAS_PULL_DOWN, { A12, A13 }, SCU90, 12 }, 2347 { PIN_CONFIG_BIAS_DISABLE, { A12, A13 }, SCU90, 12 }, 2348 2349 /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */ 2350 { PIN_CONFIG_DRIVE_STRENGTH, { D9, D10 }, SCU90, 11 }, 2351 { PIN_CONFIG_BIAS_PULL_DOWN, { D9, D10 }, SCU90, 14 }, 2352 { PIN_CONFIG_BIAS_DISABLE, { D9, D10 }, SCU90, 14 }, 2353 2354 /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */ 2355 { PIN_CONFIG_BIAS_PULL_DOWN, { E11, E10 }, SCU90, 13 }, 2356 { PIN_CONFIG_BIAS_DISABLE, { E11, E10 }, SCU90, 13 }, 2357 2358 /* GPIOs V[2-7] (RGMII2 Rx pins) */ 2359 { PIN_CONFIG_BIAS_PULL_DOWN, { C9, C8 }, SCU90, 15 }, 2360 { PIN_CONFIG_BIAS_DISABLE, { C9, C8 }, SCU90, 15 }, 2361 2362 /* ADC pull-downs (SCUA8[19:4]) */ 2363 { PIN_CONFIG_BIAS_PULL_DOWN, { L5, L5 }, SCUA8, 4 }, 2364 { PIN_CONFIG_BIAS_DISABLE, { L5, L5 }, SCUA8, 4 }, 2365 { PIN_CONFIG_BIAS_PULL_DOWN, { L4, L4 }, SCUA8, 5 }, 2366 { PIN_CONFIG_BIAS_DISABLE, { L4, L4 }, SCUA8, 5 }, 2367 { PIN_CONFIG_BIAS_PULL_DOWN, { L3, L3 }, SCUA8, 6 }, 2368 { PIN_CONFIG_BIAS_DISABLE, { L3, L3 }, SCUA8, 6 }, 2369 { PIN_CONFIG_BIAS_PULL_DOWN, { L2, L2 }, SCUA8, 7 }, 2370 { PIN_CONFIG_BIAS_DISABLE, { L2, L2 }, SCUA8, 7 }, 2371 { PIN_CONFIG_BIAS_PULL_DOWN, { L1, L1 }, SCUA8, 8 }, 2372 { PIN_CONFIG_BIAS_DISABLE, { L1, L1 }, SCUA8, 8 }, 2373 { PIN_CONFIG_BIAS_PULL_DOWN, { M5, M5 }, SCUA8, 9 }, 2374 { PIN_CONFIG_BIAS_DISABLE, { M5, M5 }, SCUA8, 9 }, 2375 { PIN_CONFIG_BIAS_PULL_DOWN, { M4, M4 }, SCUA8, 10 }, 2376 { PIN_CONFIG_BIAS_DISABLE, { M4, M4 }, SCUA8, 10 }, 2377 { PIN_CONFIG_BIAS_PULL_DOWN, { M3, M3 }, SCUA8, 11 }, 2378 { PIN_CONFIG_BIAS_DISABLE, { M3, M3 }, SCUA8, 11 }, 2379 { PIN_CONFIG_BIAS_PULL_DOWN, { M2, M2 }, SCUA8, 12 }, 2380 { PIN_CONFIG_BIAS_DISABLE, { M2, M2 }, SCUA8, 12 }, 2381 { PIN_CONFIG_BIAS_PULL_DOWN, { M1, M1 }, SCUA8, 13 }, 2382 { PIN_CONFIG_BIAS_DISABLE, { M1, M1 }, SCUA8, 13 }, 2383 { PIN_CONFIG_BIAS_PULL_DOWN, { N5, N5 }, SCUA8, 14 }, 2384 { PIN_CONFIG_BIAS_DISABLE, { N5, N5 }, SCUA8, 14 }, 2385 { PIN_CONFIG_BIAS_PULL_DOWN, { N4, N4 }, SCUA8, 15 }, 2386 { PIN_CONFIG_BIAS_DISABLE, { N4, N4 }, SCUA8, 15 }, 2387 { PIN_CONFIG_BIAS_PULL_DOWN, { N3, N3 }, SCUA8, 16 }, 2388 { PIN_CONFIG_BIAS_DISABLE, { N3, N3 }, SCUA8, 16 }, 2389 { PIN_CONFIG_BIAS_PULL_DOWN, { N2, N2 }, SCUA8, 17 }, 2390 { PIN_CONFIG_BIAS_DISABLE, { N2, N2 }, SCUA8, 17 }, 2391 { PIN_CONFIG_BIAS_PULL_DOWN, { N1, N1 }, SCUA8, 18 }, 2392 { PIN_CONFIG_BIAS_DISABLE, { N1, N1 }, SCUA8, 18 }, 2393 { PIN_CONFIG_BIAS_PULL_DOWN, { P5, P5 }, SCUA8, 19 }, 2394 { PIN_CONFIG_BIAS_DISABLE, { P5, P5 }, SCUA8, 19 }, 2395 2396 /* 2397 * Debounce settings for GPIOs D and E passthrough mode are in 2398 * SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for 2399 * banks D and E is handled by the GPIO driver - GPIO passthrough is 2400 * treated like any other non-GPIO mux function. There is a catch 2401 * however, in that the debounce period is configured in the GPIO 2402 * controller. Due to this tangle between GPIO and pinctrl we don't yet 2403 * fully support pass-through debounce. 2404 */ 2405 { PIN_CONFIG_INPUT_DEBOUNCE, { A18, D16 }, SCUA8, 20 }, 2406 { PIN_CONFIG_INPUT_DEBOUNCE, { B17, A17 }, SCUA8, 21 }, 2407 { PIN_CONFIG_INPUT_DEBOUNCE, { C16, B16 }, SCUA8, 22 }, 2408 { PIN_CONFIG_INPUT_DEBOUNCE, { A16, E15 }, SCUA8, 23 }, 2409 { PIN_CONFIG_INPUT_DEBOUNCE, { D15, C15 }, SCUA8, 24 }, 2410 { PIN_CONFIG_INPUT_DEBOUNCE, { B15, A15 }, SCUA8, 25 }, 2411 { PIN_CONFIG_INPUT_DEBOUNCE, { E14, D14 }, SCUA8, 26 }, 2412 { PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 }, 2413 }; 2414 2415 static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx, 2416 const struct aspeed_sig_expr *expr, 2417 bool enable) 2418 { 2419 int ret; 2420 int i; 2421 2422 for (i = 0; i < expr->ndescs; i++) { 2423 const struct aspeed_sig_desc *desc = &expr->descs[i]; 2424 u32 pattern = enable ? desc->enable : desc->disable; 2425 u32 val = (pattern << __ffs(desc->mask)); 2426 2427 if (!ctx->maps[desc->ip]) 2428 return -ENODEV; 2429 2430 /* 2431 * Strap registers are configured in hardware or by early-boot 2432 * firmware. Treat them as read-only despite that we can write 2433 * them. This may mean that certain functions cannot be 2434 * deconfigured and is the reason we re-evaluate after writing 2435 * all descriptor bits. 2436 * 2437 * Port D and port E GPIO loopback modes are the only exception 2438 * as those are commonly used with front-panel buttons to allow 2439 * normal operation of the host when the BMC is powered off or 2440 * fails to boot. Once the BMC has booted, the loopback mode 2441 * must be disabled for the BMC to control host power-on and 2442 * reset. 2443 */ 2444 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 && 2445 !(desc->mask & (BIT(21) | BIT(22)))) 2446 continue; 2447 2448 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2) 2449 continue; 2450 2451 ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, 2452 desc->mask, val); 2453 2454 if (ret) 2455 return ret; 2456 } 2457 2458 ret = aspeed_sig_expr_eval(ctx, expr, enable); 2459 if (ret < 0) 2460 return ret; 2461 2462 if (!ret) 2463 return -EPERM; 2464 2465 return 0; 2466 } 2467 2468 static const struct aspeed_pinmux_ops aspeed_g4_ops = { 2469 .set = aspeed_g4_sig_expr_set, 2470 }; 2471 2472 static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = { 2473 .pins = aspeed_g4_pins, 2474 .npins = ARRAY_SIZE(aspeed_g4_pins), 2475 .pinmux = { 2476 .ops = &aspeed_g4_ops, 2477 .groups = aspeed_g4_groups, 2478 .ngroups = ARRAY_SIZE(aspeed_g4_groups), 2479 .functions = aspeed_g4_functions, 2480 .nfunctions = ARRAY_SIZE(aspeed_g4_functions), 2481 }, 2482 .configs = aspeed_g4_configs, 2483 .nconfigs = ARRAY_SIZE(aspeed_g4_configs), 2484 }; 2485 2486 static const struct pinmux_ops aspeed_g4_pinmux_ops = { 2487 .get_functions_count = aspeed_pinmux_get_fn_count, 2488 .get_function_name = aspeed_pinmux_get_fn_name, 2489 .get_function_groups = aspeed_pinmux_get_fn_groups, 2490 .set_mux = aspeed_pinmux_set_mux, 2491 .gpio_request_enable = aspeed_gpio_request_enable, 2492 .strict = true, 2493 }; 2494 2495 static const struct pinctrl_ops aspeed_g4_pinctrl_ops = { 2496 .get_groups_count = aspeed_pinctrl_get_groups_count, 2497 .get_group_name = aspeed_pinctrl_get_group_name, 2498 .get_group_pins = aspeed_pinctrl_get_group_pins, 2499 .pin_dbg_show = aspeed_pinctrl_pin_dbg_show, 2500 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 2501 .dt_free_map = pinctrl_utils_free_map, 2502 }; 2503 2504 static const struct pinconf_ops aspeed_g4_conf_ops = { 2505 .is_generic = true, 2506 .pin_config_get = aspeed_pin_config_get, 2507 .pin_config_set = aspeed_pin_config_set, 2508 .pin_config_group_get = aspeed_pin_config_group_get, 2509 .pin_config_group_set = aspeed_pin_config_group_set, 2510 }; 2511 2512 static struct pinctrl_desc aspeed_g4_pinctrl_desc = { 2513 .name = "aspeed-g4-pinctrl", 2514 .pins = aspeed_g4_pins, 2515 .npins = ARRAY_SIZE(aspeed_g4_pins), 2516 .pctlops = &aspeed_g4_pinctrl_ops, 2517 .pmxops = &aspeed_g4_pinmux_ops, 2518 .confops = &aspeed_g4_conf_ops, 2519 }; 2520 2521 static int aspeed_g4_pinctrl_probe(struct platform_device *pdev) 2522 { 2523 int i; 2524 2525 for (i = 0; i < ARRAY_SIZE(aspeed_g4_pins); i++) 2526 aspeed_g4_pins[i].number = i; 2527 2528 return aspeed_pinctrl_probe(pdev, &aspeed_g4_pinctrl_desc, 2529 &aspeed_g4_pinctrl_data); 2530 } 2531 2532 static const struct of_device_id aspeed_g4_pinctrl_of_match[] = { 2533 { .compatible = "aspeed,ast2400-pinctrl", }, 2534 { .compatible = "aspeed,g4-pinctrl", }, 2535 { }, 2536 }; 2537 2538 static struct platform_driver aspeed_g4_pinctrl_driver = { 2539 .probe = aspeed_g4_pinctrl_probe, 2540 .driver = { 2541 .name = "aspeed-g4-pinctrl", 2542 .of_match_table = aspeed_g4_pinctrl_of_match, 2543 }, 2544 }; 2545 2546 static int aspeed_g4_pinctrl_init(void) 2547 { 2548 return platform_driver_register(&aspeed_g4_pinctrl_driver); 2549 } 2550 2551 arch_initcall(aspeed_g4_pinctrl_init); 2552