1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Copyright (C) 2019 IBM Corp. */ 3 #include <linux/bitops.h> 4 #include <linux/init.h> 5 #include <linux/io.h> 6 #include <linux/kernel.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/mutex.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/pinctrl/pinctrl.h> 12 #include <linux/pinctrl/pinmux.h> 13 #include <linux/string.h> 14 #include <linux/types.h> 15 16 #include "../core.h" 17 #include "../pinctrl-utils.h" 18 #include "pinctrl-aspeed.h" 19 20 #define SCU400 0x400 /* Multi-function Pin Control #1 */ 21 #define SCU404 0x404 /* Multi-function Pin Control #2 */ 22 #define SCU410 0x410 /* Multi-function Pin Control #4 */ 23 #define SCU414 0x414 /* Multi-function Pin Control #5 */ 24 #define SCU418 0x418 /* Multi-function Pin Control #6 */ 25 #define SCU41C 0x41C /* Multi-function Pin Control #7 */ 26 #define SCU430 0x430 /* Multi-function Pin Control #8 */ 27 #define SCU434 0x434 /* Multi-function Pin Control #9 */ 28 #define SCU438 0x438 /* Multi-function Pin Control #10 */ 29 #define SCU440 0x440 /* USB Multi-function Pin Control #12 */ 30 #define SCU450 0x450 /* Multi-function Pin Control #14 */ 31 #define SCU454 0x454 /* Multi-function Pin Control #15 */ 32 #define SCU458 0x458 /* Multi-function Pin Control #16 */ 33 #define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */ 34 #define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */ 35 #define SCU4B8 0x4B8 /* Multi-function Pin Control #19 */ 36 #define SCU4BC 0x4BC /* Multi-function Pin Control #20 */ 37 #define SCU4D4 0x4D4 /* Multi-function Pin Control #22 */ 38 #define SCU4D8 0x4D8 /* Multi-function Pin Control #23 */ 39 #define SCU500 0x500 /* Hardware Strap 1 */ 40 #define SCU510 0x510 /* Hardware Strap 2 */ 41 #define SCU610 0x610 /* Disable GPIO Internal Pull-Down #0 */ 42 #define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */ 43 #define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */ 44 #define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */ 45 #define SCU620 0x620 /* Disable GPIO Internal Pull-Down #4 */ 46 #define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */ 47 #define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */ 48 #define SCU694 0x694 /* Multi-function Pin Control #25 */ 49 #define SCUC20 0xC20 /* PCIE configuration Setting Control */ 50 51 #define ASPEED_G6_NR_PINS 256 52 53 #define M24 0 54 SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0)); 55 SIG_EXPR_LIST_DECL_SESG(M24, SCL11, I2C11, SIG_DESC_SET(SCU4B0, 0)); 56 PIN_DECL_2(M24, GPIOA0, MDC3, SCL11); 57 58 #define M25 1 59 SIG_EXPR_LIST_DECL_SESG(M25, MDIO3, MDIO3, SIG_DESC_SET(SCU410, 1)); 60 SIG_EXPR_LIST_DECL_SESG(M25, SDA11, I2C11, SIG_DESC_SET(SCU4B0, 1)); 61 PIN_DECL_2(M25, GPIOA1, MDIO3, SDA11); 62 63 FUNC_GROUP_DECL(MDIO3, M24, M25); 64 FUNC_GROUP_DECL(I2C11, M24, M25); 65 66 #define L26 2 67 SIG_EXPR_LIST_DECL_SESG(L26, MDC4, MDIO4, SIG_DESC_SET(SCU410, 2)); 68 SIG_EXPR_LIST_DECL_SESG(L26, SCL12, I2C12, SIG_DESC_SET(SCU4B0, 2)); 69 PIN_DECL_2(L26, GPIOA2, MDC4, SCL12); 70 71 #define K24 3 72 SIG_EXPR_LIST_DECL_SESG(K24, MDIO4, MDIO4, SIG_DESC_SET(SCU410, 3)); 73 SIG_EXPR_LIST_DECL_SESG(K24, SDA12, I2C12, SIG_DESC_SET(SCU4B0, 3)); 74 PIN_DECL_2(K24, GPIOA3, MDIO4, SDA12); 75 76 FUNC_GROUP_DECL(MDIO4, L26, K24); 77 FUNC_GROUP_DECL(I2C12, L26, K24); 78 79 #define K26 4 80 SIG_EXPR_LIST_DECL_SESG(K26, MACLINK1, MACLINK1, SIG_DESC_SET(SCU410, 4)); 81 SIG_EXPR_LIST_DECL_SESG(K26, SCL13, I2C13, SIG_DESC_SET(SCU4B0, 4)); 82 PIN_DECL_2(K26, GPIOA4, MACLINK1, SCL13); 83 FUNC_GROUP_DECL(MACLINK1, K26); 84 85 #define L24 5 86 SIG_EXPR_LIST_DECL_SESG(L24, MACLINK2, MACLINK2, SIG_DESC_SET(SCU410, 5)); 87 SIG_EXPR_LIST_DECL_SESG(L24, SDA13, I2C13, SIG_DESC_SET(SCU4B0, 5)); 88 PIN_DECL_2(L24, GPIOA5, MACLINK2, SDA13); 89 FUNC_GROUP_DECL(MACLINK2, L24); 90 91 FUNC_GROUP_DECL(I2C13, K26, L24); 92 93 #define L23 6 94 SIG_EXPR_LIST_DECL_SESG(L23, MACLINK3, MACLINK3, SIG_DESC_SET(SCU410, 6)); 95 SIG_EXPR_LIST_DECL_SESG(L23, SCL14, I2C14, SIG_DESC_SET(SCU4B0, 6)); 96 PIN_DECL_2(L23, GPIOA6, MACLINK3, SCL14); 97 FUNC_GROUP_DECL(MACLINK3, L23); 98 99 #define K25 7 100 SIG_EXPR_LIST_DECL_SESG(K25, MACLINK4, MACLINK4, SIG_DESC_SET(SCU410, 7)); 101 SIG_EXPR_LIST_DECL_SESG(K25, SDA14, I2C14, SIG_DESC_SET(SCU4B0, 7)); 102 PIN_DECL_2(K25, GPIOA7, MACLINK4, SDA14); 103 FUNC_GROUP_DECL(MACLINK4, K25); 104 105 FUNC_GROUP_DECL(I2C14, L23, K25); 106 107 #define J26 8 108 SIG_EXPR_LIST_DECL_SESG(J26, SALT1, SALT1, SIG_DESC_SET(SCU410, 8)); 109 SIG_EXPR_LIST_DECL_SESG(J26, LHAD0, LPCHC, SIG_DESC_SET(SCU4B0, 8)); 110 PIN_DECL_2(J26, GPIOB0, SALT1, LHAD0); 111 FUNC_GROUP_DECL(SALT1, J26); 112 113 #define K23 9 114 SIG_EXPR_LIST_DECL_SESG(K23, SALT2, SALT2, SIG_DESC_SET(SCU410, 9)); 115 SIG_EXPR_LIST_DECL_SESG(K23, LHAD1, LPCHC, SIG_DESC_SET(SCU4B0, 9)); 116 PIN_DECL_2(K23, GPIOB1, SALT2, LHAD1); 117 FUNC_GROUP_DECL(SALT2, K23); 118 119 #define H26 10 120 SIG_EXPR_LIST_DECL_SESG(H26, SALT3, SALT3, SIG_DESC_SET(SCU410, 10)); 121 SIG_EXPR_LIST_DECL_SESG(H26, LHAD2, LPCHC, SIG_DESC_SET(SCU4B0, 10)); 122 PIN_DECL_2(H26, GPIOB2, SALT3, LHAD2); 123 FUNC_GROUP_DECL(SALT3, H26); 124 125 #define J25 11 126 SIG_EXPR_LIST_DECL_SESG(J25, SALT4, SALT4, SIG_DESC_SET(SCU410, 11)); 127 SIG_EXPR_LIST_DECL_SESG(J25, LHAD3, LPCHC, SIG_DESC_SET(SCU4B0, 11)); 128 PIN_DECL_2(J25, GPIOB3, SALT4, LHAD3); 129 FUNC_GROUP_DECL(SALT4, J25); 130 131 #define J23 12 132 SIG_EXPR_LIST_DECL_SESG(J23, MDC2, MDIO2, SIG_DESC_SET(SCU410, 12)); 133 SIG_EXPR_LIST_DECL_SESG(J23, LHCLK, LPCHC, SIG_DESC_SET(SCU4B0, 12)); 134 PIN_DECL_2(J23, GPIOB4, MDC2, LHCLK); 135 136 #define G26 13 137 SIG_EXPR_LIST_DECL_SESG(G26, MDIO2, MDIO2, SIG_DESC_SET(SCU410, 13)); 138 SIG_EXPR_LIST_DECL_SESG(G26, LHFRAME, LPCHC, SIG_DESC_SET(SCU4B0, 13)); 139 PIN_DECL_2(G26, GPIOB5, MDIO2, LHFRAME); 140 141 FUNC_GROUP_DECL(MDIO2, J23, G26); 142 143 #define H25 14 144 SIG_EXPR_LIST_DECL_SESG(H25, TXD4, TXD4, SIG_DESC_SET(SCU410, 14)); 145 SIG_EXPR_LIST_DECL_SESG(H25, LHSIRQ, LHSIRQ, SIG_DESC_SET(SCU4B0, 14)); 146 PIN_DECL_2(H25, GPIOB6, TXD4, LHSIRQ); 147 FUNC_GROUP_DECL(TXD4, H25); 148 FUNC_GROUP_DECL(LHSIRQ, H25); 149 150 #define J24 15 151 SIG_EXPR_LIST_DECL_SESG(J24, RXD4, RXD4, SIG_DESC_SET(SCU410, 15)); 152 SIG_EXPR_LIST_DECL_SESG(J24, LHRST, LPCHC, SIG_DESC_SET(SCU4B0, 15)); 153 PIN_DECL_2(J24, GPIOB7, RXD4, LHRST); 154 FUNC_GROUP_DECL(RXD4, J24); 155 156 FUNC_GROUP_DECL(LPCHC, J26, K23, H26, J25, J23, G26, H25, J24); 157 158 #define H24 16 159 SIG_EXPR_LIST_DECL_SESG(H24, RGMII3TXCK, RGMII3, SIG_DESC_SET(SCU410, 16), 160 SIG_DESC_SET(SCU510, 0)); 161 SIG_EXPR_LIST_DECL_SESG(H24, RMII3RCLKO, RMII3, SIG_DESC_SET(SCU410, 16), 162 SIG_DESC_CLEAR(SCU510, 0)); 163 PIN_DECL_2(H24, GPIOC0, RGMII3TXCK, RMII3RCLKO); 164 165 #define J22 17 166 SIG_EXPR_LIST_DECL_SESG(J22, RGMII3TXCTL, RGMII3, SIG_DESC_SET(SCU410, 17), 167 SIG_DESC_SET(SCU510, 0)); 168 SIG_EXPR_LIST_DECL_SESG(J22, RMII3TXEN, RMII3, SIG_DESC_SET(SCU410, 17), 169 SIG_DESC_CLEAR(SCU510, 0)); 170 PIN_DECL_2(J22, GPIOC1, RGMII3TXCTL, RMII3TXEN); 171 172 #define H22 18 173 SIG_EXPR_LIST_DECL_SESG(H22, RGMII3TXD0, RGMII3, SIG_DESC_SET(SCU410, 18), 174 SIG_DESC_SET(SCU510, 0)); 175 SIG_EXPR_LIST_DECL_SESG(H22, RMII3TXD0, RMII3, SIG_DESC_SET(SCU410, 18), 176 SIG_DESC_CLEAR(SCU510, 0)); 177 PIN_DECL_2(H22, GPIOC2, RGMII3TXD0, RMII3TXD0); 178 179 #define H23 19 180 SIG_EXPR_LIST_DECL_SESG(H23, RGMII3TXD1, RGMII3, SIG_DESC_SET(SCU410, 19), 181 SIG_DESC_SET(SCU510, 0)); 182 SIG_EXPR_LIST_DECL_SESG(H23, RMII3TXD1, RMII3, SIG_DESC_SET(SCU410, 19), 183 SIG_DESC_CLEAR(SCU510, 0)); 184 PIN_DECL_2(H23, GPIOC3, RGMII3TXD1, RMII3TXD1); 185 186 #define G22 20 187 SIG_EXPR_LIST_DECL_SESG(G22, RGMII3TXD2, RGMII3, SIG_DESC_SET(SCU410, 20), 188 SIG_DESC_SET(SCU510, 0)); 189 PIN_DECL_1(G22, GPIOC4, RGMII3TXD2); 190 191 #define F22 21 192 SIG_EXPR_LIST_DECL_SESG(F22, RGMII3TXD3, RGMII3, SIG_DESC_SET(SCU410, 21), 193 SIG_DESC_SET(SCU510, 0)); 194 PIN_DECL_1(F22, GPIOC5, RGMII3TXD3); 195 196 #define G23 22 197 SIG_EXPR_LIST_DECL_SESG(G23, RGMII3RXCK, RGMII3, SIG_DESC_SET(SCU410, 22), 198 SIG_DESC_SET(SCU510, 0)); 199 SIG_EXPR_LIST_DECL_SESG(G23, RMII3RCLKI, RMII3, SIG_DESC_SET(SCU410, 22), 200 SIG_DESC_CLEAR(SCU510, 0)); 201 PIN_DECL_2(G23, GPIOC6, RGMII3RXCK, RMII3RCLKI); 202 203 #define G24 23 204 SIG_EXPR_LIST_DECL_SESG(G24, RGMII3RXCTL, RGMII3, SIG_DESC_SET(SCU410, 23), 205 SIG_DESC_SET(SCU510, 0)); 206 PIN_DECL_1(G24, GPIOC7, RGMII3RXCTL); 207 208 #define F23 24 209 SIG_EXPR_LIST_DECL_SESG(F23, RGMII3RXD0, RGMII3, SIG_DESC_SET(SCU410, 24), 210 SIG_DESC_SET(SCU510, 0)); 211 SIG_EXPR_LIST_DECL_SESG(F23, RMII3RXD0, RMII3, SIG_DESC_SET(SCU410, 24), 212 SIG_DESC_CLEAR(SCU510, 0)); 213 PIN_DECL_2(F23, GPIOD0, RGMII3RXD0, RMII3RXD0); 214 215 #define F26 25 216 SIG_EXPR_LIST_DECL_SESG(F26, RGMII3RXD1, RGMII3, SIG_DESC_SET(SCU410, 25), 217 SIG_DESC_SET(SCU510, 0)); 218 SIG_EXPR_LIST_DECL_SESG(F26, RMII3RXD1, RMII3, SIG_DESC_SET(SCU410, 25), 219 SIG_DESC_CLEAR(SCU510, 0)); 220 PIN_DECL_2(F26, GPIOD1, RGMII3RXD1, RMII3RXD1); 221 222 #define F25 26 223 SIG_EXPR_LIST_DECL_SESG(F25, RGMII3RXD2, RGMII3, SIG_DESC_SET(SCU410, 26), 224 SIG_DESC_SET(SCU510, 0)); 225 SIG_EXPR_LIST_DECL_SESG(F25, RMII3CRSDV, RMII3, SIG_DESC_SET(SCU410, 26), 226 SIG_DESC_CLEAR(SCU510, 0)); 227 PIN_DECL_2(F25, GPIOD2, RGMII3RXD2, RMII3CRSDV); 228 229 #define E26 27 230 SIG_EXPR_LIST_DECL_SESG(E26, RGMII3RXD3, RGMII3, SIG_DESC_SET(SCU410, 27), 231 SIG_DESC_SET(SCU510, 0)); 232 SIG_EXPR_LIST_DECL_SESG(E26, RMII3RXER, RMII3, SIG_DESC_SET(SCU410, 27), 233 SIG_DESC_CLEAR(SCU510, 0)); 234 PIN_DECL_2(E26, GPIOD3, RGMII3RXD3, RMII3RXER); 235 236 FUNC_GROUP_DECL(RGMII3, H24, J22, H22, H23, G22, F22, G23, G24, F23, F26, F25, 237 E26); 238 FUNC_GROUP_DECL(RMII3, H24, J22, H22, H23, G23, F23, F26, F25, E26); 239 240 #define F24 28 241 SIG_EXPR_LIST_DECL_SESG(F24, NCTS3, NCTS3, SIG_DESC_SET(SCU410, 28)); 242 SIG_EXPR_LIST_DECL_SESG(F24, RGMII4TXCK, RGMII4, SIG_DESC_SET(SCU4B0, 28), 243 SIG_DESC_SET(SCU510, 1)); 244 SIG_EXPR_LIST_DECL_SESG(F24, RMII4RCLKO, RMII4, SIG_DESC_SET(SCU4B0, 28), 245 SIG_DESC_CLEAR(SCU510, 1)); 246 PIN_DECL_3(F24, GPIOD4, NCTS3, RGMII4TXCK, RMII4RCLKO); 247 FUNC_GROUP_DECL(NCTS3, F24); 248 249 #define E23 29 250 SIG_EXPR_LIST_DECL_SESG(E23, NDCD3, NDCD3, SIG_DESC_SET(SCU410, 29)); 251 SIG_EXPR_LIST_DECL_SESG(E23, RGMII4TXCTL, RGMII4, SIG_DESC_SET(SCU4B0, 29), 252 SIG_DESC_SET(SCU510, 1)); 253 SIG_EXPR_LIST_DECL_SESG(E23, RMII4TXEN, RMII4, SIG_DESC_SET(SCU4B0, 29), 254 SIG_DESC_CLEAR(SCU510, 1)); 255 PIN_DECL_3(E23, GPIOD5, NDCD3, RGMII4TXCTL, RMII4TXEN); 256 FUNC_GROUP_DECL(NDCD3, E23); 257 258 #define E24 30 259 SIG_EXPR_LIST_DECL_SESG(E24, NDSR3, NDSR3, SIG_DESC_SET(SCU410, 30)); 260 SIG_EXPR_LIST_DECL_SESG(E24, RGMII4TXD0, RGMII4, SIG_DESC_SET(SCU4B0, 30), 261 SIG_DESC_SET(SCU510, 1)); 262 SIG_EXPR_LIST_DECL_SESG(E24, RMII4TXD0, RMII4, SIG_DESC_SET(SCU4B0, 30), 263 SIG_DESC_CLEAR(SCU510, 1)); 264 PIN_DECL_3(E24, GPIOD6, NDSR3, RGMII4TXD0, RMII4TXD0); 265 FUNC_GROUP_DECL(NDSR3, E24); 266 267 #define E25 31 268 SIG_EXPR_LIST_DECL_SESG(E25, NRI3, NRI3, SIG_DESC_SET(SCU410, 31)); 269 SIG_EXPR_LIST_DECL_SESG(E25, RGMII4TXD1, RGMII4, SIG_DESC_SET(SCU4B0, 31), 270 SIG_DESC_SET(SCU510, 1)); 271 SIG_EXPR_LIST_DECL_SESG(E25, RMII4TXD1, RMII4, SIG_DESC_SET(SCU4B0, 31), 272 SIG_DESC_CLEAR(SCU510, 1)); 273 PIN_DECL_3(E25, GPIOD7, NRI3, RGMII4TXD1, RMII4TXD1); 274 FUNC_GROUP_DECL(NRI3, E25); 275 276 #define D26 32 277 SIG_EXPR_LIST_DECL_SESG(D26, NDTR3, NDTR3, SIG_DESC_SET(SCU414, 0)); 278 SIG_EXPR_LIST_DECL_SESG(D26, RGMII4TXD2, RGMII4, SIG_DESC_SET(SCU4B4, 0), 279 SIG_DESC_SET(SCU510, 1)); 280 PIN_DECL_2(D26, GPIOE0, NDTR3, RGMII4TXD2); 281 FUNC_GROUP_DECL(NDTR3, D26); 282 283 #define D24 33 284 SIG_EXPR_LIST_DECL_SESG(D24, NRTS3, NRTS3, SIG_DESC_SET(SCU414, 1)); 285 SIG_EXPR_LIST_DECL_SESG(D24, RGMII4TXD3, RGMII4, SIG_DESC_SET(SCU4B4, 1), 286 SIG_DESC_SET(SCU510, 1)); 287 PIN_DECL_2(D24, GPIOE1, NRTS3, RGMII4TXD3); 288 FUNC_GROUP_DECL(NRTS3, D24); 289 290 #define C25 34 291 SIG_EXPR_LIST_DECL_SESG(C25, NCTS4, NCTS4, SIG_DESC_SET(SCU414, 2)); 292 SIG_EXPR_LIST_DECL_SESG(C25, RGMII4RXCK, RGMII4, SIG_DESC_SET(SCU4B4, 2), 293 SIG_DESC_SET(SCU510, 1)); 294 SIG_EXPR_LIST_DECL_SESG(C25, RMII4RCLKI, RMII4, SIG_DESC_SET(SCU4B4, 2), 295 SIG_DESC_CLEAR(SCU510, 1)); 296 PIN_DECL_3(C25, GPIOE2, NCTS4, RGMII4RXCK, RMII4RCLKI); 297 FUNC_GROUP_DECL(NCTS4, C25); 298 299 #define C26 35 300 SIG_EXPR_LIST_DECL_SESG(C26, NDCD4, NDCD4, SIG_DESC_SET(SCU414, 3)); 301 SIG_EXPR_LIST_DECL_SESG(C26, RGMII4RXCTL, RGMII4, SIG_DESC_SET(SCU4B4, 3), 302 SIG_DESC_SET(SCU510, 1)); 303 PIN_DECL_2(C26, GPIOE3, NDCD4, RGMII4RXCTL); 304 FUNC_GROUP_DECL(NDCD4, C26); 305 306 #define C24 36 307 SIG_EXPR_LIST_DECL_SESG(C24, NDSR4, NDSR4, SIG_DESC_SET(SCU414, 4)); 308 SIG_EXPR_LIST_DECL_SESG(C24, RGMII4RXD0, RGMII4, SIG_DESC_SET(SCU4B4, 4), 309 SIG_DESC_SET(SCU510, 1)); 310 SIG_EXPR_LIST_DECL_SESG(C24, RMII4RXD0, RMII4, SIG_DESC_SET(SCU4B4, 4), 311 SIG_DESC_CLEAR(SCU510, 1)); 312 PIN_DECL_3(C24, GPIOE4, NDSR4, RGMII4RXD0, RMII4RXD0); 313 FUNC_GROUP_DECL(NDSR4, C24); 314 315 #define B26 37 316 SIG_EXPR_LIST_DECL_SESG(B26, NRI4, NRI4, SIG_DESC_SET(SCU414, 5)); 317 SIG_EXPR_LIST_DECL_SESG(B26, RGMII4RXD1, RGMII4, SIG_DESC_SET(SCU4B4, 5), 318 SIG_DESC_SET(SCU510, 1)); 319 SIG_EXPR_LIST_DECL_SESG(B26, RMII4RXD1, RMII4, SIG_DESC_SET(SCU4B4, 5), 320 SIG_DESC_CLEAR(SCU510, 1)); 321 PIN_DECL_3(B26, GPIOE5, NRI4, RGMII4RXD1, RMII4RXD1); 322 FUNC_GROUP_DECL(NRI4, B26); 323 324 #define B25 38 325 SIG_EXPR_LIST_DECL_SESG(B25, NDTR4, NDTR4, SIG_DESC_SET(SCU414, 6)); 326 SIG_EXPR_LIST_DECL_SESG(B25, RGMII4RXD2, RGMII4, SIG_DESC_SET(SCU4B4, 6), 327 SIG_DESC_SET(SCU510, 1)); 328 SIG_EXPR_LIST_DECL_SESG(B25, RMII4CRSDV, RMII4, SIG_DESC_SET(SCU4B4, 6), 329 SIG_DESC_CLEAR(SCU510, 1)); 330 PIN_DECL_3(B25, GPIOE6, NDTR4, RGMII4RXD2, RMII4CRSDV); 331 FUNC_GROUP_DECL(NDTR4, B25); 332 333 #define B24 39 334 SIG_EXPR_LIST_DECL_SESG(B24, NRTS4, NRTS4, SIG_DESC_SET(SCU414, 7)); 335 SIG_EXPR_LIST_DECL_SESG(B24, RGMII4RXD3, RGMII4, SIG_DESC_SET(SCU4B4, 7), 336 SIG_DESC_SET(SCU510, 1)); 337 SIG_EXPR_LIST_DECL_SESG(B24, RMII4RXER, RMII4, SIG_DESC_SET(SCU4B4, 7), 338 SIG_DESC_CLEAR(SCU510, 1)); 339 PIN_DECL_3(B24, GPIOE7, NRTS4, RGMII4RXD3, RMII4RXER); 340 FUNC_GROUP_DECL(NRTS4, B24); 341 342 FUNC_GROUP_DECL(RGMII4, F24, E23, E24, E25, D26, D24, C25, C26, C24, B26, B25, 343 B24); 344 FUNC_GROUP_DECL(RMII4, F24, E23, E24, E25, C25, C24, B26, B25, B24); 345 346 #define D22 40 347 SIG_EXPR_LIST_DECL_SESG(D22, SD1CLK, SD1, SIG_DESC_SET(SCU414, 8)); 348 SIG_EXPR_LIST_DECL_SEMG(D22, PWM8, PWM8G0, PWM8, SIG_DESC_SET(SCU414, 8)); 349 PIN_DECL_2(D22, GPIOF0, SD1CLK, PWM8); 350 GROUP_DECL(PWM8G0, D22); 351 352 #define E22 41 353 SIG_EXPR_LIST_DECL_SESG(E22, SD1CMD, SD1, SIG_DESC_SET(SCU414, 9)); 354 SIG_EXPR_LIST_DECL_SEMG(E22, PWM9, PWM9G0, PWM9, SIG_DESC_SET(SCU4B4, 9)); 355 PIN_DECL_2(E22, GPIOF1, SD1CMD, PWM9); 356 GROUP_DECL(PWM9G0, E22); 357 358 #define D23 42 359 SIG_EXPR_LIST_DECL_SESG(D23, SD1DAT0, SD1, SIG_DESC_SET(SCU414, 10)); 360 SIG_EXPR_LIST_DECL_SEMG(D23, PWM10, PWM10G0, PWM10, SIG_DESC_SET(SCU4B4, 10)); 361 PIN_DECL_2(D23, GPIOF2, SD1DAT0, PWM10); 362 GROUP_DECL(PWM10G0, D23); 363 364 #define C23 43 365 SIG_EXPR_LIST_DECL_SESG(C23, SD1DAT1, SD1, SIG_DESC_SET(SCU414, 11)); 366 SIG_EXPR_LIST_DECL_SEMG(C23, PWM11, PWM11G0, PWM11, SIG_DESC_SET(SCU4B4, 11)); 367 PIN_DECL_2(C23, GPIOF3, SD1DAT1, PWM11); 368 GROUP_DECL(PWM11G0, C23); 369 370 #define C22 44 371 SIG_EXPR_LIST_DECL_SESG(C22, SD1DAT2, SD1, SIG_DESC_SET(SCU414, 12)); 372 SIG_EXPR_LIST_DECL_SEMG(C22, PWM12, PWM12G0, PWM12, SIG_DESC_SET(SCU4B4, 12)); 373 PIN_DECL_2(C22, GPIOF4, SD1DAT2, PWM12); 374 GROUP_DECL(PWM12G0, C22); 375 376 #define A25 45 377 SIG_EXPR_LIST_DECL_SESG(A25, SD1DAT3, SD1, SIG_DESC_SET(SCU414, 13)); 378 SIG_EXPR_LIST_DECL_SEMG(A25, PWM13, PWM13G0, PWM13, SIG_DESC_SET(SCU4B4, 13)); 379 PIN_DECL_2(A25, GPIOF5, SD1DAT3, PWM13); 380 GROUP_DECL(PWM13G0, A25); 381 382 #define A24 46 383 SIG_EXPR_LIST_DECL_SESG(A24, SD1CD, SD1, SIG_DESC_SET(SCU414, 14)); 384 SIG_EXPR_LIST_DECL_SEMG(A24, PWM14, PWM14G0, PWM14, SIG_DESC_SET(SCU4B4, 14)); 385 PIN_DECL_2(A24, GPIOF6, SD1CD, PWM14); 386 GROUP_DECL(PWM14G0, A24); 387 388 #define A23 47 389 SIG_EXPR_LIST_DECL_SESG(A23, SD1WP, SD1, SIG_DESC_SET(SCU414, 15)); 390 SIG_EXPR_LIST_DECL_SEMG(A23, PWM15, PWM15G0, PWM15, SIG_DESC_SET(SCU4B4, 15)); 391 PIN_DECL_2(A23, GPIOF7, SD1WP, PWM15); 392 GROUP_DECL(PWM15G0, A23); 393 394 FUNC_GROUP_DECL(SD1, D22, E22, D23, C23, C22, A25, A24, A23); 395 396 #define E21 48 397 SIG_EXPR_LIST_DECL_SESG(E21, TXD6, UART6, SIG_DESC_SET(SCU414, 16)); 398 SIG_EXPR_LIST_DECL_SESG(E21, SD2CLK, SD2, SIG_DESC_SET(SCU4B4, 16), 399 SIG_DESC_SET(SCU450, 1)); 400 SIG_EXPR_LIST_DECL_SEMG(E21, SALT9, SALT9G0, SALT9, SIG_DESC_SET(SCU694, 16)); 401 PIN_DECL_3(E21, GPIOG0, TXD6, SD2CLK, SALT9); 402 GROUP_DECL(SALT9G0, E21); 403 404 #define B22 49 405 SIG_EXPR_LIST_DECL_SESG(B22, RXD6, UART6, SIG_DESC_SET(SCU414, 17)); 406 SIG_EXPR_LIST_DECL_SESG(B22, SD2CMD, SD2, SIG_DESC_SET(SCU4B4, 17), 407 SIG_DESC_SET(SCU450, 1)); 408 SIG_EXPR_LIST_DECL_SEMG(B22, SALT10, SALT10G0, SALT10, 409 SIG_DESC_SET(SCU694, 17)); 410 PIN_DECL_3(B22, GPIOG1, RXD6, SD2CMD, SALT10); 411 GROUP_DECL(SALT10G0, B22); 412 413 FUNC_GROUP_DECL(UART6, E21, B22); 414 415 #define C21 50 416 SIG_EXPR_LIST_DECL_SESG(C21, TXD7, UART7, SIG_DESC_SET(SCU414, 18)); 417 SIG_EXPR_LIST_DECL_SESG(C21, SD2DAT0, SD2, SIG_DESC_SET(SCU4B4, 18), 418 SIG_DESC_SET(SCU450, 1)); 419 SIG_EXPR_LIST_DECL_SEMG(C21, SALT11, SALT11G0, SALT11, 420 SIG_DESC_SET(SCU694, 18)); 421 PIN_DECL_3(C21, GPIOG2, TXD7, SD2DAT0, SALT11); 422 GROUP_DECL(SALT11G0, C21); 423 424 #define A22 51 425 SIG_EXPR_LIST_DECL_SESG(A22, RXD7, UART7, SIG_DESC_SET(SCU414, 19)); 426 SIG_EXPR_LIST_DECL_SESG(A22, SD2DAT1, SD2, SIG_DESC_SET(SCU4B4, 19), 427 SIG_DESC_SET(SCU450, 1)); 428 SIG_EXPR_LIST_DECL_SEMG(A22, SALT12, SALT12G0, SALT12, 429 SIG_DESC_SET(SCU694, 19)); 430 PIN_DECL_3(A22, GPIOG3, RXD7, SD2DAT1, SALT12); 431 GROUP_DECL(SALT12G0, A22); 432 433 FUNC_GROUP_DECL(UART7, C21, A22); 434 435 #define A21 52 436 SIG_EXPR_LIST_DECL_SESG(A21, TXD8, UART8, SIG_DESC_SET(SCU414, 20)); 437 SIG_EXPR_LIST_DECL_SESG(A21, SD2DAT2, SD2, SIG_DESC_SET(SCU4B4, 20), 438 SIG_DESC_SET(SCU450, 1)); 439 SIG_EXPR_LIST_DECL_SEMG(A21, SALT13, SALT13G0, SALT13, 440 SIG_DESC_SET(SCU694, 20)); 441 PIN_DECL_3(A21, GPIOG4, TXD8, SD2DAT2, SALT13); 442 GROUP_DECL(SALT13G0, A21); 443 444 #define E20 53 445 SIG_EXPR_LIST_DECL_SESG(E20, RXD8, UART8, SIG_DESC_SET(SCU414, 21)); 446 SIG_EXPR_LIST_DECL_SESG(E20, SD2DAT3, SD2, SIG_DESC_SET(SCU4B4, 21), 447 SIG_DESC_SET(SCU450, 1)); 448 SIG_EXPR_LIST_DECL_SEMG(E20, SALT14, SALT14G0, SALT14, 449 SIG_DESC_SET(SCU694, 21)); 450 PIN_DECL_3(E20, GPIOG5, RXD8, SD2DAT3, SALT14); 451 GROUP_DECL(SALT14G0, E20); 452 453 FUNC_GROUP_DECL(UART8, A21, E20); 454 455 #define D21 54 456 SIG_EXPR_LIST_DECL_SESG(D21, TXD9, UART9, SIG_DESC_SET(SCU414, 22)); 457 SIG_EXPR_LIST_DECL_SESG(D21, SD2CD, SD2, SIG_DESC_SET(SCU4B4, 22), 458 SIG_DESC_SET(SCU450, 1)); 459 SIG_EXPR_LIST_DECL_SEMG(D21, SALT15, SALT15G0, SALT15, 460 SIG_DESC_SET(SCU694, 22)); 461 PIN_DECL_3(D21, GPIOG6, TXD9, SD2CD, SALT15); 462 GROUP_DECL(SALT15G0, D21); 463 464 #define B21 55 465 SIG_EXPR_LIST_DECL_SESG(B21, RXD9, UART9, SIG_DESC_SET(SCU414, 23)); 466 SIG_EXPR_LIST_DECL_SESG(B21, SD2WP, SD2, SIG_DESC_SET(SCU4B4, 23), 467 SIG_DESC_SET(SCU450, 1)); 468 SIG_EXPR_LIST_DECL_SEMG(B21, SALT16, SALT16G0, SALT16, 469 SIG_DESC_SET(SCU694, 23)); 470 PIN_DECL_3(B21, GPIOG7, RXD9, SD2WP, SALT16); 471 GROUP_DECL(SALT16G0, B21); 472 473 FUNC_GROUP_DECL(UART9, D21, B21); 474 475 FUNC_GROUP_DECL(SD2, E21, B22, C21, A22, A21, E20, D21, B21); 476 477 #define A18 56 478 SIG_EXPR_LIST_DECL_SESG(A18, SGPM1CLK, SGPM1, SIG_DESC_SET(SCU414, 24)); 479 PIN_DECL_1(A18, GPIOH0, SGPM1CLK); 480 481 #define B18 57 482 SIG_EXPR_LIST_DECL_SESG(B18, SGPM1LD, SGPM1, SIG_DESC_SET(SCU414, 25)); 483 PIN_DECL_1(B18, GPIOH1, SGPM1LD); 484 485 #define C18 58 486 SIG_EXPR_LIST_DECL_SESG(C18, SGPM1O, SGPM1, SIG_DESC_SET(SCU414, 26)); 487 PIN_DECL_1(C18, GPIOH2, SGPM1O); 488 489 #define A17 59 490 SIG_EXPR_LIST_DECL_SESG(A17, SGPM1I, SGPM1, SIG_DESC_SET(SCU414, 27)); 491 PIN_DECL_1(A17, GPIOH3, SGPM1I); 492 493 FUNC_GROUP_DECL(SGPM1, A18, B18, C18, A17); 494 495 #define D18 60 496 SIG_EXPR_LIST_DECL_SESG(D18, SGPS1CK, SGPS1, SIG_DESC_SET(SCU414, 28)); 497 SIG_EXPR_LIST_DECL_SESG(D18, SCL15, I2C15, SIG_DESC_SET(SCU4B4, 28)); 498 PIN_DECL_2(D18, GPIOH4, SGPS1CK, SCL15); 499 500 #define B17 61 501 SIG_EXPR_LIST_DECL_SESG(B17, SGPS1LD, SGPS1, SIG_DESC_SET(SCU414, 29)); 502 SIG_EXPR_LIST_DECL_SESG(B17, SDA15, I2C15, SIG_DESC_SET(SCU4B4, 29)); 503 PIN_DECL_2(B17, GPIOH5, SGPS1LD, SDA15); 504 505 FUNC_GROUP_DECL(I2C15, D18, B17); 506 507 #define C17 62 508 SIG_EXPR_LIST_DECL_SESG(C17, SGPS1O, SGPS1, SIG_DESC_SET(SCU414, 30)); 509 SIG_EXPR_LIST_DECL_SESG(C17, SCL16, I2C16, SIG_DESC_SET(SCU4B4, 30)); 510 PIN_DECL_2(C17, GPIOH6, SGPS1O, SCL16); 511 512 #define E18 63 513 SIG_EXPR_LIST_DECL_SESG(E18, SGPS1I, SGPS1, SIG_DESC_SET(SCU414, 31)); 514 SIG_EXPR_LIST_DECL_SESG(E18, SDA16, I2C16, SIG_DESC_SET(SCU4B4, 31)); 515 PIN_DECL_2(E18, GPIOH7, SGPS1I, SDA16); 516 517 FUNC_GROUP_DECL(I2C16, C17, E18); 518 FUNC_GROUP_DECL(SGPS1, D18, B17, C17, E18); 519 520 #define D17 64 521 SIG_EXPR_LIST_DECL_SESG(D17, MTRSTN, JTAGM, SIG_DESC_SET(SCU418, 0)); 522 SIG_EXPR_LIST_DECL_SEMG(D17, TXD12, UART12G0, UART12, SIG_DESC_SET(SCU4B8, 0)); 523 PIN_DECL_2(D17, GPIOI0, MTRSTN, TXD12); 524 525 #define A16 65 526 SIG_EXPR_LIST_DECL_SESG(A16, MTDI, JTAGM, SIG_DESC_SET(SCU418, 1)); 527 SIG_EXPR_LIST_DECL_SEMG(A16, RXD12, UART12G0, UART12, SIG_DESC_SET(SCU4B8, 1)); 528 PIN_DECL_2(A16, GPIOI1, MTDI, RXD12); 529 530 GROUP_DECL(UART12G0, D17, A16); 531 532 #define E17 66 533 SIG_EXPR_LIST_DECL_SESG(E17, MTCK, JTAGM, SIG_DESC_SET(SCU418, 2)); 534 SIG_EXPR_LIST_DECL_SEMG(E17, TXD13, UART13G0, UART13, SIG_DESC_SET(SCU4B8, 2)); 535 PIN_DECL_2(E17, GPIOI2, MTCK, TXD13); 536 537 #define D16 67 538 SIG_EXPR_LIST_DECL_SESG(D16, MTMS, JTAGM, SIG_DESC_SET(SCU418, 3)); 539 SIG_EXPR_LIST_DECL_SEMG(D16, RXD13, UART13G0, UART13, SIG_DESC_SET(SCU4B8, 3)); 540 PIN_DECL_2(D16, GPIOI3, MTMS, RXD13); 541 542 GROUP_DECL(UART13G0, E17, D16); 543 544 #define C16 68 545 SIG_EXPR_LIST_DECL_SESG(C16, MTDO, JTAGM, SIG_DESC_SET(SCU418, 4)); 546 PIN_DECL_1(C16, GPIOI4, MTDO); 547 548 FUNC_GROUP_DECL(JTAGM, D17, A16, E17, D16, C16); 549 550 #define E16 69 551 SIG_EXPR_LIST_DECL_SESG(E16, SIOPBO, SIOPBO, SIG_DESC_SET(SCU418, 5)); 552 PIN_DECL_1(E16, GPIOI5, SIOPBO); 553 FUNC_GROUP_DECL(SIOPBO, E16); 554 555 #define B16 70 556 SIG_EXPR_LIST_DECL_SESG(B16, SIOPBI, SIOPBI, SIG_DESC_SET(SCU418, 6)); 557 PIN_DECL_1(B16, GPIOI6, SIOPBI); 558 FUNC_GROUP_DECL(SIOPBI, B16); 559 560 #define A15 71 561 SIG_EXPR_LIST_DECL_SESG(A15, BMCINT, BMCINT, SIG_DESC_SET(SCU418, 7)); 562 SIG_EXPR_LIST_DECL_SESG(A15, SIOSCI, SIOSCI, SIG_DESC_SET(SCU4B8, 7)); 563 PIN_DECL_2(A15, GPIOI7, BMCINT, SIOSCI); 564 FUNC_GROUP_DECL(BMCINT, A15); 565 FUNC_GROUP_DECL(SIOSCI, A15); 566 567 #define B20 72 568 SIG_EXPR_LIST_DECL_SEMG(B20, I3C3SCL, HVI3C3, I3C3, SIG_DESC_SET(SCU418, 8)); 569 SIG_EXPR_LIST_DECL_SESG(B20, SCL1, I2C1, SIG_DESC_SET(SCU4B8, 8)); 570 PIN_DECL_2(B20, GPIOJ0, I3C3SCL, SCL1); 571 572 #define A20 73 573 SIG_EXPR_LIST_DECL_SEMG(A20, I3C3SDA, HVI3C3, I3C3, SIG_DESC_SET(SCU418, 9)); 574 SIG_EXPR_LIST_DECL_SESG(A20, SDA1, I2C1, SIG_DESC_SET(SCU4B8, 9)); 575 PIN_DECL_2(A20, GPIOJ1, I3C3SDA, SDA1); 576 577 GROUP_DECL(HVI3C3, B20, A20); 578 FUNC_GROUP_DECL(I2C1, B20, A20); 579 580 #define E19 74 581 SIG_EXPR_LIST_DECL_SEMG(E19, I3C4SCL, HVI3C4, I3C4, SIG_DESC_SET(SCU418, 10)); 582 SIG_EXPR_LIST_DECL_SESG(E19, SCL2, I2C2, SIG_DESC_SET(SCU4B8, 10)); 583 PIN_DECL_2(E19, GPIOJ2, I3C4SCL, SCL2); 584 585 #define D20 75 586 SIG_EXPR_LIST_DECL_SEMG(D20, I3C4SDA, HVI3C4, I3C4, SIG_DESC_SET(SCU418, 11)); 587 SIG_EXPR_LIST_DECL_SESG(D20, SDA2, I2C2, SIG_DESC_SET(SCU4B8, 11)); 588 PIN_DECL_2(D20, GPIOJ3, I3C4SDA, SDA2); 589 590 GROUP_DECL(HVI3C4, E19, D20); 591 FUNC_GROUP_DECL(I2C2, E19, D20); 592 593 #define C19 76 594 SIG_EXPR_LIST_DECL_SESG(C19, I3C5SCL, I3C5, SIG_DESC_SET(SCU418, 12)); 595 SIG_EXPR_LIST_DECL_SESG(C19, SCL3, I2C3, SIG_DESC_SET(SCU4B8, 12)); 596 PIN_DECL_2(C19, GPIOJ4, I3C5SCL, SCL3); 597 598 #define A19 77 599 SIG_EXPR_LIST_DECL_SESG(A19, I3C5SDA, I3C5, SIG_DESC_SET(SCU418, 13)); 600 SIG_EXPR_LIST_DECL_SESG(A19, SDA3, I2C3, SIG_DESC_SET(SCU4B8, 13)); 601 PIN_DECL_2(A19, GPIOJ5, I3C5SDA, SDA3); 602 603 FUNC_GROUP_DECL(I3C5, C19, A19); 604 FUNC_GROUP_DECL(I2C3, C19, A19); 605 606 #define C20 78 607 SIG_EXPR_LIST_DECL_SESG(C20, I3C6SCL, I3C6, SIG_DESC_SET(SCU418, 14)); 608 SIG_EXPR_LIST_DECL_SESG(C20, SCL4, I2C4, SIG_DESC_SET(SCU4B8, 14)); 609 PIN_DECL_2(C20, GPIOJ6, I3C6SCL, SCL4); 610 611 #define D19 79 612 SIG_EXPR_LIST_DECL_SESG(D19, I3C6SDA, I3C6, SIG_DESC_SET(SCU418, 15)); 613 SIG_EXPR_LIST_DECL_SESG(D19, SDA4, I2C4, SIG_DESC_SET(SCU4B8, 15)); 614 PIN_DECL_2(D19, GPIOJ7, I3C6SDA, SDA4); 615 616 FUNC_GROUP_DECL(I3C6, C20, D19); 617 FUNC_GROUP_DECL(I2C4, C20, D19); 618 619 #define A11 80 620 SIG_EXPR_LIST_DECL_SESG(A11, SCL5, I2C5, SIG_DESC_SET(SCU418, 16)); 621 PIN_DECL_1(A11, GPIOK0, SCL5); 622 623 #define C11 81 624 SIG_EXPR_LIST_DECL_SESG(C11, SDA5, I2C5, SIG_DESC_SET(SCU418, 17)); 625 PIN_DECL_1(C11, GPIOK1, SDA5); 626 627 FUNC_GROUP_DECL(I2C5, A11, C11); 628 629 #define D12 82 630 SIG_EXPR_LIST_DECL_SESG(D12, SCL6, I2C6, SIG_DESC_SET(SCU418, 18)); 631 PIN_DECL_1(D12, GPIOK2, SCL6); 632 633 #define E13 83 634 SIG_EXPR_LIST_DECL_SESG(E13, SDA6, I2C6, SIG_DESC_SET(SCU418, 19)); 635 PIN_DECL_1(E13, GPIOK3, SDA6); 636 637 FUNC_GROUP_DECL(I2C6, D12, E13); 638 639 #define D11 84 640 SIG_EXPR_LIST_DECL_SESG(D11, SCL7, I2C7, SIG_DESC_SET(SCU418, 20)); 641 PIN_DECL_1(D11, GPIOK4, SCL7); 642 643 #define E11 85 644 SIG_EXPR_LIST_DECL_SESG(E11, SDA7, I2C7, SIG_DESC_SET(SCU418, 21)); 645 PIN_DECL_1(E11, GPIOK5, SDA7); 646 647 FUNC_GROUP_DECL(I2C7, D11, E11); 648 649 #define F13 86 650 SIG_EXPR_LIST_DECL_SESG(F13, SCL8, I2C8, SIG_DESC_SET(SCU418, 22)); 651 PIN_DECL_1(F13, GPIOK6, SCL8); 652 653 #define E12 87 654 SIG_EXPR_LIST_DECL_SESG(E12, SDA8, I2C8, SIG_DESC_SET(SCU418, 23)); 655 PIN_DECL_1(E12, GPIOK7, SDA8); 656 657 FUNC_GROUP_DECL(I2C8, F13, E12); 658 659 #define D15 88 660 SIG_EXPR_LIST_DECL_SESG(D15, SCL9, I2C9, SIG_DESC_SET(SCU418, 24)); 661 PIN_DECL_1(D15, GPIOL0, SCL9); 662 663 #define A14 89 664 SIG_EXPR_LIST_DECL_SESG(A14, SDA9, I2C9, SIG_DESC_SET(SCU418, 25)); 665 PIN_DECL_1(A14, GPIOL1, SDA9); 666 667 FUNC_GROUP_DECL(I2C9, D15, A14); 668 669 #define E15 90 670 SIG_EXPR_LIST_DECL_SESG(E15, SCL10, I2C10, SIG_DESC_SET(SCU418, 26)); 671 PIN_DECL_1(E15, GPIOL2, SCL10); 672 673 #define A13 91 674 SIG_EXPR_LIST_DECL_SESG(A13, SDA10, I2C10, SIG_DESC_SET(SCU418, 27)); 675 PIN_DECL_1(A13, GPIOL3, SDA10); 676 677 FUNC_GROUP_DECL(I2C10, E15, A13); 678 679 #define C15 92 680 SSSF_PIN_DECL(C15, GPIOL4, TXD3, SIG_DESC_SET(SCU418, 28)); 681 682 #define F15 93 683 SSSF_PIN_DECL(F15, GPIOL5, RXD3, SIG_DESC_SET(SCU418, 29)); 684 685 #define B14 94 686 SSSF_PIN_DECL(B14, GPIOL6, VGAHS, SIG_DESC_SET(SCU418, 30)); 687 688 #define C14 95 689 SSSF_PIN_DECL(C14, GPIOL7, VGAVS, SIG_DESC_SET(SCU418, 31)); 690 691 #define D14 96 692 SSSF_PIN_DECL(D14, GPIOM0, NCTS1, SIG_DESC_SET(SCU41C, 0)); 693 694 #define B13 97 695 SSSF_PIN_DECL(B13, GPIOM1, NDCD1, SIG_DESC_SET(SCU41C, 1)); 696 697 #define A12 98 698 SSSF_PIN_DECL(A12, GPIOM2, NDSR1, SIG_DESC_SET(SCU41C, 2)); 699 700 #define E14 99 701 SSSF_PIN_DECL(E14, GPIOM3, NRI1, SIG_DESC_SET(SCU41C, 3)); 702 703 #define B12 100 704 SSSF_PIN_DECL(B12, GPIOM4, NDTR1, SIG_DESC_SET(SCU41C, 4)); 705 706 #define C12 101 707 SSSF_PIN_DECL(C12, GPIOM5, NRTS1, SIG_DESC_SET(SCU41C, 5)); 708 709 #define C13 102 710 SSSF_PIN_DECL(C13, GPIOM6, TXD1, SIG_DESC_SET(SCU41C, 6)); 711 712 #define D13 103 713 SSSF_PIN_DECL(D13, GPIOM7, RXD1, SIG_DESC_SET(SCU41C, 7)); 714 715 #define P25 104 716 SSSF_PIN_DECL(P25, GPION0, NCTS2, SIG_DESC_SET(SCU41C, 8)); 717 718 #define N23 105 719 SSSF_PIN_DECL(N23, GPION1, NDCD2, SIG_DESC_SET(SCU41C, 9)); 720 721 #define N25 106 722 SSSF_PIN_DECL(N25, GPION2, NDSR2, SIG_DESC_SET(SCU41C, 10)); 723 724 #define N24 107 725 SSSF_PIN_DECL(N24, GPION3, NRI2, SIG_DESC_SET(SCU41C, 11)); 726 727 #define P26 108 728 SSSF_PIN_DECL(P26, GPION4, NDTR2, SIG_DESC_SET(SCU41C, 12)); 729 730 #define M23 109 731 SSSF_PIN_DECL(M23, GPION5, NRTS2, SIG_DESC_SET(SCU41C, 13)); 732 733 #define N26 110 734 SSSF_PIN_DECL(N26, GPION6, TXD2, SIG_DESC_SET(SCU41C, 14)); 735 736 #define M26 111 737 SSSF_PIN_DECL(M26, GPION7, RXD2, SIG_DESC_SET(SCU41C, 15)); 738 739 #define AD26 112 740 SSSF_PIN_DECL(AD26, GPIOO0, PWM0, SIG_DESC_SET(SCU41C, 16)); 741 742 #define AD22 113 743 SSSF_PIN_DECL(AD22, GPIOO1, PWM1, SIG_DESC_SET(SCU41C, 17)); 744 745 #define AD23 114 746 SSSF_PIN_DECL(AD23, GPIOO2, PWM2, SIG_DESC_SET(SCU41C, 18)); 747 748 #define AD24 115 749 SSSF_PIN_DECL(AD24, GPIOO3, PWM3, SIG_DESC_SET(SCU41C, 19)); 750 751 #define AD25 116 752 SSSF_PIN_DECL(AD25, GPIOO4, PWM4, SIG_DESC_SET(SCU41C, 20)); 753 754 #define AC22 117 755 SSSF_PIN_DECL(AC22, GPIOO5, PWM5, SIG_DESC_SET(SCU41C, 21)); 756 757 #define AC24 118 758 SSSF_PIN_DECL(AC24, GPIOO6, PWM6, SIG_DESC_SET(SCU41C, 22)); 759 760 #define AC23 119 761 SSSF_PIN_DECL(AC23, GPIOO7, PWM7, SIG_DESC_SET(SCU41C, 23)); 762 763 #define AB22 120 764 SIG_EXPR_LIST_DECL_SEMG(AB22, PWM8, PWM8G1, PWM8, SIG_DESC_SET(SCU41C, 24)); 765 SIG_EXPR_LIST_DECL_SESG(AB22, THRUIN0, THRU0, SIG_DESC_SET(SCU4BC, 24)); 766 PIN_DECL_2(AB22, GPIOP0, PWM8, THRUIN0); 767 GROUP_DECL(PWM8G1, AB22); 768 FUNC_DECL_2(PWM8, PWM8G0, PWM8G1); 769 770 #define W24 121 771 SIG_EXPR_LIST_DECL_SEMG(W24, PWM9, PWM9G1, PWM9, SIG_DESC_SET(SCU41C, 25)); 772 SIG_EXPR_LIST_DECL_SESG(W24, THRUOUT0, THRU0, SIG_DESC_SET(SCU4BC, 25)); 773 PIN_DECL_2(W24, GPIOP1, PWM9, THRUOUT0); 774 775 FUNC_GROUP_DECL(THRU0, AB22, W24); 776 777 GROUP_DECL(PWM9G1, W24); 778 FUNC_DECL_2(PWM9, PWM9G0, PWM9G1); 779 780 #define AA23 122 781 SIG_EXPR_LIST_DECL_SEMG(AA23, PWM10, PWM10G1, PWM10, SIG_DESC_SET(SCU41C, 26)); 782 SIG_EXPR_LIST_DECL_SESG(AA23, THRUIN1, THRU1, SIG_DESC_SET(SCU4BC, 26)); 783 PIN_DECL_2(AA23, GPIOP2, PWM10, THRUIN1); 784 GROUP_DECL(PWM10G1, AA23); 785 FUNC_DECL_2(PWM10, PWM10G0, PWM10G1); 786 787 #define AA24 123 788 SIG_EXPR_LIST_DECL_SEMG(AA24, PWM11, PWM11G1, PWM11, SIG_DESC_SET(SCU41C, 27)); 789 SIG_EXPR_LIST_DECL_SESG(AA24, THRUOUT1, THRU1, SIG_DESC_SET(SCU4BC, 27)); 790 PIN_DECL_2(AA24, GPIOP3, PWM11, THRUOUT1); 791 GROUP_DECL(PWM11G1, AA24); 792 FUNC_DECL_2(PWM11, PWM11G0, PWM11G1); 793 794 FUNC_GROUP_DECL(THRU1, AA23, AA24); 795 796 #define W23 124 797 SIG_EXPR_LIST_DECL_SEMG(W23, PWM12, PWM12G1, PWM12, SIG_DESC_SET(SCU41C, 28)); 798 SIG_EXPR_LIST_DECL_SESG(W23, THRUIN2, THRU2, SIG_DESC_SET(SCU4BC, 28)); 799 PIN_DECL_2(W23, GPIOP4, PWM12, THRUIN2); 800 GROUP_DECL(PWM12G1, W23); 801 FUNC_DECL_2(PWM12, PWM12G0, PWM12G1); 802 803 #define AB23 125 804 SIG_EXPR_LIST_DECL_SEMG(AB23, PWM13, PWM13G1, PWM13, SIG_DESC_SET(SCU41C, 29)); 805 SIG_EXPR_LIST_DECL_SESG(AB23, THRUOUT2, THRU2, SIG_DESC_SET(SCU4BC, 29)); 806 PIN_DECL_2(AB23, GPIOP5, PWM13, THRUOUT2); 807 GROUP_DECL(PWM13G1, AB23); 808 FUNC_DECL_2(PWM13, PWM13G0, PWM13G1); 809 810 FUNC_GROUP_DECL(THRU2, W23, AB23); 811 812 #define AB24 126 813 SIG_EXPR_LIST_DECL_SEMG(AB24, PWM14, PWM14G1, PWM14, SIG_DESC_SET(SCU41C, 30)); 814 SIG_EXPR_LIST_DECL_SESG(AB24, THRUIN3, THRU3, SIG_DESC_SET(SCU4BC, 30)); 815 PIN_DECL_2(AB24, GPIOP6, PWM14, THRUIN3); 816 GROUP_DECL(PWM14G1, AB24); 817 FUNC_DECL_2(PWM14, PWM14G0, PWM14G1); 818 819 #define Y23 127 820 SIG_EXPR_LIST_DECL_SEMG(Y23, PWM15, PWM15G1, PWM15, SIG_DESC_SET(SCU41C, 31)); 821 SIG_EXPR_LIST_DECL_SESG(Y23, THRUOUT3, THRU3, SIG_DESC_SET(SCU4BC, 31)); 822 PIN_DECL_2(Y23, GPIOP7, PWM15, THRUOUT3); 823 GROUP_DECL(PWM15G1, Y23); 824 FUNC_DECL_2(PWM15, PWM15G0, PWM15G1); 825 826 FUNC_GROUP_DECL(THRU3, AB24, Y23); 827 828 #define AA25 128 829 SSSF_PIN_DECL(AA25, GPIOQ0, TACH0, SIG_DESC_SET(SCU430, 0)); 830 831 #define AB25 129 832 SSSF_PIN_DECL(AB25, GPIOQ1, TACH1, SIG_DESC_SET(SCU430, 1)); 833 834 #define Y24 130 835 SSSF_PIN_DECL(Y24, GPIOQ2, TACH2, SIG_DESC_SET(SCU430, 2)); 836 837 #define AB26 131 838 SSSF_PIN_DECL(AB26, GPIOQ3, TACH3, SIG_DESC_SET(SCU430, 3)); 839 840 #define Y26 132 841 SSSF_PIN_DECL(Y26, GPIOQ4, TACH4, SIG_DESC_SET(SCU430, 4)); 842 843 #define AC26 133 844 SSSF_PIN_DECL(AC26, GPIOQ5, TACH5, SIG_DESC_SET(SCU430, 5)); 845 846 #define Y25 134 847 SSSF_PIN_DECL(Y25, GPIOQ6, TACH6, SIG_DESC_SET(SCU430, 6)); 848 849 #define AA26 135 850 SSSF_PIN_DECL(AA26, GPIOQ7, TACH7, SIG_DESC_SET(SCU430, 7)); 851 852 #define V25 136 853 SSSF_PIN_DECL(V25, GPIOR0, TACH8, SIG_DESC_SET(SCU430, 8)); 854 855 #define U24 137 856 SSSF_PIN_DECL(U24, GPIOR1, TACH9, SIG_DESC_SET(SCU430, 9)); 857 858 #define V24 138 859 SSSF_PIN_DECL(V24, GPIOR2, TACH10, SIG_DESC_SET(SCU430, 10)); 860 861 #define V26 139 862 SSSF_PIN_DECL(V26, GPIOR3, TACH11, SIG_DESC_SET(SCU430, 11)); 863 864 #define U25 140 865 SSSF_PIN_DECL(U25, GPIOR4, TACH12, SIG_DESC_SET(SCU430, 12)); 866 867 #define T23 141 868 SSSF_PIN_DECL(T23, GPIOR5, TACH13, SIG_DESC_SET(SCU430, 13)); 869 870 #define W26 142 871 SSSF_PIN_DECL(W26, GPIOR6, TACH14, SIG_DESC_SET(SCU430, 14)); 872 873 #define U26 143 874 SSSF_PIN_DECL(U26, GPIOR7, TACH15, SIG_DESC_SET(SCU430, 15)); 875 876 #define R23 144 877 SIG_EXPR_LIST_DECL_SESG(R23, MDC1, MDIO1, SIG_DESC_SET(SCU430, 16)); 878 PIN_DECL_1(R23, GPIOS0, MDC1); 879 880 #define T25 145 881 SIG_EXPR_LIST_DECL_SESG(T25, MDIO1, MDIO1, SIG_DESC_SET(SCU430, 17)); 882 PIN_DECL_1(T25, GPIOS1, MDIO1); 883 884 FUNC_GROUP_DECL(MDIO1, R23, T25); 885 886 #define T26 146 887 SSSF_PIN_DECL(T26, GPIOS2, PEWAKE, SIG_DESC_SET(SCU430, 18)); 888 889 #define R24 147 890 SSSF_PIN_DECL(R24, GPIOS3, OSCCLK, SIG_DESC_SET(SCU430, 19)); 891 892 #define R26 148 893 SIG_EXPR_LIST_DECL_SESG(R26, TXD10, UART10, SIG_DESC_SET(SCU430, 20)); 894 PIN_DECL_1(R26, GPIOS4, TXD10); 895 896 #define P24 149 897 SIG_EXPR_LIST_DECL_SESG(P24, RXD10, UART10, SIG_DESC_SET(SCU430, 21)); 898 PIN_DECL_1(P24, GPIOS5, RXD10); 899 900 FUNC_GROUP_DECL(UART10, R26, P24); 901 902 #define P23 150 903 SIG_EXPR_LIST_DECL_SESG(P23, TXD11, UART11, SIG_DESC_SET(SCU430, 22)); 904 PIN_DECL_1(P23, GPIOS6, TXD11); 905 906 #define T24 151 907 SIG_EXPR_LIST_DECL_SESG(T24, RXD11, UART11, SIG_DESC_SET(SCU430, 23)); 908 PIN_DECL_1(T24, GPIOS7, RXD11); 909 910 FUNC_GROUP_DECL(UART11, P23, T24); 911 912 #define AD20 152 913 SIG_EXPR_LIST_DECL_SESG(AD20, GPIT0, GPIT0, SIG_DESC_SET(SCU430, 24)); 914 SIG_EXPR_LIST_DECL_SESG(AD20, ADC0, ADC0); 915 PIN_DECL_(AD20, SIG_EXPR_LIST_PTR(AD20, GPIT0), SIG_EXPR_LIST_PTR(AD20, ADC0)); 916 FUNC_GROUP_DECL(GPIT0, AD20); 917 FUNC_GROUP_DECL(ADC0, AD20); 918 919 #define AC18 153 920 SIG_EXPR_LIST_DECL_SESG(AC18, GPIT1, GPIT1, SIG_DESC_SET(SCU430, 25)); 921 SIG_EXPR_LIST_DECL_SESG(AC18, ADC1, ADC1); 922 PIN_DECL_(AC18, SIG_EXPR_LIST_PTR(AC18, GPIT1), SIG_EXPR_LIST_PTR(AC18, ADC1)); 923 FUNC_GROUP_DECL(GPIT1, AC18); 924 FUNC_GROUP_DECL(ADC1, AC18); 925 926 #define AE19 154 927 SIG_EXPR_LIST_DECL_SESG(AE19, GPIT2, GPIT2, SIG_DESC_SET(SCU430, 26)); 928 SIG_EXPR_LIST_DECL_SESG(AE19, ADC2, ADC2); 929 PIN_DECL_(AE19, SIG_EXPR_LIST_PTR(AE19, GPIT2), SIG_EXPR_LIST_PTR(AE19, ADC2)); 930 FUNC_GROUP_DECL(GPIT2, AE19); 931 FUNC_GROUP_DECL(ADC2, AE19); 932 933 #define AD19 155 934 SIG_EXPR_LIST_DECL_SESG(AD19, GPIT3, GPIT3, SIG_DESC_SET(SCU430, 27)); 935 SIG_EXPR_LIST_DECL_SESG(AD19, ADC3, ADC3); 936 PIN_DECL_(AD19, SIG_EXPR_LIST_PTR(AD19, GPIT3), SIG_EXPR_LIST_PTR(AD19, ADC3)); 937 FUNC_GROUP_DECL(GPIT3, AD19); 938 FUNC_GROUP_DECL(ADC3, AD19); 939 940 #define AC19 156 941 SIG_EXPR_LIST_DECL_SESG(AC19, GPIT4, GPIT4, SIG_DESC_SET(SCU430, 28)); 942 SIG_EXPR_LIST_DECL_SESG(AC19, ADC4, ADC4); 943 PIN_DECL_(AC19, SIG_EXPR_LIST_PTR(AC19, GPIT4), SIG_EXPR_LIST_PTR(AC19, ADC4)); 944 FUNC_GROUP_DECL(GPIT4, AC19); 945 FUNC_GROUP_DECL(ADC4, AC19); 946 947 #define AB19 157 948 SIG_EXPR_LIST_DECL_SESG(AB19, GPIT5, GPIT5, SIG_DESC_SET(SCU430, 29)); 949 SIG_EXPR_LIST_DECL_SESG(AB19, ADC5, ADC5); 950 PIN_DECL_(AB19, SIG_EXPR_LIST_PTR(AB19, GPIT5), SIG_EXPR_LIST_PTR(AB19, ADC5)); 951 FUNC_GROUP_DECL(GPIT5, AB19); 952 FUNC_GROUP_DECL(ADC5, AB19); 953 954 #define AB18 158 955 SIG_EXPR_LIST_DECL_SESG(AB18, GPIT6, GPIT6, SIG_DESC_SET(SCU430, 30)); 956 SIG_EXPR_LIST_DECL_SESG(AB18, ADC6, ADC6); 957 PIN_DECL_(AB18, SIG_EXPR_LIST_PTR(AB18, GPIT6), SIG_EXPR_LIST_PTR(AB18, ADC6)); 958 FUNC_GROUP_DECL(GPIT6, AB18); 959 FUNC_GROUP_DECL(ADC6, AB18); 960 961 #define AE18 159 962 SIG_EXPR_LIST_DECL_SESG(AE18, GPIT7, GPIT7, SIG_DESC_SET(SCU430, 31)); 963 SIG_EXPR_LIST_DECL_SESG(AE18, ADC7, ADC7); 964 PIN_DECL_(AE18, SIG_EXPR_LIST_PTR(AE18, GPIT7), SIG_EXPR_LIST_PTR(AE18, ADC7)); 965 FUNC_GROUP_DECL(GPIT7, AE18); 966 FUNC_GROUP_DECL(ADC7, AE18); 967 968 #define AB16 160 969 SIG_EXPR_LIST_DECL_SEMG(AB16, SALT9, SALT9G1, SALT9, SIG_DESC_SET(SCU434, 0), 970 SIG_DESC_CLEAR(SCU694, 16)); 971 SIG_EXPR_LIST_DECL_SESG(AB16, GPIU0, GPIU0, SIG_DESC_SET(SCU434, 0), 972 SIG_DESC_SET(SCU694, 16)); 973 SIG_EXPR_LIST_DECL_SESG(AB16, ADC8, ADC8); 974 PIN_DECL_(AB16, SIG_EXPR_LIST_PTR(AB16, SALT9), SIG_EXPR_LIST_PTR(AB16, GPIU0), 975 SIG_EXPR_LIST_PTR(AB16, ADC8)); 976 GROUP_DECL(SALT9G1, AB16); 977 FUNC_DECL_2(SALT9, SALT9G0, SALT9G1); 978 FUNC_GROUP_DECL(GPIU0, AB16); 979 FUNC_GROUP_DECL(ADC8, AB16); 980 981 #define AA17 161 982 SIG_EXPR_LIST_DECL_SEMG(AA17, SALT10, SALT10G1, SALT10, SIG_DESC_SET(SCU434, 1), 983 SIG_DESC_CLEAR(SCU694, 17)); 984 SIG_EXPR_LIST_DECL_SESG(AA17, GPIU1, GPIU1, SIG_DESC_SET(SCU434, 1), 985 SIG_DESC_SET(SCU694, 17)); 986 SIG_EXPR_LIST_DECL_SESG(AA17, ADC9, ADC9); 987 PIN_DECL_(AA17, SIG_EXPR_LIST_PTR(AA17, SALT10), SIG_EXPR_LIST_PTR(AA17, GPIU1), 988 SIG_EXPR_LIST_PTR(AA17, ADC9)); 989 GROUP_DECL(SALT10G1, AA17); 990 FUNC_DECL_2(SALT10, SALT10G0, SALT10G1); 991 FUNC_GROUP_DECL(GPIU1, AA17); 992 FUNC_GROUP_DECL(ADC9, AA17); 993 994 #define AB17 162 995 SIG_EXPR_LIST_DECL_SEMG(AB17, SALT11, SALT11G1, SALT11, SIG_DESC_SET(SCU434, 2), 996 SIG_DESC_CLEAR(SCU694, 18)); 997 SIG_EXPR_LIST_DECL_SESG(AB17, GPIU2, GPIU2, SIG_DESC_SET(SCU434, 2), 998 SIG_DESC_SET(SCU694, 18)); 999 SIG_EXPR_LIST_DECL_SESG(AB17, ADC10, ADC10); 1000 PIN_DECL_(AB17, SIG_EXPR_LIST_PTR(AB17, SALT11), SIG_EXPR_LIST_PTR(AB17, GPIU2), 1001 SIG_EXPR_LIST_PTR(AB17, ADC10)); 1002 GROUP_DECL(SALT11G1, AB17); 1003 FUNC_DECL_2(SALT11, SALT11G0, SALT11G1); 1004 FUNC_GROUP_DECL(GPIU2, AB17); 1005 FUNC_GROUP_DECL(ADC10, AB17); 1006 1007 #define AE16 163 1008 SIG_EXPR_LIST_DECL_SEMG(AE16, SALT12, SALT12G1, SALT12, SIG_DESC_SET(SCU434, 3), 1009 SIG_DESC_CLEAR(SCU694, 19)); 1010 SIG_EXPR_LIST_DECL_SESG(AE16, GPIU3, GPIU3, SIG_DESC_SET(SCU434, 3), 1011 SIG_DESC_SET(SCU694, 19)); 1012 SIG_EXPR_LIST_DECL_SESG(AE16, ADC11, ADC11); 1013 PIN_DECL_(AE16, SIG_EXPR_LIST_PTR(AE16, SALT12), SIG_EXPR_LIST_PTR(AE16, GPIU3), 1014 SIG_EXPR_LIST_PTR(AE16, ADC11)); 1015 GROUP_DECL(SALT12G1, AE16); 1016 FUNC_DECL_2(SALT12, SALT12G0, SALT12G1); 1017 FUNC_GROUP_DECL(GPIU3, AE16); 1018 FUNC_GROUP_DECL(ADC11, AE16); 1019 1020 #define AC16 164 1021 SIG_EXPR_LIST_DECL_SEMG(AC16, SALT13, SALT13G1, SALT13, SIG_DESC_SET(SCU434, 4), 1022 SIG_DESC_CLEAR(SCU694, 20)); 1023 SIG_EXPR_LIST_DECL_SESG(AC16, GPIU4, GPIU4, SIG_DESC_SET(SCU434, 4), 1024 SIG_DESC_SET(SCU694, 20)); 1025 SIG_EXPR_LIST_DECL_SESG(AC16, ADC12, ADC12); 1026 PIN_DECL_(AC16, SIG_EXPR_LIST_PTR(AC16, SALT13), SIG_EXPR_LIST_PTR(AC16, GPIU4), 1027 SIG_EXPR_LIST_PTR(AC16, ADC12)); 1028 GROUP_DECL(SALT13G1, AC16); 1029 FUNC_DECL_2(SALT13, SALT13G0, SALT13G1); 1030 FUNC_GROUP_DECL(GPIU4, AC16); 1031 FUNC_GROUP_DECL(ADC12, AC16); 1032 1033 #define AA16 165 1034 SIG_EXPR_LIST_DECL_SEMG(AA16, SALT14, SALT14G1, SALT14, SIG_DESC_SET(SCU434, 5), 1035 SIG_DESC_CLEAR(SCU694, 21)); 1036 SIG_EXPR_LIST_DECL_SESG(AA16, GPIU5, GPIU5, SIG_DESC_SET(SCU434, 5), 1037 SIG_DESC_SET(SCU694, 21)); 1038 SIG_EXPR_LIST_DECL_SESG(AA16, ADC13, ADC13); 1039 PIN_DECL_(AA16, SIG_EXPR_LIST_PTR(AA16, SALT14), SIG_EXPR_LIST_PTR(AA16, GPIU5), 1040 SIG_EXPR_LIST_PTR(AA16, ADC13)); 1041 GROUP_DECL(SALT14G1, AA16); 1042 FUNC_DECL_2(SALT14, SALT14G0, SALT14G1); 1043 FUNC_GROUP_DECL(GPIU5, AA16); 1044 FUNC_GROUP_DECL(ADC13, AA16); 1045 1046 #define AD16 166 1047 SIG_EXPR_LIST_DECL_SEMG(AD16, SALT15, SALT15G1, SALT15, SIG_DESC_SET(SCU434, 6), 1048 SIG_DESC_CLEAR(SCU694, 22)); 1049 SIG_EXPR_LIST_DECL_SESG(AD16, GPIU6, GPIU6, SIG_DESC_SET(SCU434, 6), 1050 SIG_DESC_SET(SCU694, 22)); 1051 SIG_EXPR_LIST_DECL_SESG(AD16, ADC14, ADC14); 1052 PIN_DECL_(AD16, SIG_EXPR_LIST_PTR(AD16, SALT15), SIG_EXPR_LIST_PTR(AD16, GPIU6), 1053 SIG_EXPR_LIST_PTR(AD16, ADC14)); 1054 GROUP_DECL(SALT15G1, AD16); 1055 FUNC_DECL_2(SALT15, SALT15G0, SALT15G1); 1056 FUNC_GROUP_DECL(GPIU6, AD16); 1057 FUNC_GROUP_DECL(ADC14, AD16); 1058 1059 #define AC17 167 1060 SIG_EXPR_LIST_DECL_SEMG(AC17, SALT16, SALT16G1, SALT16, SIG_DESC_SET(SCU434, 7), 1061 SIG_DESC_CLEAR(SCU694, 23)); 1062 SIG_EXPR_LIST_DECL_SESG(AC17, GPIU7, GPIU7, SIG_DESC_SET(SCU434, 7), 1063 SIG_DESC_SET(SCU694, 23)); 1064 SIG_EXPR_LIST_DECL_SESG(AC17, ADC15, ADC15); 1065 PIN_DECL_(AC17, SIG_EXPR_LIST_PTR(AC17, SALT16), SIG_EXPR_LIST_PTR(AC17, GPIU7), 1066 SIG_EXPR_LIST_PTR(AC17, ADC15)); 1067 GROUP_DECL(SALT16G1, AC17); 1068 FUNC_DECL_2(SALT16, SALT16G0, SALT16G1); 1069 FUNC_GROUP_DECL(GPIU7, AC17); 1070 FUNC_GROUP_DECL(ADC15, AC17); 1071 1072 #define AB15 168 1073 SSSF_PIN_DECL(AB15, GPIOV0, SIOS3, SIG_DESC_SET(SCU434, 8)); 1074 1075 #define AF14 169 1076 SSSF_PIN_DECL(AF14, GPIOV1, SIOS5, SIG_DESC_SET(SCU434, 9)); 1077 1078 #define AD14 170 1079 SSSF_PIN_DECL(AD14, GPIOV2, SIOPWREQ, SIG_DESC_SET(SCU434, 10)); 1080 1081 #define AC15 171 1082 SSSF_PIN_DECL(AC15, GPIOV3, SIOONCTRL, SIG_DESC_SET(SCU434, 11)); 1083 1084 #define AE15 172 1085 SSSF_PIN_DECL(AE15, GPIOV4, SIOPWRGD, SIG_DESC_SET(SCU434, 12)); 1086 1087 #define AE14 173 1088 SIG_EXPR_LIST_DECL_SESG(AE14, LPCPD, LPCPD, SIG_DESC_SET(SCU434, 13)); 1089 SIG_EXPR_LIST_DECL_SESG(AE14, LHPD, LHPD, SIG_DESC_SET(SCU4D4, 13)); 1090 PIN_DECL_2(AE14, GPIOV5, LPCPD, LHPD); 1091 FUNC_GROUP_DECL(LPCPD, AE14); 1092 FUNC_GROUP_DECL(LHPD, AE14); 1093 1094 #define AD15 174 1095 SSSF_PIN_DECL(AD15, GPIOV6, LPCPME, SIG_DESC_SET(SCU434, 14)); 1096 1097 #define AF15 175 1098 SSSF_PIN_DECL(AF15, GPIOV7, LPCSMI, SIG_DESC_SET(SCU434, 15)); 1099 1100 #define AB7 176 1101 SIG_EXPR_LIST_DECL_SESG(AB7, LAD0, LPC, SIG_DESC_SET(SCU434, 16), 1102 SIG_DESC_SET(SCU510, 6)); 1103 SIG_EXPR_LIST_DECL_SESG(AB7, ESPID0, ESPI, SIG_DESC_SET(SCU434, 16)); 1104 PIN_DECL_2(AB7, GPIOW0, LAD0, ESPID0); 1105 1106 #define AB8 177 1107 SIG_EXPR_LIST_DECL_SESG(AB8, LAD1, LPC, SIG_DESC_SET(SCU434, 17), 1108 SIG_DESC_SET(SCU510, 6)); 1109 SIG_EXPR_LIST_DECL_SESG(AB8, ESPID1, ESPI, SIG_DESC_SET(SCU434, 17)); 1110 PIN_DECL_2(AB8, GPIOW1, LAD1, ESPID1); 1111 1112 #define AC8 178 1113 SIG_EXPR_LIST_DECL_SESG(AC8, LAD2, LPC, SIG_DESC_SET(SCU434, 18), 1114 SIG_DESC_SET(SCU510, 6)); 1115 SIG_EXPR_LIST_DECL_SESG(AC8, ESPID2, ESPI, SIG_DESC_SET(SCU434, 18)); 1116 PIN_DECL_2(AC8, GPIOW2, LAD2, ESPID2); 1117 1118 #define AC7 179 1119 SIG_EXPR_LIST_DECL_SESG(AC7, LAD3, LPC, SIG_DESC_SET(SCU434, 19), 1120 SIG_DESC_SET(SCU510, 6)); 1121 SIG_EXPR_LIST_DECL_SESG(AC7, ESPID3, ESPI, SIG_DESC_SET(SCU434, 19)); 1122 PIN_DECL_2(AC7, GPIOW3, LAD3, ESPID3); 1123 1124 #define AE7 180 1125 SIG_EXPR_LIST_DECL_SESG(AE7, LCLK, LPC, SIG_DESC_SET(SCU434, 20), 1126 SIG_DESC_SET(SCU510, 6)); 1127 SIG_EXPR_LIST_DECL_SESG(AE7, ESPICK, ESPI, SIG_DESC_SET(SCU434, 20)); 1128 PIN_DECL_2(AE7, GPIOW4, LCLK, ESPICK); 1129 1130 #define AF7 181 1131 SIG_EXPR_LIST_DECL_SESG(AF7, LFRAME, LPC, SIG_DESC_SET(SCU434, 21), 1132 SIG_DESC_SET(SCU510, 6)); 1133 SIG_EXPR_LIST_DECL_SESG(AF7, ESPICS, ESPI, SIG_DESC_SET(SCU434, 21)); 1134 PIN_DECL_2(AF7, GPIOW5, LFRAME, ESPICS); 1135 1136 #define AD7 182 1137 SIG_EXPR_LIST_DECL_SESG(AD7, LSIRQ, LSIRQ, SIG_DESC_SET(SCU434, 22), 1138 SIG_DESC_SET(SCU510, 6)); 1139 SIG_EXPR_LIST_DECL_SESG(AD7, ESPIALT, ESPIALT, SIG_DESC_SET(SCU434, 22)); 1140 PIN_DECL_2(AD7, GPIOW6, LSIRQ, ESPIALT); 1141 FUNC_GROUP_DECL(LSIRQ, AD7); 1142 FUNC_GROUP_DECL(ESPIALT, AD7); 1143 1144 #define AD8 183 1145 SIG_EXPR_LIST_DECL_SESG(AD8, LPCRST, LPC, SIG_DESC_SET(SCU434, 23), 1146 SIG_DESC_SET(SCU510, 6)); 1147 SIG_EXPR_LIST_DECL_SESG(AD8, ESPIRST, ESPI, SIG_DESC_SET(SCU434, 23)); 1148 PIN_DECL_2(AD8, GPIOW7, LPCRST, ESPIRST); 1149 1150 FUNC_GROUP_DECL(LPC, AB7, AB8, AC8, AC7, AE7, AF7, AD8); 1151 FUNC_GROUP_DECL(ESPI, AB7, AB8, AC8, AC7, AE7, AF7, AD8); 1152 1153 #define AE8 184 1154 SIG_EXPR_LIST_DECL_SEMG(AE8, SPI2CS0, SPI2, SPI2, SIG_DESC_SET(SCU434, 24)); 1155 PIN_DECL_1(AE8, GPIOX0, SPI2CS0); 1156 1157 #define AA9 185 1158 SSSF_PIN_DECL(AA9, GPIOX1, SPI2CS1, SIG_DESC_SET(SCU434, 25)); 1159 1160 #define AC9 186 1161 SSSF_PIN_DECL(AC9, GPIOX2, SPI2CS2, SIG_DESC_SET(SCU434, 26)); 1162 1163 #define AF8 187 1164 SIG_EXPR_LIST_DECL_SEMG(AF8, SPI2CK, SPI2, SPI2, SIG_DESC_SET(SCU434, 27)); 1165 PIN_DECL_1(AF8, GPIOX3, SPI2CK); 1166 1167 #define AB9 188 1168 SIG_EXPR_LIST_DECL_SEMG(AB9, SPI2MOSI, SPI2, SPI2, SIG_DESC_SET(SCU434, 28)); 1169 PIN_DECL_1(AB9, GPIOX4, SPI2MOSI); 1170 1171 #define AD9 189 1172 SIG_EXPR_LIST_DECL_SEMG(AD9, SPI2MISO, SPI2, SPI2, SIG_DESC_SET(SCU434, 29)); 1173 PIN_DECL_1(AD9, GPIOX5, SPI2MISO); 1174 1175 GROUP_DECL(SPI2, AE8, AF8, AB9, AD9); 1176 1177 #define AF9 190 1178 SIG_EXPR_LIST_DECL_SEMG(AF9, SPI2DQ2, QSPI2, SPI2, SIG_DESC_SET(SCU434, 30)); 1179 SIG_EXPR_LIST_DECL_SEMG(AF9, TXD12, UART12G1, UART12, SIG_DESC_SET(SCU4D4, 30)); 1180 PIN_DECL_2(AF9, GPIOX6, SPI2DQ2, TXD12); 1181 1182 #define AB10 191 1183 SIG_EXPR_LIST_DECL_SEMG(AB10, SPI2DQ3, QSPI2, SPI2, SIG_DESC_SET(SCU434, 31)); 1184 SIG_EXPR_LIST_DECL_SEMG(AB10, RXD12, UART12G1, UART12, 1185 SIG_DESC_SET(SCU4D4, 31)); 1186 PIN_DECL_2(AB10, GPIOX7, SPI2DQ3, RXD12); 1187 1188 GROUP_DECL(QSPI2, AE8, AF8, AB9, AD9, AF9, AB10); 1189 FUNC_DECL_2(SPI2, SPI2, QSPI2); 1190 1191 GROUP_DECL(UART12G1, AF9, AB10); 1192 FUNC_DECL_2(UART12, UART12G0, UART12G1); 1193 1194 #define AF11 192 1195 SIG_EXPR_LIST_DECL_SESG(AF11, SALT5, SALT5, SIG_DESC_SET(SCU438, 0)); 1196 SIG_EXPR_LIST_DECL_SESG(AF11, WDTRST1, WDTRST1, SIG_DESC_SET(SCU4D8, 0)); 1197 PIN_DECL_2(AF11, GPIOY0, SALT5, WDTRST1); 1198 FUNC_GROUP_DECL(SALT5, AF11); 1199 FUNC_GROUP_DECL(WDTRST1, AF11); 1200 1201 #define AD12 193 1202 SIG_EXPR_LIST_DECL_SESG(AD12, SALT6, SALT6, SIG_DESC_SET(SCU438, 1)); 1203 SIG_EXPR_LIST_DECL_SESG(AD12, WDTRST2, WDTRST2, SIG_DESC_SET(SCU4D8, 1)); 1204 PIN_DECL_2(AD12, GPIOY1, SALT6, WDTRST2); 1205 FUNC_GROUP_DECL(SALT6, AD12); 1206 FUNC_GROUP_DECL(WDTRST2, AD12); 1207 1208 #define AE11 194 1209 SIG_EXPR_LIST_DECL_SESG(AE11, SALT7, SALT7, SIG_DESC_SET(SCU438, 2)); 1210 SIG_EXPR_LIST_DECL_SESG(AE11, WDTRST3, WDTRST3, SIG_DESC_SET(SCU4D8, 2)); 1211 PIN_DECL_2(AE11, GPIOY2, SALT7, WDTRST3); 1212 FUNC_GROUP_DECL(SALT7, AE11); 1213 FUNC_GROUP_DECL(WDTRST3, AE11); 1214 1215 #define AA12 195 1216 SIG_EXPR_LIST_DECL_SESG(AA12, SALT8, SALT8, SIG_DESC_SET(SCU438, 3)); 1217 SIG_EXPR_LIST_DECL_SESG(AA12, WDTRST4, WDTRST4, SIG_DESC_SET(SCU4D8, 3)); 1218 PIN_DECL_2(AA12, GPIOY3, SALT8, WDTRST4); 1219 FUNC_GROUP_DECL(SALT8, AA12); 1220 FUNC_GROUP_DECL(WDTRST4, AA12); 1221 1222 #define AE12 196 1223 SIG_EXPR_LIST_DECL_SEMG(AE12, FWSPIDQ2, FWQSPID, FWSPID, 1224 SIG_DESC_SET(SCU438, 4)); 1225 SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4); 1226 PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIDQ2), 1227 SIG_EXPR_LIST_PTR(AE12, GPIOY4)); 1228 1229 #define AF12 197 1230 SIG_EXPR_LIST_DECL_SEMG(AF12, FWSPIDQ3, FWQSPID, FWSPID, 1231 SIG_DESC_SET(SCU438, 5)); 1232 SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5); 1233 PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIDQ3), 1234 SIG_EXPR_LIST_PTR(AF12, GPIOY5)); 1235 1236 #define AC12 198 1237 SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6)); 1238 1239 #define AB12 199 1240 SSSF_PIN_DECL(AB12, GPIOY7, FWSPIWP, SIG_DESC_SET(SCU438, 7)); 1241 1242 #define AC10 200 1243 SSSF_PIN_DECL(AC10, GPIOZ0, SPI1CS1, SIG_DESC_SET(SCU438, 8)); 1244 1245 #define AD10 201 1246 SSSF_PIN_DECL(AD10, GPIOZ1, SPI1ABR, SIG_DESC_SET(SCU438, 9)); 1247 1248 #define AE10 202 1249 SSSF_PIN_DECL(AE10, GPIOZ2, SPI1WP, SIG_DESC_SET(SCU438, 10)); 1250 1251 #define AB11 203 1252 SIG_EXPR_LIST_DECL_SEMG(AB11, SPI1CK, SPI1, SPI1, SIG_DESC_SET(SCU438, 11)); 1253 PIN_DECL_1(AB11, GPIOZ3, SPI1CK); 1254 1255 #define AC11 204 1256 SIG_EXPR_LIST_DECL_SEMG(AC11, SPI1MOSI, SPI1, SPI1, SIG_DESC_SET(SCU438, 12)); 1257 PIN_DECL_1(AC11, GPIOZ4, SPI1MOSI); 1258 1259 #define AA11 205 1260 SIG_EXPR_LIST_DECL_SEMG(AA11, SPI1MISO, SPI1, SPI1, SIG_DESC_SET(SCU438, 13)); 1261 PIN_DECL_1(AA11, GPIOZ5, SPI1MISO); 1262 1263 GROUP_DECL(SPI1, AB11, AC11, AA11); 1264 1265 #define AD11 206 1266 SIG_EXPR_LIST_DECL_SEMG(AD11, SPI1DQ2, QSPI1, SPI1, SIG_DESC_SET(SCU438, 14)); 1267 SIG_EXPR_LIST_DECL_SEMG(AD11, TXD13, UART13G1, UART13, 1268 SIG_DESC_CLEAR(SCU4B8, 2), SIG_DESC_SET(SCU4D8, 14)); 1269 PIN_DECL_2(AD11, GPIOZ6, SPI1DQ2, TXD13); 1270 1271 #define AF10 207 1272 SIG_EXPR_LIST_DECL_SEMG(AF10, SPI1DQ3, QSPI1, SPI1, SIG_DESC_SET(SCU438, 15)); 1273 SIG_EXPR_LIST_DECL_SEMG(AF10, RXD13, UART13G1, UART13, 1274 SIG_DESC_CLEAR(SCU4B8, 3), SIG_DESC_SET(SCU4D8, 15)); 1275 PIN_DECL_2(AF10, GPIOZ7, SPI1DQ3, RXD13); 1276 1277 GROUP_DECL(QSPI1, AB11, AC11, AA11, AD11, AF10); 1278 FUNC_DECL_2(SPI1, SPI1, QSPI1); 1279 1280 GROUP_DECL(UART13G1, AD11, AF10); 1281 FUNC_DECL_2(UART13, UART13G0, UART13G1); 1282 1283 #define C6 208 1284 SIG_EXPR_LIST_DECL_SESG(C6, RGMII1TXCK, RGMII1, SIG_DESC_SET(SCU400, 0), 1285 SIG_DESC_SET(SCU500, 6)); 1286 SIG_EXPR_LIST_DECL_SESG(C6, RMII1RCLKO, RMII1, SIG_DESC_SET(SCU400, 0), 1287 SIG_DESC_CLEAR(SCU500, 6)); 1288 PIN_DECL_2(C6, GPIO18A0, RGMII1TXCK, RMII1RCLKO); 1289 1290 #define D6 209 1291 SIG_EXPR_LIST_DECL_SESG(D6, RGMII1TXCTL, RGMII1, SIG_DESC_SET(SCU400, 1), 1292 SIG_DESC_SET(SCU500, 6)); 1293 SIG_EXPR_LIST_DECL_SESG(D6, RMII1TXEN, RMII1, SIG_DESC_SET(SCU400, 1), 1294 SIG_DESC_CLEAR(SCU500, 6)); 1295 PIN_DECL_2(D6, GPIO18A1, RGMII1TXCTL, RMII1TXEN); 1296 1297 #define D5 210 1298 SIG_EXPR_LIST_DECL_SESG(D5, RGMII1TXD0, RGMII1, SIG_DESC_SET(SCU400, 2), 1299 SIG_DESC_SET(SCU500, 6)); 1300 SIG_EXPR_LIST_DECL_SESG(D5, RMII1TXD0, RMII1, SIG_DESC_SET(SCU400, 2), 1301 SIG_DESC_CLEAR(SCU500, 6)); 1302 PIN_DECL_2(D5, GPIO18A2, RGMII1TXD0, RMII1TXD0); 1303 1304 #define A3 211 1305 SIG_EXPR_LIST_DECL_SESG(A3, RGMII1TXD1, RGMII1, SIG_DESC_SET(SCU400, 3), 1306 SIG_DESC_SET(SCU500, 6)); 1307 SIG_EXPR_LIST_DECL_SESG(A3, RMII1TXD1, RMII1, SIG_DESC_SET(SCU400, 3), 1308 SIG_DESC_CLEAR(SCU500, 6)); 1309 PIN_DECL_2(A3, GPIO18A3, RGMII1TXD1, RMII1TXD1); 1310 1311 #define C5 212 1312 SIG_EXPR_LIST_DECL_SESG(C5, RGMII1TXD2, RGMII1, SIG_DESC_SET(SCU400, 4), 1313 SIG_DESC_SET(SCU500, 6)); 1314 PIN_DECL_1(C5, GPIO18A4, RGMII1TXD2); 1315 1316 #define E6 213 1317 SIG_EXPR_LIST_DECL_SESG(E6, RGMII1TXD3, RGMII1, SIG_DESC_SET(SCU400, 5), 1318 SIG_DESC_SET(SCU500, 6)); 1319 PIN_DECL_1(E6, GPIO18A5, RGMII1TXD3); 1320 1321 #define B3 214 1322 SIG_EXPR_LIST_DECL_SESG(B3, RGMII1RXCK, RGMII1, SIG_DESC_SET(SCU400, 6), 1323 SIG_DESC_SET(SCU500, 6)); 1324 SIG_EXPR_LIST_DECL_SESG(B3, RMII1RCLKI, RMII1, SIG_DESC_SET(SCU400, 6), 1325 SIG_DESC_CLEAR(SCU500, 6)); 1326 PIN_DECL_2(B3, GPIO18A6, RGMII1RXCK, RMII1RCLKI); 1327 1328 #define A2 215 1329 SIG_EXPR_LIST_DECL_SESG(A2, RGMII1RXCTL, RGMII1, SIG_DESC_SET(SCU400, 7), 1330 SIG_DESC_SET(SCU500, 6)); 1331 PIN_DECL_1(A2, GPIO18A7, RGMII1RXCTL); 1332 1333 #define B2 216 1334 SIG_EXPR_LIST_DECL_SESG(B2, RGMII1RXD0, RGMII1, SIG_DESC_SET(SCU400, 8), 1335 SIG_DESC_SET(SCU500, 6)); 1336 SIG_EXPR_LIST_DECL_SESG(B2, RMII1RXD0, RMII1, SIG_DESC_SET(SCU400, 8), 1337 SIG_DESC_CLEAR(SCU500, 6)); 1338 PIN_DECL_2(B2, GPIO18B0, RGMII1RXD0, RMII1RXD0); 1339 1340 #define B1 217 1341 SIG_EXPR_LIST_DECL_SESG(B1, RGMII1RXD1, RGMII1, SIG_DESC_SET(SCU400, 9), 1342 SIG_DESC_SET(SCU500, 6)); 1343 SIG_EXPR_LIST_DECL_SESG(B1, RMII1RXD1, RMII1, SIG_DESC_SET(SCU400, 9), 1344 SIG_DESC_CLEAR(SCU500, 6)); 1345 PIN_DECL_2(B1, GPIO18B1, RGMII1RXD1, RMII1RXD1); 1346 1347 #define C4 218 1348 SIG_EXPR_LIST_DECL_SESG(C4, RGMII1RXD2, RGMII1, SIG_DESC_SET(SCU400, 10), 1349 SIG_DESC_SET(SCU500, 6)); 1350 SIG_EXPR_LIST_DECL_SESG(C4, RMII1CRSDV, RMII1, SIG_DESC_SET(SCU400, 10), 1351 SIG_DESC_CLEAR(SCU500, 6)); 1352 PIN_DECL_2(C4, GPIO18B2, RGMII1RXD2, RMII1CRSDV); 1353 1354 #define E5 219 1355 SIG_EXPR_LIST_DECL_SESG(E5, RGMII1RXD3, RGMII1, SIG_DESC_SET(SCU400, 11), 1356 SIG_DESC_SET(SCU500, 6)); 1357 SIG_EXPR_LIST_DECL_SESG(E5, RMII1RXER, RMII1, SIG_DESC_SET(SCU400, 11), 1358 SIG_DESC_CLEAR(SCU500, 6)); 1359 PIN_DECL_2(E5, GPIO18B3, RGMII1RXD3, RMII1RXER); 1360 1361 FUNC_GROUP_DECL(RGMII1, C6, D6, D5, A3, C5, E6, B3, A2, B2, B1, C4, E5); 1362 FUNC_GROUP_DECL(RMII1, C6, D6, D5, A3, B3, B2, B1, C4, E5); 1363 1364 #define D4 220 1365 SIG_EXPR_LIST_DECL_SESG(D4, RGMII2TXCK, RGMII2, SIG_DESC_SET(SCU400, 12), 1366 SIG_DESC_SET(SCU500, 7)); 1367 SIG_EXPR_LIST_DECL_SESG(D4, RMII2RCLKO, RMII2, SIG_DESC_SET(SCU400, 12), 1368 SIG_DESC_CLEAR(SCU500, 7)); 1369 PIN_DECL_2(D4, GPIO18B4, RGMII2TXCK, RMII2RCLKO); 1370 1371 #define C2 221 1372 SIG_EXPR_LIST_DECL_SESG(C2, RGMII2TXCTL, RGMII2, SIG_DESC_SET(SCU400, 13), 1373 SIG_DESC_SET(SCU500, 7)); 1374 SIG_EXPR_LIST_DECL_SESG(C2, RMII2TXEN, RMII2, SIG_DESC_SET(SCU400, 13), 1375 SIG_DESC_CLEAR(SCU500, 7)); 1376 PIN_DECL_2(C2, GPIO18B5, RGMII2TXCTL, RMII2TXEN); 1377 1378 #define C1 222 1379 SIG_EXPR_LIST_DECL_SESG(C1, RGMII2TXD0, RGMII2, SIG_DESC_SET(SCU400, 14), 1380 SIG_DESC_SET(SCU500, 7)); 1381 SIG_EXPR_LIST_DECL_SESG(C1, RMII2TXD0, RMII2, SIG_DESC_SET(SCU400, 14), 1382 SIG_DESC_CLEAR(SCU500, 7)); 1383 PIN_DECL_2(C1, GPIO18B6, RGMII2TXD0, RMII2TXD0); 1384 1385 #define D3 223 1386 SIG_EXPR_LIST_DECL_SESG(D3, RGMII2TXD1, RGMII2, SIG_DESC_SET(SCU400, 15), 1387 SIG_DESC_SET(SCU500, 7)); 1388 SIG_EXPR_LIST_DECL_SESG(D3, RMII2TXD1, RMII2, SIG_DESC_SET(SCU400, 15), 1389 SIG_DESC_CLEAR(SCU500, 7)); 1390 PIN_DECL_2(D3, GPIO18B7, RGMII2TXD1, RMII2TXD1); 1391 1392 #define E4 224 1393 SIG_EXPR_LIST_DECL_SESG(E4, RGMII2TXD2, RGMII2, SIG_DESC_SET(SCU400, 16), 1394 SIG_DESC_SET(SCU500, 7)); 1395 PIN_DECL_1(E4, GPIO18C0, RGMII2TXD2); 1396 1397 #define F5 225 1398 SIG_EXPR_LIST_DECL_SESG(F5, RGMII2TXD3, RGMII2, SIG_DESC_SET(SCU400, 17), 1399 SIG_DESC_SET(SCU500, 7)); 1400 PIN_DECL_1(F5, GPIO18C1, RGMII2TXD3); 1401 1402 #define D2 226 1403 SIG_EXPR_LIST_DECL_SESG(D2, RGMII2RXCK, RGMII2, SIG_DESC_SET(SCU400, 18), 1404 SIG_DESC_SET(SCU500, 7)); 1405 SIG_EXPR_LIST_DECL_SESG(D2, RMII2RCLKI, RMII2, SIG_DESC_SET(SCU400, 18), 1406 SIG_DESC_CLEAR(SCU500, 7)); 1407 PIN_DECL_2(D2, GPIO18C2, RGMII2RXCK, RMII2RCLKI); 1408 1409 #define E3 227 1410 SIG_EXPR_LIST_DECL_SESG(E3, RGMII2RXCTL, RGMII2, SIG_DESC_SET(SCU400, 19), 1411 SIG_DESC_SET(SCU500, 7)); 1412 PIN_DECL_1(E3, GPIO18C3, RGMII2RXCTL); 1413 1414 #define D1 228 1415 SIG_EXPR_LIST_DECL_SESG(D1, RGMII2RXD0, RGMII2, SIG_DESC_SET(SCU400, 20), 1416 SIG_DESC_SET(SCU500, 7)); 1417 SIG_EXPR_LIST_DECL_SESG(D1, RMII2RXD0, RMII2, SIG_DESC_SET(SCU400, 20), 1418 SIG_DESC_CLEAR(SCU500, 7)); 1419 PIN_DECL_2(D1, GPIO18C4, RGMII2RXD0, RMII2RXD0); 1420 1421 #define F4 229 1422 SIG_EXPR_LIST_DECL_SESG(F4, RGMII2RXD1, RGMII2, SIG_DESC_SET(SCU400, 21), 1423 SIG_DESC_SET(SCU500, 7)); 1424 SIG_EXPR_LIST_DECL_SESG(F4, RMII2RXD1, RMII2, SIG_DESC_SET(SCU400, 21), 1425 SIG_DESC_CLEAR(SCU500, 7)); 1426 PIN_DECL_2(F4, GPIO18C5, RGMII2RXD1, RMII2RXD1); 1427 1428 #define E2 230 1429 SIG_EXPR_LIST_DECL_SESG(E2, RGMII2RXD2, RGMII2, SIG_DESC_SET(SCU400, 22), 1430 SIG_DESC_SET(SCU500, 7)); 1431 SIG_EXPR_LIST_DECL_SESG(E2, RMII2CRSDV, RMII2, SIG_DESC_SET(SCU400, 22), 1432 SIG_DESC_CLEAR(SCU500, 7)); 1433 PIN_DECL_2(E2, GPIO18C6, RGMII2RXD2, RMII2CRSDV); 1434 1435 #define E1 231 1436 SIG_EXPR_LIST_DECL_SESG(E1, RGMII2RXD3, RGMII2, SIG_DESC_SET(SCU400, 23), 1437 SIG_DESC_SET(SCU500, 7)); 1438 SIG_EXPR_LIST_DECL_SESG(E1, RMII2RXER, RMII2, SIG_DESC_SET(SCU400, 23), 1439 SIG_DESC_CLEAR(SCU500, 7)); 1440 PIN_DECL_2(E1, GPIO18C7, RGMII2RXD3, RMII2RXER); 1441 1442 FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1); 1443 FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1); 1444 1445 #define AB4 232 1446 SIG_EXPR_LIST_DECL_SEMG(AB4, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 24)); 1447 PIN_DECL_1(AB4, GPIO18D0, EMMCCLK); 1448 1449 #define AA4 233 1450 SIG_EXPR_LIST_DECL_SEMG(AA4, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 25)); 1451 PIN_DECL_1(AA4, GPIO18D1, EMMCCMD); 1452 1453 #define AC4 234 1454 SIG_EXPR_LIST_DECL_SEMG(AC4, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 26)); 1455 PIN_DECL_1(AC4, GPIO18D2, EMMCDAT0); 1456 1457 #define AA5 235 1458 SIG_EXPR_LIST_DECL_SEMG(AA5, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 27)); 1459 PIN_DECL_1(AA5, GPIO18D3, EMMCDAT1); 1460 1461 #define Y5 236 1462 SIG_EXPR_LIST_DECL_SEMG(Y5, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 28)); 1463 PIN_DECL_1(Y5, GPIO18D4, EMMCDAT2); 1464 1465 #define AB5 237 1466 SIG_EXPR_LIST_DECL_SEMG(AB5, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 29)); 1467 PIN_DECL_1(AB5, GPIO18D5, EMMCDAT3); 1468 1469 #define AB6 238 1470 SIG_EXPR_LIST_DECL_SEMG(AB6, EMMCCD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 30)); 1471 PIN_DECL_1(AB6, GPIO18D6, EMMCCD); 1472 1473 #define AC5 239 1474 SIG_EXPR_LIST_DECL_SEMG(AC5, EMMCWP, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 31)); 1475 PIN_DECL_1(AC5, GPIO18D7, EMMCWP); 1476 1477 GROUP_DECL(EMMCG1, AB4, AA4, AC4, AB6, AC5); 1478 GROUP_DECL(EMMCG4, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5); 1479 1480 #define Y1 240 1481 SIG_EXPR_LIST_DECL_SEMG(Y1, FWSPIDCS, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); 1482 SIG_EXPR_LIST_DECL_SESG(Y1, VBCS, VB, SIG_DESC_SET(SCU500, 5)); 1483 SIG_EXPR_LIST_DECL_SEMG(Y1, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 0)); 1484 PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, EMMCDAT4); 1485 1486 #define Y2 241 1487 SIG_EXPR_LIST_DECL_SEMG(Y2, FWSPIDCK, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); 1488 SIG_EXPR_LIST_DECL_SESG(Y2, VBCK, VB, SIG_DESC_SET(SCU500, 5)); 1489 SIG_EXPR_LIST_DECL_SEMG(Y2, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 1)); 1490 PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, EMMCDAT5); 1491 1492 #define Y3 242 1493 SIG_EXPR_LIST_DECL_SEMG(Y3, FWSPIDMOSI, FWSPID, FWSPID, 1494 SIG_DESC_SET(SCU500, 3)); 1495 SIG_EXPR_LIST_DECL_SESG(Y3, VBMOSI, VB, SIG_DESC_SET(SCU500, 5)); 1496 SIG_EXPR_LIST_DECL_SEMG(Y3, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 2)); 1497 PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, EMMCDAT6); 1498 1499 #define Y4 243 1500 SIG_EXPR_LIST_DECL_SEMG(Y4, FWSPIDMISO, FWSPID, FWSPID, 1501 SIG_DESC_SET(SCU500, 3)); 1502 SIG_EXPR_LIST_DECL_SESG(Y4, VBMISO, VB, SIG_DESC_SET(SCU500, 5)); 1503 SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 3)); 1504 PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7); 1505 1506 GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4); 1507 GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12); 1508 GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, Y4); 1509 FUNC_DECL_2(FWSPID, FWSPID, FWQSPID); 1510 FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4); 1511 FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8); 1512 /* 1513 * FIXME: Confirm bits and priorities are the right way around for the 1514 * following 4 pins 1515 */ 1516 #define AF25 244 1517 SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20)); 1518 SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_SET(SCU4D8, 20)); 1519 PIN_DECL_(AF25, SIG_EXPR_LIST_PTR(AF25, I3C3SCL), 1520 SIG_EXPR_LIST_PTR(AF25, FSI1CLK)); 1521 1522 #define AE26 245 1523 SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21)); 1524 SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_SET(SCU4D8, 21)); 1525 PIN_DECL_(AE26, SIG_EXPR_LIST_PTR(AE26, I3C3SDA), 1526 SIG_EXPR_LIST_PTR(AE26, FSI1DATA)); 1527 1528 GROUP_DECL(I3C3, AF25, AE26); 1529 FUNC_DECL_2(I3C3, HVI3C3, I3C3); 1530 FUNC_GROUP_DECL(FSI1, AF25, AE26); 1531 1532 #define AE25 246 1533 SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22)); 1534 SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_SET(SCU4D8, 22)); 1535 PIN_DECL_(AE25, SIG_EXPR_LIST_PTR(AE25, I3C4SCL), 1536 SIG_EXPR_LIST_PTR(AE25, FSI2CLK)); 1537 1538 #define AF24 247 1539 SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23)); 1540 SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_SET(SCU4D8, 23)); 1541 PIN_DECL_(AF24, SIG_EXPR_LIST_PTR(AF24, I3C4SDA), 1542 SIG_EXPR_LIST_PTR(AF24, FSI2DATA)); 1543 1544 GROUP_DECL(I3C4, AE25, AF24); 1545 FUNC_DECL_2(I3C4, HVI3C4, I3C4); 1546 FUNC_GROUP_DECL(FSI2, AE25, AF24); 1547 1548 #define AF23 248 1549 SIG_EXPR_LIST_DECL_SESG(AF23, I3C1SCL, I3C1, SIG_DESC_SET(SCU438, 16)); 1550 PIN_DECL_(AF23, SIG_EXPR_LIST_PTR(AF23, I3C1SCL)); 1551 1552 #define AE24 249 1553 SIG_EXPR_LIST_DECL_SESG(AE24, I3C1SDA, I3C1, SIG_DESC_SET(SCU438, 17)); 1554 PIN_DECL_(AE24, SIG_EXPR_LIST_PTR(AE24, I3C1SDA)); 1555 1556 FUNC_GROUP_DECL(I3C1, AF23, AE24); 1557 1558 #define AF22 250 1559 SIG_EXPR_LIST_DECL_SESG(AF22, I3C2SCL, I3C2, SIG_DESC_SET(SCU438, 18)); 1560 PIN_DECL_(AF22, SIG_EXPR_LIST_PTR(AF22, I3C2SCL)); 1561 1562 #define AE22 251 1563 SIG_EXPR_LIST_DECL_SESG(AE22, I3C2SDA, I3C2, SIG_DESC_SET(SCU438, 19)); 1564 PIN_DECL_(AE22, SIG_EXPR_LIST_PTR(AE22, I3C2SDA)); 1565 1566 FUNC_GROUP_DECL(I3C2, AF22, AE22); 1567 1568 #define USB2ADP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 0, 0 } 1569 #define USB2AD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 1, 0 } 1570 #define USB2AH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 2, 0 } 1571 #define USB2AHP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 3, 0 } 1572 #define USB11BHID_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 0, 0 } 1573 #define USB2BD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 1, 0 } 1574 #define USB2BH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 2, 0 } 1575 1576 #define A4 252 1577 SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADPDP, USBA, USB2ADP, USB2ADP_DESC, 1578 SIG_DESC_SET(SCUC20, 16)); 1579 SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADDP, USBA, USB2AD, USB2AD_DESC); 1580 SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHDP, USBA, USB2AH, USB2AH_DESC); 1581 SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHPDP, USBA, USB2AHP, USB2AHP_DESC); 1582 PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, USB2ADPDP), SIG_EXPR_LIST_PTR(A4, USB2ADDP), 1583 SIG_EXPR_LIST_PTR(A4, USB2AHDP)); 1584 1585 #define B4 253 1586 SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADPDN, USBA, USB2ADP, USB2ADP_DESC); 1587 SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADDN, USBA, USB2AD, USB2AD_DESC); 1588 SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHDN, USBA, USB2AH, USB2AH_DESC); 1589 SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHPDN, USBA, USB2AHP, USB2AHP_DESC); 1590 PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, USB2ADPDN), SIG_EXPR_LIST_PTR(B4, USB2ADDN), 1591 SIG_EXPR_LIST_PTR(B4, USB2AHDN)); 1592 1593 GROUP_DECL(USBA, A4, B4); 1594 1595 FUNC_DECL_1(USB2ADP, USBA); 1596 FUNC_DECL_1(USB2AD, USBA); 1597 FUNC_DECL_1(USB2AH, USBA); 1598 FUNC_DECL_1(USB2AHP, USBA); 1599 1600 #define A6 254 1601 SIG_EXPR_LIST_DECL_SEMG(A6, USB11BDP, USBB, USB11BHID, USB11BHID_DESC); 1602 SIG_EXPR_LIST_DECL_SEMG(A6, USB2BDDP, USBB, USB2BD, USB2BD_DESC); 1603 SIG_EXPR_LIST_DECL_SEMG(A6, USB2BHDP, USBB, USB2BH, USB2BH_DESC); 1604 PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDP), SIG_EXPR_LIST_PTR(A6, USB2BDDP), 1605 SIG_EXPR_LIST_PTR(A6, USB2BHDP)); 1606 1607 #define B6 255 1608 SIG_EXPR_LIST_DECL_SEMG(B6, USB11BDN, USBB, USB11BHID, USB11BHID_DESC); 1609 SIG_EXPR_LIST_DECL_SEMG(B6, USB2BDDN, USBB, USB2BD, USB2BD_DESC); 1610 SIG_EXPR_LIST_DECL_SEMG(B6, USB2BHDN, USBB, USB2BH, USB2BH_DESC); 1611 PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDN), SIG_EXPR_LIST_PTR(B6, USB2BDDN), 1612 SIG_EXPR_LIST_PTR(B6, USB2BHDN)); 1613 1614 GROUP_DECL(USBB, A6, B6); 1615 1616 FUNC_DECL_1(USB11BHID, USBB); 1617 FUNC_DECL_1(USB2BD, USBB); 1618 FUNC_DECL_1(USB2BH, USBB); 1619 1620 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ 1621 1622 static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { 1623 ASPEED_PINCTRL_PIN(A11), 1624 ASPEED_PINCTRL_PIN(A12), 1625 ASPEED_PINCTRL_PIN(A13), 1626 ASPEED_PINCTRL_PIN(A14), 1627 ASPEED_PINCTRL_PIN(A15), 1628 ASPEED_PINCTRL_PIN(A16), 1629 ASPEED_PINCTRL_PIN(A17), 1630 ASPEED_PINCTRL_PIN(A18), 1631 ASPEED_PINCTRL_PIN(A19), 1632 ASPEED_PINCTRL_PIN(A2), 1633 ASPEED_PINCTRL_PIN(A20), 1634 ASPEED_PINCTRL_PIN(A21), 1635 ASPEED_PINCTRL_PIN(A22), 1636 ASPEED_PINCTRL_PIN(A23), 1637 ASPEED_PINCTRL_PIN(A24), 1638 ASPEED_PINCTRL_PIN(A25), 1639 ASPEED_PINCTRL_PIN(A3), 1640 ASPEED_PINCTRL_PIN(A4), 1641 ASPEED_PINCTRL_PIN(A6), 1642 ASPEED_PINCTRL_PIN(AA11), 1643 ASPEED_PINCTRL_PIN(AA12), 1644 ASPEED_PINCTRL_PIN(AA16), 1645 ASPEED_PINCTRL_PIN(AA17), 1646 ASPEED_PINCTRL_PIN(AA23), 1647 ASPEED_PINCTRL_PIN(AA24), 1648 ASPEED_PINCTRL_PIN(AA25), 1649 ASPEED_PINCTRL_PIN(AA26), 1650 ASPEED_PINCTRL_PIN(AA4), 1651 ASPEED_PINCTRL_PIN(AA5), 1652 ASPEED_PINCTRL_PIN(AA9), 1653 ASPEED_PINCTRL_PIN(AB10), 1654 ASPEED_PINCTRL_PIN(AB11), 1655 ASPEED_PINCTRL_PIN(AB12), 1656 ASPEED_PINCTRL_PIN(AB15), 1657 ASPEED_PINCTRL_PIN(AB16), 1658 ASPEED_PINCTRL_PIN(AB17), 1659 ASPEED_PINCTRL_PIN(AB18), 1660 ASPEED_PINCTRL_PIN(AB19), 1661 ASPEED_PINCTRL_PIN(AB22), 1662 ASPEED_PINCTRL_PIN(AB23), 1663 ASPEED_PINCTRL_PIN(AB24), 1664 ASPEED_PINCTRL_PIN(AB25), 1665 ASPEED_PINCTRL_PIN(AB26), 1666 ASPEED_PINCTRL_PIN(AB4), 1667 ASPEED_PINCTRL_PIN(AB5), 1668 ASPEED_PINCTRL_PIN(AB6), 1669 ASPEED_PINCTRL_PIN(AB7), 1670 ASPEED_PINCTRL_PIN(AB8), 1671 ASPEED_PINCTRL_PIN(AB9), 1672 ASPEED_PINCTRL_PIN(AC10), 1673 ASPEED_PINCTRL_PIN(AC11), 1674 ASPEED_PINCTRL_PIN(AC12), 1675 ASPEED_PINCTRL_PIN(AC15), 1676 ASPEED_PINCTRL_PIN(AC16), 1677 ASPEED_PINCTRL_PIN(AC17), 1678 ASPEED_PINCTRL_PIN(AC18), 1679 ASPEED_PINCTRL_PIN(AC19), 1680 ASPEED_PINCTRL_PIN(AC22), 1681 ASPEED_PINCTRL_PIN(AC23), 1682 ASPEED_PINCTRL_PIN(AC24), 1683 ASPEED_PINCTRL_PIN(AC26), 1684 ASPEED_PINCTRL_PIN(AC4), 1685 ASPEED_PINCTRL_PIN(AC5), 1686 ASPEED_PINCTRL_PIN(AC7), 1687 ASPEED_PINCTRL_PIN(AC8), 1688 ASPEED_PINCTRL_PIN(AC9), 1689 ASPEED_PINCTRL_PIN(AD10), 1690 ASPEED_PINCTRL_PIN(AD11), 1691 ASPEED_PINCTRL_PIN(AD12), 1692 ASPEED_PINCTRL_PIN(AD14), 1693 ASPEED_PINCTRL_PIN(AD15), 1694 ASPEED_PINCTRL_PIN(AD16), 1695 ASPEED_PINCTRL_PIN(AD19), 1696 ASPEED_PINCTRL_PIN(AD20), 1697 ASPEED_PINCTRL_PIN(AD22), 1698 ASPEED_PINCTRL_PIN(AD23), 1699 ASPEED_PINCTRL_PIN(AD24), 1700 ASPEED_PINCTRL_PIN(AD25), 1701 ASPEED_PINCTRL_PIN(AD26), 1702 ASPEED_PINCTRL_PIN(AD7), 1703 ASPEED_PINCTRL_PIN(AD8), 1704 ASPEED_PINCTRL_PIN(AD9), 1705 ASPEED_PINCTRL_PIN(AE10), 1706 ASPEED_PINCTRL_PIN(AE11), 1707 ASPEED_PINCTRL_PIN(AE12), 1708 ASPEED_PINCTRL_PIN(AE14), 1709 ASPEED_PINCTRL_PIN(AE15), 1710 ASPEED_PINCTRL_PIN(AE16), 1711 ASPEED_PINCTRL_PIN(AE18), 1712 ASPEED_PINCTRL_PIN(AE19), 1713 ASPEED_PINCTRL_PIN(AE22), 1714 ASPEED_PINCTRL_PIN(AE24), 1715 ASPEED_PINCTRL_PIN(AE25), 1716 ASPEED_PINCTRL_PIN(AE26), 1717 ASPEED_PINCTRL_PIN(AE7), 1718 ASPEED_PINCTRL_PIN(AE8), 1719 ASPEED_PINCTRL_PIN(AF10), 1720 ASPEED_PINCTRL_PIN(AF11), 1721 ASPEED_PINCTRL_PIN(AF12), 1722 ASPEED_PINCTRL_PIN(AF14), 1723 ASPEED_PINCTRL_PIN(AF15), 1724 ASPEED_PINCTRL_PIN(AF22), 1725 ASPEED_PINCTRL_PIN(AF23), 1726 ASPEED_PINCTRL_PIN(AF24), 1727 ASPEED_PINCTRL_PIN(AF25), 1728 ASPEED_PINCTRL_PIN(AF7), 1729 ASPEED_PINCTRL_PIN(AF8), 1730 ASPEED_PINCTRL_PIN(AF9), 1731 ASPEED_PINCTRL_PIN(B1), 1732 ASPEED_PINCTRL_PIN(B12), 1733 ASPEED_PINCTRL_PIN(B13), 1734 ASPEED_PINCTRL_PIN(B14), 1735 ASPEED_PINCTRL_PIN(B16), 1736 ASPEED_PINCTRL_PIN(B17), 1737 ASPEED_PINCTRL_PIN(B18), 1738 ASPEED_PINCTRL_PIN(B2), 1739 ASPEED_PINCTRL_PIN(B20), 1740 ASPEED_PINCTRL_PIN(B21), 1741 ASPEED_PINCTRL_PIN(B22), 1742 ASPEED_PINCTRL_PIN(B24), 1743 ASPEED_PINCTRL_PIN(B25), 1744 ASPEED_PINCTRL_PIN(B26), 1745 ASPEED_PINCTRL_PIN(B3), 1746 ASPEED_PINCTRL_PIN(B4), 1747 ASPEED_PINCTRL_PIN(B6), 1748 ASPEED_PINCTRL_PIN(C1), 1749 ASPEED_PINCTRL_PIN(C11), 1750 ASPEED_PINCTRL_PIN(C12), 1751 ASPEED_PINCTRL_PIN(C13), 1752 ASPEED_PINCTRL_PIN(C14), 1753 ASPEED_PINCTRL_PIN(C15), 1754 ASPEED_PINCTRL_PIN(C16), 1755 ASPEED_PINCTRL_PIN(C17), 1756 ASPEED_PINCTRL_PIN(C18), 1757 ASPEED_PINCTRL_PIN(C19), 1758 ASPEED_PINCTRL_PIN(C2), 1759 ASPEED_PINCTRL_PIN(C20), 1760 ASPEED_PINCTRL_PIN(C21), 1761 ASPEED_PINCTRL_PIN(C22), 1762 ASPEED_PINCTRL_PIN(C23), 1763 ASPEED_PINCTRL_PIN(C24), 1764 ASPEED_PINCTRL_PIN(C25), 1765 ASPEED_PINCTRL_PIN(C26), 1766 ASPEED_PINCTRL_PIN(C4), 1767 ASPEED_PINCTRL_PIN(C5), 1768 ASPEED_PINCTRL_PIN(C6), 1769 ASPEED_PINCTRL_PIN(D1), 1770 ASPEED_PINCTRL_PIN(D11), 1771 ASPEED_PINCTRL_PIN(D12), 1772 ASPEED_PINCTRL_PIN(D13), 1773 ASPEED_PINCTRL_PIN(D14), 1774 ASPEED_PINCTRL_PIN(D15), 1775 ASPEED_PINCTRL_PIN(D16), 1776 ASPEED_PINCTRL_PIN(D17), 1777 ASPEED_PINCTRL_PIN(D18), 1778 ASPEED_PINCTRL_PIN(D19), 1779 ASPEED_PINCTRL_PIN(D2), 1780 ASPEED_PINCTRL_PIN(D20), 1781 ASPEED_PINCTRL_PIN(D21), 1782 ASPEED_PINCTRL_PIN(D22), 1783 ASPEED_PINCTRL_PIN(D23), 1784 ASPEED_PINCTRL_PIN(D24), 1785 ASPEED_PINCTRL_PIN(D26), 1786 ASPEED_PINCTRL_PIN(D3), 1787 ASPEED_PINCTRL_PIN(D4), 1788 ASPEED_PINCTRL_PIN(D5), 1789 ASPEED_PINCTRL_PIN(D6), 1790 ASPEED_PINCTRL_PIN(E1), 1791 ASPEED_PINCTRL_PIN(E11), 1792 ASPEED_PINCTRL_PIN(E12), 1793 ASPEED_PINCTRL_PIN(E13), 1794 ASPEED_PINCTRL_PIN(E14), 1795 ASPEED_PINCTRL_PIN(E15), 1796 ASPEED_PINCTRL_PIN(E16), 1797 ASPEED_PINCTRL_PIN(E17), 1798 ASPEED_PINCTRL_PIN(E18), 1799 ASPEED_PINCTRL_PIN(E19), 1800 ASPEED_PINCTRL_PIN(E2), 1801 ASPEED_PINCTRL_PIN(E20), 1802 ASPEED_PINCTRL_PIN(E21), 1803 ASPEED_PINCTRL_PIN(E22), 1804 ASPEED_PINCTRL_PIN(E23), 1805 ASPEED_PINCTRL_PIN(E24), 1806 ASPEED_PINCTRL_PIN(E25), 1807 ASPEED_PINCTRL_PIN(E26), 1808 ASPEED_PINCTRL_PIN(E3), 1809 ASPEED_PINCTRL_PIN(E4), 1810 ASPEED_PINCTRL_PIN(E5), 1811 ASPEED_PINCTRL_PIN(E6), 1812 ASPEED_PINCTRL_PIN(F13), 1813 ASPEED_PINCTRL_PIN(F15), 1814 ASPEED_PINCTRL_PIN(F22), 1815 ASPEED_PINCTRL_PIN(F23), 1816 ASPEED_PINCTRL_PIN(F24), 1817 ASPEED_PINCTRL_PIN(F25), 1818 ASPEED_PINCTRL_PIN(F26), 1819 ASPEED_PINCTRL_PIN(F4), 1820 ASPEED_PINCTRL_PIN(F5), 1821 ASPEED_PINCTRL_PIN(G22), 1822 ASPEED_PINCTRL_PIN(G23), 1823 ASPEED_PINCTRL_PIN(G24), 1824 ASPEED_PINCTRL_PIN(G26), 1825 ASPEED_PINCTRL_PIN(H22), 1826 ASPEED_PINCTRL_PIN(H23), 1827 ASPEED_PINCTRL_PIN(H24), 1828 ASPEED_PINCTRL_PIN(H25), 1829 ASPEED_PINCTRL_PIN(H26), 1830 ASPEED_PINCTRL_PIN(J22), 1831 ASPEED_PINCTRL_PIN(J23), 1832 ASPEED_PINCTRL_PIN(J24), 1833 ASPEED_PINCTRL_PIN(J25), 1834 ASPEED_PINCTRL_PIN(J26), 1835 ASPEED_PINCTRL_PIN(K23), 1836 ASPEED_PINCTRL_PIN(K24), 1837 ASPEED_PINCTRL_PIN(K25), 1838 ASPEED_PINCTRL_PIN(K26), 1839 ASPEED_PINCTRL_PIN(L23), 1840 ASPEED_PINCTRL_PIN(L24), 1841 ASPEED_PINCTRL_PIN(L26), 1842 ASPEED_PINCTRL_PIN(M23), 1843 ASPEED_PINCTRL_PIN(M24), 1844 ASPEED_PINCTRL_PIN(M25), 1845 ASPEED_PINCTRL_PIN(M26), 1846 ASPEED_PINCTRL_PIN(N23), 1847 ASPEED_PINCTRL_PIN(N24), 1848 ASPEED_PINCTRL_PIN(N25), 1849 ASPEED_PINCTRL_PIN(N26), 1850 ASPEED_PINCTRL_PIN(P23), 1851 ASPEED_PINCTRL_PIN(P24), 1852 ASPEED_PINCTRL_PIN(P25), 1853 ASPEED_PINCTRL_PIN(P26), 1854 ASPEED_PINCTRL_PIN(R23), 1855 ASPEED_PINCTRL_PIN(R24), 1856 ASPEED_PINCTRL_PIN(R26), 1857 ASPEED_PINCTRL_PIN(T23), 1858 ASPEED_PINCTRL_PIN(T24), 1859 ASPEED_PINCTRL_PIN(T25), 1860 ASPEED_PINCTRL_PIN(T26), 1861 ASPEED_PINCTRL_PIN(U24), 1862 ASPEED_PINCTRL_PIN(U25), 1863 ASPEED_PINCTRL_PIN(U26), 1864 ASPEED_PINCTRL_PIN(V24), 1865 ASPEED_PINCTRL_PIN(V25), 1866 ASPEED_PINCTRL_PIN(V26), 1867 ASPEED_PINCTRL_PIN(W23), 1868 ASPEED_PINCTRL_PIN(W24), 1869 ASPEED_PINCTRL_PIN(W26), 1870 ASPEED_PINCTRL_PIN(Y1), 1871 ASPEED_PINCTRL_PIN(Y2), 1872 ASPEED_PINCTRL_PIN(Y23), 1873 ASPEED_PINCTRL_PIN(Y24), 1874 ASPEED_PINCTRL_PIN(Y25), 1875 ASPEED_PINCTRL_PIN(Y26), 1876 ASPEED_PINCTRL_PIN(Y3), 1877 ASPEED_PINCTRL_PIN(Y4), 1878 ASPEED_PINCTRL_PIN(Y5), 1879 }; 1880 1881 static const struct aspeed_pin_group aspeed_g6_groups[] = { 1882 ASPEED_PINCTRL_GROUP(ADC0), 1883 ASPEED_PINCTRL_GROUP(ADC1), 1884 ASPEED_PINCTRL_GROUP(ADC10), 1885 ASPEED_PINCTRL_GROUP(ADC11), 1886 ASPEED_PINCTRL_GROUP(ADC12), 1887 ASPEED_PINCTRL_GROUP(ADC13), 1888 ASPEED_PINCTRL_GROUP(ADC14), 1889 ASPEED_PINCTRL_GROUP(ADC15), 1890 ASPEED_PINCTRL_GROUP(ADC2), 1891 ASPEED_PINCTRL_GROUP(ADC3), 1892 ASPEED_PINCTRL_GROUP(ADC4), 1893 ASPEED_PINCTRL_GROUP(ADC5), 1894 ASPEED_PINCTRL_GROUP(ADC6), 1895 ASPEED_PINCTRL_GROUP(ADC7), 1896 ASPEED_PINCTRL_GROUP(ADC8), 1897 ASPEED_PINCTRL_GROUP(ADC9), 1898 ASPEED_PINCTRL_GROUP(BMCINT), 1899 ASPEED_PINCTRL_GROUP(ESPI), 1900 ASPEED_PINCTRL_GROUP(ESPIALT), 1901 ASPEED_PINCTRL_GROUP(FSI1), 1902 ASPEED_PINCTRL_GROUP(FSI2), 1903 ASPEED_PINCTRL_GROUP(FWSPIABR), 1904 ASPEED_PINCTRL_GROUP(FWSPID), 1905 ASPEED_PINCTRL_GROUP(FWQSPID), 1906 ASPEED_PINCTRL_GROUP(FWSPIWP), 1907 ASPEED_PINCTRL_GROUP(GPIT0), 1908 ASPEED_PINCTRL_GROUP(GPIT1), 1909 ASPEED_PINCTRL_GROUP(GPIT2), 1910 ASPEED_PINCTRL_GROUP(GPIT3), 1911 ASPEED_PINCTRL_GROUP(GPIT4), 1912 ASPEED_PINCTRL_GROUP(GPIT5), 1913 ASPEED_PINCTRL_GROUP(GPIT6), 1914 ASPEED_PINCTRL_GROUP(GPIT7), 1915 ASPEED_PINCTRL_GROUP(GPIU0), 1916 ASPEED_PINCTRL_GROUP(GPIU1), 1917 ASPEED_PINCTRL_GROUP(GPIU2), 1918 ASPEED_PINCTRL_GROUP(GPIU3), 1919 ASPEED_PINCTRL_GROUP(GPIU4), 1920 ASPEED_PINCTRL_GROUP(GPIU5), 1921 ASPEED_PINCTRL_GROUP(GPIU6), 1922 ASPEED_PINCTRL_GROUP(GPIU7), 1923 ASPEED_PINCTRL_GROUP(HVI3C3), 1924 ASPEED_PINCTRL_GROUP(HVI3C4), 1925 ASPEED_PINCTRL_GROUP(I2C1), 1926 ASPEED_PINCTRL_GROUP(I2C10), 1927 ASPEED_PINCTRL_GROUP(I2C11), 1928 ASPEED_PINCTRL_GROUP(I2C12), 1929 ASPEED_PINCTRL_GROUP(I2C13), 1930 ASPEED_PINCTRL_GROUP(I2C14), 1931 ASPEED_PINCTRL_GROUP(I2C15), 1932 ASPEED_PINCTRL_GROUP(I2C16), 1933 ASPEED_PINCTRL_GROUP(I2C2), 1934 ASPEED_PINCTRL_GROUP(I2C3), 1935 ASPEED_PINCTRL_GROUP(I2C4), 1936 ASPEED_PINCTRL_GROUP(I2C5), 1937 ASPEED_PINCTRL_GROUP(I2C6), 1938 ASPEED_PINCTRL_GROUP(I2C7), 1939 ASPEED_PINCTRL_GROUP(I2C8), 1940 ASPEED_PINCTRL_GROUP(I2C9), 1941 ASPEED_PINCTRL_GROUP(I3C1), 1942 ASPEED_PINCTRL_GROUP(I3C2), 1943 ASPEED_PINCTRL_GROUP(I3C3), 1944 ASPEED_PINCTRL_GROUP(I3C4), 1945 ASPEED_PINCTRL_GROUP(I3C5), 1946 ASPEED_PINCTRL_GROUP(I3C6), 1947 ASPEED_PINCTRL_GROUP(JTAGM), 1948 ASPEED_PINCTRL_GROUP(LHPD), 1949 ASPEED_PINCTRL_GROUP(LHSIRQ), 1950 ASPEED_PINCTRL_GROUP(LPC), 1951 ASPEED_PINCTRL_GROUP(LPCHC), 1952 ASPEED_PINCTRL_GROUP(LPCPD), 1953 ASPEED_PINCTRL_GROUP(LPCPME), 1954 ASPEED_PINCTRL_GROUP(LPCSMI), 1955 ASPEED_PINCTRL_GROUP(LSIRQ), 1956 ASPEED_PINCTRL_GROUP(MACLINK1), 1957 ASPEED_PINCTRL_GROUP(MACLINK2), 1958 ASPEED_PINCTRL_GROUP(MACLINK3), 1959 ASPEED_PINCTRL_GROUP(MACLINK4), 1960 ASPEED_PINCTRL_GROUP(MDIO1), 1961 ASPEED_PINCTRL_GROUP(MDIO2), 1962 ASPEED_PINCTRL_GROUP(MDIO3), 1963 ASPEED_PINCTRL_GROUP(MDIO4), 1964 ASPEED_PINCTRL_GROUP(NCTS1), 1965 ASPEED_PINCTRL_GROUP(NCTS2), 1966 ASPEED_PINCTRL_GROUP(NCTS3), 1967 ASPEED_PINCTRL_GROUP(NCTS4), 1968 ASPEED_PINCTRL_GROUP(NDCD1), 1969 ASPEED_PINCTRL_GROUP(NDCD2), 1970 ASPEED_PINCTRL_GROUP(NDCD3), 1971 ASPEED_PINCTRL_GROUP(NDCD4), 1972 ASPEED_PINCTRL_GROUP(NDSR1), 1973 ASPEED_PINCTRL_GROUP(NDSR2), 1974 ASPEED_PINCTRL_GROUP(NDSR3), 1975 ASPEED_PINCTRL_GROUP(NDSR4), 1976 ASPEED_PINCTRL_GROUP(NDTR1), 1977 ASPEED_PINCTRL_GROUP(NDTR2), 1978 ASPEED_PINCTRL_GROUP(NDTR3), 1979 ASPEED_PINCTRL_GROUP(NDTR4), 1980 ASPEED_PINCTRL_GROUP(NRI1), 1981 ASPEED_PINCTRL_GROUP(NRI2), 1982 ASPEED_PINCTRL_GROUP(NRI3), 1983 ASPEED_PINCTRL_GROUP(NRI4), 1984 ASPEED_PINCTRL_GROUP(NRTS1), 1985 ASPEED_PINCTRL_GROUP(NRTS2), 1986 ASPEED_PINCTRL_GROUP(NRTS3), 1987 ASPEED_PINCTRL_GROUP(NRTS4), 1988 ASPEED_PINCTRL_GROUP(OSCCLK), 1989 ASPEED_PINCTRL_GROUP(PEWAKE), 1990 ASPEED_PINCTRL_GROUP(PWM0), 1991 ASPEED_PINCTRL_GROUP(PWM1), 1992 ASPEED_PINCTRL_GROUP(PWM10G0), 1993 ASPEED_PINCTRL_GROUP(PWM10G1), 1994 ASPEED_PINCTRL_GROUP(PWM11G0), 1995 ASPEED_PINCTRL_GROUP(PWM11G1), 1996 ASPEED_PINCTRL_GROUP(PWM12G0), 1997 ASPEED_PINCTRL_GROUP(PWM12G1), 1998 ASPEED_PINCTRL_GROUP(PWM13G0), 1999 ASPEED_PINCTRL_GROUP(PWM13G1), 2000 ASPEED_PINCTRL_GROUP(PWM14G0), 2001 ASPEED_PINCTRL_GROUP(PWM14G1), 2002 ASPEED_PINCTRL_GROUP(PWM15G0), 2003 ASPEED_PINCTRL_GROUP(PWM15G1), 2004 ASPEED_PINCTRL_GROUP(PWM2), 2005 ASPEED_PINCTRL_GROUP(PWM3), 2006 ASPEED_PINCTRL_GROUP(PWM4), 2007 ASPEED_PINCTRL_GROUP(PWM5), 2008 ASPEED_PINCTRL_GROUP(PWM6), 2009 ASPEED_PINCTRL_GROUP(PWM7), 2010 ASPEED_PINCTRL_GROUP(PWM8G0), 2011 ASPEED_PINCTRL_GROUP(PWM8G1), 2012 ASPEED_PINCTRL_GROUP(PWM9G0), 2013 ASPEED_PINCTRL_GROUP(PWM9G1), 2014 ASPEED_PINCTRL_GROUP(QSPI1), 2015 ASPEED_PINCTRL_GROUP(QSPI2), 2016 ASPEED_PINCTRL_GROUP(RGMII1), 2017 ASPEED_PINCTRL_GROUP(RGMII2), 2018 ASPEED_PINCTRL_GROUP(RGMII3), 2019 ASPEED_PINCTRL_GROUP(RGMII4), 2020 ASPEED_PINCTRL_GROUP(RMII1), 2021 ASPEED_PINCTRL_GROUP(RMII2), 2022 ASPEED_PINCTRL_GROUP(RMII3), 2023 ASPEED_PINCTRL_GROUP(RMII4), 2024 ASPEED_PINCTRL_GROUP(RXD1), 2025 ASPEED_PINCTRL_GROUP(RXD2), 2026 ASPEED_PINCTRL_GROUP(RXD3), 2027 ASPEED_PINCTRL_GROUP(RXD4), 2028 ASPEED_PINCTRL_GROUP(SALT1), 2029 ASPEED_PINCTRL_GROUP(SALT10G0), 2030 ASPEED_PINCTRL_GROUP(SALT10G1), 2031 ASPEED_PINCTRL_GROUP(SALT11G0), 2032 ASPEED_PINCTRL_GROUP(SALT11G1), 2033 ASPEED_PINCTRL_GROUP(SALT12G0), 2034 ASPEED_PINCTRL_GROUP(SALT12G1), 2035 ASPEED_PINCTRL_GROUP(SALT13G0), 2036 ASPEED_PINCTRL_GROUP(SALT13G1), 2037 ASPEED_PINCTRL_GROUP(SALT14G0), 2038 ASPEED_PINCTRL_GROUP(SALT14G1), 2039 ASPEED_PINCTRL_GROUP(SALT15G0), 2040 ASPEED_PINCTRL_GROUP(SALT15G1), 2041 ASPEED_PINCTRL_GROUP(SALT16G0), 2042 ASPEED_PINCTRL_GROUP(SALT16G1), 2043 ASPEED_PINCTRL_GROUP(SALT2), 2044 ASPEED_PINCTRL_GROUP(SALT3), 2045 ASPEED_PINCTRL_GROUP(SALT4), 2046 ASPEED_PINCTRL_GROUP(SALT5), 2047 ASPEED_PINCTRL_GROUP(SALT6), 2048 ASPEED_PINCTRL_GROUP(SALT7), 2049 ASPEED_PINCTRL_GROUP(SALT8), 2050 ASPEED_PINCTRL_GROUP(SALT9G0), 2051 ASPEED_PINCTRL_GROUP(SALT9G1), 2052 ASPEED_PINCTRL_GROUP(SD1), 2053 ASPEED_PINCTRL_GROUP(SD2), 2054 ASPEED_PINCTRL_GROUP(EMMCG1), 2055 ASPEED_PINCTRL_GROUP(EMMCG4), 2056 ASPEED_PINCTRL_GROUP(EMMCG8), 2057 ASPEED_PINCTRL_GROUP(SGPM1), 2058 ASPEED_PINCTRL_GROUP(SGPS1), 2059 ASPEED_PINCTRL_GROUP(SIOONCTRL), 2060 ASPEED_PINCTRL_GROUP(SIOPBI), 2061 ASPEED_PINCTRL_GROUP(SIOPBO), 2062 ASPEED_PINCTRL_GROUP(SIOPWREQ), 2063 ASPEED_PINCTRL_GROUP(SIOPWRGD), 2064 ASPEED_PINCTRL_GROUP(SIOS3), 2065 ASPEED_PINCTRL_GROUP(SIOS5), 2066 ASPEED_PINCTRL_GROUP(SIOSCI), 2067 ASPEED_PINCTRL_GROUP(SPI1), 2068 ASPEED_PINCTRL_GROUP(SPI1ABR), 2069 ASPEED_PINCTRL_GROUP(SPI1CS1), 2070 ASPEED_PINCTRL_GROUP(SPI1WP), 2071 ASPEED_PINCTRL_GROUP(SPI2), 2072 ASPEED_PINCTRL_GROUP(SPI2CS1), 2073 ASPEED_PINCTRL_GROUP(SPI2CS2), 2074 ASPEED_PINCTRL_GROUP(TACH0), 2075 ASPEED_PINCTRL_GROUP(TACH1), 2076 ASPEED_PINCTRL_GROUP(TACH10), 2077 ASPEED_PINCTRL_GROUP(TACH11), 2078 ASPEED_PINCTRL_GROUP(TACH12), 2079 ASPEED_PINCTRL_GROUP(TACH13), 2080 ASPEED_PINCTRL_GROUP(TACH14), 2081 ASPEED_PINCTRL_GROUP(TACH15), 2082 ASPEED_PINCTRL_GROUP(TACH2), 2083 ASPEED_PINCTRL_GROUP(TACH3), 2084 ASPEED_PINCTRL_GROUP(TACH4), 2085 ASPEED_PINCTRL_GROUP(TACH5), 2086 ASPEED_PINCTRL_GROUP(TACH6), 2087 ASPEED_PINCTRL_GROUP(TACH7), 2088 ASPEED_PINCTRL_GROUP(TACH8), 2089 ASPEED_PINCTRL_GROUP(TACH9), 2090 ASPEED_PINCTRL_GROUP(THRU0), 2091 ASPEED_PINCTRL_GROUP(THRU1), 2092 ASPEED_PINCTRL_GROUP(THRU2), 2093 ASPEED_PINCTRL_GROUP(THRU3), 2094 ASPEED_PINCTRL_GROUP(TXD1), 2095 ASPEED_PINCTRL_GROUP(TXD2), 2096 ASPEED_PINCTRL_GROUP(TXD3), 2097 ASPEED_PINCTRL_GROUP(TXD4), 2098 ASPEED_PINCTRL_GROUP(UART10), 2099 ASPEED_PINCTRL_GROUP(UART11), 2100 ASPEED_PINCTRL_GROUP(UART12G0), 2101 ASPEED_PINCTRL_GROUP(UART12G1), 2102 ASPEED_PINCTRL_GROUP(UART13G0), 2103 ASPEED_PINCTRL_GROUP(UART13G1), 2104 ASPEED_PINCTRL_GROUP(UART6), 2105 ASPEED_PINCTRL_GROUP(UART7), 2106 ASPEED_PINCTRL_GROUP(UART8), 2107 ASPEED_PINCTRL_GROUP(UART9), 2108 ASPEED_PINCTRL_GROUP(USBA), 2109 ASPEED_PINCTRL_GROUP(USBB), 2110 ASPEED_PINCTRL_GROUP(VB), 2111 ASPEED_PINCTRL_GROUP(VGAHS), 2112 ASPEED_PINCTRL_GROUP(VGAVS), 2113 ASPEED_PINCTRL_GROUP(WDTRST1), 2114 ASPEED_PINCTRL_GROUP(WDTRST2), 2115 ASPEED_PINCTRL_GROUP(WDTRST3), 2116 ASPEED_PINCTRL_GROUP(WDTRST4), 2117 }; 2118 2119 static const struct aspeed_pin_function aspeed_g6_functions[] = { 2120 ASPEED_PINCTRL_FUNC(ADC0), 2121 ASPEED_PINCTRL_FUNC(ADC1), 2122 ASPEED_PINCTRL_FUNC(ADC10), 2123 ASPEED_PINCTRL_FUNC(ADC11), 2124 ASPEED_PINCTRL_FUNC(ADC12), 2125 ASPEED_PINCTRL_FUNC(ADC13), 2126 ASPEED_PINCTRL_FUNC(ADC14), 2127 ASPEED_PINCTRL_FUNC(ADC15), 2128 ASPEED_PINCTRL_FUNC(ADC2), 2129 ASPEED_PINCTRL_FUNC(ADC3), 2130 ASPEED_PINCTRL_FUNC(ADC4), 2131 ASPEED_PINCTRL_FUNC(ADC5), 2132 ASPEED_PINCTRL_FUNC(ADC6), 2133 ASPEED_PINCTRL_FUNC(ADC7), 2134 ASPEED_PINCTRL_FUNC(ADC8), 2135 ASPEED_PINCTRL_FUNC(ADC9), 2136 ASPEED_PINCTRL_FUNC(BMCINT), 2137 ASPEED_PINCTRL_FUNC(EMMC), 2138 ASPEED_PINCTRL_FUNC(ESPI), 2139 ASPEED_PINCTRL_FUNC(ESPIALT), 2140 ASPEED_PINCTRL_FUNC(FSI1), 2141 ASPEED_PINCTRL_FUNC(FSI2), 2142 ASPEED_PINCTRL_FUNC(FWSPIABR), 2143 ASPEED_PINCTRL_FUNC(FWSPID), 2144 ASPEED_PINCTRL_FUNC(FWSPIWP), 2145 ASPEED_PINCTRL_FUNC(GPIT0), 2146 ASPEED_PINCTRL_FUNC(GPIT1), 2147 ASPEED_PINCTRL_FUNC(GPIT2), 2148 ASPEED_PINCTRL_FUNC(GPIT3), 2149 ASPEED_PINCTRL_FUNC(GPIT4), 2150 ASPEED_PINCTRL_FUNC(GPIT5), 2151 ASPEED_PINCTRL_FUNC(GPIT6), 2152 ASPEED_PINCTRL_FUNC(GPIT7), 2153 ASPEED_PINCTRL_FUNC(GPIU0), 2154 ASPEED_PINCTRL_FUNC(GPIU1), 2155 ASPEED_PINCTRL_FUNC(GPIU2), 2156 ASPEED_PINCTRL_FUNC(GPIU3), 2157 ASPEED_PINCTRL_FUNC(GPIU4), 2158 ASPEED_PINCTRL_FUNC(GPIU5), 2159 ASPEED_PINCTRL_FUNC(GPIU6), 2160 ASPEED_PINCTRL_FUNC(GPIU7), 2161 ASPEED_PINCTRL_FUNC(I2C1), 2162 ASPEED_PINCTRL_FUNC(I2C10), 2163 ASPEED_PINCTRL_FUNC(I2C11), 2164 ASPEED_PINCTRL_FUNC(I2C12), 2165 ASPEED_PINCTRL_FUNC(I2C13), 2166 ASPEED_PINCTRL_FUNC(I2C14), 2167 ASPEED_PINCTRL_FUNC(I2C15), 2168 ASPEED_PINCTRL_FUNC(I2C16), 2169 ASPEED_PINCTRL_FUNC(I2C2), 2170 ASPEED_PINCTRL_FUNC(I2C3), 2171 ASPEED_PINCTRL_FUNC(I2C4), 2172 ASPEED_PINCTRL_FUNC(I2C5), 2173 ASPEED_PINCTRL_FUNC(I2C6), 2174 ASPEED_PINCTRL_FUNC(I2C7), 2175 ASPEED_PINCTRL_FUNC(I2C8), 2176 ASPEED_PINCTRL_FUNC(I2C9), 2177 ASPEED_PINCTRL_FUNC(I3C1), 2178 ASPEED_PINCTRL_FUNC(I3C2), 2179 ASPEED_PINCTRL_FUNC(I3C3), 2180 ASPEED_PINCTRL_FUNC(I3C4), 2181 ASPEED_PINCTRL_FUNC(I3C5), 2182 ASPEED_PINCTRL_FUNC(I3C6), 2183 ASPEED_PINCTRL_FUNC(JTAGM), 2184 ASPEED_PINCTRL_FUNC(LHPD), 2185 ASPEED_PINCTRL_FUNC(LHSIRQ), 2186 ASPEED_PINCTRL_FUNC(LPC), 2187 ASPEED_PINCTRL_FUNC(LPCHC), 2188 ASPEED_PINCTRL_FUNC(LPCPD), 2189 ASPEED_PINCTRL_FUNC(LPCPME), 2190 ASPEED_PINCTRL_FUNC(LPCSMI), 2191 ASPEED_PINCTRL_FUNC(LSIRQ), 2192 ASPEED_PINCTRL_FUNC(MACLINK1), 2193 ASPEED_PINCTRL_FUNC(MACLINK2), 2194 ASPEED_PINCTRL_FUNC(MACLINK3), 2195 ASPEED_PINCTRL_FUNC(MACLINK4), 2196 ASPEED_PINCTRL_FUNC(MDIO1), 2197 ASPEED_PINCTRL_FUNC(MDIO2), 2198 ASPEED_PINCTRL_FUNC(MDIO3), 2199 ASPEED_PINCTRL_FUNC(MDIO4), 2200 ASPEED_PINCTRL_FUNC(NCTS1), 2201 ASPEED_PINCTRL_FUNC(NCTS2), 2202 ASPEED_PINCTRL_FUNC(NCTS3), 2203 ASPEED_PINCTRL_FUNC(NCTS4), 2204 ASPEED_PINCTRL_FUNC(NDCD1), 2205 ASPEED_PINCTRL_FUNC(NDCD2), 2206 ASPEED_PINCTRL_FUNC(NDCD3), 2207 ASPEED_PINCTRL_FUNC(NDCD4), 2208 ASPEED_PINCTRL_FUNC(NDSR1), 2209 ASPEED_PINCTRL_FUNC(NDSR2), 2210 ASPEED_PINCTRL_FUNC(NDSR3), 2211 ASPEED_PINCTRL_FUNC(NDSR4), 2212 ASPEED_PINCTRL_FUNC(NDTR1), 2213 ASPEED_PINCTRL_FUNC(NDTR2), 2214 ASPEED_PINCTRL_FUNC(NDTR3), 2215 ASPEED_PINCTRL_FUNC(NDTR4), 2216 ASPEED_PINCTRL_FUNC(NRI1), 2217 ASPEED_PINCTRL_FUNC(NRI2), 2218 ASPEED_PINCTRL_FUNC(NRI3), 2219 ASPEED_PINCTRL_FUNC(NRI4), 2220 ASPEED_PINCTRL_FUNC(NRTS1), 2221 ASPEED_PINCTRL_FUNC(NRTS2), 2222 ASPEED_PINCTRL_FUNC(NRTS3), 2223 ASPEED_PINCTRL_FUNC(NRTS4), 2224 ASPEED_PINCTRL_FUNC(OSCCLK), 2225 ASPEED_PINCTRL_FUNC(PEWAKE), 2226 ASPEED_PINCTRL_FUNC(PWM0), 2227 ASPEED_PINCTRL_FUNC(PWM1), 2228 ASPEED_PINCTRL_FUNC(PWM10), 2229 ASPEED_PINCTRL_FUNC(PWM11), 2230 ASPEED_PINCTRL_FUNC(PWM12), 2231 ASPEED_PINCTRL_FUNC(PWM13), 2232 ASPEED_PINCTRL_FUNC(PWM14), 2233 ASPEED_PINCTRL_FUNC(PWM15), 2234 ASPEED_PINCTRL_FUNC(PWM2), 2235 ASPEED_PINCTRL_FUNC(PWM3), 2236 ASPEED_PINCTRL_FUNC(PWM4), 2237 ASPEED_PINCTRL_FUNC(PWM5), 2238 ASPEED_PINCTRL_FUNC(PWM6), 2239 ASPEED_PINCTRL_FUNC(PWM7), 2240 ASPEED_PINCTRL_FUNC(PWM8), 2241 ASPEED_PINCTRL_FUNC(PWM9), 2242 ASPEED_PINCTRL_FUNC(RGMII1), 2243 ASPEED_PINCTRL_FUNC(RGMII2), 2244 ASPEED_PINCTRL_FUNC(RGMII3), 2245 ASPEED_PINCTRL_FUNC(RGMII4), 2246 ASPEED_PINCTRL_FUNC(RMII1), 2247 ASPEED_PINCTRL_FUNC(RMII2), 2248 ASPEED_PINCTRL_FUNC(RMII3), 2249 ASPEED_PINCTRL_FUNC(RMII4), 2250 ASPEED_PINCTRL_FUNC(RXD1), 2251 ASPEED_PINCTRL_FUNC(RXD2), 2252 ASPEED_PINCTRL_FUNC(RXD3), 2253 ASPEED_PINCTRL_FUNC(RXD4), 2254 ASPEED_PINCTRL_FUNC(SALT1), 2255 ASPEED_PINCTRL_FUNC(SALT10), 2256 ASPEED_PINCTRL_FUNC(SALT11), 2257 ASPEED_PINCTRL_FUNC(SALT12), 2258 ASPEED_PINCTRL_FUNC(SALT13), 2259 ASPEED_PINCTRL_FUNC(SALT14), 2260 ASPEED_PINCTRL_FUNC(SALT15), 2261 ASPEED_PINCTRL_FUNC(SALT16), 2262 ASPEED_PINCTRL_FUNC(SALT2), 2263 ASPEED_PINCTRL_FUNC(SALT3), 2264 ASPEED_PINCTRL_FUNC(SALT4), 2265 ASPEED_PINCTRL_FUNC(SALT5), 2266 ASPEED_PINCTRL_FUNC(SALT6), 2267 ASPEED_PINCTRL_FUNC(SALT7), 2268 ASPEED_PINCTRL_FUNC(SALT8), 2269 ASPEED_PINCTRL_FUNC(SALT9), 2270 ASPEED_PINCTRL_FUNC(SD1), 2271 ASPEED_PINCTRL_FUNC(SD2), 2272 ASPEED_PINCTRL_FUNC(SGPM1), 2273 ASPEED_PINCTRL_FUNC(SGPS1), 2274 ASPEED_PINCTRL_FUNC(SIOONCTRL), 2275 ASPEED_PINCTRL_FUNC(SIOPBI), 2276 ASPEED_PINCTRL_FUNC(SIOPBO), 2277 ASPEED_PINCTRL_FUNC(SIOPWREQ), 2278 ASPEED_PINCTRL_FUNC(SIOPWRGD), 2279 ASPEED_PINCTRL_FUNC(SIOS3), 2280 ASPEED_PINCTRL_FUNC(SIOS5), 2281 ASPEED_PINCTRL_FUNC(SIOSCI), 2282 ASPEED_PINCTRL_FUNC(SPI1), 2283 ASPEED_PINCTRL_FUNC(SPI1ABR), 2284 ASPEED_PINCTRL_FUNC(SPI1CS1), 2285 ASPEED_PINCTRL_FUNC(SPI1WP), 2286 ASPEED_PINCTRL_FUNC(SPI2), 2287 ASPEED_PINCTRL_FUNC(SPI2CS1), 2288 ASPEED_PINCTRL_FUNC(SPI2CS2), 2289 ASPEED_PINCTRL_FUNC(TACH0), 2290 ASPEED_PINCTRL_FUNC(TACH1), 2291 ASPEED_PINCTRL_FUNC(TACH10), 2292 ASPEED_PINCTRL_FUNC(TACH11), 2293 ASPEED_PINCTRL_FUNC(TACH12), 2294 ASPEED_PINCTRL_FUNC(TACH13), 2295 ASPEED_PINCTRL_FUNC(TACH14), 2296 ASPEED_PINCTRL_FUNC(TACH15), 2297 ASPEED_PINCTRL_FUNC(TACH2), 2298 ASPEED_PINCTRL_FUNC(TACH3), 2299 ASPEED_PINCTRL_FUNC(TACH4), 2300 ASPEED_PINCTRL_FUNC(TACH5), 2301 ASPEED_PINCTRL_FUNC(TACH6), 2302 ASPEED_PINCTRL_FUNC(TACH7), 2303 ASPEED_PINCTRL_FUNC(TACH8), 2304 ASPEED_PINCTRL_FUNC(TACH9), 2305 ASPEED_PINCTRL_FUNC(THRU0), 2306 ASPEED_PINCTRL_FUNC(THRU1), 2307 ASPEED_PINCTRL_FUNC(THRU2), 2308 ASPEED_PINCTRL_FUNC(THRU3), 2309 ASPEED_PINCTRL_FUNC(TXD1), 2310 ASPEED_PINCTRL_FUNC(TXD2), 2311 ASPEED_PINCTRL_FUNC(TXD3), 2312 ASPEED_PINCTRL_FUNC(TXD4), 2313 ASPEED_PINCTRL_FUNC(UART10), 2314 ASPEED_PINCTRL_FUNC(UART11), 2315 ASPEED_PINCTRL_FUNC(UART12), 2316 ASPEED_PINCTRL_FUNC(UART13), 2317 ASPEED_PINCTRL_FUNC(UART6), 2318 ASPEED_PINCTRL_FUNC(UART7), 2319 ASPEED_PINCTRL_FUNC(UART8), 2320 ASPEED_PINCTRL_FUNC(UART9), 2321 ASPEED_PINCTRL_FUNC(USB11BHID), 2322 ASPEED_PINCTRL_FUNC(USB2AD), 2323 ASPEED_PINCTRL_FUNC(USB2ADP), 2324 ASPEED_PINCTRL_FUNC(USB2AH), 2325 ASPEED_PINCTRL_FUNC(USB2AHP), 2326 ASPEED_PINCTRL_FUNC(USB2BD), 2327 ASPEED_PINCTRL_FUNC(USB2BH), 2328 ASPEED_PINCTRL_FUNC(VB), 2329 ASPEED_PINCTRL_FUNC(VGAHS), 2330 ASPEED_PINCTRL_FUNC(VGAVS), 2331 ASPEED_PINCTRL_FUNC(WDTRST1), 2332 ASPEED_PINCTRL_FUNC(WDTRST2), 2333 ASPEED_PINCTRL_FUNC(WDTRST3), 2334 ASPEED_PINCTRL_FUNC(WDTRST4), 2335 }; 2336 2337 static struct aspeed_pin_config aspeed_g6_configs[] = { 2338 /* GPIOB7 */ 2339 ASPEED_PULL_DOWN_PINCONF(J24, SCU610, 15), 2340 /* GPIOB6 */ 2341 ASPEED_PULL_DOWN_PINCONF(H25, SCU610, 14), 2342 /* GPIOB5 */ 2343 ASPEED_PULL_DOWN_PINCONF(G26, SCU610, 13), 2344 /* GPIOB4 */ 2345 ASPEED_PULL_DOWN_PINCONF(J23, SCU610, 12), 2346 /* GPIOB3 */ 2347 ASPEED_PULL_DOWN_PINCONF(J25, SCU610, 11), 2348 /* GPIOB2 */ 2349 ASPEED_PULL_DOWN_PINCONF(H26, SCU610, 10), 2350 /* GPIOB1 */ 2351 ASPEED_PULL_DOWN_PINCONF(K23, SCU610, 9), 2352 /* GPIOB0 */ 2353 ASPEED_PULL_DOWN_PINCONF(J26, SCU610, 8), 2354 2355 /* GPIOH3 */ 2356 ASPEED_PULL_DOWN_PINCONF(A17, SCU614, 27), 2357 /* GPIOH2 */ 2358 ASPEED_PULL_DOWN_PINCONF(C18, SCU614, 26), 2359 /* GPIOH1 */ 2360 ASPEED_PULL_DOWN_PINCONF(B18, SCU614, 25), 2361 /* GPIOH0 */ 2362 ASPEED_PULL_DOWN_PINCONF(A18, SCU614, 24), 2363 2364 /* GPIOL7 */ 2365 ASPEED_PULL_DOWN_PINCONF(C14, SCU618, 31), 2366 /* GPIOL6 */ 2367 ASPEED_PULL_DOWN_PINCONF(B14, SCU618, 30), 2368 /* GPIOL5 */ 2369 ASPEED_PULL_DOWN_PINCONF(F15, SCU618, 29), 2370 /* GPIOL4 */ 2371 ASPEED_PULL_DOWN_PINCONF(C15, SCU618, 28), 2372 2373 /* GPIOJ7 */ 2374 ASPEED_PULL_UP_PINCONF(D19, SCU618, 15), 2375 /* GPIOJ6 */ 2376 ASPEED_PULL_UP_PINCONF(C20, SCU618, 14), 2377 /* GPIOJ5 */ 2378 ASPEED_PULL_UP_PINCONF(A19, SCU618, 13), 2379 /* GPIOJ4 */ 2380 ASPEED_PULL_UP_PINCONF(C19, SCU618, 12), 2381 /* GPIOJ3 */ 2382 ASPEED_PULL_UP_PINCONF(D20, SCU618, 11), 2383 /* GPIOJ2 */ 2384 ASPEED_PULL_UP_PINCONF(E19, SCU618, 10), 2385 /* GPIOJ1 */ 2386 ASPEED_PULL_UP_PINCONF(A20, SCU618, 9), 2387 /* GPIOJ0 */ 2388 ASPEED_PULL_UP_PINCONF(B20, SCU618, 8), 2389 2390 /* GPIOI7 */ 2391 ASPEED_PULL_DOWN_PINCONF(A15, SCU618, 7), 2392 /* GPIOI6 */ 2393 ASPEED_PULL_DOWN_PINCONF(B16, SCU618, 6), 2394 /* GPIOI5 */ 2395 ASPEED_PULL_DOWN_PINCONF(E16, SCU618, 5), 2396 /* GPIOI4 */ 2397 ASPEED_PULL_DOWN_PINCONF(C16, SCU618, 4), 2398 /* GPIOI3 */ 2399 ASPEED_PULL_DOWN_PINCONF(D16, SCU618, 3), 2400 /* GPIOI2 */ 2401 ASPEED_PULL_DOWN_PINCONF(E17, SCU618, 2), 2402 /* GPIOI1 */ 2403 ASPEED_PULL_DOWN_PINCONF(A16, SCU618, 1), 2404 /* GPIOI0 */ 2405 ASPEED_PULL_DOWN_PINCONF(D17, SCU618, 0), 2406 2407 /* GPIOP7 */ 2408 ASPEED_PULL_DOWN_PINCONF(Y23, SCU61C, 31), 2409 /* GPIOP6 */ 2410 ASPEED_PULL_DOWN_PINCONF(AB24, SCU61C, 30), 2411 /* GPIOP5 */ 2412 ASPEED_PULL_DOWN_PINCONF(AB23, SCU61C, 29), 2413 /* GPIOP4 */ 2414 ASPEED_PULL_DOWN_PINCONF(W23, SCU61C, 28), 2415 /* GPIOP3 */ 2416 ASPEED_PULL_DOWN_PINCONF(AA24, SCU61C, 27), 2417 /* GPIOP2 */ 2418 ASPEED_PULL_DOWN_PINCONF(AA23, SCU61C, 26), 2419 /* GPIOP1 */ 2420 ASPEED_PULL_DOWN_PINCONF(W24, SCU61C, 25), 2421 /* GPIOP0 */ 2422 ASPEED_PULL_DOWN_PINCONF(AB22, SCU61C, 24), 2423 2424 /* GPIOO7 */ 2425 ASPEED_PULL_DOWN_PINCONF(AC23, SCU61C, 23), 2426 /* GPIOO6 */ 2427 ASPEED_PULL_DOWN_PINCONF(AC24, SCU61C, 22), 2428 /* GPIOO5 */ 2429 ASPEED_PULL_DOWN_PINCONF(AC22, SCU61C, 21), 2430 /* GPIOO4 */ 2431 ASPEED_PULL_DOWN_PINCONF(AD25, SCU61C, 20), 2432 /* GPIOO3 */ 2433 ASPEED_PULL_DOWN_PINCONF(AD24, SCU61C, 19), 2434 /* GPIOO2 */ 2435 ASPEED_PULL_DOWN_PINCONF(AD23, SCU61C, 18), 2436 /* GPIOO1 */ 2437 ASPEED_PULL_DOWN_PINCONF(AD22, SCU61C, 17), 2438 /* GPIOO0 */ 2439 ASPEED_PULL_DOWN_PINCONF(AD26, SCU61C, 16), 2440 2441 /* GPION7 */ 2442 ASPEED_PULL_DOWN_PINCONF(M26, SCU61C, 15), 2443 /* GPION6 */ 2444 ASPEED_PULL_DOWN_PINCONF(N26, SCU61C, 14), 2445 /* GPION5 */ 2446 ASPEED_PULL_DOWN_PINCONF(M23, SCU61C, 13), 2447 /* GPION4 */ 2448 ASPEED_PULL_DOWN_PINCONF(P26, SCU61C, 12), 2449 /* GPION3 */ 2450 ASPEED_PULL_DOWN_PINCONF(N24, SCU61C, 11), 2451 /* GPION2 */ 2452 ASPEED_PULL_DOWN_PINCONF(N25, SCU61C, 10), 2453 /* GPION1 */ 2454 ASPEED_PULL_DOWN_PINCONF(N23, SCU61C, 9), 2455 /* GPION0 */ 2456 ASPEED_PULL_DOWN_PINCONF(P25, SCU61C, 8), 2457 2458 /* GPIOM7 */ 2459 ASPEED_PULL_DOWN_PINCONF(D13, SCU61C, 7), 2460 /* GPIOM6 */ 2461 ASPEED_PULL_DOWN_PINCONF(C13, SCU61C, 6), 2462 /* GPIOM5 */ 2463 ASPEED_PULL_DOWN_PINCONF(C12, SCU61C, 5), 2464 /* GPIOM4 */ 2465 ASPEED_PULL_DOWN_PINCONF(B12, SCU61C, 4), 2466 /* GPIOM3 */ 2467 ASPEED_PULL_DOWN_PINCONF(E14, SCU61C, 3), 2468 /* GPIOM2 */ 2469 ASPEED_PULL_DOWN_PINCONF(A12, SCU61C, 2), 2470 /* GPIOM1 */ 2471 ASPEED_PULL_DOWN_PINCONF(B13, SCU61C, 1), 2472 /* GPIOM0 */ 2473 ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0), 2474 2475 /* GPIOS7 */ 2476 ASPEED_PULL_DOWN_PINCONF(T24, SCU620, 23), 2477 /* GPIOS6 */ 2478 ASPEED_PULL_DOWN_PINCONF(P23, SCU620, 22), 2479 /* GPIOS5 */ 2480 ASPEED_PULL_DOWN_PINCONF(P24, SCU620, 21), 2481 /* GPIOS4 */ 2482 ASPEED_PULL_DOWN_PINCONF(R26, SCU620, 20), 2483 /* GPIOS3*/ 2484 ASPEED_PULL_DOWN_PINCONF(R24, SCU620, 19), 2485 /* GPIOS2 */ 2486 ASPEED_PULL_DOWN_PINCONF(T26, SCU620, 18), 2487 /* GPIOS1 */ 2488 ASPEED_PULL_DOWN_PINCONF(T25, SCU620, 17), 2489 /* GPIOS0 */ 2490 ASPEED_PULL_DOWN_PINCONF(R23, SCU620, 16), 2491 2492 /* GPIOR7 */ 2493 ASPEED_PULL_DOWN_PINCONF(U26, SCU620, 15), 2494 /* GPIOR6 */ 2495 ASPEED_PULL_DOWN_PINCONF(W26, SCU620, 14), 2496 /* GPIOR5 */ 2497 ASPEED_PULL_DOWN_PINCONF(T23, SCU620, 13), 2498 /* GPIOR4 */ 2499 ASPEED_PULL_DOWN_PINCONF(U25, SCU620, 12), 2500 /* GPIOR3*/ 2501 ASPEED_PULL_DOWN_PINCONF(V26, SCU620, 11), 2502 /* GPIOR2 */ 2503 ASPEED_PULL_DOWN_PINCONF(V24, SCU620, 10), 2504 /* GPIOR1 */ 2505 ASPEED_PULL_DOWN_PINCONF(U24, SCU620, 9), 2506 /* GPIOR0 */ 2507 ASPEED_PULL_DOWN_PINCONF(V25, SCU620, 8), 2508 2509 /* GPIOX7 */ 2510 ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31), 2511 /* GPIOX6 */ 2512 ASPEED_PULL_DOWN_PINCONF(AF9, SCU634, 30), 2513 /* GPIOX5 */ 2514 ASPEED_PULL_DOWN_PINCONF(AD9, SCU634, 29), 2515 /* GPIOX4 */ 2516 ASPEED_PULL_DOWN_PINCONF(AB9, SCU634, 28), 2517 /* GPIOX3*/ 2518 ASPEED_PULL_DOWN_PINCONF(AF8, SCU634, 27), 2519 /* GPIOX2 */ 2520 ASPEED_PULL_DOWN_PINCONF(AC9, SCU634, 26), 2521 /* GPIOX1 */ 2522 ASPEED_PULL_DOWN_PINCONF(AA9, SCU634, 25), 2523 /* GPIOX0 */ 2524 ASPEED_PULL_DOWN_PINCONF(AE8, SCU634, 24), 2525 2526 /* GPIOV7 */ 2527 ASPEED_PULL_DOWN_PINCONF(AF15, SCU634, 15), 2528 /* GPIOV6 */ 2529 ASPEED_PULL_DOWN_PINCONF(AD15, SCU634, 14), 2530 /* GPIOV5 */ 2531 ASPEED_PULL_DOWN_PINCONF(AE14, SCU634, 13), 2532 /* GPIOV4 */ 2533 ASPEED_PULL_DOWN_PINCONF(AE15, SCU634, 12), 2534 /* GPIOV3*/ 2535 ASPEED_PULL_DOWN_PINCONF(AC15, SCU634, 11), 2536 /* GPIOV2 */ 2537 ASPEED_PULL_DOWN_PINCONF(AD14, SCU634, 10), 2538 /* GPIOV1 */ 2539 ASPEED_PULL_DOWN_PINCONF(AF14, SCU634, 9), 2540 /* GPIOV0 */ 2541 ASPEED_PULL_DOWN_PINCONF(AB15, SCU634, 8), 2542 2543 /* GPIOZ7 */ 2544 ASPEED_PULL_DOWN_PINCONF(AF10, SCU638, 15), 2545 /* GPIOZ6 */ 2546 ASPEED_PULL_DOWN_PINCONF(AD11, SCU638, 14), 2547 /* GPIOZ5 */ 2548 ASPEED_PULL_DOWN_PINCONF(AA11, SCU638, 13), 2549 /* GPIOZ4 */ 2550 ASPEED_PULL_DOWN_PINCONF(AC11, SCU638, 12), 2551 /* GPIOZ3*/ 2552 ASPEED_PULL_DOWN_PINCONF(AB11, SCU638, 11), 2553 2554 /* GPIOZ1 */ 2555 ASPEED_PULL_DOWN_PINCONF(AD10, SCU638, 9), 2556 /* GPIOZ0 */ 2557 ASPEED_PULL_DOWN_PINCONF(AC10, SCU638, 8), 2558 2559 /* GPIOY6 */ 2560 ASPEED_PULL_DOWN_PINCONF(AC12, SCU638, 6), 2561 /* GPIOY5 */ 2562 ASPEED_PULL_DOWN_PINCONF(AF12, SCU638, 5), 2563 /* GPIOY4 */ 2564 ASPEED_PULL_DOWN_PINCONF(AE12, SCU638, 4), 2565 /* GPIOY3 */ 2566 ASPEED_PULL_DOWN_PINCONF(AA12, SCU638, 3), 2567 /* GPIOY2 */ 2568 ASPEED_PULL_DOWN_PINCONF(AE11, SCU638, 2), 2569 /* GPIOY1 */ 2570 ASPEED_PULL_DOWN_PINCONF(AD12, SCU638, 1), 2571 /* GPIOY0 */ 2572 ASPEED_PULL_DOWN_PINCONF(AF11, SCU638, 0), 2573 2574 /* LAD3 */ 2575 { PIN_CONFIG_DRIVE_STRENGTH, { AC7, AC7 }, SCU454, GENMASK(31, 30)}, 2576 /* LAD2 */ 2577 { PIN_CONFIG_DRIVE_STRENGTH, { AC8, AC8 }, SCU454, GENMASK(29, 28)}, 2578 /* LAD1 */ 2579 { PIN_CONFIG_DRIVE_STRENGTH, { AB8, AB8 }, SCU454, GENMASK(27, 26)}, 2580 /* LAD0 */ 2581 { PIN_CONFIG_DRIVE_STRENGTH, { AB7, AB7 }, SCU454, GENMASK(25, 24)}, 2582 2583 /* MAC3 */ 2584 { PIN_CONFIG_POWER_SOURCE, { H24, E26 }, SCU458, BIT_MASK(4)}, 2585 { PIN_CONFIG_DRIVE_STRENGTH, { H24, E26 }, SCU458, GENMASK(1, 0)}, 2586 /* MAC4 */ 2587 { PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)}, 2588 { PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)}, 2589 }; 2590 2591 /** 2592 * Configure a pin's signal by applying an expression's descriptor state for 2593 * all descriptors in the expression. 2594 * 2595 * @ctx: The pinmux context 2596 * @expr: The expression associated with the function whose signal is to be 2597 * configured 2598 * @enable: true to enable an function's signal through a pin's signal 2599 * expression, false to disable the function's signal 2600 * 2601 * Return: 0 if the expression is configured as requested and a negative error 2602 * code otherwise 2603 */ 2604 static int aspeed_g6_sig_expr_set(struct aspeed_pinmux_data *ctx, 2605 const struct aspeed_sig_expr *expr, 2606 bool enable) 2607 { 2608 int ret; 2609 int i; 2610 2611 for (i = 0; i < expr->ndescs; i++) { 2612 const struct aspeed_sig_desc *desc = &expr->descs[i]; 2613 u32 pattern = enable ? desc->enable : desc->disable; 2614 u32 val = (pattern << __ffs(desc->mask)); 2615 bool is_strap; 2616 2617 if (!ctx->maps[desc->ip]) 2618 return -ENODEV; 2619 2620 WARN_ON(desc->ip != ASPEED_IP_SCU); 2621 is_strap = desc->reg == SCU500 || desc->reg == SCU510; 2622 2623 if (is_strap) { 2624 /* 2625 * The AST2600 has write protection mask registers for 2626 * the hardware strapping in SCU508 and SCU518. Assume 2627 * that if the platform doesn't want the strapping 2628 * values changed that it has set the write mask. 2629 * 2630 * The strapping registers implement write-1-clear 2631 * behaviour. SCU500 is paired with clear writes on 2632 * SCU504, likewise SCU510 is paired with SCU514. 2633 */ 2634 u32 clear = ~val & desc->mask; 2635 u32 w1c = desc->reg + 4; 2636 2637 if (clear) 2638 ret = regmap_update_bits(ctx->maps[desc->ip], 2639 w1c, desc->mask, 2640 clear); 2641 } 2642 2643 ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, 2644 desc->mask, val); 2645 if (ret) 2646 return ret; 2647 } 2648 2649 ret = aspeed_sig_expr_eval(ctx, expr, enable); 2650 if (ret < 0) 2651 return ret; 2652 2653 if (!ret) 2654 return -EPERM; 2655 return 0; 2656 } 2657 2658 static const struct aspeed_pin_config_map aspeed_g6_pin_config_map[] = { 2659 { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, 2660 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, 2661 { PIN_CONFIG_BIAS_PULL_UP, 0, 1, BIT_MASK(0)}, 2662 { PIN_CONFIG_BIAS_PULL_UP, -1, 0, BIT_MASK(0)}, 2663 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)}, 2664 { PIN_CONFIG_DRIVE_STRENGTH, 4, 0, GENMASK(1, 0)}, 2665 { PIN_CONFIG_DRIVE_STRENGTH, 8, 1, GENMASK(1, 0)}, 2666 { PIN_CONFIG_DRIVE_STRENGTH, 12, 2, GENMASK(1, 0)}, 2667 { PIN_CONFIG_DRIVE_STRENGTH, 16, 3, GENMASK(1, 0)}, 2668 { PIN_CONFIG_POWER_SOURCE, 3300, 0, BIT_MASK(0)}, 2669 { PIN_CONFIG_POWER_SOURCE, 1800, 1, BIT_MASK(0)}, 2670 }; 2671 2672 static const struct aspeed_pinmux_ops aspeed_g5_ops = { 2673 .set = aspeed_g6_sig_expr_set, 2674 }; 2675 2676 static struct aspeed_pinctrl_data aspeed_g6_pinctrl_data = { 2677 .pins = aspeed_g6_pins, 2678 .npins = ARRAY_SIZE(aspeed_g6_pins), 2679 .pinmux = { 2680 .ops = &aspeed_g5_ops, 2681 .groups = aspeed_g6_groups, 2682 .ngroups = ARRAY_SIZE(aspeed_g6_groups), 2683 .functions = aspeed_g6_functions, 2684 .nfunctions = ARRAY_SIZE(aspeed_g6_functions), 2685 }, 2686 .configs = aspeed_g6_configs, 2687 .nconfigs = ARRAY_SIZE(aspeed_g6_configs), 2688 .confmaps = aspeed_g6_pin_config_map, 2689 .nconfmaps = ARRAY_SIZE(aspeed_g6_pin_config_map), 2690 }; 2691 2692 static const struct pinmux_ops aspeed_g6_pinmux_ops = { 2693 .get_functions_count = aspeed_pinmux_get_fn_count, 2694 .get_function_name = aspeed_pinmux_get_fn_name, 2695 .get_function_groups = aspeed_pinmux_get_fn_groups, 2696 .set_mux = aspeed_pinmux_set_mux, 2697 .gpio_request_enable = aspeed_gpio_request_enable, 2698 .strict = true, 2699 }; 2700 2701 static const struct pinctrl_ops aspeed_g6_pinctrl_ops = { 2702 .get_groups_count = aspeed_pinctrl_get_groups_count, 2703 .get_group_name = aspeed_pinctrl_get_group_name, 2704 .get_group_pins = aspeed_pinctrl_get_group_pins, 2705 .pin_dbg_show = aspeed_pinctrl_pin_dbg_show, 2706 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 2707 .dt_free_map = pinctrl_utils_free_map, 2708 }; 2709 2710 static const struct pinconf_ops aspeed_g6_conf_ops = { 2711 .is_generic = true, 2712 .pin_config_get = aspeed_pin_config_get, 2713 .pin_config_set = aspeed_pin_config_set, 2714 .pin_config_group_get = aspeed_pin_config_group_get, 2715 .pin_config_group_set = aspeed_pin_config_group_set, 2716 }; 2717 2718 static struct pinctrl_desc aspeed_g6_pinctrl_desc = { 2719 .name = "aspeed-g6-pinctrl", 2720 .pins = aspeed_g6_pins, 2721 .npins = ARRAY_SIZE(aspeed_g6_pins), 2722 .pctlops = &aspeed_g6_pinctrl_ops, 2723 .pmxops = &aspeed_g6_pinmux_ops, 2724 .confops = &aspeed_g6_conf_ops, 2725 }; 2726 2727 static int aspeed_g6_pinctrl_probe(struct platform_device *pdev) 2728 { 2729 int i; 2730 2731 for (i = 0; i < ARRAY_SIZE(aspeed_g6_pins); i++) 2732 aspeed_g6_pins[i].number = i; 2733 2734 return aspeed_pinctrl_probe(pdev, &aspeed_g6_pinctrl_desc, 2735 &aspeed_g6_pinctrl_data); 2736 } 2737 2738 static const struct of_device_id aspeed_g6_pinctrl_of_match[] = { 2739 { .compatible = "aspeed,ast2600-pinctrl", }, 2740 { }, 2741 }; 2742 2743 static struct platform_driver aspeed_g6_pinctrl_driver = { 2744 .probe = aspeed_g6_pinctrl_probe, 2745 .driver = { 2746 .name = "aspeed-g6-pinctrl", 2747 .of_match_table = aspeed_g6_pinctrl_of_match, 2748 }, 2749 }; 2750 2751 static int aspeed_g6_pinctrl_init(void) 2752 { 2753 return platform_driver_register(&aspeed_g6_pinctrl_driver); 2754 } 2755 2756 arch_initcall(aspeed_g6_pinctrl_init); 2757