1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
4 *
5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
6 *
7 * This driver is inspired by:
8 * pinctrl-nomadik.c, please see original file for copyright information
9 * pinctrl-tegra.c, please see original file for copyright information
10 */
11
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/of_address.h>
25 #include <linux/of.h>
26 #include <linux/of_irq.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pinctrl/machine.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/pinctrl/pinctrl.h>
31 #include <linux/pinctrl/pinmux.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/platform_device.h>
34 #include <linux/seq_file.h>
35 #include <linux/slab.h>
36 #include <linux/spinlock.h>
37 #include <linux/string_choices.h>
38 #include <linux/types.h>
39 #include <dt-bindings/pinctrl/bcm2835.h>
40
41 #define MODULE_NAME "pinctrl-bcm2835"
42 #define BCM2835_NUM_GPIOS 54
43 #define BCM2711_NUM_GPIOS 58
44 #define BCM2835_NUM_BANKS 2
45 #define BCM2835_NUM_IRQS 3
46
47 /* GPIO register offsets */
48 #define GPFSEL0 0x0 /* Function Select */
49 #define GPSET0 0x1c /* Pin Output Set */
50 #define GPCLR0 0x28 /* Pin Output Clear */
51 #define GPLEV0 0x34 /* Pin Level */
52 #define GPEDS0 0x40 /* Pin Event Detect Status */
53 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
54 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
55 #define GPHEN0 0x64 /* Pin High Detect Enable */
56 #define GPLEN0 0x70 /* Pin Low Detect Enable */
57 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
58 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
59 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
60 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
61 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
62
63 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
64 #define FSEL_SHIFT(p) (((p) % 10) * 3)
65 #define GPIO_REG_OFFSET(p) ((p) / 32)
66 #define GPIO_REG_SHIFT(p) ((p) % 32)
67
68 #define PUD_2711_MASK 0x3
69 #define PUD_2711_REG_OFFSET(p) ((p) / 16)
70 #define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2)
71
72 /* argument: bcm2835_pinconf_pull */
73 #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
74
75 #define BCM2711_PULL_NONE 0x0
76 #define BCM2711_PULL_UP 0x1
77 #define BCM2711_PULL_DOWN 0x2
78
79 struct bcm2835_pinctrl {
80 struct device *dev;
81 void __iomem *base;
82 int *wake_irq;
83
84 /* note: locking assumes each bank will have its own unsigned long */
85 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
86 unsigned int irq_type[BCM2711_NUM_GPIOS];
87
88 struct pinctrl_dev *pctl_dev;
89 struct gpio_chip gpio_chip;
90 struct pinctrl_desc pctl_desc;
91 struct pinctrl_gpio_range gpio_range;
92
93 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
94 /* Protect FSEL registers */
95 spinlock_t fsel_lock;
96 };
97
98 /* pins are just named GPIO0..GPIO53 */
99 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
100 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
101 BCM2835_GPIO_PIN(0),
102 BCM2835_GPIO_PIN(1),
103 BCM2835_GPIO_PIN(2),
104 BCM2835_GPIO_PIN(3),
105 BCM2835_GPIO_PIN(4),
106 BCM2835_GPIO_PIN(5),
107 BCM2835_GPIO_PIN(6),
108 BCM2835_GPIO_PIN(7),
109 BCM2835_GPIO_PIN(8),
110 BCM2835_GPIO_PIN(9),
111 BCM2835_GPIO_PIN(10),
112 BCM2835_GPIO_PIN(11),
113 BCM2835_GPIO_PIN(12),
114 BCM2835_GPIO_PIN(13),
115 BCM2835_GPIO_PIN(14),
116 BCM2835_GPIO_PIN(15),
117 BCM2835_GPIO_PIN(16),
118 BCM2835_GPIO_PIN(17),
119 BCM2835_GPIO_PIN(18),
120 BCM2835_GPIO_PIN(19),
121 BCM2835_GPIO_PIN(20),
122 BCM2835_GPIO_PIN(21),
123 BCM2835_GPIO_PIN(22),
124 BCM2835_GPIO_PIN(23),
125 BCM2835_GPIO_PIN(24),
126 BCM2835_GPIO_PIN(25),
127 BCM2835_GPIO_PIN(26),
128 BCM2835_GPIO_PIN(27),
129 BCM2835_GPIO_PIN(28),
130 BCM2835_GPIO_PIN(29),
131 BCM2835_GPIO_PIN(30),
132 BCM2835_GPIO_PIN(31),
133 BCM2835_GPIO_PIN(32),
134 BCM2835_GPIO_PIN(33),
135 BCM2835_GPIO_PIN(34),
136 BCM2835_GPIO_PIN(35),
137 BCM2835_GPIO_PIN(36),
138 BCM2835_GPIO_PIN(37),
139 BCM2835_GPIO_PIN(38),
140 BCM2835_GPIO_PIN(39),
141 BCM2835_GPIO_PIN(40),
142 BCM2835_GPIO_PIN(41),
143 BCM2835_GPIO_PIN(42),
144 BCM2835_GPIO_PIN(43),
145 BCM2835_GPIO_PIN(44),
146 BCM2835_GPIO_PIN(45),
147 BCM2835_GPIO_PIN(46),
148 BCM2835_GPIO_PIN(47),
149 BCM2835_GPIO_PIN(48),
150 BCM2835_GPIO_PIN(49),
151 BCM2835_GPIO_PIN(50),
152 BCM2835_GPIO_PIN(51),
153 BCM2835_GPIO_PIN(52),
154 BCM2835_GPIO_PIN(53),
155 BCM2835_GPIO_PIN(54),
156 BCM2835_GPIO_PIN(55),
157 BCM2835_GPIO_PIN(56),
158 BCM2835_GPIO_PIN(57),
159 };
160
161 /* one pin per group */
162 static const char * const bcm2835_gpio_groups[] = {
163 "gpio0",
164 "gpio1",
165 "gpio2",
166 "gpio3",
167 "gpio4",
168 "gpio5",
169 "gpio6",
170 "gpio7",
171 "gpio8",
172 "gpio9",
173 "gpio10",
174 "gpio11",
175 "gpio12",
176 "gpio13",
177 "gpio14",
178 "gpio15",
179 "gpio16",
180 "gpio17",
181 "gpio18",
182 "gpio19",
183 "gpio20",
184 "gpio21",
185 "gpio22",
186 "gpio23",
187 "gpio24",
188 "gpio25",
189 "gpio26",
190 "gpio27",
191 "gpio28",
192 "gpio29",
193 "gpio30",
194 "gpio31",
195 "gpio32",
196 "gpio33",
197 "gpio34",
198 "gpio35",
199 "gpio36",
200 "gpio37",
201 "gpio38",
202 "gpio39",
203 "gpio40",
204 "gpio41",
205 "gpio42",
206 "gpio43",
207 "gpio44",
208 "gpio45",
209 "gpio46",
210 "gpio47",
211 "gpio48",
212 "gpio49",
213 "gpio50",
214 "gpio51",
215 "gpio52",
216 "gpio53",
217 "gpio54",
218 "gpio55",
219 "gpio56",
220 "gpio57",
221 };
222
223 enum bcm2835_fsel {
224 BCM2835_FSEL_COUNT = 8,
225 BCM2835_FSEL_MASK = 0x7,
226 };
227
228 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
229 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
230 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
231 [BCM2835_FSEL_ALT0] = "alt0",
232 [BCM2835_FSEL_ALT1] = "alt1",
233 [BCM2835_FSEL_ALT2] = "alt2",
234 [BCM2835_FSEL_ALT3] = "alt3",
235 [BCM2835_FSEL_ALT4] = "alt4",
236 [BCM2835_FSEL_ALT5] = "alt5",
237 };
238
239 static const char * const irq_type_names[] = {
240 [IRQ_TYPE_NONE] = "none",
241 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
242 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
243 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
244 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
245 [IRQ_TYPE_LEVEL_LOW] = "level-low",
246 };
247
248 static bool persist_gpio_outputs;
249 module_param(persist_gpio_outputs, bool, 0444);
250 MODULE_PARM_DESC(persist_gpio_outputs, "Enable GPIO_OUT persistence when pin is freed");
251
bcm2835_gpio_rd(struct bcm2835_pinctrl * pc,unsigned reg)252 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
253 {
254 return readl(pc->base + reg);
255 }
256
bcm2835_gpio_wr(struct bcm2835_pinctrl * pc,unsigned reg,u32 val)257 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
258 u32 val)
259 {
260 writel(val, pc->base + reg);
261 }
262
bcm2835_gpio_get_bit(struct bcm2835_pinctrl * pc,unsigned reg,unsigned bit)263 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
264 unsigned bit)
265 {
266 reg += GPIO_REG_OFFSET(bit) * 4;
267 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
268 }
269
270 /* note NOT a read/modify/write cycle */
bcm2835_gpio_set_bit(struct bcm2835_pinctrl * pc,unsigned reg,unsigned bit)271 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
272 unsigned reg, unsigned bit)
273 {
274 reg += GPIO_REG_OFFSET(bit) * 4;
275 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
276 }
277
bcm2835_pinctrl_fsel_get(struct bcm2835_pinctrl * pc,unsigned pin)278 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
279 struct bcm2835_pinctrl *pc, unsigned pin)
280 {
281 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
282 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
283
284 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
285 bcm2835_functions[status]);
286
287 return status;
288 }
289
bcm2835_pinctrl_fsel_set(struct bcm2835_pinctrl * pc,unsigned pin,enum bcm2835_fsel fsel)290 static inline void bcm2835_pinctrl_fsel_set(
291 struct bcm2835_pinctrl *pc, unsigned pin,
292 enum bcm2835_fsel fsel)
293 {
294 u32 val;
295 enum bcm2835_fsel cur;
296 unsigned long flags;
297
298 spin_lock_irqsave(&pc->fsel_lock, flags);
299 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
300 cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
301
302 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
303 bcm2835_functions[cur]);
304
305 if (cur == fsel)
306 goto unlock;
307
308 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
309 /* always transition through GPIO_IN */
310 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
311 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
312
313 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
314 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
315 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
316 }
317
318 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
319 val |= fsel << FSEL_SHIFT(pin);
320
321 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
322 bcm2835_functions[fsel]);
323 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
324
325 unlock:
326 spin_unlock_irqrestore(&pc->fsel_lock, flags);
327 }
328
bcm2835_gpio_direction_input(struct gpio_chip * chip,unsigned offset)329 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
330 {
331 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
332
333 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
334 return 0;
335 }
336
bcm2835_gpio_get(struct gpio_chip * chip,unsigned offset)337 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
338 {
339 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
340
341 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
342 }
343
bcm2835_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)344 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
345 {
346 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
347 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
348
349 /* Alternative function doesn't clearly provide a direction */
350 if (fsel > BCM2835_FSEL_GPIO_OUT)
351 return -EINVAL;
352
353 if (fsel == BCM2835_FSEL_GPIO_IN)
354 return GPIO_LINE_DIRECTION_IN;
355
356 return GPIO_LINE_DIRECTION_OUT;
357 }
358
bcm2835_gpio_set(struct gpio_chip * chip,unsigned offset,int value)359 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
360 {
361 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
362
363 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
364 }
365
bcm2835_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)366 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
367 unsigned offset, int value)
368 {
369 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
370
371 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
372 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT);
373 return 0;
374 }
375
bcm2835_add_pin_ranges_fallback(struct gpio_chip * gc)376 static int bcm2835_add_pin_ranges_fallback(struct gpio_chip *gc)
377 {
378 struct device_node *np = dev_of_node(gc->parent);
379 struct pinctrl_dev *pctldev = of_pinctrl_get(np);
380
381 if (!pctldev)
382 return 0;
383
384 return gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0,
385 gc->ngpio);
386 }
387
388 static const struct gpio_chip bcm2835_gpio_chip = {
389 .label = MODULE_NAME,
390 .owner = THIS_MODULE,
391 .request = gpiochip_generic_request,
392 .free = gpiochip_generic_free,
393 .direction_input = bcm2835_gpio_direction_input,
394 .direction_output = bcm2835_gpio_direction_output,
395 .get_direction = bcm2835_gpio_get_direction,
396 .get = bcm2835_gpio_get,
397 .set = bcm2835_gpio_set,
398 .set_config = gpiochip_generic_config,
399 .base = -1,
400 .ngpio = BCM2835_NUM_GPIOS,
401 .can_sleep = false,
402 .add_pin_ranges = bcm2835_add_pin_ranges_fallback,
403 };
404
405 static const struct gpio_chip bcm2711_gpio_chip = {
406 .label = "pinctrl-bcm2711",
407 .owner = THIS_MODULE,
408 .request = gpiochip_generic_request,
409 .free = gpiochip_generic_free,
410 .direction_input = bcm2835_gpio_direction_input,
411 .direction_output = bcm2835_gpio_direction_output,
412 .get_direction = bcm2835_gpio_get_direction,
413 .get = bcm2835_gpio_get,
414 .set = bcm2835_gpio_set,
415 .set_config = gpiochip_generic_config,
416 .base = -1,
417 .ngpio = BCM2711_NUM_GPIOS,
418 .can_sleep = false,
419 .add_pin_ranges = bcm2835_add_pin_ranges_fallback,
420 };
421
bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl * pc,unsigned int bank,u32 mask)422 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
423 unsigned int bank, u32 mask)
424 {
425 unsigned long events;
426 unsigned offset;
427 unsigned gpio;
428
429 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
430 events &= mask;
431 events &= pc->enabled_irq_map[bank];
432 for_each_set_bit(offset, &events, 32) {
433 gpio = (32 * bank) + offset;
434 generic_handle_domain_irq(pc->gpio_chip.irq.domain,
435 gpio);
436 }
437 }
438
bcm2835_gpio_irq_handler(struct irq_desc * desc)439 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
440 {
441 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
442 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
443 struct irq_chip *host_chip = irq_desc_get_chip(desc);
444 int irq = irq_desc_get_irq(desc);
445 int group = 0;
446 int i;
447
448 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
449 if (chip->irq.parents[i] == irq) {
450 group = i;
451 break;
452 }
453 }
454 /* This should not happen, every IRQ has a bank */
455 BUG_ON(i == BCM2835_NUM_IRQS);
456
457 chained_irq_enter(host_chip, desc);
458
459 switch (group) {
460 case 0: /* IRQ0 covers GPIOs 0-27 */
461 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
462 break;
463 case 1: /* IRQ1 covers GPIOs 28-45 */
464 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
465 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
466 break;
467 case 2: /* IRQ2 covers GPIOs 46-57 */
468 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
469 break;
470 }
471
472 chained_irq_exit(host_chip, desc);
473 }
474
bcm2835_gpio_wake_irq_handler(int irq,void * dev_id)475 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
476 {
477 return IRQ_HANDLED;
478 }
479
__bcm2835_gpio_irq_config(struct bcm2835_pinctrl * pc,unsigned reg,unsigned offset,bool enable)480 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
481 unsigned reg, unsigned offset, bool enable)
482 {
483 u32 value;
484 reg += GPIO_REG_OFFSET(offset) * 4;
485 value = bcm2835_gpio_rd(pc, reg);
486 if (enable)
487 value |= BIT(GPIO_REG_SHIFT(offset));
488 else
489 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
490 bcm2835_gpio_wr(pc, reg, value);
491 }
492
493 /* fast path for IRQ handler */
bcm2835_gpio_irq_config(struct bcm2835_pinctrl * pc,unsigned offset,bool enable)494 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
495 unsigned offset, bool enable)
496 {
497 switch (pc->irq_type[offset]) {
498 case IRQ_TYPE_EDGE_RISING:
499 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
500 break;
501
502 case IRQ_TYPE_EDGE_FALLING:
503 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
504 break;
505
506 case IRQ_TYPE_EDGE_BOTH:
507 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
508 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
509 break;
510
511 case IRQ_TYPE_LEVEL_HIGH:
512 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
513 break;
514
515 case IRQ_TYPE_LEVEL_LOW:
516 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
517 break;
518 }
519 }
520
bcm2835_gpio_irq_unmask(struct irq_data * data)521 static void bcm2835_gpio_irq_unmask(struct irq_data *data)
522 {
523 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
524 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
525 unsigned gpio = irqd_to_hwirq(data);
526 unsigned offset = GPIO_REG_SHIFT(gpio);
527 unsigned bank = GPIO_REG_OFFSET(gpio);
528 unsigned long flags;
529
530 gpiochip_enable_irq(chip, gpio);
531
532 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
533 set_bit(offset, &pc->enabled_irq_map[bank]);
534 bcm2835_gpio_irq_config(pc, gpio, true);
535 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
536 }
537
bcm2835_gpio_irq_mask(struct irq_data * data)538 static void bcm2835_gpio_irq_mask(struct irq_data *data)
539 {
540 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
541 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
542 unsigned gpio = irqd_to_hwirq(data);
543 unsigned offset = GPIO_REG_SHIFT(gpio);
544 unsigned bank = GPIO_REG_OFFSET(gpio);
545 unsigned long flags;
546
547 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
548 bcm2835_gpio_irq_config(pc, gpio, false);
549 /* Clear events that were latched prior to clearing event sources */
550 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
551 clear_bit(offset, &pc->enabled_irq_map[bank]);
552 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
553
554 gpiochip_disable_irq(chip, gpio);
555 }
556
__bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl * pc,unsigned offset,unsigned int type)557 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
558 unsigned offset, unsigned int type)
559 {
560 switch (type) {
561 case IRQ_TYPE_NONE:
562 case IRQ_TYPE_EDGE_RISING:
563 case IRQ_TYPE_EDGE_FALLING:
564 case IRQ_TYPE_EDGE_BOTH:
565 case IRQ_TYPE_LEVEL_HIGH:
566 case IRQ_TYPE_LEVEL_LOW:
567 pc->irq_type[offset] = type;
568 break;
569
570 default:
571 return -EINVAL;
572 }
573 return 0;
574 }
575
576 /* slower path for reconfiguring IRQ type */
__bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl * pc,unsigned offset,unsigned int type)577 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
578 unsigned offset, unsigned int type)
579 {
580 switch (type) {
581 case IRQ_TYPE_NONE:
582 if (pc->irq_type[offset] != type) {
583 bcm2835_gpio_irq_config(pc, offset, false);
584 pc->irq_type[offset] = type;
585 }
586 break;
587
588 case IRQ_TYPE_EDGE_RISING:
589 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
590 /* RISING already enabled, disable FALLING */
591 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
592 bcm2835_gpio_irq_config(pc, offset, false);
593 pc->irq_type[offset] = type;
594 } else if (pc->irq_type[offset] != type) {
595 bcm2835_gpio_irq_config(pc, offset, false);
596 pc->irq_type[offset] = type;
597 bcm2835_gpio_irq_config(pc, offset, true);
598 }
599 break;
600
601 case IRQ_TYPE_EDGE_FALLING:
602 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
603 /* FALLING already enabled, disable RISING */
604 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
605 bcm2835_gpio_irq_config(pc, offset, false);
606 pc->irq_type[offset] = type;
607 } else if (pc->irq_type[offset] != type) {
608 bcm2835_gpio_irq_config(pc, offset, false);
609 pc->irq_type[offset] = type;
610 bcm2835_gpio_irq_config(pc, offset, true);
611 }
612 break;
613
614 case IRQ_TYPE_EDGE_BOTH:
615 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
616 /* RISING already enabled, enable FALLING too */
617 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
618 bcm2835_gpio_irq_config(pc, offset, true);
619 pc->irq_type[offset] = type;
620 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
621 /* FALLING already enabled, enable RISING too */
622 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
623 bcm2835_gpio_irq_config(pc, offset, true);
624 pc->irq_type[offset] = type;
625 } else if (pc->irq_type[offset] != type) {
626 bcm2835_gpio_irq_config(pc, offset, false);
627 pc->irq_type[offset] = type;
628 bcm2835_gpio_irq_config(pc, offset, true);
629 }
630 break;
631
632 case IRQ_TYPE_LEVEL_HIGH:
633 case IRQ_TYPE_LEVEL_LOW:
634 if (pc->irq_type[offset] != type) {
635 bcm2835_gpio_irq_config(pc, offset, false);
636 pc->irq_type[offset] = type;
637 bcm2835_gpio_irq_config(pc, offset, true);
638 }
639 break;
640
641 default:
642 return -EINVAL;
643 }
644 return 0;
645 }
646
bcm2835_gpio_irq_set_type(struct irq_data * data,unsigned int type)647 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
648 {
649 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
650 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
651 unsigned gpio = irqd_to_hwirq(data);
652 unsigned offset = GPIO_REG_SHIFT(gpio);
653 unsigned bank = GPIO_REG_OFFSET(gpio);
654 unsigned long flags;
655 int ret;
656
657 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
658
659 if (test_bit(offset, &pc->enabled_irq_map[bank]))
660 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
661 else
662 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
663
664 if (type & IRQ_TYPE_EDGE_BOTH)
665 irq_set_handler_locked(data, handle_edge_irq);
666 else
667 irq_set_handler_locked(data, handle_level_irq);
668
669 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
670
671 return ret;
672 }
673
bcm2835_gpio_irq_ack(struct irq_data * data)674 static void bcm2835_gpio_irq_ack(struct irq_data *data)
675 {
676 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
677 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
678 unsigned gpio = irqd_to_hwirq(data);
679
680 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
681 }
682
bcm2835_gpio_irq_set_wake(struct irq_data * data,unsigned int on)683 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
684 {
685 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
686 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
687 unsigned gpio = irqd_to_hwirq(data);
688 unsigned int irqgroup;
689 int ret = -EINVAL;
690
691 if (!pc->wake_irq)
692 return ret;
693
694 if (gpio <= 27)
695 irqgroup = 0;
696 else if (gpio >= 28 && gpio <= 45)
697 irqgroup = 1;
698 else if (gpio >= 46 && gpio <= 57)
699 irqgroup = 2;
700 else
701 return ret;
702
703 if (on)
704 ret = enable_irq_wake(pc->wake_irq[irqgroup]);
705 else
706 ret = disable_irq_wake(pc->wake_irq[irqgroup]);
707
708 return ret;
709 }
710
711 static const struct irq_chip bcm2835_gpio_irq_chip = {
712 .name = MODULE_NAME,
713 .irq_set_type = bcm2835_gpio_irq_set_type,
714 .irq_ack = bcm2835_gpio_irq_ack,
715 .irq_mask = bcm2835_gpio_irq_mask,
716 .irq_unmask = bcm2835_gpio_irq_unmask,
717 .irq_set_wake = bcm2835_gpio_irq_set_wake,
718 .flags = (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE),
719 GPIOCHIP_IRQ_RESOURCE_HELPERS,
720 };
721
bcm2835_pctl_get_groups_count(struct pinctrl_dev * pctldev)722 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
723 {
724 return BCM2835_NUM_GPIOS;
725 }
726
bcm2835_pctl_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)727 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
728 unsigned selector)
729 {
730 return bcm2835_gpio_groups[selector];
731 }
732
bcm2835_pctl_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * num_pins)733 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
734 unsigned selector,
735 const unsigned **pins,
736 unsigned *num_pins)
737 {
738 *pins = &bcm2835_gpio_pins[selector].number;
739 *num_pins = 1;
740
741 return 0;
742 }
743
bcm2835_pctl_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned offset)744 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
745 struct seq_file *s,
746 unsigned offset)
747 {
748 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
749 struct gpio_chip *chip = &pc->gpio_chip;
750 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
751 const char *fname = bcm2835_functions[fsel];
752 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
753 int irq = irq_find_mapping(chip->irq.domain, offset);
754
755 seq_printf(s, "function %s in %s; irq %d (%s)",
756 fname, str_hi_lo(value),
757 irq, irq_type_names[pc->irq_type[offset]]);
758 }
759
bcm2835_pctl_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * maps,unsigned num_maps)760 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
761 struct pinctrl_map *maps, unsigned num_maps)
762 {
763 int i;
764
765 for (i = 0; i < num_maps; i++)
766 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
767 kfree(maps[i].data.configs.configs);
768
769 kfree(maps);
770 }
771
bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl * pc,struct device_node * np,u32 pin,u32 fnum,struct pinctrl_map ** maps)772 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
773 struct device_node *np, u32 pin, u32 fnum,
774 struct pinctrl_map **maps)
775 {
776 struct pinctrl_map *map = *maps;
777
778 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
779 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
780 return -EINVAL;
781 }
782
783 map->type = PIN_MAP_TYPE_MUX_GROUP;
784 map->data.mux.group = bcm2835_gpio_groups[pin];
785 map->data.mux.function = bcm2835_functions[fnum];
786 (*maps)++;
787
788 return 0;
789 }
790
bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl * pc,struct device_node * np,u32 pin,u32 pull,struct pinctrl_map ** maps)791 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
792 struct device_node *np, u32 pin, u32 pull,
793 struct pinctrl_map **maps)
794 {
795 struct pinctrl_map *map = *maps;
796 unsigned long *configs;
797
798 if (pull > 2) {
799 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
800 return -EINVAL;
801 }
802
803 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
804 if (!configs)
805 return -ENOMEM;
806 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
807
808 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
809 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
810 map->data.configs.configs = configs;
811 map->data.configs.num_configs = 1;
812 (*maps)++;
813
814 return 0;
815 }
816
bcm2835_pctl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)817 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
818 struct device_node *np,
819 struct pinctrl_map **map, unsigned int *num_maps)
820 {
821 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
822 struct property *pins, *funcs, *pulls;
823 int num_pins, num_funcs, num_pulls, maps_per_pin;
824 struct pinctrl_map *maps, *cur_map;
825 int i, err;
826 u32 pin, func, pull;
827
828 /* Check for generic binding in this node */
829 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
830 if (err || *num_maps)
831 return err;
832
833 /* Generic binding did not find anything continue with legacy parse */
834 pins = of_find_property(np, "brcm,pins", NULL);
835 if (!pins) {
836 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
837 return -EINVAL;
838 }
839
840 funcs = of_find_property(np, "brcm,function", NULL);
841 pulls = of_find_property(np, "brcm,pull", NULL);
842
843 if (!funcs && !pulls) {
844 dev_err(pc->dev,
845 "%pOF: neither brcm,function nor brcm,pull specified\n",
846 np);
847 return -EINVAL;
848 }
849
850 num_pins = pins->length / 4;
851 num_funcs = funcs ? (funcs->length / 4) : 0;
852 num_pulls = pulls ? (pulls->length / 4) : 0;
853
854 if (num_funcs > 1 && num_funcs != num_pins) {
855 dev_err(pc->dev,
856 "%pOF: brcm,function must have 1 or %d entries\n",
857 np, num_pins);
858 return -EINVAL;
859 }
860
861 if (num_pulls > 1 && num_pulls != num_pins) {
862 dev_err(pc->dev,
863 "%pOF: brcm,pull must have 1 or %d entries\n",
864 np, num_pins);
865 return -EINVAL;
866 }
867
868 maps_per_pin = 0;
869 if (num_funcs)
870 maps_per_pin++;
871 if (num_pulls)
872 maps_per_pin++;
873 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
874 GFP_KERNEL);
875 if (!maps)
876 return -ENOMEM;
877
878 for (i = 0; i < num_pins; i++) {
879 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
880 if (err)
881 goto out;
882 if (pin >= pc->pctl_desc.npins) {
883 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
884 np, pin);
885 err = -EINVAL;
886 goto out;
887 }
888
889 if (num_funcs) {
890 err = of_property_read_u32_index(np, "brcm,function",
891 (num_funcs > 1) ? i : 0, &func);
892 if (err)
893 goto out;
894 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
895 func, &cur_map);
896 if (err)
897 goto out;
898 }
899 if (num_pulls) {
900 err = of_property_read_u32_index(np, "brcm,pull",
901 (num_pulls > 1) ? i : 0, &pull);
902 if (err)
903 goto out;
904 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
905 pull, &cur_map);
906 if (err)
907 goto out;
908 }
909 }
910
911 *map = maps;
912 *num_maps = num_pins * maps_per_pin;
913
914 return 0;
915
916 out:
917 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
918 return err;
919 }
920
921 static const struct pinctrl_ops bcm2835_pctl_ops = {
922 .get_groups_count = bcm2835_pctl_get_groups_count,
923 .get_group_name = bcm2835_pctl_get_group_name,
924 .get_group_pins = bcm2835_pctl_get_group_pins,
925 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
926 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
927 .dt_free_map = bcm2835_pctl_dt_free_map,
928 };
929
bcm2835_pmx_free(struct pinctrl_dev * pctldev,unsigned offset)930 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
931 unsigned offset)
932 {
933 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
934 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
935
936 if (fsel == BCM2835_FSEL_GPIO_IN)
937 return 0;
938
939 if (persist_gpio_outputs && fsel == BCM2835_FSEL_GPIO_OUT)
940 return 0;
941
942 /* disable by setting to GPIO_IN */
943 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
944 return 0;
945 }
946
bcm2835_pmx_get_functions_count(struct pinctrl_dev * pctldev)947 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
948 {
949 return BCM2835_FSEL_COUNT;
950 }
951
bcm2835_pmx_get_function_name(struct pinctrl_dev * pctldev,unsigned selector)952 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
953 unsigned selector)
954 {
955 return bcm2835_functions[selector];
956 }
957
bcm2835_pmx_get_function_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** groups,unsigned * const num_groups)958 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
959 unsigned selector,
960 const char * const **groups,
961 unsigned * const num_groups)
962 {
963 /* every pin can do every function */
964 *groups = bcm2835_gpio_groups;
965 *num_groups = BCM2835_NUM_GPIOS;
966
967 return 0;
968 }
969
bcm2835_pmx_set(struct pinctrl_dev * pctldev,unsigned func_selector,unsigned group_selector)970 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
971 unsigned func_selector,
972 unsigned group_selector)
973 {
974 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
975
976 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
977
978 return 0;
979 }
980
bcm2835_pmx_gpio_disable_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)981 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
982 struct pinctrl_gpio_range *range,
983 unsigned offset)
984 {
985 bcm2835_pmx_free(pctldev, offset);
986 }
987
bcm2835_pmx_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset,bool input)988 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
989 struct pinctrl_gpio_range *range,
990 unsigned offset,
991 bool input)
992 {
993 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
994 enum bcm2835_fsel fsel = input ?
995 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
996
997 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
998
999 return 0;
1000 }
1001
1002 static const struct pinmux_ops bcm2835_pmx_ops = {
1003 .free = bcm2835_pmx_free,
1004 .get_functions_count = bcm2835_pmx_get_functions_count,
1005 .get_function_name = bcm2835_pmx_get_function_name,
1006 .get_function_groups = bcm2835_pmx_get_function_groups,
1007 .set_mux = bcm2835_pmx_set,
1008 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
1009 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
1010 };
1011
bcm2835_pinconf_get(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * config)1012 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
1013 unsigned pin, unsigned long *config)
1014 {
1015 enum pin_config_param param = pinconf_to_config_param(*config);
1016 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1017 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, pin);
1018 u32 val;
1019
1020 /* No way to read back bias config in HW */
1021
1022 switch (param) {
1023 case PIN_CONFIG_OUTPUT:
1024 if (fsel != BCM2835_FSEL_GPIO_OUT)
1025 return -EINVAL;
1026
1027 val = bcm2835_gpio_get_bit(pc, GPLEV0, pin);
1028 *config = pinconf_to_config_packed(param, val);
1029 break;
1030
1031 default:
1032 return -ENOTSUPP;
1033 }
1034
1035 return 0;
1036 }
1037
bcm2835_pull_config_set(struct bcm2835_pinctrl * pc,unsigned int pin,unsigned int arg)1038 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
1039 unsigned int pin, unsigned int arg)
1040 {
1041 u32 off, bit;
1042
1043 off = GPIO_REG_OFFSET(pin);
1044 bit = GPIO_REG_SHIFT(pin);
1045
1046 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
1047 /*
1048 * BCM2835 datasheet say to wait 150 cycles, but not of what.
1049 * But the VideoCore firmware delay for this operation
1050 * based nearly on the same amount of VPU cycles and this clock
1051 * runs at 250 MHz.
1052 */
1053 udelay(1);
1054 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
1055 udelay(1);
1056 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
1057 }
1058
bcm2835_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)1059 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
1060 unsigned int pin, unsigned long *configs,
1061 unsigned int num_configs)
1062 {
1063 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1064 u32 param, arg;
1065 int i;
1066
1067 for (i = 0; i < num_configs; i++) {
1068 param = pinconf_to_config_param(configs[i]);
1069 arg = pinconf_to_config_argument(configs[i]);
1070
1071 switch (param) {
1072 /* Set legacy brcm,pull */
1073 case BCM2835_PINCONF_PARAM_PULL:
1074 bcm2835_pull_config_set(pc, pin, arg);
1075 break;
1076
1077 /* Set pull generic bindings */
1078 case PIN_CONFIG_BIAS_DISABLE:
1079 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1080 break;
1081
1082 case PIN_CONFIG_BIAS_PULL_DOWN:
1083 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1084 break;
1085
1086 case PIN_CONFIG_BIAS_PULL_UP:
1087 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1088 break;
1089
1090 /* Set output-high or output-low */
1091 case PIN_CONFIG_OUTPUT:
1092 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1093 break;
1094
1095 default:
1096 return -ENOTSUPP;
1097
1098 } /* switch param type */
1099 } /* for each config */
1100
1101 return 0;
1102 }
1103
1104 static const struct pinconf_ops bcm2835_pinconf_ops = {
1105 .is_generic = true,
1106 .pin_config_get = bcm2835_pinconf_get,
1107 .pin_config_set = bcm2835_pinconf_set,
1108 };
1109
bcm2711_pinconf_get(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * config)1110 static int bcm2711_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
1111 unsigned long *config)
1112 {
1113 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1114 enum pin_config_param param = pinconf_to_config_param(*config);
1115 u32 offset, shift, val;
1116
1117 offset = PUD_2711_REG_OFFSET(pin);
1118 shift = PUD_2711_REG_SHIFT(pin);
1119 val = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (offset * 4));
1120
1121 switch (param) {
1122 case PIN_CONFIG_BIAS_DISABLE:
1123 if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_NONE)
1124 return -EINVAL;
1125
1126 break;
1127
1128 case PIN_CONFIG_BIAS_PULL_UP:
1129 if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_UP)
1130 return -EINVAL;
1131
1132 *config = pinconf_to_config_packed(param, 50000);
1133 break;
1134
1135 case PIN_CONFIG_BIAS_PULL_DOWN:
1136 if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_DOWN)
1137 return -EINVAL;
1138
1139 *config = pinconf_to_config_packed(param, 50000);
1140 break;
1141
1142 default:
1143 return bcm2835_pinconf_get(pctldev, pin, config);
1144 }
1145
1146 return 0;
1147 }
1148
bcm2711_pull_config_set(struct bcm2835_pinctrl * pc,unsigned int pin,unsigned int arg)1149 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1150 unsigned int pin, unsigned int arg)
1151 {
1152 u32 shifter;
1153 u32 value;
1154 u32 off;
1155
1156 off = PUD_2711_REG_OFFSET(pin);
1157 shifter = PUD_2711_REG_SHIFT(pin);
1158
1159 value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1160 value &= ~(PUD_2711_MASK << shifter);
1161 value |= (arg << shifter);
1162 bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1163 }
1164
bcm2711_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)1165 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1166 unsigned int pin, unsigned long *configs,
1167 unsigned int num_configs)
1168 {
1169 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1170 u32 param, arg;
1171 int i;
1172
1173 for (i = 0; i < num_configs; i++) {
1174 param = pinconf_to_config_param(configs[i]);
1175 arg = pinconf_to_config_argument(configs[i]);
1176
1177 switch (param) {
1178 /* convert legacy brcm,pull */
1179 case BCM2835_PINCONF_PARAM_PULL:
1180 if (arg == BCM2835_PUD_UP)
1181 arg = BCM2711_PULL_UP;
1182 else if (arg == BCM2835_PUD_DOWN)
1183 arg = BCM2711_PULL_DOWN;
1184 else
1185 arg = BCM2711_PULL_NONE;
1186
1187 bcm2711_pull_config_set(pc, pin, arg);
1188 break;
1189
1190 /* Set pull generic bindings */
1191 case PIN_CONFIG_BIAS_DISABLE:
1192 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1193 break;
1194 case PIN_CONFIG_BIAS_PULL_DOWN:
1195 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1196 break;
1197 case PIN_CONFIG_BIAS_PULL_UP:
1198 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1199 break;
1200
1201 /* Set output-high or output-low */
1202 case PIN_CONFIG_OUTPUT:
1203 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1204 break;
1205
1206 default:
1207 return -ENOTSUPP;
1208 }
1209 } /* for each config */
1210
1211 return 0;
1212 }
1213
1214 static const struct pinconf_ops bcm2711_pinconf_ops = {
1215 .is_generic = true,
1216 .pin_config_get = bcm2711_pinconf_get,
1217 .pin_config_set = bcm2711_pinconf_set,
1218 };
1219
1220 static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1221 .name = MODULE_NAME,
1222 .pins = bcm2835_gpio_pins,
1223 .npins = BCM2835_NUM_GPIOS,
1224 .pctlops = &bcm2835_pctl_ops,
1225 .pmxops = &bcm2835_pmx_ops,
1226 .confops = &bcm2835_pinconf_ops,
1227 .owner = THIS_MODULE,
1228 };
1229
1230 static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1231 .name = "pinctrl-bcm2711",
1232 .pins = bcm2835_gpio_pins,
1233 .npins = BCM2711_NUM_GPIOS,
1234 .pctlops = &bcm2835_pctl_ops,
1235 .pmxops = &bcm2835_pmx_ops,
1236 .confops = &bcm2711_pinconf_ops,
1237 .owner = THIS_MODULE,
1238 };
1239
1240 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1241 .name = MODULE_NAME,
1242 .npins = BCM2835_NUM_GPIOS,
1243 };
1244
1245 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1246 .name = "pinctrl-bcm2711",
1247 .npins = BCM2711_NUM_GPIOS,
1248 };
1249
1250 struct bcm_plat_data {
1251 const struct gpio_chip *gpio_chip;
1252 const struct pinctrl_desc *pctl_desc;
1253 const struct pinctrl_gpio_range *gpio_range;
1254 };
1255
1256 static const struct bcm_plat_data bcm2835_plat_data = {
1257 .gpio_chip = &bcm2835_gpio_chip,
1258 .pctl_desc = &bcm2835_pinctrl_desc,
1259 .gpio_range = &bcm2835_pinctrl_gpio_range,
1260 };
1261
1262 static const struct bcm_plat_data bcm2711_plat_data = {
1263 .gpio_chip = &bcm2711_gpio_chip,
1264 .pctl_desc = &bcm2711_pinctrl_desc,
1265 .gpio_range = &bcm2711_pinctrl_gpio_range,
1266 };
1267
1268 static const struct of_device_id bcm2835_pinctrl_match[] = {
1269 {
1270 .compatible = "brcm,bcm2835-gpio",
1271 .data = &bcm2835_plat_data,
1272 },
1273 {
1274 .compatible = "brcm,bcm2711-gpio",
1275 .data = &bcm2711_plat_data,
1276 },
1277 {
1278 .compatible = "brcm,bcm7211-gpio",
1279 .data = &bcm2711_plat_data,
1280 },
1281 {}
1282 };
1283
bcm2835_pinctrl_probe(struct platform_device * pdev)1284 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1285 {
1286 struct device *dev = &pdev->dev;
1287 struct device_node *np = dev->of_node;
1288 const struct bcm_plat_data *pdata;
1289 struct bcm2835_pinctrl *pc;
1290 struct gpio_irq_chip *girq;
1291 struct resource iomem;
1292 int err, i;
1293 const struct of_device_id *match;
1294 int is_7211 = 0;
1295
1296 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1297 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1298
1299 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1300 if (!pc)
1301 return -ENOMEM;
1302
1303 platform_set_drvdata(pdev, pc);
1304 pc->dev = dev;
1305
1306 err = of_address_to_resource(np, 0, &iomem);
1307 if (err) {
1308 dev_err(dev, "could not get IO memory\n");
1309 return err;
1310 }
1311
1312 pc->base = devm_ioremap_resource(dev, &iomem);
1313 if (IS_ERR(pc->base))
1314 return PTR_ERR(pc->base);
1315
1316 match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1317 if (!match)
1318 return -EINVAL;
1319
1320 pdata = match->data;
1321 is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1322
1323 pc->gpio_chip = *pdata->gpio_chip;
1324 pc->gpio_chip.parent = dev;
1325
1326 spin_lock_init(&pc->fsel_lock);
1327 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1328 unsigned long events;
1329 unsigned offset;
1330
1331 /* clear event detection flags */
1332 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1333 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1334 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1335 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1336 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1337 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1338
1339 /* clear all the events */
1340 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1341 for_each_set_bit(offset, &events, 32)
1342 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1343
1344 raw_spin_lock_init(&pc->irq_lock[i]);
1345 }
1346
1347 pc->pctl_desc = *pdata->pctl_desc;
1348 pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1349 if (IS_ERR(pc->pctl_dev)) {
1350 gpiochip_remove(&pc->gpio_chip);
1351 return PTR_ERR(pc->pctl_dev);
1352 }
1353
1354 pc->gpio_range = *pdata->gpio_range;
1355 pc->gpio_range.base = pc->gpio_chip.base;
1356 pc->gpio_range.gc = &pc->gpio_chip;
1357 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1358
1359 girq = &pc->gpio_chip.irq;
1360 gpio_irq_chip_set_chip(girq, &bcm2835_gpio_irq_chip);
1361 girq->parent_handler = bcm2835_gpio_irq_handler;
1362 girq->num_parents = BCM2835_NUM_IRQS;
1363 girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1364 sizeof(*girq->parents),
1365 GFP_KERNEL);
1366 if (!girq->parents) {
1367 err = -ENOMEM;
1368 goto out_remove;
1369 }
1370
1371 if (is_7211) {
1372 pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1373 sizeof(*pc->wake_irq),
1374 GFP_KERNEL);
1375 if (!pc->wake_irq) {
1376 err = -ENOMEM;
1377 goto out_remove;
1378 }
1379 }
1380
1381 /*
1382 * Use the same handler for all groups: this is necessary
1383 * since we use one gpiochip to cover all lines - the
1384 * irq handler then needs to figure out which group and
1385 * bank that was firing the IRQ and look up the per-group
1386 * and bank data.
1387 */
1388 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1389 int len;
1390 char *name;
1391
1392 girq->parents[i] = irq_of_parse_and_map(np, i);
1393 if (!is_7211) {
1394 if (!girq->parents[i]) {
1395 girq->num_parents = i;
1396 break;
1397 }
1398 continue;
1399 }
1400 /* Skip over the all banks interrupts */
1401 pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1402 BCM2835_NUM_IRQS + 1);
1403
1404 len = strlen(dev_name(pc->dev)) + 16;
1405 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1406 if (!name) {
1407 err = -ENOMEM;
1408 goto out_remove;
1409 }
1410
1411 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1412
1413 /* These are optional interrupts */
1414 err = devm_request_irq(dev, pc->wake_irq[i],
1415 bcm2835_gpio_wake_irq_handler,
1416 IRQF_SHARED, name, pc);
1417 if (err)
1418 dev_warn(dev, "unable to request wake IRQ %d\n",
1419 pc->wake_irq[i]);
1420 }
1421
1422 girq->default_type = IRQ_TYPE_NONE;
1423 girq->handler = handle_level_irq;
1424
1425 err = gpiochip_add_data(&pc->gpio_chip, pc);
1426 if (err) {
1427 dev_err(dev, "could not add GPIO chip\n");
1428 goto out_remove;
1429 }
1430
1431 dev_info(dev, "GPIO_OUT persistence: %s\n",
1432 str_yes_no(persist_gpio_outputs));
1433
1434 return 0;
1435
1436 out_remove:
1437 pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
1438 return err;
1439 }
1440
1441 static struct platform_driver bcm2835_pinctrl_driver = {
1442 .probe = bcm2835_pinctrl_probe,
1443 .driver = {
1444 .name = MODULE_NAME,
1445 .of_match_table = bcm2835_pinctrl_match,
1446 .suppress_bind_attrs = true,
1447 },
1448 };
1449 module_platform_driver(bcm2835_pinctrl_driver);
1450
1451 MODULE_AUTHOR("Chris Boot");
1452 MODULE_AUTHOR("Simon Arlott");
1453 MODULE_AUTHOR("Stephen Warren");
1454 MODULE_DESCRIPTION("Broadcom BCM2835/2711 pinctrl and GPIO driver");
1455 MODULE_LICENSE("GPL");
1456