1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cherryview/Braswell pinctrl driver 4 * 5 * Copyright (C) 2014, 2020 Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * 8 * This driver is based on the original Cherryview GPIO driver by 9 * Ning Li <ning.li@intel.com> 10 * Alan Cox <alan@linux.intel.com> 11 */ 12 13 #include <linux/acpi.h> 14 #include <linux/array_size.h> 15 #include <linux/cleanup.h> 16 #include <linux/dmi.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/seq_file.h> 21 #include <linux/types.h> 22 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinmux.h> 28 29 #include "pinctrl-intel.h" 30 31 #define CHV_INTSTAT 0x300 32 #define CHV_INTMASK 0x380 33 34 #define FAMILY_PAD_REGS_OFF 0x4400 35 #define FAMILY_PAD_REGS_SIZE 0x400 36 #define MAX_FAMILY_PAD_GPIO_NO 15 37 #define GPIO_REGS_SIZE 8 38 39 #define CHV_PADCTRL0 0x000 40 #define CHV_PADCTRL0_INTSEL_SHIFT 28 41 #define CHV_PADCTRL0_INTSEL_MASK GENMASK(31, 28) 42 #define CHV_PADCTRL0_TERM_UP BIT(23) 43 #define CHV_PADCTRL0_TERM_SHIFT 20 44 #define CHV_PADCTRL0_TERM_MASK GENMASK(22, 20) 45 #define CHV_PADCTRL0_TERM_20K 1 46 #define CHV_PADCTRL0_TERM_5K 2 47 #define CHV_PADCTRL0_TERM_1K 4 48 #define CHV_PADCTRL0_PMODE_SHIFT 16 49 #define CHV_PADCTRL0_PMODE_MASK GENMASK(19, 16) 50 #define CHV_PADCTRL0_GPIOEN BIT(15) 51 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 52 #define CHV_PADCTRL0_GPIOCFG_MASK GENMASK(10, 8) 53 #define CHV_PADCTRL0_GPIOCFG_GPIO 0 54 #define CHV_PADCTRL0_GPIOCFG_GPO 1 55 #define CHV_PADCTRL0_GPIOCFG_GPI 2 56 #define CHV_PADCTRL0_GPIOCFG_HIZ 3 57 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 58 #define CHV_PADCTRL0_GPIORXSTATE BIT(0) 59 60 #define CHV_PADCTRL1 0x004 61 #define CHV_PADCTRL1_CFGLOCK BIT(31) 62 #define CHV_PADCTRL1_INVRXTX_SHIFT 4 63 #define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4) 64 #define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7) 65 #define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6) 66 #define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5) 67 #define CHV_PADCTRL1_ODEN BIT(3) 68 #define CHV_PADCTRL1_INTWAKECFG_MASK GENMASK(2, 0) 69 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 70 #define CHV_PADCTRL1_INTWAKECFG_RISING 2 71 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 72 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 73 74 struct intel_pad_context { 75 u32 padctrl0; 76 u32 padctrl1; 77 }; 78 79 #define CHV_INVALID_HWIRQ (~0U) 80 81 /** 82 * struct intel_community_context - community context for Cherryview 83 * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space) 84 * @saved_intmask: Interrupt mask saved for system sleep 85 */ 86 struct intel_community_context { 87 unsigned int intr_lines[16]; 88 u32 saved_intmask; 89 }; 90 91 #define PINMODE_INVERT_OE BIT(15) 92 93 #define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE)) 94 95 #define CHV_GPP(start, end) \ 96 { \ 97 .base = (start), \ 98 .size = (end) - (start) + 1, \ 99 } 100 101 #define CHV_COMMUNITY(g, i, a) \ 102 { \ 103 .gpps = (g), \ 104 .ngpps = ARRAY_SIZE(g), \ 105 .nirqs = (i), \ 106 .acpi_space_id = (a), \ 107 } 108 109 static const struct pinctrl_pin_desc southwest_pins[] = { 110 PINCTRL_PIN(0, "FST_SPI_D2"), 111 PINCTRL_PIN(1, "FST_SPI_D0"), 112 PINCTRL_PIN(2, "FST_SPI_CLK"), 113 PINCTRL_PIN(3, "FST_SPI_D3"), 114 PINCTRL_PIN(4, "FST_SPI_CS1_B"), 115 PINCTRL_PIN(5, "FST_SPI_D1"), 116 PINCTRL_PIN(6, "FST_SPI_CS0_B"), 117 PINCTRL_PIN(7, "FST_SPI_CS2_B"), 118 119 PINCTRL_PIN(15, "UART1_RTS_B"), 120 PINCTRL_PIN(16, "UART1_RXD"), 121 PINCTRL_PIN(17, "UART2_RXD"), 122 PINCTRL_PIN(18, "UART1_CTS_B"), 123 PINCTRL_PIN(19, "UART2_RTS_B"), 124 PINCTRL_PIN(20, "UART1_TXD"), 125 PINCTRL_PIN(21, "UART2_TXD"), 126 PINCTRL_PIN(22, "UART2_CTS_B"), 127 128 PINCTRL_PIN(30, "MF_HDA_CLK"), 129 PINCTRL_PIN(31, "MF_HDA_RSTB"), 130 PINCTRL_PIN(32, "MF_HDA_SDIO"), 131 PINCTRL_PIN(33, "MF_HDA_SDO"), 132 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 133 PINCTRL_PIN(35, "MF_HDA_SYNC"), 134 PINCTRL_PIN(36, "MF_HDA_SDI1"), 135 PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 136 137 PINCTRL_PIN(45, "I2C5_SDA"), 138 PINCTRL_PIN(46, "I2C4_SDA"), 139 PINCTRL_PIN(47, "I2C6_SDA"), 140 PINCTRL_PIN(48, "I2C5_SCL"), 141 PINCTRL_PIN(49, "I2C_NFC_SDA"), 142 PINCTRL_PIN(50, "I2C4_SCL"), 143 PINCTRL_PIN(51, "I2C6_SCL"), 144 PINCTRL_PIN(52, "I2C_NFC_SCL"), 145 146 PINCTRL_PIN(60, "I2C1_SDA"), 147 PINCTRL_PIN(61, "I2C0_SDA"), 148 PINCTRL_PIN(62, "I2C2_SDA"), 149 PINCTRL_PIN(63, "I2C1_SCL"), 150 PINCTRL_PIN(64, "I2C3_SDA"), 151 PINCTRL_PIN(65, "I2C0_SCL"), 152 PINCTRL_PIN(66, "I2C2_SCL"), 153 PINCTRL_PIN(67, "I2C3_SCL"), 154 155 PINCTRL_PIN(75, "SATA_GP0"), 156 PINCTRL_PIN(76, "SATA_GP1"), 157 PINCTRL_PIN(77, "SATA_LEDN"), 158 PINCTRL_PIN(78, "SATA_GP2"), 159 PINCTRL_PIN(79, "MF_SMB_ALERTB"), 160 PINCTRL_PIN(80, "SATA_GP3"), 161 PINCTRL_PIN(81, "MF_SMB_CLK"), 162 PINCTRL_PIN(82, "MF_SMB_DATA"), 163 164 PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 165 PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 166 PINCTRL_PIN(92, "GP_SSP_2_CLK"), 167 PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 168 PINCTRL_PIN(94, "GP_SSP_2_RXD"), 169 PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 170 PINCTRL_PIN(96, "GP_SSP_2_FS"), 171 PINCTRL_PIN(97, "GP_SSP_2_TXD"), 172 }; 173 174 static const unsigned southwest_uart0_pins[] = { 16, 20 }; 175 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 176 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 177 static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 178 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 179 static const unsigned southwest_lpe_pins[] = { 180 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 181 }; 182 static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 183 static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 184 static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 185 static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 186 static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 187 static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 188 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 189 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 190 191 /* Some of LPE I2S TXD pins need to have OE inversion set */ 192 static const unsigned int southwest_lpe_altfuncs[] = { 193 PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */ 194 PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */ 195 PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */ 196 }; 197 198 /* 199 * Two spi3 chipselects are available in different mode than the main spi3 200 * functionality, which is using mode 2. 201 */ 202 static const unsigned int southwest_spi3_altfuncs[] = { 203 PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */ 204 PINMODE(2, 0), /* 82 */ 205 }; 206 207 static const struct intel_pingroup southwest_groups[] = { 208 PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)), 209 PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)), 210 PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)), 211 PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)), 212 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)), 213 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)), 214 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)), 215 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)), 216 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)), 217 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)), 218 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)), 219 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)), 220 PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs), 221 PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs), 222 }; 223 224 static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 225 static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 226 static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 227 static const char * const southwest_hda_groups[] = { "hda_grp" }; 228 static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 229 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 230 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 231 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 232 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 233 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 234 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 235 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 236 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 237 static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 238 239 /* 240 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 241 * enabled only as GPIOs. 242 */ 243 static const struct intel_function southwest_functions[] = { 244 FUNCTION("uart0", southwest_uart0_groups), 245 FUNCTION("uart1", southwest_uart1_groups), 246 FUNCTION("uart2", southwest_uart2_groups), 247 FUNCTION("hda", southwest_hda_groups), 248 FUNCTION("lpe", southwest_lpe_groups), 249 FUNCTION("i2c0", southwest_i2c0_groups), 250 FUNCTION("i2c1", southwest_i2c1_groups), 251 FUNCTION("i2c2", southwest_i2c2_groups), 252 FUNCTION("i2c3", southwest_i2c3_groups), 253 FUNCTION("i2c4", southwest_i2c4_groups), 254 FUNCTION("i2c5", southwest_i2c5_groups), 255 FUNCTION("i2c6", southwest_i2c6_groups), 256 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 257 FUNCTION("spi3", southwest_spi3_groups), 258 }; 259 260 static const struct intel_padgroup southwest_gpps[] = { 261 CHV_GPP(0, 7), 262 CHV_GPP(15, 22), 263 CHV_GPP(30, 37), 264 CHV_GPP(45, 52), 265 CHV_GPP(60, 67), 266 CHV_GPP(75, 82), 267 CHV_GPP(90, 97), 268 }; 269 270 /* 271 * Southwest community can generate GPIO interrupts only for the first 8 272 * interrupts. The upper half (8-15) can only be used to trigger GPEs. 273 */ 274 static const struct intel_community southwest_communities[] = { 275 CHV_COMMUNITY(southwest_gpps, 8, 0x91), 276 }; 277 278 static const struct intel_pinctrl_soc_data southwest_soc_data = { 279 .uid = "1", 280 .pins = southwest_pins, 281 .npins = ARRAY_SIZE(southwest_pins), 282 .groups = southwest_groups, 283 .ngroups = ARRAY_SIZE(southwest_groups), 284 .functions = southwest_functions, 285 .nfunctions = ARRAY_SIZE(southwest_functions), 286 .communities = southwest_communities, 287 .ncommunities = ARRAY_SIZE(southwest_communities), 288 }; 289 290 static const struct pinctrl_pin_desc north_pins[] = { 291 PINCTRL_PIN(0, "GPIO_DFX_0"), 292 PINCTRL_PIN(1, "GPIO_DFX_3"), 293 PINCTRL_PIN(2, "GPIO_DFX_7"), 294 PINCTRL_PIN(3, "GPIO_DFX_1"), 295 PINCTRL_PIN(4, "GPIO_DFX_5"), 296 PINCTRL_PIN(5, "GPIO_DFX_4"), 297 PINCTRL_PIN(6, "GPIO_DFX_8"), 298 PINCTRL_PIN(7, "GPIO_DFX_2"), 299 PINCTRL_PIN(8, "GPIO_DFX_6"), 300 301 PINCTRL_PIN(15, "GPIO_SUS0"), 302 PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 303 PINCTRL_PIN(17, "GPIO_SUS3"), 304 PINCTRL_PIN(18, "GPIO_SUS7"), 305 PINCTRL_PIN(19, "GPIO_SUS1"), 306 PINCTRL_PIN(20, "GPIO_SUS5"), 307 PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 308 PINCTRL_PIN(22, "GPIO_SUS4"), 309 PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 310 PINCTRL_PIN(24, "GPIO_SUS2"), 311 PINCTRL_PIN(25, "GPIO_SUS6"), 312 PINCTRL_PIN(26, "CX_PREQ_B"), 313 PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 314 315 PINCTRL_PIN(30, "TRST_B"), 316 PINCTRL_PIN(31, "TCK"), 317 PINCTRL_PIN(32, "PROCHOT_B"), 318 PINCTRL_PIN(33, "SVIDO_DATA"), 319 PINCTRL_PIN(34, "TMS"), 320 PINCTRL_PIN(35, "CX_PRDY_B_2"), 321 PINCTRL_PIN(36, "TDO_2"), 322 PINCTRL_PIN(37, "CX_PRDY_B"), 323 PINCTRL_PIN(38, "SVIDO_ALERT_B"), 324 PINCTRL_PIN(39, "TDO"), 325 PINCTRL_PIN(40, "SVIDO_CLK"), 326 PINCTRL_PIN(41, "TDI"), 327 328 PINCTRL_PIN(45, "GP_CAMERASB_05"), 329 PINCTRL_PIN(46, "GP_CAMERASB_02"), 330 PINCTRL_PIN(47, "GP_CAMERASB_08"), 331 PINCTRL_PIN(48, "GP_CAMERASB_00"), 332 PINCTRL_PIN(49, "GP_CAMERASB_06"), 333 PINCTRL_PIN(50, "GP_CAMERASB_10"), 334 PINCTRL_PIN(51, "GP_CAMERASB_03"), 335 PINCTRL_PIN(52, "GP_CAMERASB_09"), 336 PINCTRL_PIN(53, "GP_CAMERASB_01"), 337 PINCTRL_PIN(54, "GP_CAMERASB_07"), 338 PINCTRL_PIN(55, "GP_CAMERASB_11"), 339 PINCTRL_PIN(56, "GP_CAMERASB_04"), 340 341 PINCTRL_PIN(60, "PANEL0_BKLTEN"), 342 PINCTRL_PIN(61, "HV_DDI0_HPD"), 343 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 344 PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 345 PINCTRL_PIN(64, "HV_DDI1_HPD"), 346 PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 347 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 348 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 349 PINCTRL_PIN(68, "HV_DDI2_HPD"), 350 PINCTRL_PIN(69, "PANEL1_VDDEN"), 351 PINCTRL_PIN(70, "PANEL1_BKLTEN"), 352 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 353 PINCTRL_PIN(72, "PANEL0_VDDEN"), 354 }; 355 356 static const struct intel_padgroup north_gpps[] = { 357 CHV_GPP(0, 8), 358 CHV_GPP(15, 27), 359 CHV_GPP(30, 41), 360 CHV_GPP(45, 56), 361 CHV_GPP(60, 72), 362 }; 363 364 /* 365 * North community can generate GPIO interrupts only for the first 8 366 * interrupts. The upper half (8-15) can only be used to trigger GPEs. 367 */ 368 static const struct intel_community north_communities[] = { 369 CHV_COMMUNITY(north_gpps, 8, 0x92), 370 }; 371 372 static const struct intel_pinctrl_soc_data north_soc_data = { 373 .uid = "2", 374 .pins = north_pins, 375 .npins = ARRAY_SIZE(north_pins), 376 .communities = north_communities, 377 .ncommunities = ARRAY_SIZE(north_communities), 378 }; 379 380 static const struct pinctrl_pin_desc east_pins[] = { 381 PINCTRL_PIN(0, "PMU_SLP_S3_B"), 382 PINCTRL_PIN(1, "PMU_BATLOW_B"), 383 PINCTRL_PIN(2, "SUS_STAT_B"), 384 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 385 PINCTRL_PIN(4, "PMU_AC_PRESENT"), 386 PINCTRL_PIN(5, "PMU_PLTRST_B"), 387 PINCTRL_PIN(6, "PMU_SUSCLK"), 388 PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 389 PINCTRL_PIN(8, "PMU_PWRBTN_B"), 390 PINCTRL_PIN(9, "PMU_SLP_S4_B"), 391 PINCTRL_PIN(10, "PMU_WAKE_B"), 392 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 393 394 PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 395 PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 396 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 397 PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 398 PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 399 PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 400 PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 401 PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 402 PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 403 PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 404 PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 405 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 406 }; 407 408 static const struct intel_padgroup east_gpps[] = { 409 CHV_GPP(0, 11), 410 CHV_GPP(15, 26), 411 }; 412 413 static const struct intel_community east_communities[] = { 414 CHV_COMMUNITY(east_gpps, 16, 0x93), 415 }; 416 417 static const struct intel_pinctrl_soc_data east_soc_data = { 418 .uid = "3", 419 .pins = east_pins, 420 .npins = ARRAY_SIZE(east_pins), 421 .communities = east_communities, 422 .ncommunities = ARRAY_SIZE(east_communities), 423 }; 424 425 static const struct pinctrl_pin_desc southeast_pins[] = { 426 PINCTRL_PIN(0, "MF_PLT_CLK0"), 427 PINCTRL_PIN(1, "PWM1"), 428 PINCTRL_PIN(2, "MF_PLT_CLK1"), 429 PINCTRL_PIN(3, "MF_PLT_CLK4"), 430 PINCTRL_PIN(4, "MF_PLT_CLK3"), 431 PINCTRL_PIN(5, "PWM0"), 432 PINCTRL_PIN(6, "MF_PLT_CLK5"), 433 PINCTRL_PIN(7, "MF_PLT_CLK2"), 434 435 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 436 PINCTRL_PIN(16, "SDMMC1_CLK"), 437 PINCTRL_PIN(17, "SDMMC1_D0"), 438 PINCTRL_PIN(18, "SDMMC2_D1"), 439 PINCTRL_PIN(19, "SDMMC2_CLK"), 440 PINCTRL_PIN(20, "SDMMC1_D2"), 441 PINCTRL_PIN(21, "SDMMC2_D2"), 442 PINCTRL_PIN(22, "SDMMC2_CMD"), 443 PINCTRL_PIN(23, "SDMMC1_CMD"), 444 PINCTRL_PIN(24, "SDMMC1_D1"), 445 PINCTRL_PIN(25, "SDMMC2_D0"), 446 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 447 448 PINCTRL_PIN(30, "SDMMC3_D1"), 449 PINCTRL_PIN(31, "SDMMC3_CLK"), 450 PINCTRL_PIN(32, "SDMMC3_D3"), 451 PINCTRL_PIN(33, "SDMMC3_D2"), 452 PINCTRL_PIN(34, "SDMMC3_CMD"), 453 PINCTRL_PIN(35, "SDMMC3_D0"), 454 455 PINCTRL_PIN(45, "MF_LPC_AD2"), 456 PINCTRL_PIN(46, "LPC_CLKRUNB"), 457 PINCTRL_PIN(47, "MF_LPC_AD0"), 458 PINCTRL_PIN(48, "LPC_FRAMEB"), 459 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 460 PINCTRL_PIN(50, "MF_LPC_AD3"), 461 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 462 PINCTRL_PIN(52, "MF_LPC_AD1"), 463 464 PINCTRL_PIN(60, "SPI1_MISO"), 465 PINCTRL_PIN(61, "SPI1_CSO_B"), 466 PINCTRL_PIN(62, "SPI1_CLK"), 467 PINCTRL_PIN(63, "MMC1_D6"), 468 PINCTRL_PIN(64, "SPI1_MOSI"), 469 PINCTRL_PIN(65, "MMC1_D5"), 470 PINCTRL_PIN(66, "SPI1_CS1_B"), 471 PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 472 PINCTRL_PIN(68, "MMC1_D7"), 473 PINCTRL_PIN(69, "MMC1_RCLK"), 474 475 PINCTRL_PIN(75, "USB_OC1_B"), 476 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 477 PINCTRL_PIN(77, "GPIO_ALERT"), 478 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 479 PINCTRL_PIN(79, "ILB_SERIRQ"), 480 PINCTRL_PIN(80, "USB_OC0_B"), 481 PINCTRL_PIN(81, "SDMMC3_CD_B"), 482 PINCTRL_PIN(82, "SPKR"), 483 PINCTRL_PIN(83, "SUSPWRDNACK"), 484 PINCTRL_PIN(84, "SPARE_PIN"), 485 PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 486 }; 487 488 static const unsigned southeast_pwm0_pins[] = { 5 }; 489 static const unsigned southeast_pwm1_pins[] = { 1 }; 490 static const unsigned southeast_sdmmc1_pins[] = { 491 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 492 }; 493 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 494 static const unsigned southeast_sdmmc3_pins[] = { 495 30, 31, 32, 33, 34, 35, 78, 81, 85, 496 }; 497 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 498 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 499 500 static const struct intel_pingroup southeast_groups[] = { 501 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)), 502 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)), 503 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)), 504 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)), 505 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)), 506 PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)), 507 PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)), 508 }; 509 510 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 511 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 512 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 513 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 514 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 515 static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 516 static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 517 518 static const struct intel_function southeast_functions[] = { 519 FUNCTION("pwm0", southeast_pwm0_groups), 520 FUNCTION("pwm1", southeast_pwm1_groups), 521 FUNCTION("sdmmc1", southeast_sdmmc1_groups), 522 FUNCTION("sdmmc2", southeast_sdmmc2_groups), 523 FUNCTION("sdmmc3", southeast_sdmmc3_groups), 524 FUNCTION("spi1", southeast_spi1_groups), 525 FUNCTION("spi2", southeast_spi2_groups), 526 }; 527 528 static const struct intel_padgroup southeast_gpps[] = { 529 CHV_GPP(0, 7), 530 CHV_GPP(15, 26), 531 CHV_GPP(30, 35), 532 CHV_GPP(45, 52), 533 CHV_GPP(60, 69), 534 CHV_GPP(75, 85), 535 }; 536 537 static const struct intel_community southeast_communities[] = { 538 CHV_COMMUNITY(southeast_gpps, 16, 0x94), 539 }; 540 541 static const struct intel_pinctrl_soc_data southeast_soc_data = { 542 .uid = "4", 543 .pins = southeast_pins, 544 .npins = ARRAY_SIZE(southeast_pins), 545 .groups = southeast_groups, 546 .ngroups = ARRAY_SIZE(southeast_groups), 547 .functions = southeast_functions, 548 .nfunctions = ARRAY_SIZE(southeast_functions), 549 .communities = southeast_communities, 550 .ncommunities = ARRAY_SIZE(southeast_communities), 551 }; 552 553 static const struct intel_pinctrl_soc_data *chv_soc_data[] = { 554 &southwest_soc_data, 555 &north_soc_data, 556 &east_soc_data, 557 &southeast_soc_data, 558 NULL 559 }; 560 561 /* 562 * Lock to serialize register accesses 563 * 564 * Due to a silicon issue, a shared lock must be used to prevent 565 * concurrent accesses across the 4 GPIO controllers. 566 * 567 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), 568 * errata #CHT34, for further information. 569 */ 570 static DEFINE_RAW_SPINLOCK(chv_lock); 571 572 static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset) 573 { 574 const struct intel_community *community = &pctrl->communities[0]; 575 576 return readl(community->regs + offset); 577 } 578 579 static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value) 580 { 581 const struct intel_community *community = &pctrl->communities[0]; 582 void __iomem *reg = community->regs + offset; 583 584 /* Write and simple read back to confirm the bus transferring done */ 585 writel(value, reg); 586 readl(reg); 587 } 588 589 static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset, 590 unsigned int reg) 591 { 592 const struct intel_community *community = &pctrl->communities[0]; 593 unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 594 unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 595 596 offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no; 597 598 return community->pad_regs + offset + reg; 599 } 600 601 static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset) 602 { 603 return readl(chv_padreg(pctrl, pin, offset)); 604 } 605 606 static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value) 607 { 608 void __iomem *reg = chv_padreg(pctrl, pin, offset); 609 610 /* Write and simple read back to confirm the bus transferring done */ 611 writel(value, reg); 612 readl(reg); 613 } 614 615 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 616 static bool chv_pad_is_locked(u32 ctrl1) 617 { 618 return ctrl1 & CHV_PADCTRL1_CFGLOCK; 619 } 620 621 static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset) 622 { 623 return chv_pad_is_locked(chv_readl(pctrl, offset, CHV_PADCTRL1)); 624 } 625 626 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 627 unsigned int offset) 628 { 629 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 630 u32 ctrl0, ctrl1; 631 632 scoped_guard(raw_spinlock_irqsave, &chv_lock) { 633 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 634 ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1); 635 } 636 637 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 638 seq_puts(s, "GPIO "); 639 } else { 640 u32 mode; 641 642 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 643 mode >>= CHV_PADCTRL0_PMODE_SHIFT; 644 645 seq_printf(s, "mode %d ", mode); 646 } 647 648 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); 649 650 if (chv_pad_is_locked(ctrl1)) 651 seq_puts(s, " [LOCKED]"); 652 } 653 654 static const struct pinctrl_ops chv_pinctrl_ops = { 655 .get_groups_count = intel_get_groups_count, 656 .get_group_name = intel_get_group_name, 657 .get_group_pins = intel_get_group_pins, 658 .pin_dbg_show = chv_pin_dbg_show, 659 }; 660 661 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, 662 unsigned int function, unsigned int group) 663 { 664 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 665 struct device *dev = pctrl->dev; 666 const struct intel_pingroup *grp; 667 int i; 668 669 grp = &pctrl->soc->groups[group]; 670 671 guard(raw_spinlock_irqsave)(&chv_lock); 672 673 /* Check first that the pad is not locked */ 674 for (i = 0; i < grp->grp.npins; i++) { 675 if (chv_pad_locked(pctrl, grp->grp.pins[i])) { 676 dev_warn(dev, "unable to set mode for locked pin %u\n", grp->grp.pins[i]); 677 return -EBUSY; 678 } 679 } 680 681 for (i = 0; i < grp->grp.npins; i++) { 682 int pin = grp->grp.pins[i]; 683 unsigned int mode; 684 bool invert_oe; 685 u32 value; 686 687 /* Check if there is pin-specific config */ 688 if (grp->modes) 689 mode = grp->modes[i]; 690 else 691 mode = grp->mode; 692 693 /* Extract OE inversion */ 694 invert_oe = mode & PINMODE_INVERT_OE; 695 mode &= ~PINMODE_INVERT_OE; 696 697 value = chv_readl(pctrl, pin, CHV_PADCTRL0); 698 /* Disable GPIO mode */ 699 value &= ~CHV_PADCTRL0_GPIOEN; 700 /* Set to desired mode */ 701 value &= ~CHV_PADCTRL0_PMODE_MASK; 702 value |= mode << CHV_PADCTRL0_PMODE_SHIFT; 703 chv_writel(pctrl, pin, CHV_PADCTRL0, value); 704 705 /* Update for invert_oe */ 706 value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK; 707 if (invert_oe) 708 value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 709 chv_writel(pctrl, pin, CHV_PADCTRL1, value); 710 711 dev_dbg(dev, "configured pin %u mode %u OE %sinverted\n", pin, mode, 712 invert_oe ? "" : "not "); 713 } 714 715 return 0; 716 } 717 718 static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl, 719 unsigned int offset) 720 { 721 u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK; 722 u32 value; 723 724 /* 725 * One some devices the GPIO should output the inverted value from what 726 * device-drivers / ACPI code expects (inverted external buffer?). The 727 * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag, 728 * preserve this flag if the pin is already setup as GPIO. 729 */ 730 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 731 if (value & CHV_PADCTRL0_GPIOEN) 732 invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA; 733 734 value = chv_readl(pctrl, offset, CHV_PADCTRL1); 735 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 736 value &= ~invrxtx_mask; 737 chv_writel(pctrl, offset, CHV_PADCTRL1, value); 738 } 739 740 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 741 struct pinctrl_gpio_range *range, 742 unsigned int offset) 743 { 744 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 745 u32 value; 746 747 guard(raw_spinlock_irqsave)(&chv_lock); 748 749 if (chv_pad_locked(pctrl, offset)) { 750 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 751 if (!(value & CHV_PADCTRL0_GPIOEN)) { 752 /* Locked so cannot enable */ 753 return -EBUSY; 754 } 755 } else { 756 struct intel_community_context *cctx = &pctrl->context.communities[0]; 757 int i; 758 759 /* Reset the interrupt mapping */ 760 for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) { 761 if (cctx->intr_lines[i] == offset) { 762 cctx->intr_lines[i] = CHV_INVALID_HWIRQ; 763 break; 764 } 765 } 766 767 /* Disable interrupt generation */ 768 chv_gpio_clear_triggering(pctrl, offset); 769 770 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 771 772 /* 773 * If the pin is in HiZ mode (both TX and RX buffers are 774 * disabled) we turn it to be input now. 775 */ 776 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 777 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 778 value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 779 value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 780 } 781 782 /* Switch to a GPIO mode */ 783 value |= CHV_PADCTRL0_GPIOEN; 784 chv_writel(pctrl, offset, CHV_PADCTRL0, value); 785 } 786 787 return 0; 788 } 789 790 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 791 struct pinctrl_gpio_range *range, 792 unsigned int offset) 793 { 794 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 795 796 guard(raw_spinlock_irqsave)(&chv_lock); 797 798 if (chv_pad_locked(pctrl, offset)) 799 return; 800 801 chv_gpio_clear_triggering(pctrl, offset); 802 } 803 804 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 805 struct pinctrl_gpio_range *range, 806 unsigned int offset, bool input) 807 { 808 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 809 u32 ctrl0; 810 811 guard(raw_spinlock_irqsave)(&chv_lock); 812 813 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK; 814 if (input) 815 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 816 else 817 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 818 chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0); 819 820 return 0; 821 } 822 823 static const struct pinmux_ops chv_pinmux_ops = { 824 .get_functions_count = intel_get_functions_count, 825 .get_function_name = intel_get_function_name, 826 .get_function_groups = intel_get_function_groups, 827 .set_mux = chv_pinmux_set_mux, 828 .gpio_request_enable = chv_gpio_request_enable, 829 .gpio_disable_free = chv_gpio_disable_free, 830 .gpio_set_direction = chv_gpio_set_direction, 831 }; 832 833 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 834 unsigned long *config) 835 { 836 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 837 enum pin_config_param param = pinconf_to_config_param(*config); 838 u32 ctrl0, ctrl1; 839 u16 arg = 0; 840 u32 term; 841 842 scoped_guard(raw_spinlock_irqsave, &chv_lock) { 843 ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0); 844 ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1); 845 } 846 847 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 848 849 switch (param) { 850 case PIN_CONFIG_BIAS_DISABLE: 851 if (term) 852 return -EINVAL; 853 break; 854 855 case PIN_CONFIG_BIAS_PULL_UP: 856 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 857 return -EINVAL; 858 859 switch (term) { 860 case CHV_PADCTRL0_TERM_20K: 861 arg = 20000; 862 break; 863 case CHV_PADCTRL0_TERM_5K: 864 arg = 5000; 865 break; 866 case CHV_PADCTRL0_TERM_1K: 867 arg = 1000; 868 break; 869 } 870 871 break; 872 873 case PIN_CONFIG_BIAS_PULL_DOWN: 874 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 875 return -EINVAL; 876 877 switch (term) { 878 case CHV_PADCTRL0_TERM_20K: 879 arg = 20000; 880 break; 881 case CHV_PADCTRL0_TERM_5K: 882 arg = 5000; 883 break; 884 } 885 886 break; 887 888 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 889 u32 cfg; 890 891 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 892 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 893 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 894 return -EINVAL; 895 896 break; 897 } 898 899 case PIN_CONFIG_DRIVE_PUSH_PULL: 900 if (ctrl1 & CHV_PADCTRL1_ODEN) 901 return -EINVAL; 902 break; 903 904 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 905 if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 906 return -EINVAL; 907 break; 908 909 default: 910 return -ENOTSUPP; 911 } 912 913 *config = pinconf_to_config_packed(param, arg); 914 return 0; 915 } 916 917 static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 918 enum pin_config_param param, u32 arg) 919 { 920 u32 ctrl0, pull; 921 922 guard(raw_spinlock_irqsave)(&chv_lock); 923 924 ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0); 925 926 switch (param) { 927 case PIN_CONFIG_BIAS_DISABLE: 928 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 929 break; 930 931 case PIN_CONFIG_BIAS_PULL_UP: 932 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 933 934 switch (arg) { 935 case 1000: 936 /* For 1k there is only pull up */ 937 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 938 break; 939 case 5000: 940 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 941 break; 942 case 20000: 943 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 944 break; 945 default: 946 return -EINVAL; 947 } 948 949 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 950 break; 951 952 case PIN_CONFIG_BIAS_PULL_DOWN: 953 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 954 955 switch (arg) { 956 case 5000: 957 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 958 break; 959 case 20000: 960 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 961 break; 962 default: 963 return -EINVAL; 964 } 965 966 ctrl0 |= pull; 967 break; 968 969 default: 970 return -EINVAL; 971 } 972 973 chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0); 974 975 return 0; 976 } 977 978 static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin, 979 bool enable) 980 { 981 u32 ctrl1; 982 983 guard(raw_spinlock_irqsave)(&chv_lock); 984 985 ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1); 986 987 if (enable) 988 ctrl1 |= CHV_PADCTRL1_ODEN; 989 else 990 ctrl1 &= ~CHV_PADCTRL1_ODEN; 991 992 chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1); 993 994 return 0; 995 } 996 997 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 998 unsigned long *configs, unsigned int nconfigs) 999 { 1000 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1001 struct device *dev = pctrl->dev; 1002 enum pin_config_param param; 1003 int i, ret; 1004 u32 arg; 1005 1006 if (chv_pad_locked(pctrl, pin)) 1007 return -EBUSY; 1008 1009 for (i = 0; i < nconfigs; i++) { 1010 param = pinconf_to_config_param(configs[i]); 1011 arg = pinconf_to_config_argument(configs[i]); 1012 1013 switch (param) { 1014 case PIN_CONFIG_BIAS_DISABLE: 1015 case PIN_CONFIG_BIAS_PULL_UP: 1016 case PIN_CONFIG_BIAS_PULL_DOWN: 1017 ret = chv_config_set_pull(pctrl, pin, param, arg); 1018 if (ret) 1019 return ret; 1020 break; 1021 1022 case PIN_CONFIG_DRIVE_PUSH_PULL: 1023 ret = chv_config_set_oden(pctrl, pin, false); 1024 if (ret) 1025 return ret; 1026 break; 1027 1028 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1029 ret = chv_config_set_oden(pctrl, pin, true); 1030 if (ret) 1031 return ret; 1032 break; 1033 1034 default: 1035 return -ENOTSUPP; 1036 } 1037 1038 dev_dbg(dev, "pin %d set config %d arg %u\n", pin, param, arg); 1039 } 1040 1041 return 0; 1042 } 1043 1044 static int chv_config_group_get(struct pinctrl_dev *pctldev, 1045 unsigned int group, 1046 unsigned long *config) 1047 { 1048 const unsigned int *pins; 1049 unsigned int npins; 1050 int ret; 1051 1052 ret = intel_get_group_pins(pctldev, group, &pins, &npins); 1053 if (ret) 1054 return ret; 1055 1056 ret = chv_config_get(pctldev, pins[0], config); 1057 if (ret) 1058 return ret; 1059 1060 return 0; 1061 } 1062 1063 static int chv_config_group_set(struct pinctrl_dev *pctldev, 1064 unsigned int group, unsigned long *configs, 1065 unsigned int num_configs) 1066 { 1067 const unsigned int *pins; 1068 unsigned int npins; 1069 int i, ret; 1070 1071 ret = intel_get_group_pins(pctldev, group, &pins, &npins); 1072 if (ret) 1073 return ret; 1074 1075 for (i = 0; i < npins; i++) { 1076 ret = chv_config_set(pctldev, pins[i], configs, num_configs); 1077 if (ret) 1078 return ret; 1079 } 1080 1081 return 0; 1082 } 1083 1084 static const struct pinconf_ops chv_pinconf_ops = { 1085 .is_generic = true, 1086 .pin_config_set = chv_config_set, 1087 .pin_config_get = chv_config_get, 1088 .pin_config_group_get = chv_config_group_get, 1089 .pin_config_group_set = chv_config_group_set, 1090 }; 1091 1092 static struct pinctrl_desc chv_pinctrl_desc = { 1093 .pctlops = &chv_pinctrl_ops, 1094 .pmxops = &chv_pinmux_ops, 1095 .confops = &chv_pinconf_ops, 1096 .owner = THIS_MODULE, 1097 }; 1098 1099 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset) 1100 { 1101 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1102 u32 ctrl0, cfg; 1103 1104 scoped_guard(raw_spinlock_irqsave, &chv_lock) 1105 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1106 1107 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1108 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1109 1110 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 1111 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 1112 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 1113 } 1114 1115 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1116 { 1117 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1118 u32 ctrl0; 1119 1120 guard(raw_spinlock_irqsave)(&chv_lock); 1121 1122 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1123 1124 if (value) 1125 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 1126 else 1127 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 1128 1129 chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0); 1130 } 1131 1132 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1133 { 1134 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1135 u32 ctrl0, direction; 1136 1137 scoped_guard(raw_spinlock_irqsave, &chv_lock) 1138 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1139 1140 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1141 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1142 1143 if (direction == CHV_PADCTRL0_GPIOCFG_GPO) 1144 return GPIO_LINE_DIRECTION_OUT; 1145 1146 return GPIO_LINE_DIRECTION_IN; 1147 } 1148 1149 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1150 { 1151 return pinctrl_gpio_direction_input(chip, offset); 1152 } 1153 1154 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 1155 int value) 1156 { 1157 chv_gpio_set(chip, offset, value); 1158 return pinctrl_gpio_direction_output(chip, offset); 1159 } 1160 1161 static const struct gpio_chip chv_gpio_chip = { 1162 .owner = THIS_MODULE, 1163 .request = gpiochip_generic_request, 1164 .free = gpiochip_generic_free, 1165 .get_direction = chv_gpio_get_direction, 1166 .direction_input = chv_gpio_direction_input, 1167 .direction_output = chv_gpio_direction_output, 1168 .get = chv_gpio_get, 1169 .set = chv_gpio_set, 1170 }; 1171 1172 static void chv_gpio_irq_ack(struct irq_data *d) 1173 { 1174 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1175 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1176 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1177 u32 intr_line; 1178 1179 guard(raw_spinlock)(&chv_lock); 1180 1181 intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0); 1182 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1183 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1184 chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line)); 1185 } 1186 1187 static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) 1188 { 1189 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1190 u32 value, intr_line; 1191 1192 guard(raw_spinlock_irqsave)(&chv_lock); 1193 1194 intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0); 1195 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1196 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1197 1198 value = chv_pctrl_readl(pctrl, CHV_INTMASK); 1199 if (mask) 1200 value &= ~BIT(intr_line); 1201 else 1202 value |= BIT(intr_line); 1203 chv_pctrl_writel(pctrl, CHV_INTMASK, value); 1204 } 1205 1206 static void chv_gpio_irq_mask(struct irq_data *d) 1207 { 1208 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1209 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1210 1211 chv_gpio_irq_mask_unmask(gc, hwirq, true); 1212 gpiochip_disable_irq(gc, hwirq); 1213 } 1214 1215 static void chv_gpio_irq_unmask(struct irq_data *d) 1216 { 1217 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1218 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1219 1220 gpiochip_enable_irq(gc, hwirq); 1221 chv_gpio_irq_mask_unmask(gc, hwirq, false); 1222 } 1223 1224 static unsigned chv_gpio_irq_startup(struct irq_data *d) 1225 { 1226 /* 1227 * Check if the interrupt has been requested with 0 as triggering 1228 * type. If not, bail out, ... 1229 */ 1230 if (irqd_get_trigger_type(d) != IRQ_TYPE_NONE) { 1231 chv_gpio_irq_unmask(d); 1232 return 0; 1233 } 1234 1235 /* 1236 * ...otherwise it is assumed that the current values 1237 * programmed to the hardware are used (e.g BIOS configured 1238 * defaults). 1239 * 1240 * In that case ->irq_set_type() will never be called so we need to 1241 * read back the values from hardware now, set correct flow handler 1242 * and update mappings before the interrupt is being used. 1243 */ 1244 scoped_guard(raw_spinlock_irqsave, &chv_lock) { 1245 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1246 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1247 struct device *dev = pctrl->dev; 1248 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1249 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1250 irq_flow_handler_t handler; 1251 u32 intsel, value; 1252 1253 intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0); 1254 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1255 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1256 1257 value = chv_readl(pctrl, hwirq, CHV_PADCTRL1); 1258 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1259 handler = handle_level_irq; 1260 else 1261 handler = handle_edge_irq; 1262 1263 if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { 1264 irq_set_handler_locked(d, handler); 1265 dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %lu\n", 1266 intsel, hwirq); 1267 cctx->intr_lines[intsel] = hwirq; 1268 } 1269 } 1270 1271 chv_gpio_irq_unmask(d); 1272 return 0; 1273 } 1274 1275 static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin) 1276 { 1277 struct device *dev = pctrl->dev; 1278 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1279 const struct intel_community *community = &pctrl->communities[0]; 1280 u32 value, intsel; 1281 int i; 1282 1283 value = chv_readl(pctrl, pin, CHV_PADCTRL0); 1284 intsel = (value & CHV_PADCTRL0_INTSEL_MASK) >> CHV_PADCTRL0_INTSEL_SHIFT; 1285 1286 if (cctx->intr_lines[intsel] == pin) 1287 return 0; 1288 1289 if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { 1290 dev_dbg(dev, "using interrupt line %u for pin %u\n", intsel, pin); 1291 cctx->intr_lines[intsel] = pin; 1292 return 0; 1293 } 1294 1295 /* 1296 * The interrupt line selected by the BIOS is already in use by 1297 * another pin, this is a known BIOS bug found on several models. 1298 * But this may also be caused by Linux deciding to use a pin as 1299 * IRQ which was not expected to be used as such by the BIOS authors, 1300 * so log this at info level only. 1301 */ 1302 dev_info(dev, "interrupt line %u is used by both pin %u and pin %u\n", intsel, 1303 cctx->intr_lines[intsel], pin); 1304 1305 if (chv_pad_locked(pctrl, pin)) 1306 return -EBUSY; 1307 1308 /* 1309 * The BIOS fills the interrupt lines from 0 counting up, start at 1310 * the other end to find a free interrupt line to workaround this. 1311 */ 1312 for (i = community->nirqs - 1; i >= 0; i--) { 1313 if (cctx->intr_lines[i] == CHV_INVALID_HWIRQ) 1314 break; 1315 } 1316 if (i < 0) 1317 return -EBUSY; 1318 1319 dev_info(dev, "changing the interrupt line for pin %u to %d\n", pin, i); 1320 1321 value = (value & ~CHV_PADCTRL0_INTSEL_MASK) | (i << CHV_PADCTRL0_INTSEL_SHIFT); 1322 chv_writel(pctrl, pin, CHV_PADCTRL0, value); 1323 cctx->intr_lines[i] = pin; 1324 1325 return 0; 1326 } 1327 1328 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) 1329 { 1330 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1331 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1332 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1333 u32 value; 1334 int ret; 1335 1336 guard(raw_spinlock_irqsave)(&chv_lock); 1337 1338 ret = chv_gpio_set_intr_line(pctrl, hwirq); 1339 if (ret) 1340 return ret; 1341 1342 /* 1343 * Pins which can be used as shared interrupt are configured in 1344 * BIOS. Driver trusts BIOS configurations and assigns different 1345 * handler according to the irq type. 1346 * 1347 * Driver needs to save the mapping between each pin and 1348 * its interrupt line. 1349 * 1. If the pin cfg is locked in BIOS: 1350 * Trust BIOS has programmed IntWakeCfg bits correctly, 1351 * driver just needs to save the mapping. 1352 * 2. If the pin cfg is not locked in BIOS: 1353 * Driver programs the IntWakeCfg bits and save the mapping. 1354 */ 1355 if (!chv_pad_locked(pctrl, hwirq)) { 1356 value = chv_readl(pctrl, hwirq, CHV_PADCTRL1); 1357 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 1358 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 1359 1360 if (type & IRQ_TYPE_EDGE_BOTH) { 1361 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1362 value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 1363 else if (type & IRQ_TYPE_EDGE_RISING) 1364 value |= CHV_PADCTRL1_INTWAKECFG_RISING; 1365 else if (type & IRQ_TYPE_EDGE_FALLING) 1366 value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 1367 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1368 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 1369 if (type & IRQ_TYPE_LEVEL_LOW) 1370 value |= CHV_PADCTRL1_INVRXTX_RXDATA; 1371 } 1372 1373 chv_writel(pctrl, hwirq, CHV_PADCTRL1, value); 1374 } 1375 1376 if (type & IRQ_TYPE_EDGE_BOTH) 1377 irq_set_handler_locked(d, handle_edge_irq); 1378 else if (type & IRQ_TYPE_LEVEL_MASK) 1379 irq_set_handler_locked(d, handle_level_irq); 1380 1381 return 0; 1382 } 1383 1384 static const struct irq_chip chv_gpio_irq_chip = { 1385 .name = "chv-gpio", 1386 .irq_startup = chv_gpio_irq_startup, 1387 .irq_ack = chv_gpio_irq_ack, 1388 .irq_mask = chv_gpio_irq_mask, 1389 .irq_unmask = chv_gpio_irq_unmask, 1390 .irq_set_type = chv_gpio_irq_type, 1391 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 1392 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1393 }; 1394 1395 static void chv_gpio_irq_handler(struct irq_desc *desc) 1396 { 1397 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1398 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1399 struct device *dev = pctrl->dev; 1400 const struct intel_community *community = &pctrl->communities[0]; 1401 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1402 struct irq_chip *chip = irq_desc_get_chip(desc); 1403 unsigned long pending; 1404 u32 intr_line; 1405 1406 chained_irq_enter(chip, desc); 1407 1408 scoped_guard(raw_spinlock_irqsave, &chv_lock) 1409 pending = chv_pctrl_readl(pctrl, CHV_INTSTAT); 1410 1411 for_each_set_bit(intr_line, &pending, community->nirqs) { 1412 unsigned int offset; 1413 1414 offset = cctx->intr_lines[intr_line]; 1415 if (offset == CHV_INVALID_HWIRQ) { 1416 dev_warn_once(dev, "interrupt on unmapped interrupt line %u\n", intr_line); 1417 /* Some boards expect hwirq 0 to trigger in this case */ 1418 offset = 0; 1419 } 1420 1421 generic_handle_domain_irq(gc->irq.domain, offset); 1422 } 1423 1424 chained_irq_exit(chip, desc); 1425 } 1426 1427 /* 1428 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI 1429 * tables. Since we leave GPIOs that are not capable of generating 1430 * interrupts out of the irqdomain the numbering will be different and 1431 * cause devices using the hardcoded IRQ numbers fail. In order not to 1432 * break such machines we will only mask pins from irqdomain if the machine 1433 * is not listed below. 1434 */ 1435 static const struct dmi_system_id chv_no_valid_mask[] = { 1436 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */ 1437 { 1438 .ident = "Intel_Strago based Chromebooks (All models)", 1439 .matches = { 1440 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1441 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"), 1442 }, 1443 }, 1444 { 1445 .ident = "HP Chromebook 11 G5 (Setzer)", 1446 .matches = { 1447 DMI_MATCH(DMI_SYS_VENDOR, "HP"), 1448 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 1449 }, 1450 }, 1451 { 1452 .ident = "Acer Chromebook R11 (Cyan)", 1453 .matches = { 1454 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1455 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"), 1456 }, 1457 }, 1458 { 1459 .ident = "Samsung Chromebook 3 (Celes)", 1460 .matches = { 1461 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1462 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"), 1463 }, 1464 }, 1465 {} 1466 }; 1467 1468 static void chv_init_irq_valid_mask(struct gpio_chip *chip, 1469 unsigned long *valid_mask, 1470 unsigned int ngpios) 1471 { 1472 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1473 const struct intel_community *community = &pctrl->communities[0]; 1474 int i; 1475 1476 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ 1477 for (i = 0; i < pctrl->soc->npins; i++) { 1478 const struct pinctrl_pin_desc *desc; 1479 u32 intsel; 1480 1481 desc = &pctrl->soc->pins[i]; 1482 1483 intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1484 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1485 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1486 1487 if (intsel >= community->nirqs) 1488 clear_bit(desc->number, valid_mask); 1489 } 1490 } 1491 1492 static int chv_gpio_irq_init_hw(struct gpio_chip *chip) 1493 { 1494 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1495 const struct intel_community *community = &pctrl->communities[0]; 1496 1497 /* 1498 * The same set of machines in chv_no_valid_mask[] have incorrectly 1499 * configured GPIOs that generate spurious interrupts so we use 1500 * this same list to apply another quirk for them. 1501 * 1502 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953. 1503 */ 1504 if (!pctrl->chip.irq.init_valid_mask) { 1505 /* 1506 * Mask all interrupts the community is able to generate 1507 * but leave the ones that can only generate GPEs unmasked. 1508 */ 1509 chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs)); 1510 } 1511 1512 /* Clear all interrupts */ 1513 chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff); 1514 1515 return 0; 1516 } 1517 1518 static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) 1519 { 1520 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1521 struct device *dev = pctrl->dev; 1522 const struct intel_community *community = &pctrl->communities[0]; 1523 const struct intel_padgroup *gpp; 1524 int ret, i; 1525 1526 for (i = 0; i < community->ngpps; i++) { 1527 gpp = &community->gpps[i]; 1528 ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size); 1529 if (ret) { 1530 dev_err(dev, "failed to add GPIO pin range\n"); 1531 return ret; 1532 } 1533 } 1534 1535 return 0; 1536 } 1537 1538 static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1539 { 1540 const struct intel_community *community = &pctrl->communities[0]; 1541 const struct intel_padgroup *gpp; 1542 struct gpio_chip *chip = &pctrl->chip; 1543 struct device *dev = pctrl->dev; 1544 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); 1545 int ret, i, irq_base; 1546 1547 *chip = chv_gpio_chip; 1548 1549 chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1; 1550 chip->label = dev_name(dev); 1551 chip->add_pin_ranges = chv_gpio_add_pin_ranges; 1552 chip->parent = dev; 1553 chip->base = -1; 1554 1555 pctrl->irq = irq; 1556 1557 gpio_irq_chip_set_chip(&chip->irq, &chv_gpio_irq_chip); 1558 chip->irq.init_hw = chv_gpio_irq_init_hw; 1559 chip->irq.parent_handler = chv_gpio_irq_handler; 1560 chip->irq.num_parents = 1; 1561 chip->irq.parents = &pctrl->irq; 1562 chip->irq.default_type = IRQ_TYPE_NONE; 1563 chip->irq.handler = handle_bad_irq; 1564 if (need_valid_mask) { 1565 chip->irq.init_valid_mask = chv_init_irq_valid_mask; 1566 } else { 1567 irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE); 1568 if (irq_base < 0) { 1569 dev_err(dev, "Failed to allocate IRQ numbers\n"); 1570 return irq_base; 1571 } 1572 } 1573 1574 ret = devm_gpiochip_add_data(dev, chip, pctrl); 1575 if (ret) { 1576 dev_err(dev, "Failed to register gpiochip\n"); 1577 return ret; 1578 } 1579 1580 if (!need_valid_mask) { 1581 for (i = 0; i < community->ngpps; i++) { 1582 gpp = &community->gpps[i]; 1583 1584 irq_domain_associate_many(chip->irq.domain, irq_base, 1585 gpp->base, gpp->size); 1586 irq_base += gpp->size; 1587 } 1588 } 1589 1590 return 0; 1591 } 1592 1593 static acpi_status chv_pinctrl_mmio_access_handler(u32 function, 1594 acpi_physical_address address, u32 bits, u64 *value, 1595 void *handler_context, void *region_context) 1596 { 1597 struct intel_pinctrl *pctrl = region_context; 1598 1599 guard(raw_spinlock_irqsave)(&chv_lock); 1600 1601 if (function == ACPI_WRITE) 1602 chv_pctrl_writel(pctrl, address, *value); 1603 else if (function == ACPI_READ) 1604 *value = chv_pctrl_readl(pctrl, address); 1605 else 1606 return AE_BAD_PARAMETER; 1607 1608 return AE_OK; 1609 } 1610 1611 static int chv_pinctrl_probe(struct platform_device *pdev) 1612 { 1613 const struct intel_pinctrl_soc_data *soc_data; 1614 struct intel_community_context *cctx; 1615 struct intel_community *community; 1616 struct device *dev = &pdev->dev; 1617 struct intel_pinctrl *pctrl; 1618 acpi_status status; 1619 unsigned int i; 1620 int ret, irq; 1621 1622 soc_data = intel_pinctrl_get_soc_data(pdev); 1623 if (IS_ERR(soc_data)) 1624 return PTR_ERR(soc_data); 1625 1626 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 1627 if (!pctrl) 1628 return -ENOMEM; 1629 1630 pctrl->dev = dev; 1631 pctrl->soc = soc_data; 1632 1633 pctrl->ncommunities = pctrl->soc->ncommunities; 1634 pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities, 1635 pctrl->ncommunities * sizeof(*pctrl->communities), 1636 GFP_KERNEL); 1637 if (!pctrl->communities) 1638 return -ENOMEM; 1639 1640 community = &pctrl->communities[0]; 1641 community->regs = devm_platform_ioremap_resource(pdev, 0); 1642 if (IS_ERR(community->regs)) 1643 return PTR_ERR(community->regs); 1644 1645 community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF; 1646 1647 #ifdef CONFIG_PM_SLEEP 1648 pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins, 1649 sizeof(*pctrl->context.pads), 1650 GFP_KERNEL); 1651 if (!pctrl->context.pads) 1652 return -ENOMEM; 1653 #endif 1654 1655 pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities, 1656 sizeof(*pctrl->context.communities), 1657 GFP_KERNEL); 1658 if (!pctrl->context.communities) 1659 return -ENOMEM; 1660 1661 cctx = &pctrl->context.communities[0]; 1662 for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) 1663 cctx->intr_lines[i] = CHV_INVALID_HWIRQ; 1664 1665 irq = platform_get_irq(pdev, 0); 1666 if (irq < 0) 1667 return irq; 1668 1669 pctrl->pctldesc = chv_pinctrl_desc; 1670 pctrl->pctldesc.name = dev_name(dev); 1671 pctrl->pctldesc.pins = pctrl->soc->pins; 1672 pctrl->pctldesc.npins = pctrl->soc->npins; 1673 1674 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); 1675 if (IS_ERR(pctrl->pctldev)) { 1676 dev_err(dev, "failed to register pinctrl driver\n"); 1677 return PTR_ERR(pctrl->pctldev); 1678 } 1679 1680 ret = chv_gpio_probe(pctrl, irq); 1681 if (ret) 1682 return ret; 1683 1684 status = acpi_install_address_space_handler(ACPI_HANDLE(dev), 1685 community->acpi_space_id, 1686 chv_pinctrl_mmio_access_handler, 1687 NULL, pctrl); 1688 if (ACPI_FAILURE(status)) 1689 dev_err(dev, "failed to install ACPI addr space handler\n"); 1690 1691 platform_set_drvdata(pdev, pctrl); 1692 1693 return 0; 1694 } 1695 1696 static void chv_pinctrl_remove(struct platform_device *pdev) 1697 { 1698 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1699 const struct intel_community *community = &pctrl->communities[0]; 1700 1701 acpi_remove_address_space_handler(ACPI_HANDLE(&pdev->dev), 1702 community->acpi_space_id, 1703 chv_pinctrl_mmio_access_handler); 1704 } 1705 1706 static int chv_pinctrl_suspend_noirq(struct device *dev) 1707 { 1708 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1709 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1710 int i; 1711 1712 guard(raw_spinlock_irqsave)(&chv_lock); 1713 1714 cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK); 1715 1716 for (i = 0; i < pctrl->soc->npins; i++) { 1717 const struct pinctrl_pin_desc *desc; 1718 struct intel_pad_context *ctx = &pctrl->context.pads[i]; 1719 1720 desc = &pctrl->soc->pins[i]; 1721 if (chv_pad_locked(pctrl, desc->number)) 1722 continue; 1723 1724 ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1725 ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE; 1726 1727 ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1); 1728 } 1729 1730 return 0; 1731 } 1732 1733 static int chv_pinctrl_resume_noirq(struct device *dev) 1734 { 1735 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1736 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1737 int i; 1738 1739 guard(raw_spinlock_irqsave)(&chv_lock); 1740 1741 /* 1742 * Mask all interrupts before restoring per-pin configuration 1743 * registers because we don't know in which state BIOS left them 1744 * upon exiting suspend. 1745 */ 1746 chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000); 1747 1748 for (i = 0; i < pctrl->soc->npins; i++) { 1749 const struct pinctrl_pin_desc *desc; 1750 struct intel_pad_context *ctx = &pctrl->context.pads[i]; 1751 u32 val; 1752 1753 desc = &pctrl->soc->pins[i]; 1754 if (chv_pad_locked(pctrl, desc->number)) 1755 continue; 1756 1757 /* Only restore if our saved state differs from the current */ 1758 val = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1759 val &= ~CHV_PADCTRL0_GPIORXSTATE; 1760 if (ctx->padctrl0 != val) { 1761 chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0); 1762 dev_dbg(dev, "restored pin %2u ctrl0 0x%08x\n", desc->number, 1763 chv_readl(pctrl, desc->number, CHV_PADCTRL0)); 1764 } 1765 1766 val = chv_readl(pctrl, desc->number, CHV_PADCTRL1); 1767 if (ctx->padctrl1 != val) { 1768 chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1); 1769 dev_dbg(dev, "restored pin %2u ctrl1 0x%08x\n", desc->number, 1770 chv_readl(pctrl, desc->number, CHV_PADCTRL1)); 1771 } 1772 } 1773 1774 /* 1775 * Now that all pins are restored to known state, we can restore 1776 * the interrupt mask register as well. 1777 */ 1778 chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff); 1779 chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask); 1780 1781 return 0; 1782 } 1783 1784 static DEFINE_NOIRQ_DEV_PM_OPS(chv_pinctrl_pm_ops, 1785 chv_pinctrl_suspend_noirq, chv_pinctrl_resume_noirq); 1786 1787 static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 1788 { "INT33FF", (kernel_ulong_t)chv_soc_data }, 1789 { } 1790 }; 1791 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 1792 1793 static struct platform_driver chv_pinctrl_driver = { 1794 .probe = chv_pinctrl_probe, 1795 .remove_new = chv_pinctrl_remove, 1796 .driver = { 1797 .name = "cherryview-pinctrl", 1798 .pm = pm_sleep_ptr(&chv_pinctrl_pm_ops), 1799 .acpi_match_table = chv_pinctrl_acpi_match, 1800 }, 1801 }; 1802 1803 static int __init chv_pinctrl_init(void) 1804 { 1805 return platform_driver_register(&chv_pinctrl_driver); 1806 } 1807 subsys_initcall(chv_pinctrl_init); 1808 1809 static void __exit chv_pinctrl_exit(void) 1810 { 1811 platform_driver_unregister(&chv_pinctrl_driver); 1812 } 1813 module_exit(chv_pinctrl_exit); 1814 1815 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1816 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 1817 MODULE_LICENSE("GPL v2"); 1818 MODULE_IMPORT_NS(PINCTRL_INTEL); 1819