1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2016-2018 Nuvoton Technology corporation. 3 // Copyright (c) 2016, Dell Inc 4 5 #include <linux/device.h> 6 #include <linux/gpio/driver.h> 7 #include <linux/interrupt.h> 8 #include <linux/irq.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/of_irq.h> 14 #include <linux/pinctrl/machine.h> 15 #include <linux/pinctrl/pinconf.h> 16 #include <linux/pinctrl/pinconf-generic.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 #include <linux/platform_device.h> 20 #include <linux/regmap.h> 21 22 /* GCR registers */ 23 #define NPCM7XX_GCR_PDID 0x00 24 #define NPCM7XX_GCR_MFSEL1 0x0C 25 #define NPCM7XX_GCR_MFSEL2 0x10 26 #define NPCM7XX_GCR_MFSEL3 0x64 27 #define NPCM7XX_GCR_MFSEL4 0xb0 28 #define NPCM7XX_GCR_CPCTL 0xD0 29 #define NPCM7XX_GCR_CP2BST 0xD4 30 #define NPCM7XX_GCR_B2CPNT 0xD8 31 #define NPCM7XX_GCR_I2CSEGSEL 0xE0 32 #define NPCM7XX_GCR_I2CSEGCTL 0xE4 33 #define NPCM7XX_GCR_SRCNT 0x68 34 #define NPCM7XX_GCR_FLOCKR1 0x74 35 #define NPCM7XX_GCR_DSCNT 0x78 36 37 #define SRCNT_ESPI BIT(3) 38 39 /* GPIO registers */ 40 #define NPCM7XX_GP_N_TLOCK1 0x00 41 #define NPCM7XX_GP_N_DIN 0x04 /* Data IN */ 42 #define NPCM7XX_GP_N_POL 0x08 /* Polarity */ 43 #define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */ 44 #define NPCM7XX_GP_N_OE 0x10 /* Output Enable */ 45 #define NPCM7XX_GP_N_OTYP 0x14 46 #define NPCM7XX_GP_N_MP 0x18 47 #define NPCM7XX_GP_N_PU 0x1c /* Pull-up */ 48 #define NPCM7XX_GP_N_PD 0x20 /* Pull-down */ 49 #define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */ 50 #define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */ 51 #define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */ 52 #define NPCM7XX_GP_N_OBL0 0x30 53 #define NPCM7XX_GP_N_OBL1 0x34 54 #define NPCM7XX_GP_N_OBL2 0x38 55 #define NPCM7XX_GP_N_OBL3 0x3c 56 #define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */ 57 #define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */ 58 #define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */ 59 #define NPCM7XX_GP_N_EVST 0x4c /* Event Status */ 60 #define NPCM7XX_GP_N_SPLCK 0x50 61 #define NPCM7XX_GP_N_MPLCK 0x54 62 #define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */ 63 #define NPCM7XX_GP_N_OSRC 0x5c 64 #define NPCM7XX_GP_N_ODSC 0x60 65 #define NPCM7XX_GP_N_DOS 0x68 /* Data OUT Set */ 66 #define NPCM7XX_GP_N_DOC 0x6c /* Data OUT Clear */ 67 #define NPCM7XX_GP_N_OES 0x70 /* Output Enable Set */ 68 #define NPCM7XX_GP_N_OEC 0x74 /* Output Enable Clear */ 69 #define NPCM7XX_GP_N_TLOCK2 0x7c 70 71 #define NPCM7XX_GPIO_PER_BANK 32 72 #define NPCM7XX_GPIO_BANK_NUM 8 73 #define NPCM7XX_GCR_NONE 0 74 75 /* Structure for register banks */ 76 struct npcm7xx_gpio { 77 void __iomem *base; 78 struct gpio_chip gc; 79 int irqbase; 80 int irq; 81 struct irq_chip irq_chip; 82 u32 pinctrl_id; 83 int (*direction_input)(struct gpio_chip *chip, unsigned offset); 84 int (*direction_output)(struct gpio_chip *chip, unsigned offset, 85 int value); 86 int (*request)(struct gpio_chip *chip, unsigned offset); 87 void (*free)(struct gpio_chip *chip, unsigned offset); 88 }; 89 90 struct npcm7xx_pinctrl { 91 struct pinctrl_dev *pctldev; 92 struct device *dev; 93 struct npcm7xx_gpio gpio_bank[NPCM7XX_GPIO_BANK_NUM]; 94 struct irq_domain *domain; 95 struct regmap *gcr_regmap; 96 void __iomem *regs; 97 u32 bank_num; 98 }; 99 100 /* GPIO handling in the pinctrl driver */ 101 static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg, 102 unsigned int pinmask) 103 { 104 unsigned long flags; 105 unsigned long val; 106 107 spin_lock_irqsave(&gc->bgpio_lock, flags); 108 109 val = ioread32(reg) | pinmask; 110 iowrite32(val, reg); 111 112 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 113 } 114 115 static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg, 116 unsigned int pinmask) 117 { 118 unsigned long flags; 119 unsigned long val; 120 121 spin_lock_irqsave(&gc->bgpio_lock, flags); 122 123 val = ioread32(reg) & ~pinmask; 124 iowrite32(val, reg); 125 126 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 127 } 128 129 static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 130 { 131 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); 132 133 seq_printf(s, "-- module %d [gpio%d - %d]\n", 134 bank->gc.base / bank->gc.ngpio, 135 bank->gc.base, 136 bank->gc.base + bank->gc.ngpio); 137 seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n", 138 ioread32(bank->base + NPCM7XX_GP_N_DIN), 139 ioread32(bank->base + NPCM7XX_GP_N_DOUT), 140 ioread32(bank->base + NPCM7XX_GP_N_IEM), 141 ioread32(bank->base + NPCM7XX_GP_N_OE)); 142 seq_printf(s, "PU :%.8x PD :%.8x DB :%.8x POL :%.8x\n", 143 ioread32(bank->base + NPCM7XX_GP_N_PU), 144 ioread32(bank->base + NPCM7XX_GP_N_PD), 145 ioread32(bank->base + NPCM7XX_GP_N_DBNC), 146 ioread32(bank->base + NPCM7XX_GP_N_POL)); 147 seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n", 148 ioread32(bank->base + NPCM7XX_GP_N_EVTYP), 149 ioread32(bank->base + NPCM7XX_GP_N_EVBE), 150 ioread32(bank->base + NPCM7XX_GP_N_EVEN), 151 ioread32(bank->base + NPCM7XX_GP_N_EVST)); 152 seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n", 153 ioread32(bank->base + NPCM7XX_GP_N_OTYP), 154 ioread32(bank->base + NPCM7XX_GP_N_OSRC), 155 ioread32(bank->base + NPCM7XX_GP_N_ODSC)); 156 seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n", 157 ioread32(bank->base + NPCM7XX_GP_N_OBL0), 158 ioread32(bank->base + NPCM7XX_GP_N_OBL1), 159 ioread32(bank->base + NPCM7XX_GP_N_OBL2), 160 ioread32(bank->base + NPCM7XX_GP_N_OBL3)); 161 seq_printf(s, "SLCK:%.8x MLCK:%.8x\n", 162 ioread32(bank->base + NPCM7XX_GP_N_SPLCK), 163 ioread32(bank->base + NPCM7XX_GP_N_MPLCK)); 164 } 165 166 static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset) 167 { 168 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); 169 int ret; 170 171 ret = pinctrl_gpio_direction_input(offset + chip->base); 172 if (ret) 173 return ret; 174 175 return bank->direction_input(chip, offset); 176 } 177 178 /* Set GPIO to Output with initial value */ 179 static int npcmgpio_direction_output(struct gpio_chip *chip, 180 unsigned int offset, int value) 181 { 182 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); 183 int ret; 184 185 dev_dbg(chip->parent, "gpio_direction_output: offset%d = %x\n", offset, 186 value); 187 188 ret = pinctrl_gpio_direction_output(offset + chip->base); 189 if (ret) 190 return ret; 191 192 return bank->direction_output(chip, offset, value); 193 } 194 195 static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset) 196 { 197 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); 198 int ret; 199 200 dev_dbg(chip->parent, "gpio_request: offset%d\n", offset); 201 ret = pinctrl_gpio_request(offset + chip->base); 202 if (ret) 203 return ret; 204 205 return bank->request(chip, offset); 206 } 207 208 static void npcmgpio_gpio_free(struct gpio_chip *chip, unsigned int offset) 209 { 210 dev_dbg(chip->parent, "gpio_free: offset%d\n", offset); 211 pinctrl_gpio_free(offset + chip->base); 212 } 213 214 static void npcmgpio_irq_handler(struct irq_desc *desc) 215 { 216 struct gpio_chip *gc; 217 struct irq_chip *chip; 218 struct npcm7xx_gpio *bank; 219 unsigned long sts, en, bit; 220 221 gc = irq_desc_get_handler_data(desc); 222 bank = gpiochip_get_data(gc); 223 chip = irq_desc_get_chip(desc); 224 225 chained_irq_enter(chip, desc); 226 sts = ioread32(bank->base + NPCM7XX_GP_N_EVST); 227 en = ioread32(bank->base + NPCM7XX_GP_N_EVEN); 228 dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts, 229 en); 230 231 sts &= en; 232 for_each_set_bit(bit, &sts, NPCM7XX_GPIO_PER_BANK) 233 generic_handle_domain_irq(gc->irq.domain, bit); 234 chained_irq_exit(chip, desc); 235 } 236 237 static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type) 238 { 239 struct npcm7xx_gpio *bank = 240 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 241 unsigned int gpio = BIT(d->hwirq); 242 243 dev_dbg(bank->gc.parent, "setirqtype: %u.%u = %u\n", gpio, 244 d->irq, type); 245 switch (type) { 246 case IRQ_TYPE_EDGE_RISING: 247 dev_dbg(bank->gc.parent, "edge.rising\n"); 248 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); 249 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); 250 break; 251 case IRQ_TYPE_EDGE_FALLING: 252 dev_dbg(bank->gc.parent, "edge.falling\n"); 253 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); 254 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); 255 break; 256 case IRQ_TYPE_EDGE_BOTH: 257 dev_dbg(bank->gc.parent, "edge.both\n"); 258 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); 259 break; 260 case IRQ_TYPE_LEVEL_LOW: 261 dev_dbg(bank->gc.parent, "level.low\n"); 262 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); 263 break; 264 case IRQ_TYPE_LEVEL_HIGH: 265 dev_dbg(bank->gc.parent, "level.high\n"); 266 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); 267 break; 268 default: 269 dev_dbg(bank->gc.parent, "invalid irq type\n"); 270 return -EINVAL; 271 } 272 273 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 274 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); 275 irq_set_handler_locked(d, handle_level_irq); 276 } else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING 277 | IRQ_TYPE_EDGE_FALLING)) { 278 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); 279 irq_set_handler_locked(d, handle_edge_irq); 280 } 281 282 return 0; 283 } 284 285 static void npcmgpio_irq_ack(struct irq_data *d) 286 { 287 struct npcm7xx_gpio *bank = 288 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 289 unsigned int gpio = d->hwirq; 290 291 dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq); 292 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST); 293 } 294 295 /* Disable GPIO interrupt */ 296 static void npcmgpio_irq_mask(struct irq_data *d) 297 { 298 struct npcm7xx_gpio *bank = 299 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 300 unsigned int gpio = d->hwirq; 301 302 /* Clear events */ 303 dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq); 304 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC); 305 } 306 307 /* Enable GPIO interrupt */ 308 static void npcmgpio_irq_unmask(struct irq_data *d) 309 { 310 struct npcm7xx_gpio *bank = 311 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 312 unsigned int gpio = d->hwirq; 313 314 /* Enable events */ 315 dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq); 316 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS); 317 } 318 319 static unsigned int npcmgpio_irq_startup(struct irq_data *d) 320 { 321 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 322 unsigned int gpio = d->hwirq; 323 324 /* active-high, input, clear interrupt, enable interrupt */ 325 dev_dbg(gc->parent, "startup: %u.%u\n", gpio, d->irq); 326 npcmgpio_direction_input(gc, gpio); 327 npcmgpio_irq_ack(d); 328 npcmgpio_irq_unmask(d); 329 330 return 0; 331 } 332 333 static const struct irq_chip npcmgpio_irqchip = { 334 .name = "NPCM7XX-GPIO-IRQ", 335 .irq_ack = npcmgpio_irq_ack, 336 .irq_unmask = npcmgpio_irq_unmask, 337 .irq_mask = npcmgpio_irq_mask, 338 .irq_set_type = npcmgpio_set_irq_type, 339 .irq_startup = npcmgpio_irq_startup, 340 }; 341 342 /* pinmux handing in the pinctrl driver*/ 343 static const int smb0_pins[] = { 115, 114 }; 344 static const int smb0b_pins[] = { 195, 194 }; 345 static const int smb0c_pins[] = { 202, 196 }; 346 static const int smb0d_pins[] = { 198, 199 }; 347 static const int smb0den_pins[] = { 197 }; 348 349 static const int smb1_pins[] = { 117, 116 }; 350 static const int smb1b_pins[] = { 126, 127 }; 351 static const int smb1c_pins[] = { 124, 125 }; 352 static const int smb1d_pins[] = { 4, 5 }; 353 354 static const int smb2_pins[] = { 119, 118 }; 355 static const int smb2b_pins[] = { 122, 123 }; 356 static const int smb2c_pins[] = { 120, 121 }; 357 static const int smb2d_pins[] = { 6, 7 }; 358 359 static const int smb3_pins[] = { 30, 31 }; 360 static const int smb3b_pins[] = { 39, 40 }; 361 static const int smb3c_pins[] = { 37, 38 }; 362 static const int smb3d_pins[] = { 59, 60 }; 363 364 static const int smb4_pins[] = { 28, 29 }; 365 static const int smb4b_pins[] = { 18, 19 }; 366 static const int smb4c_pins[] = { 20, 21 }; 367 static const int smb4d_pins[] = { 22, 23 }; 368 static const int smb4den_pins[] = { 17 }; 369 370 static const int smb5_pins[] = { 26, 27 }; 371 static const int smb5b_pins[] = { 13, 12 }; 372 static const int smb5c_pins[] = { 15, 14 }; 373 static const int smb5d_pins[] = { 94, 93 }; 374 static const int ga20kbc_pins[] = { 94, 93 }; 375 376 static const int smb6_pins[] = { 172, 171 }; 377 static const int smb7_pins[] = { 174, 173 }; 378 static const int smb8_pins[] = { 129, 128 }; 379 static const int smb9_pins[] = { 131, 130 }; 380 static const int smb10_pins[] = { 133, 132 }; 381 static const int smb11_pins[] = { 135, 134 }; 382 static const int smb12_pins[] = { 221, 220 }; 383 static const int smb13_pins[] = { 223, 222 }; 384 static const int smb14_pins[] = { 22, 23 }; 385 static const int smb15_pins[] = { 20, 21 }; 386 387 static const int fanin0_pins[] = { 64 }; 388 static const int fanin1_pins[] = { 65 }; 389 static const int fanin2_pins[] = { 66 }; 390 static const int fanin3_pins[] = { 67 }; 391 static const int fanin4_pins[] = { 68 }; 392 static const int fanin5_pins[] = { 69 }; 393 static const int fanin6_pins[] = { 70 }; 394 static const int fanin7_pins[] = { 71 }; 395 static const int fanin8_pins[] = { 72 }; 396 static const int fanin9_pins[] = { 73 }; 397 static const int fanin10_pins[] = { 74 }; 398 static const int fanin11_pins[] = { 75 }; 399 static const int fanin12_pins[] = { 76 }; 400 static const int fanin13_pins[] = { 77 }; 401 static const int fanin14_pins[] = { 78 }; 402 static const int fanin15_pins[] = { 79 }; 403 static const int faninx_pins[] = { 175, 176, 177, 203 }; 404 405 static const int pwm0_pins[] = { 80 }; 406 static const int pwm1_pins[] = { 81 }; 407 static const int pwm2_pins[] = { 82 }; 408 static const int pwm3_pins[] = { 83 }; 409 static const int pwm4_pins[] = { 144 }; 410 static const int pwm5_pins[] = { 145 }; 411 static const int pwm6_pins[] = { 146 }; 412 static const int pwm7_pins[] = { 147 }; 413 414 static const int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 }; 415 static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 }; 416 417 /* RGMII 1 pin group */ 418 static const int rg1_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 419 106, 107 }; 420 /* RGMII 1 MD interface pin group */ 421 static const int rg1mdio_pins[] = { 108, 109 }; 422 423 /* RGMII 2 pin group */ 424 static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212, 425 213, 214, 215 }; 426 /* RGMII 2 MD interface pin group */ 427 static const int rg2mdio_pins[] = { 216, 217 }; 428 429 static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212, 430 213, 214, 215, 216, 217 }; 431 /* Serial I/O Expander 1 */ 432 static const int iox1_pins[] = { 0, 1, 2, 3 }; 433 /* Serial I/O Expander 2 */ 434 static const int iox2_pins[] = { 4, 5, 6, 7 }; 435 /* Host Serial I/O Expander 2 */ 436 static const int ioxh_pins[] = { 10, 11, 24, 25 }; 437 438 static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 }; 439 static const int mmcwp_pins[] = { 153 }; 440 static const int mmccd_pins[] = { 155 }; 441 static const int mmcrst_pins[] = { 155 }; 442 static const int mmc8_pins[] = { 148, 149, 150, 151 }; 443 444 /* RMII 1 pin groups */ 445 static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 }; 446 static const int r1err_pins[] = { 56 }; 447 static const int r1md_pins[] = { 57, 58 }; 448 449 /* RMII 2 pin groups */ 450 static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 }; 451 static const int r2err_pins[] = { 90 }; 452 static const int r2md_pins[] = { 91, 92 }; 453 454 static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 }; 455 static const int sd1pwr_pins[] = { 143 }; 456 457 static const int wdog1_pins[] = { 218 }; 458 static const int wdog2_pins[] = { 219 }; 459 460 /* BMC serial port 0 */ 461 static const int bmcuart0a_pins[] = { 41, 42 }; 462 static const int bmcuart0b_pins[] = { 48, 49 }; 463 464 static const int bmcuart1_pins[] = { 43, 44, 62, 63 }; 465 466 /* System Control Interrupt and Power Management Event pin group */ 467 static const int scipme_pins[] = { 169 }; 468 /* System Management Interrupt pin group */ 469 static const int sci_pins[] = { 170 }; 470 /* Serial Interrupt Line pin group */ 471 static const int serirq_pins[] = { 162 }; 472 473 static const int clkout_pins[] = { 160 }; 474 static const int clkreq_pins[] = { 231 }; 475 476 static const int jtag2_pins[] = { 43, 44, 45, 46, 47 }; 477 /* Graphics SPI Clock pin group */ 478 static const int gspi_pins[] = { 12, 13, 14, 15 }; 479 480 static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 }; 481 static const int spixcs1_pins[] = { 228 }; 482 483 static const int pspi1_pins[] = { 175, 176, 177 }; 484 static const int pspi2_pins[] = { 17, 18, 19 }; 485 486 static const int spi0cs1_pins[] = { 32 }; 487 488 static const int spi3_pins[] = { 183, 184, 185, 186 }; 489 static const int spi3cs1_pins[] = { 187 }; 490 static const int spi3quad_pins[] = { 188, 189 }; 491 static const int spi3cs2_pins[] = { 188 }; 492 static const int spi3cs3_pins[] = { 189 }; 493 494 static const int ddc_pins[] = { 204, 205, 206, 207 }; 495 496 static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 }; 497 static const int lpcclk_pins[] = { 168 }; 498 static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 }; 499 500 static const int lkgpo0_pins[] = { 16 }; 501 static const int lkgpo1_pins[] = { 8 }; 502 static const int lkgpo2_pins[] = { 9 }; 503 504 static const int nprd_smi_pins[] = { 190 }; 505 506 /* 507 * pin: name, number 508 * group: name, npins, pins 509 * function: name, ngroups, groups 510 */ 511 struct npcm7xx_group { 512 const char *name; 513 const unsigned int *pins; 514 int npins; 515 }; 516 517 #define NPCM7XX_GRPS \ 518 NPCM7XX_GRP(smb0), \ 519 NPCM7XX_GRP(smb0b), \ 520 NPCM7XX_GRP(smb0c), \ 521 NPCM7XX_GRP(smb0d), \ 522 NPCM7XX_GRP(smb0den), \ 523 NPCM7XX_GRP(smb1), \ 524 NPCM7XX_GRP(smb1b), \ 525 NPCM7XX_GRP(smb1c), \ 526 NPCM7XX_GRP(smb1d), \ 527 NPCM7XX_GRP(smb2), \ 528 NPCM7XX_GRP(smb2b), \ 529 NPCM7XX_GRP(smb2c), \ 530 NPCM7XX_GRP(smb2d), \ 531 NPCM7XX_GRP(smb3), \ 532 NPCM7XX_GRP(smb3b), \ 533 NPCM7XX_GRP(smb3c), \ 534 NPCM7XX_GRP(smb3d), \ 535 NPCM7XX_GRP(smb4), \ 536 NPCM7XX_GRP(smb4b), \ 537 NPCM7XX_GRP(smb4c), \ 538 NPCM7XX_GRP(smb4d), \ 539 NPCM7XX_GRP(smb4den), \ 540 NPCM7XX_GRP(smb5), \ 541 NPCM7XX_GRP(smb5b), \ 542 NPCM7XX_GRP(smb5c), \ 543 NPCM7XX_GRP(smb5d), \ 544 NPCM7XX_GRP(ga20kbc), \ 545 NPCM7XX_GRP(smb6), \ 546 NPCM7XX_GRP(smb7), \ 547 NPCM7XX_GRP(smb8), \ 548 NPCM7XX_GRP(smb9), \ 549 NPCM7XX_GRP(smb10), \ 550 NPCM7XX_GRP(smb11), \ 551 NPCM7XX_GRP(smb12), \ 552 NPCM7XX_GRP(smb13), \ 553 NPCM7XX_GRP(smb14), \ 554 NPCM7XX_GRP(smb15), \ 555 NPCM7XX_GRP(fanin0), \ 556 NPCM7XX_GRP(fanin1), \ 557 NPCM7XX_GRP(fanin2), \ 558 NPCM7XX_GRP(fanin3), \ 559 NPCM7XX_GRP(fanin4), \ 560 NPCM7XX_GRP(fanin5), \ 561 NPCM7XX_GRP(fanin6), \ 562 NPCM7XX_GRP(fanin7), \ 563 NPCM7XX_GRP(fanin8), \ 564 NPCM7XX_GRP(fanin9), \ 565 NPCM7XX_GRP(fanin10), \ 566 NPCM7XX_GRP(fanin11), \ 567 NPCM7XX_GRP(fanin12), \ 568 NPCM7XX_GRP(fanin13), \ 569 NPCM7XX_GRP(fanin14), \ 570 NPCM7XX_GRP(fanin15), \ 571 NPCM7XX_GRP(faninx), \ 572 NPCM7XX_GRP(pwm0), \ 573 NPCM7XX_GRP(pwm1), \ 574 NPCM7XX_GRP(pwm2), \ 575 NPCM7XX_GRP(pwm3), \ 576 NPCM7XX_GRP(pwm4), \ 577 NPCM7XX_GRP(pwm5), \ 578 NPCM7XX_GRP(pwm6), \ 579 NPCM7XX_GRP(pwm7), \ 580 NPCM7XX_GRP(rg1), \ 581 NPCM7XX_GRP(rg1mdio), \ 582 NPCM7XX_GRP(rg2), \ 583 NPCM7XX_GRP(rg2mdio), \ 584 NPCM7XX_GRP(ddr), \ 585 NPCM7XX_GRP(uart1), \ 586 NPCM7XX_GRP(uart2), \ 587 NPCM7XX_GRP(bmcuart0a), \ 588 NPCM7XX_GRP(bmcuart0b), \ 589 NPCM7XX_GRP(bmcuart1), \ 590 NPCM7XX_GRP(iox1), \ 591 NPCM7XX_GRP(iox2), \ 592 NPCM7XX_GRP(ioxh), \ 593 NPCM7XX_GRP(gspi), \ 594 NPCM7XX_GRP(mmc), \ 595 NPCM7XX_GRP(mmcwp), \ 596 NPCM7XX_GRP(mmccd), \ 597 NPCM7XX_GRP(mmcrst), \ 598 NPCM7XX_GRP(mmc8), \ 599 NPCM7XX_GRP(r1), \ 600 NPCM7XX_GRP(r1err), \ 601 NPCM7XX_GRP(r1md), \ 602 NPCM7XX_GRP(r2), \ 603 NPCM7XX_GRP(r2err), \ 604 NPCM7XX_GRP(r2md), \ 605 NPCM7XX_GRP(sd1), \ 606 NPCM7XX_GRP(sd1pwr), \ 607 NPCM7XX_GRP(wdog1), \ 608 NPCM7XX_GRP(wdog2), \ 609 NPCM7XX_GRP(scipme), \ 610 NPCM7XX_GRP(sci), \ 611 NPCM7XX_GRP(serirq), \ 612 NPCM7XX_GRP(jtag2), \ 613 NPCM7XX_GRP(spix), \ 614 NPCM7XX_GRP(spixcs1), \ 615 NPCM7XX_GRP(pspi1), \ 616 NPCM7XX_GRP(pspi2), \ 617 NPCM7XX_GRP(ddc), \ 618 NPCM7XX_GRP(clkreq), \ 619 NPCM7XX_GRP(clkout), \ 620 NPCM7XX_GRP(spi3), \ 621 NPCM7XX_GRP(spi3cs1), \ 622 NPCM7XX_GRP(spi3quad), \ 623 NPCM7XX_GRP(spi3cs2), \ 624 NPCM7XX_GRP(spi3cs3), \ 625 NPCM7XX_GRP(spi0cs1), \ 626 NPCM7XX_GRP(lpc), \ 627 NPCM7XX_GRP(lpcclk), \ 628 NPCM7XX_GRP(espi), \ 629 NPCM7XX_GRP(lkgpo0), \ 630 NPCM7XX_GRP(lkgpo1), \ 631 NPCM7XX_GRP(lkgpo2), \ 632 NPCM7XX_GRP(nprd_smi), \ 633 \ 634 635 enum { 636 #define NPCM7XX_GRP(x) fn_ ## x 637 NPCM7XX_GRPS 638 /* add placeholder for none/gpio */ 639 NPCM7XX_GRP(none), 640 NPCM7XX_GRP(gpio), 641 #undef NPCM7XX_GRP 642 }; 643 644 static struct npcm7xx_group npcm7xx_groups[] = { 645 #define NPCM7XX_GRP(x) { .name = #x, .pins = x ## _pins, \ 646 .npins = ARRAY_SIZE(x ## _pins) } 647 NPCM7XX_GRPS 648 #undef NPCM7XX_GRP 649 }; 650 651 #define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a) 652 #define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b } 653 #define NPCM7XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \ 654 .groups = nm ## _grp } 655 struct npcm7xx_func { 656 const char *name; 657 const unsigned int ngroups; 658 const char *const *groups; 659 }; 660 661 NPCM7XX_SFUNC(smb0); 662 NPCM7XX_SFUNC(smb0b); 663 NPCM7XX_SFUNC(smb0c); 664 NPCM7XX_SFUNC(smb0d); 665 NPCM7XX_SFUNC(smb0den); 666 NPCM7XX_SFUNC(smb1); 667 NPCM7XX_SFUNC(smb1b); 668 NPCM7XX_SFUNC(smb1c); 669 NPCM7XX_SFUNC(smb1d); 670 NPCM7XX_SFUNC(smb2); 671 NPCM7XX_SFUNC(smb2b); 672 NPCM7XX_SFUNC(smb2c); 673 NPCM7XX_SFUNC(smb2d); 674 NPCM7XX_SFUNC(smb3); 675 NPCM7XX_SFUNC(smb3b); 676 NPCM7XX_SFUNC(smb3c); 677 NPCM7XX_SFUNC(smb3d); 678 NPCM7XX_SFUNC(smb4); 679 NPCM7XX_SFUNC(smb4b); 680 NPCM7XX_SFUNC(smb4c); 681 NPCM7XX_SFUNC(smb4d); 682 NPCM7XX_SFUNC(smb4den); 683 NPCM7XX_SFUNC(smb5); 684 NPCM7XX_SFUNC(smb5b); 685 NPCM7XX_SFUNC(smb5c); 686 NPCM7XX_SFUNC(smb5d); 687 NPCM7XX_SFUNC(ga20kbc); 688 NPCM7XX_SFUNC(smb6); 689 NPCM7XX_SFUNC(smb7); 690 NPCM7XX_SFUNC(smb8); 691 NPCM7XX_SFUNC(smb9); 692 NPCM7XX_SFUNC(smb10); 693 NPCM7XX_SFUNC(smb11); 694 NPCM7XX_SFUNC(smb12); 695 NPCM7XX_SFUNC(smb13); 696 NPCM7XX_SFUNC(smb14); 697 NPCM7XX_SFUNC(smb15); 698 NPCM7XX_SFUNC(fanin0); 699 NPCM7XX_SFUNC(fanin1); 700 NPCM7XX_SFUNC(fanin2); 701 NPCM7XX_SFUNC(fanin3); 702 NPCM7XX_SFUNC(fanin4); 703 NPCM7XX_SFUNC(fanin5); 704 NPCM7XX_SFUNC(fanin6); 705 NPCM7XX_SFUNC(fanin7); 706 NPCM7XX_SFUNC(fanin8); 707 NPCM7XX_SFUNC(fanin9); 708 NPCM7XX_SFUNC(fanin10); 709 NPCM7XX_SFUNC(fanin11); 710 NPCM7XX_SFUNC(fanin12); 711 NPCM7XX_SFUNC(fanin13); 712 NPCM7XX_SFUNC(fanin14); 713 NPCM7XX_SFUNC(fanin15); 714 NPCM7XX_SFUNC(faninx); 715 NPCM7XX_SFUNC(pwm0); 716 NPCM7XX_SFUNC(pwm1); 717 NPCM7XX_SFUNC(pwm2); 718 NPCM7XX_SFUNC(pwm3); 719 NPCM7XX_SFUNC(pwm4); 720 NPCM7XX_SFUNC(pwm5); 721 NPCM7XX_SFUNC(pwm6); 722 NPCM7XX_SFUNC(pwm7); 723 NPCM7XX_SFUNC(rg1); 724 NPCM7XX_SFUNC(rg1mdio); 725 NPCM7XX_SFUNC(rg2); 726 NPCM7XX_SFUNC(rg2mdio); 727 NPCM7XX_SFUNC(ddr); 728 NPCM7XX_SFUNC(uart1); 729 NPCM7XX_SFUNC(uart2); 730 NPCM7XX_SFUNC(bmcuart0a); 731 NPCM7XX_SFUNC(bmcuart0b); 732 NPCM7XX_SFUNC(bmcuart1); 733 NPCM7XX_SFUNC(iox1); 734 NPCM7XX_SFUNC(iox2); 735 NPCM7XX_SFUNC(ioxh); 736 NPCM7XX_SFUNC(gspi); 737 NPCM7XX_SFUNC(mmc); 738 NPCM7XX_SFUNC(mmcwp); 739 NPCM7XX_SFUNC(mmccd); 740 NPCM7XX_SFUNC(mmcrst); 741 NPCM7XX_SFUNC(mmc8); 742 NPCM7XX_SFUNC(r1); 743 NPCM7XX_SFUNC(r1err); 744 NPCM7XX_SFUNC(r1md); 745 NPCM7XX_SFUNC(r2); 746 NPCM7XX_SFUNC(r2err); 747 NPCM7XX_SFUNC(r2md); 748 NPCM7XX_SFUNC(sd1); 749 NPCM7XX_SFUNC(sd1pwr); 750 NPCM7XX_SFUNC(wdog1); 751 NPCM7XX_SFUNC(wdog2); 752 NPCM7XX_SFUNC(scipme); 753 NPCM7XX_SFUNC(sci); 754 NPCM7XX_SFUNC(serirq); 755 NPCM7XX_SFUNC(jtag2); 756 NPCM7XX_SFUNC(spix); 757 NPCM7XX_SFUNC(spixcs1); 758 NPCM7XX_SFUNC(pspi1); 759 NPCM7XX_SFUNC(pspi2); 760 NPCM7XX_SFUNC(ddc); 761 NPCM7XX_SFUNC(clkreq); 762 NPCM7XX_SFUNC(clkout); 763 NPCM7XX_SFUNC(spi3); 764 NPCM7XX_SFUNC(spi3cs1); 765 NPCM7XX_SFUNC(spi3quad); 766 NPCM7XX_SFUNC(spi3cs2); 767 NPCM7XX_SFUNC(spi3cs3); 768 NPCM7XX_SFUNC(spi0cs1); 769 NPCM7XX_SFUNC(lpc); 770 NPCM7XX_SFUNC(lpcclk); 771 NPCM7XX_SFUNC(espi); 772 NPCM7XX_SFUNC(lkgpo0); 773 NPCM7XX_SFUNC(lkgpo1); 774 NPCM7XX_SFUNC(lkgpo2); 775 NPCM7XX_SFUNC(nprd_smi); 776 777 /* Function names */ 778 static struct npcm7xx_func npcm7xx_funcs[] = { 779 NPCM7XX_MKFUNC(smb0), 780 NPCM7XX_MKFUNC(smb0b), 781 NPCM7XX_MKFUNC(smb0c), 782 NPCM7XX_MKFUNC(smb0d), 783 NPCM7XX_MKFUNC(smb0den), 784 NPCM7XX_MKFUNC(smb1), 785 NPCM7XX_MKFUNC(smb1b), 786 NPCM7XX_MKFUNC(smb1c), 787 NPCM7XX_MKFUNC(smb1d), 788 NPCM7XX_MKFUNC(smb2), 789 NPCM7XX_MKFUNC(smb2b), 790 NPCM7XX_MKFUNC(smb2c), 791 NPCM7XX_MKFUNC(smb2d), 792 NPCM7XX_MKFUNC(smb3), 793 NPCM7XX_MKFUNC(smb3b), 794 NPCM7XX_MKFUNC(smb3c), 795 NPCM7XX_MKFUNC(smb3d), 796 NPCM7XX_MKFUNC(smb4), 797 NPCM7XX_MKFUNC(smb4b), 798 NPCM7XX_MKFUNC(smb4c), 799 NPCM7XX_MKFUNC(smb4d), 800 NPCM7XX_MKFUNC(smb4den), 801 NPCM7XX_MKFUNC(smb5), 802 NPCM7XX_MKFUNC(smb5b), 803 NPCM7XX_MKFUNC(smb5c), 804 NPCM7XX_MKFUNC(smb5d), 805 NPCM7XX_MKFUNC(ga20kbc), 806 NPCM7XX_MKFUNC(smb6), 807 NPCM7XX_MKFUNC(smb7), 808 NPCM7XX_MKFUNC(smb8), 809 NPCM7XX_MKFUNC(smb9), 810 NPCM7XX_MKFUNC(smb10), 811 NPCM7XX_MKFUNC(smb11), 812 NPCM7XX_MKFUNC(smb12), 813 NPCM7XX_MKFUNC(smb13), 814 NPCM7XX_MKFUNC(smb14), 815 NPCM7XX_MKFUNC(smb15), 816 NPCM7XX_MKFUNC(fanin0), 817 NPCM7XX_MKFUNC(fanin1), 818 NPCM7XX_MKFUNC(fanin2), 819 NPCM7XX_MKFUNC(fanin3), 820 NPCM7XX_MKFUNC(fanin4), 821 NPCM7XX_MKFUNC(fanin5), 822 NPCM7XX_MKFUNC(fanin6), 823 NPCM7XX_MKFUNC(fanin7), 824 NPCM7XX_MKFUNC(fanin8), 825 NPCM7XX_MKFUNC(fanin9), 826 NPCM7XX_MKFUNC(fanin10), 827 NPCM7XX_MKFUNC(fanin11), 828 NPCM7XX_MKFUNC(fanin12), 829 NPCM7XX_MKFUNC(fanin13), 830 NPCM7XX_MKFUNC(fanin14), 831 NPCM7XX_MKFUNC(fanin15), 832 NPCM7XX_MKFUNC(faninx), 833 NPCM7XX_MKFUNC(pwm0), 834 NPCM7XX_MKFUNC(pwm1), 835 NPCM7XX_MKFUNC(pwm2), 836 NPCM7XX_MKFUNC(pwm3), 837 NPCM7XX_MKFUNC(pwm4), 838 NPCM7XX_MKFUNC(pwm5), 839 NPCM7XX_MKFUNC(pwm6), 840 NPCM7XX_MKFUNC(pwm7), 841 NPCM7XX_MKFUNC(rg1), 842 NPCM7XX_MKFUNC(rg1mdio), 843 NPCM7XX_MKFUNC(rg2), 844 NPCM7XX_MKFUNC(rg2mdio), 845 NPCM7XX_MKFUNC(ddr), 846 NPCM7XX_MKFUNC(uart1), 847 NPCM7XX_MKFUNC(uart2), 848 NPCM7XX_MKFUNC(bmcuart0a), 849 NPCM7XX_MKFUNC(bmcuart0b), 850 NPCM7XX_MKFUNC(bmcuart1), 851 NPCM7XX_MKFUNC(iox1), 852 NPCM7XX_MKFUNC(iox2), 853 NPCM7XX_MKFUNC(ioxh), 854 NPCM7XX_MKFUNC(gspi), 855 NPCM7XX_MKFUNC(mmc), 856 NPCM7XX_MKFUNC(mmcwp), 857 NPCM7XX_MKFUNC(mmccd), 858 NPCM7XX_MKFUNC(mmcrst), 859 NPCM7XX_MKFUNC(mmc8), 860 NPCM7XX_MKFUNC(r1), 861 NPCM7XX_MKFUNC(r1err), 862 NPCM7XX_MKFUNC(r1md), 863 NPCM7XX_MKFUNC(r2), 864 NPCM7XX_MKFUNC(r2err), 865 NPCM7XX_MKFUNC(r2md), 866 NPCM7XX_MKFUNC(sd1), 867 NPCM7XX_MKFUNC(sd1pwr), 868 NPCM7XX_MKFUNC(wdog1), 869 NPCM7XX_MKFUNC(wdog2), 870 NPCM7XX_MKFUNC(scipme), 871 NPCM7XX_MKFUNC(sci), 872 NPCM7XX_MKFUNC(serirq), 873 NPCM7XX_MKFUNC(jtag2), 874 NPCM7XX_MKFUNC(spix), 875 NPCM7XX_MKFUNC(spixcs1), 876 NPCM7XX_MKFUNC(pspi1), 877 NPCM7XX_MKFUNC(pspi2), 878 NPCM7XX_MKFUNC(ddc), 879 NPCM7XX_MKFUNC(clkreq), 880 NPCM7XX_MKFUNC(clkout), 881 NPCM7XX_MKFUNC(spi3), 882 NPCM7XX_MKFUNC(spi3cs1), 883 NPCM7XX_MKFUNC(spi3quad), 884 NPCM7XX_MKFUNC(spi3cs2), 885 NPCM7XX_MKFUNC(spi3cs3), 886 NPCM7XX_MKFUNC(spi0cs1), 887 NPCM7XX_MKFUNC(lpc), 888 NPCM7XX_MKFUNC(lpcclk), 889 NPCM7XX_MKFUNC(espi), 890 NPCM7XX_MKFUNC(lkgpo0), 891 NPCM7XX_MKFUNC(lkgpo1), 892 NPCM7XX_MKFUNC(lkgpo2), 893 NPCM7XX_MKFUNC(nprd_smi), 894 }; 895 896 #define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \ 897 [a] = { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \ 898 .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \ 899 .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \ 900 .flag = k } 901 902 /* Drive strength controlled by NPCM7XX_GP_N_ODSC */ 903 #define DRIVE_STRENGTH_LO_SHIFT 8 904 #define DRIVE_STRENGTH_HI_SHIFT 12 905 #define DRIVE_STRENGTH_MASK 0x0000FF00 906 907 #define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ 908 ((hi) << DRIVE_STRENGTH_HI_SHIFT)) 909 #define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF) 910 #define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF) 911 912 #define GPI 0x1 /* Not GPO */ 913 #define GPO 0x2 /* Not GPI */ 914 #define SLEW 0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */ 915 #define SLEWLPC 0x8 /* Has Slew Control, SRCNT.3 */ 916 917 struct npcm7xx_pincfg { 918 int flag; 919 int fn0, reg0, bit0; 920 int fn1, reg1, bit1; 921 int fn2, reg2, bit2; 922 }; 923 924 static const struct npcm7xx_pincfg pincfg[] = { 925 /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */ 926 NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), 927 NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 928 NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 929 NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), 930 NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), 931 NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), 932 NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), 933 NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), 934 NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 935 NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 936 NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 937 NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 938 NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), 939 NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), 940 NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), 941 NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), 942 NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 943 NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DSTR(8, 12)), 944 NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)), 945 NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)), 946 NPCM7XX_PINCFG(20, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0), 947 NPCM7XX_PINCFG(21, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0), 948 NPCM7XX_PINCFG(22, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0), 949 NPCM7XX_PINCFG(23, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0), 950 NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 951 NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 952 NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), 953 NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), 954 NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0), 955 NPCM7XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0), 956 NPCM7XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0), 957 NPCM7XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0), 958 959 NPCM7XX_PINCFG(32, spi0cs1, MFSEL1, 3, none, NONE, 0, none, NONE, 0, 0), 960 NPCM7XX_PINCFG(33, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 961 NPCM7XX_PINCFG(34, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 962 NPCM7XX_PINCFG(37, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW), 963 NPCM7XX_PINCFG(38, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW), 964 NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), 965 NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), 966 NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0), 967 NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO), 968 NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), 969 NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), 970 NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0), 971 NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)), 972 NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)), 973 NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO), 974 NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0), 975 NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), 976 NPCM7XX_PINCFG(51, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO), 977 NPCM7XX_PINCFG(52, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), 978 NPCM7XX_PINCFG(53, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO), 979 NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), 980 NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), 981 NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0), 982 NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), 983 NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), 984 NPCM7XX_PINCFG(59, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0), 985 NPCM7XX_PINCFG(60, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0), 986 NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO), 987 NPCM7XX_PINCFG(62, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO), 988 NPCM7XX_PINCFG(63, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO), 989 990 NPCM7XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, 0), 991 NPCM7XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, 0), 992 NPCM7XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, 0), 993 NPCM7XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, 0), 994 NPCM7XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, 0), 995 NPCM7XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, 0), 996 NPCM7XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, 0), 997 NPCM7XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, 0), 998 NPCM7XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, 0), 999 NPCM7XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, 0), 1000 NPCM7XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, 0), 1001 NPCM7XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, 0), 1002 NPCM7XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, 0), 1003 NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0), 1004 NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0), 1005 NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0), 1006 NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1007 NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1008 NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1009 NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1010 NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1011 NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1012 NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1013 NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), 1014 NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), 1015 NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), 1016 NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0), 1017 NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), 1018 NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), 1019 NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), 1020 NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), 1021 NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), 1022 1023 NPCM7XX_PINCFG(96, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1024 NPCM7XX_PINCFG(97, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1025 NPCM7XX_PINCFG(98, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1026 NPCM7XX_PINCFG(99, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1027 NPCM7XX_PINCFG(100, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1028 NPCM7XX_PINCFG(101, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1029 NPCM7XX_PINCFG(102, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1030 NPCM7XX_PINCFG(103, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1031 NPCM7XX_PINCFG(104, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1032 NPCM7XX_PINCFG(105, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1033 NPCM7XX_PINCFG(106, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1034 NPCM7XX_PINCFG(107, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1035 NPCM7XX_PINCFG(108, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0), 1036 NPCM7XX_PINCFG(109, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0), 1037 NPCM7XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1038 NPCM7XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1039 NPCM7XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1040 NPCM7XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1041 NPCM7XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0), 1042 NPCM7XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0), 1043 NPCM7XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0), 1044 NPCM7XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0), 1045 NPCM7XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0), 1046 NPCM7XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0), 1047 NPCM7XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW), 1048 NPCM7XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW), 1049 NPCM7XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW), 1050 NPCM7XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW), 1051 NPCM7XX_PINCFG(124, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW), 1052 NPCM7XX_PINCFG(125, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW), 1053 NPCM7XX_PINCFG(126, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW), 1054 NPCM7XX_PINCFG(127, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW), 1055 1056 NPCM7XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0), 1057 NPCM7XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0), 1058 NPCM7XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0), 1059 NPCM7XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0), 1060 NPCM7XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0), 1061 NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0), 1062 NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), 1063 NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), 1064 NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1065 NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1066 NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1067 NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1068 NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1069 NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0), 1070 NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1071 NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0), 1072 NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1073 NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1074 NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1075 NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1076 NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1077 NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1078 NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1079 NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1080 NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1081 NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */ 1082 NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1083 NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */ 1084 NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1085 NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1086 NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1087 NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1088 1089 NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1090 NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)), 1091 NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)), 1092 NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), 1093 NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), 1094 NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), 1095 NPCM7XX_PINCFG(166, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), 1096 NPCM7XX_PINCFG(167, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), 1097 NPCM7XX_PINCFG(168, lpcclk, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL3, 16, 0), 1098 NPCM7XX_PINCFG(169, scipme, MFSEL3, 0, none, NONE, 0, none, NONE, 0, 0), 1099 NPCM7XX_PINCFG(170, sci, MFSEL1, 22, none, NONE, 0, none, NONE, 0, 0), 1100 NPCM7XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0), 1101 NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0), 1102 NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), 1103 NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), 1104 NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), 1105 NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), 1106 NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), 1107 NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1108 NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1109 NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1110 NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), 1111 NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), 1112 NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1113 NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), 1114 NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), 1115 NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1116 NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1117 NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DSTR(8, 12) | SLEW), 1118 NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DSTR(8, 12) | SLEW), 1119 NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)), 1120 NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */ 1121 1122 NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */ 1123 NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), 1124 NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), 1125 NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), 1126 NPCM7XX_PINCFG(196, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0), 1127 NPCM7XX_PINCFG(197, smb0den, I2CSEGSEL, 22, none, NONE, 0, none, NONE, 0, SLEW), 1128 NPCM7XX_PINCFG(198, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0), 1129 NPCM7XX_PINCFG(199, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0), 1130 NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), 1131 NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), 1132 NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0), 1133 NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1134 NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), 1135 NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), 1136 NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)), 1137 NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)), 1138 NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1139 NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1140 NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1141 NPCM7XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1142 NPCM7XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1143 NPCM7XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1144 NPCM7XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1145 NPCM7XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1146 NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), 1147 NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), 1148 NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0), 1149 NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1150 NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), 1151 NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), 1152 NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), 1153 NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), 1154 1155 NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW), 1156 NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), 1157 NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), 1158 NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1159 NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1160 NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1161 NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1162 NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1163 NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */ 1164 NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */ 1165 NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */ 1166 }; 1167 1168 /* number, name, drv_data */ 1169 static const struct pinctrl_pin_desc npcm7xx_pins[] = { 1170 PINCTRL_PIN(0, "GPIO0/IOX1DI"), 1171 PINCTRL_PIN(1, "GPIO1/IOX1LD"), 1172 PINCTRL_PIN(2, "GPIO2/IOX1CK"), 1173 PINCTRL_PIN(3, "GPIO3/IOX1D0"), 1174 PINCTRL_PIN(4, "GPIO4/IOX2DI/SMB1DSDA"), 1175 PINCTRL_PIN(5, "GPIO5/IOX2LD/SMB1DSCL"), 1176 PINCTRL_PIN(6, "GPIO6/IOX2CK/SMB2DSDA"), 1177 PINCTRL_PIN(7, "GPIO7/IOX2D0/SMB2DSCL"), 1178 PINCTRL_PIN(8, "GPIO8/LKGPO1"), 1179 PINCTRL_PIN(9, "GPIO9/LKGPO2"), 1180 PINCTRL_PIN(10, "GPIO10/IOXHLD"), 1181 PINCTRL_PIN(11, "GPIO11/IOXHCK"), 1182 PINCTRL_PIN(12, "GPIO12/GSPICK/SMB5BSCL"), 1183 PINCTRL_PIN(13, "GPIO13/GSPIDO/SMB5BSDA"), 1184 PINCTRL_PIN(14, "GPIO14/GSPIDI/SMB5CSCL"), 1185 PINCTRL_PIN(15, "GPIO15/GSPICS/SMB5CSDA"), 1186 PINCTRL_PIN(16, "GPIO16/LKGPO0"), 1187 PINCTRL_PIN(17, "GPIO17/PSPI2DI/SMB4DEN"), 1188 PINCTRL_PIN(18, "GPIO18/PSPI2D0/SMB4BSDA"), 1189 PINCTRL_PIN(19, "GPIO19/PSPI2CK/SMB4BSCL"), 1190 PINCTRL_PIN(20, "GPIO20/SMB4CSDA/SMB15SDA"), 1191 PINCTRL_PIN(21, "GPIO21/SMB4CSCL/SMB15SCL"), 1192 PINCTRL_PIN(22, "GPIO22/SMB4DSDA/SMB14SDA"), 1193 PINCTRL_PIN(23, "GPIO23/SMB4DSCL/SMB14SCL"), 1194 PINCTRL_PIN(24, "GPIO24/IOXHDO"), 1195 PINCTRL_PIN(25, "GPIO25/IOXHDI"), 1196 PINCTRL_PIN(26, "GPIO26/SMB5SDA"), 1197 PINCTRL_PIN(27, "GPIO27/SMB5SCL"), 1198 PINCTRL_PIN(28, "GPIO28/SMB4SDA"), 1199 PINCTRL_PIN(29, "GPIO29/SMB4SCL"), 1200 PINCTRL_PIN(30, "GPIO30/SMB3SDA"), 1201 PINCTRL_PIN(31, "GPIO31/SMB3SCL"), 1202 1203 PINCTRL_PIN(32, "GPIO32/nSPI0CS1"), 1204 PINCTRL_PIN(33, "SPI0D2"), 1205 PINCTRL_PIN(34, "SPI0D3"), 1206 PINCTRL_PIN(37, "GPIO37/SMB3CSDA"), 1207 PINCTRL_PIN(38, "GPIO38/SMB3CSCL"), 1208 PINCTRL_PIN(39, "GPIO39/SMB3BSDA"), 1209 PINCTRL_PIN(40, "GPIO40/SMB3BSCL"), 1210 PINCTRL_PIN(41, "GPIO41/BSPRXD"), 1211 PINCTRL_PIN(42, "GPO42/BSPTXD/STRAP11"), 1212 PINCTRL_PIN(43, "GPIO43/RXD1/JTMS2/BU1RXD"), 1213 PINCTRL_PIN(44, "GPIO44/nCTS1/JTDI2/BU1CTS"), 1214 PINCTRL_PIN(45, "GPIO45/nDCD1/JTDO2"), 1215 PINCTRL_PIN(46, "GPIO46/nDSR1/JTCK2"), 1216 PINCTRL_PIN(47, "GPIO47/nRI1/JCP_RDY2"), 1217 PINCTRL_PIN(48, "GPIO48/TXD2/BSPTXD"), 1218 PINCTRL_PIN(49, "GPIO49/RXD2/BSPRXD"), 1219 PINCTRL_PIN(50, "GPIO50/nCTS2"), 1220 PINCTRL_PIN(51, "GPO51/nRTS2/STRAP2"), 1221 PINCTRL_PIN(52, "GPIO52/nDCD2"), 1222 PINCTRL_PIN(53, "GPO53/nDTR2_BOUT2/STRAP1"), 1223 PINCTRL_PIN(54, "GPIO54/nDSR2"), 1224 PINCTRL_PIN(55, "GPIO55/nRI2"), 1225 PINCTRL_PIN(56, "GPIO56/R1RXERR"), 1226 PINCTRL_PIN(57, "GPIO57/R1MDC"), 1227 PINCTRL_PIN(58, "GPIO58/R1MDIO"), 1228 PINCTRL_PIN(59, "GPIO59/SMB3DSDA"), 1229 PINCTRL_PIN(60, "GPIO60/SMB3DSCL"), 1230 PINCTRL_PIN(61, "GPO61/nDTR1_BOUT1/STRAP6"), 1231 PINCTRL_PIN(62, "GPO62/nRTST1/STRAP5"), 1232 PINCTRL_PIN(63, "GPO63/TXD1/STRAP4"), 1233 1234 PINCTRL_PIN(64, "GPIO64/FANIN0"), 1235 PINCTRL_PIN(65, "GPIO65/FANIN1"), 1236 PINCTRL_PIN(66, "GPIO66/FANIN2"), 1237 PINCTRL_PIN(67, "GPIO67/FANIN3"), 1238 PINCTRL_PIN(68, "GPIO68/FANIN4"), 1239 PINCTRL_PIN(69, "GPIO69/FANIN5"), 1240 PINCTRL_PIN(70, "GPIO70/FANIN6"), 1241 PINCTRL_PIN(71, "GPIO71/FANIN7"), 1242 PINCTRL_PIN(72, "GPIO72/FANIN8"), 1243 PINCTRL_PIN(73, "GPIO73/FANIN9"), 1244 PINCTRL_PIN(74, "GPIO74/FANIN10"), 1245 PINCTRL_PIN(75, "GPIO75/FANIN11"), 1246 PINCTRL_PIN(76, "GPIO76/FANIN12"), 1247 PINCTRL_PIN(77, "GPIO77/FANIN13"), 1248 PINCTRL_PIN(78, "GPIO78/FANIN14"), 1249 PINCTRL_PIN(79, "GPIO79/FANIN15"), 1250 PINCTRL_PIN(80, "GPIO80/PWM0"), 1251 PINCTRL_PIN(81, "GPIO81/PWM1"), 1252 PINCTRL_PIN(82, "GPIO82/PWM2"), 1253 PINCTRL_PIN(83, "GPIO83/PWM3"), 1254 PINCTRL_PIN(84, "GPIO84/R2TXD0"), 1255 PINCTRL_PIN(85, "GPIO85/R2TXD1"), 1256 PINCTRL_PIN(86, "GPIO86/R2TXEN"), 1257 PINCTRL_PIN(87, "GPIO87/R2RXD0"), 1258 PINCTRL_PIN(88, "GPIO88/R2RXD1"), 1259 PINCTRL_PIN(89, "GPIO89/R2CRSDV"), 1260 PINCTRL_PIN(90, "GPIO90/R2RXERR"), 1261 PINCTRL_PIN(91, "GPIO91/R2MDC"), 1262 PINCTRL_PIN(92, "GPIO92/R2MDIO"), 1263 PINCTRL_PIN(93, "GPIO93/GA20/SMB5DSCL"), 1264 PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5DSDA"), 1265 PINCTRL_PIN(95, "GPIO95/nLRESET/nESPIRST"), 1266 1267 PINCTRL_PIN(96, "GPIO96/RG1TXD0"), 1268 PINCTRL_PIN(97, "GPIO97/RG1TXD1"), 1269 PINCTRL_PIN(98, "GPIO98/RG1TXD2"), 1270 PINCTRL_PIN(99, "GPIO99/RG1TXD3"), 1271 PINCTRL_PIN(100, "GPIO100/RG1TXC"), 1272 PINCTRL_PIN(101, "GPIO101/RG1TXCTL"), 1273 PINCTRL_PIN(102, "GPIO102/RG1RXD0"), 1274 PINCTRL_PIN(103, "GPIO103/RG1RXD1"), 1275 PINCTRL_PIN(104, "GPIO104/RG1RXD2"), 1276 PINCTRL_PIN(105, "GPIO105/RG1RXD3"), 1277 PINCTRL_PIN(106, "GPIO106/RG1RXC"), 1278 PINCTRL_PIN(107, "GPIO107/RG1RXCTL"), 1279 PINCTRL_PIN(108, "GPIO108/RG1MDC"), 1280 PINCTRL_PIN(109, "GPIO109/RG1MDIO"), 1281 PINCTRL_PIN(110, "GPIO110/RG2TXD0/DDRV0"), 1282 PINCTRL_PIN(111, "GPIO111/RG2TXD1/DDRV1"), 1283 PINCTRL_PIN(112, "GPIO112/RG2TXD2/DDRV2"), 1284 PINCTRL_PIN(113, "GPIO113/RG2TXD3/DDRV3"), 1285 PINCTRL_PIN(114, "GPIO114/SMB0SCL"), 1286 PINCTRL_PIN(115, "GPIO115/SMB0SDA"), 1287 PINCTRL_PIN(116, "GPIO116/SMB1SCL"), 1288 PINCTRL_PIN(117, "GPIO117/SMB1SDA"), 1289 PINCTRL_PIN(118, "GPIO118/SMB2SCL"), 1290 PINCTRL_PIN(119, "GPIO119/SMB2SDA"), 1291 PINCTRL_PIN(120, "GPIO120/SMB2CSDA"), 1292 PINCTRL_PIN(121, "GPIO121/SMB2CSCL"), 1293 PINCTRL_PIN(122, "GPIO122/SMB2BSDA"), 1294 PINCTRL_PIN(123, "GPIO123/SMB2BSCL"), 1295 PINCTRL_PIN(124, "GPIO124/SMB1CSDA"), 1296 PINCTRL_PIN(125, "GPIO125/SMB1CSCL"), 1297 PINCTRL_PIN(126, "GPIO126/SMB1BSDA"), 1298 PINCTRL_PIN(127, "GPIO127/SMB1BSCL"), 1299 1300 PINCTRL_PIN(128, "GPIO128/SMB8SCL"), 1301 PINCTRL_PIN(129, "GPIO129/SMB8SDA"), 1302 PINCTRL_PIN(130, "GPIO130/SMB9SCL"), 1303 PINCTRL_PIN(131, "GPIO131/SMB9SDA"), 1304 PINCTRL_PIN(132, "GPIO132/SMB10SCL"), 1305 PINCTRL_PIN(133, "GPIO133/SMB10SDA"), 1306 PINCTRL_PIN(134, "GPIO134/SMB11SCL"), 1307 PINCTRL_PIN(135, "GPIO135/SMB11SDA"), 1308 PINCTRL_PIN(136, "GPIO136/SD1DT0"), 1309 PINCTRL_PIN(137, "GPIO137/SD1DT1"), 1310 PINCTRL_PIN(138, "GPIO138/SD1DT2"), 1311 PINCTRL_PIN(139, "GPIO139/SD1DT3"), 1312 PINCTRL_PIN(140, "GPIO140/SD1CLK"), 1313 PINCTRL_PIN(141, "GPIO141/SD1WP"), 1314 PINCTRL_PIN(142, "GPIO142/SD1CMD"), 1315 PINCTRL_PIN(143, "GPIO143/SD1CD/SD1PWR"), 1316 PINCTRL_PIN(144, "GPIO144/PWM4"), 1317 PINCTRL_PIN(145, "GPIO145/PWM5"), 1318 PINCTRL_PIN(146, "GPIO146/PWM6"), 1319 PINCTRL_PIN(147, "GPIO147/PWM7"), 1320 PINCTRL_PIN(148, "GPIO148/MMCDT4"), 1321 PINCTRL_PIN(149, "GPIO149/MMCDT5"), 1322 PINCTRL_PIN(150, "GPIO150/MMCDT6"), 1323 PINCTRL_PIN(151, "GPIO151/MMCDT7"), 1324 PINCTRL_PIN(152, "GPIO152/MMCCLK"), 1325 PINCTRL_PIN(153, "GPIO153/MMCWP"), 1326 PINCTRL_PIN(154, "GPIO154/MMCCMD"), 1327 PINCTRL_PIN(155, "GPIO155/nMMCCD/nMMCRST"), 1328 PINCTRL_PIN(156, "GPIO156/MMCDT0"), 1329 PINCTRL_PIN(157, "GPIO157/MMCDT1"), 1330 PINCTRL_PIN(158, "GPIO158/MMCDT2"), 1331 PINCTRL_PIN(159, "GPIO159/MMCDT3"), 1332 1333 PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT"), 1334 PINCTRL_PIN(161, "GPIO161/nLFRAME/nESPICS"), 1335 PINCTRL_PIN(162, "GPIO162/SERIRQ"), 1336 PINCTRL_PIN(163, "GPIO163/LCLK/ESPICLK"), 1337 PINCTRL_PIN(164, "GPIO164/LAD0/ESPI_IO0"/*dscnt6*/), 1338 PINCTRL_PIN(165, "GPIO165/LAD1/ESPI_IO1"/*dscnt6*/), 1339 PINCTRL_PIN(166, "GPIO166/LAD2/ESPI_IO2"/*dscnt6*/), 1340 PINCTRL_PIN(167, "GPIO167/LAD3/ESPI_IO3"/*dscnt6*/), 1341 PINCTRL_PIN(168, "GPIO168/nCLKRUN/nESPIALERT"), 1342 PINCTRL_PIN(169, "GPIO169/nSCIPME"), 1343 PINCTRL_PIN(170, "GPIO170/nSMI"), 1344 PINCTRL_PIN(171, "GPIO171/SMB6SCL"), 1345 PINCTRL_PIN(172, "GPIO172/SMB6SDA"), 1346 PINCTRL_PIN(173, "GPIO173/SMB7SCL"), 1347 PINCTRL_PIN(174, "GPIO174/SMB7SDA"), 1348 PINCTRL_PIN(175, "GPIO175/PSPI1CK/FANIN19"), 1349 PINCTRL_PIN(176, "GPIO176/PSPI1DO/FANIN18"), 1350 PINCTRL_PIN(177, "GPIO177/PSPI1DI/FANIN17"), 1351 PINCTRL_PIN(178, "GPIO178/R1TXD0"), 1352 PINCTRL_PIN(179, "GPIO179/R1TXD1"), 1353 PINCTRL_PIN(180, "GPIO180/R1TXEN"), 1354 PINCTRL_PIN(181, "GPIO181/R1RXD0"), 1355 PINCTRL_PIN(182, "GPIO182/R1RXD1"), 1356 PINCTRL_PIN(183, "GPIO183/SPI3CK"), 1357 PINCTRL_PIN(184, "GPO184/SPI3D0/STRAP9"), 1358 PINCTRL_PIN(185, "GPO185/SPI3D1/STRAP10"), 1359 PINCTRL_PIN(186, "GPIO186/nSPI3CS0"), 1360 PINCTRL_PIN(187, "GPIO187/nSPI3CS1"), 1361 PINCTRL_PIN(188, "GPIO188/SPI3D2/nSPI3CS2"), 1362 PINCTRL_PIN(189, "GPIO189/SPI3D3/nSPI3CS3"), 1363 PINCTRL_PIN(190, "GPIO190/nPRD_SMI"), 1364 PINCTRL_PIN(191, "GPIO191"), 1365 1366 PINCTRL_PIN(192, "GPIO192"), 1367 PINCTRL_PIN(193, "GPIO193/R1CRSDV"), 1368 PINCTRL_PIN(194, "GPIO194/SMB0BSCL"), 1369 PINCTRL_PIN(195, "GPIO195/SMB0BSDA"), 1370 PINCTRL_PIN(196, "GPIO196/SMB0CSCL"), 1371 PINCTRL_PIN(197, "GPIO197/SMB0DEN"), 1372 PINCTRL_PIN(198, "GPIO198/SMB0DSDA"), 1373 PINCTRL_PIN(199, "GPIO199/SMB0DSCL"), 1374 PINCTRL_PIN(200, "GPIO200/R2CK"), 1375 PINCTRL_PIN(201, "GPIO201/R1CK"), 1376 PINCTRL_PIN(202, "GPIO202/SMB0CSDA"), 1377 PINCTRL_PIN(203, "GPIO203/FANIN16"), 1378 PINCTRL_PIN(204, "GPIO204/DDC2SCL"), 1379 PINCTRL_PIN(205, "GPIO205/DDC2SDA"), 1380 PINCTRL_PIN(206, "GPIO206/HSYNC2"), 1381 PINCTRL_PIN(207, "GPIO207/VSYNC2"), 1382 PINCTRL_PIN(208, "GPIO208/RG2TXC/DVCK"), 1383 PINCTRL_PIN(209, "GPIO209/RG2TXCTL/DDRV4"), 1384 PINCTRL_PIN(210, "GPIO210/RG2RXD0/DDRV5"), 1385 PINCTRL_PIN(211, "GPIO211/RG2RXD1/DDRV6"), 1386 PINCTRL_PIN(212, "GPIO212/RG2RXD2/DDRV7"), 1387 PINCTRL_PIN(213, "GPIO213/RG2RXD3/DDRV8"), 1388 PINCTRL_PIN(214, "GPIO214/RG2RXC/DDRV9"), 1389 PINCTRL_PIN(215, "GPIO215/RG2RXCTL/DDRV10"), 1390 PINCTRL_PIN(216, "GPIO216/RG2MDC/DDRV11"), 1391 PINCTRL_PIN(217, "GPIO217/RG2MDIO/DVHSYNC"), 1392 PINCTRL_PIN(218, "GPIO218/nWDO1"), 1393 PINCTRL_PIN(219, "GPIO219/nWDO2"), 1394 PINCTRL_PIN(220, "GPIO220/SMB12SCL"), 1395 PINCTRL_PIN(221, "GPIO221/SMB12SDA"), 1396 PINCTRL_PIN(222, "GPIO222/SMB13SCL"), 1397 PINCTRL_PIN(223, "GPIO223/SMB13SDA"), 1398 1399 PINCTRL_PIN(224, "GPIO224/SPIXCK"), 1400 PINCTRL_PIN(225, "GPO225/SPIXD0/STRAP12"), 1401 PINCTRL_PIN(226, "GPO226/SPIXD1/STRAP13"), 1402 PINCTRL_PIN(227, "GPIO227/nSPIXCS0"), 1403 PINCTRL_PIN(228, "GPIO228/nSPIXCS1"), 1404 PINCTRL_PIN(229, "GPO229/SPIXD2/STRAP3"), 1405 PINCTRL_PIN(230, "GPIO230/SPIXD3"), 1406 PINCTRL_PIN(231, "GPIO231/nCLKREQ"), 1407 PINCTRL_PIN(255, "GPI255/DACOSEL"), 1408 }; 1409 1410 /* Enable mode in pin group */ 1411 static void npcm7xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, 1412 int pin_number, int mode) 1413 { 1414 const struct npcm7xx_pincfg *cfg; 1415 int i; 1416 1417 for (i = 0 ; i < pin_number ; i++) { 1418 cfg = &pincfg[pin[i]]; 1419 if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) { 1420 if (cfg->reg0) 1421 regmap_update_bits(gcr_regmap, cfg->reg0, 1422 BIT(cfg->bit0), 1423 !!(cfg->fn0 == mode) ? 1424 BIT(cfg->bit0) : 0); 1425 if (cfg->reg1) 1426 regmap_update_bits(gcr_regmap, cfg->reg1, 1427 BIT(cfg->bit1), 1428 !!(cfg->fn1 == mode) ? 1429 BIT(cfg->bit1) : 0); 1430 if (cfg->reg2) 1431 regmap_update_bits(gcr_regmap, cfg->reg2, 1432 BIT(cfg->bit2), 1433 !!(cfg->fn2 == mode) ? 1434 BIT(cfg->bit2) : 0); 1435 } 1436 } 1437 } 1438 1439 /* Get slew rate of pin (high/low) */ 1440 static int npcm7xx_get_slew_rate(struct npcm7xx_gpio *bank, 1441 struct regmap *gcr_regmap, unsigned int pin) 1442 { 1443 u32 val; 1444 int gpio = (pin % bank->gc.ngpio); 1445 unsigned long pinmask = BIT(gpio); 1446 1447 if (pincfg[pin].flag & SLEW) 1448 return ioread32(bank->base + NPCM7XX_GP_N_OSRC) 1449 & pinmask; 1450 /* LPC Slew rate in SRCNT register */ 1451 if (pincfg[pin].flag & SLEWLPC) { 1452 regmap_read(gcr_regmap, NPCM7XX_GCR_SRCNT, &val); 1453 return !!(val & SRCNT_ESPI); 1454 } 1455 1456 return -EINVAL; 1457 } 1458 1459 /* Set slew rate of pin (high/low) */ 1460 static int npcm7xx_set_slew_rate(struct npcm7xx_gpio *bank, 1461 struct regmap *gcr_regmap, unsigned int pin, 1462 int arg) 1463 { 1464 int gpio = BIT(pin % bank->gc.ngpio); 1465 1466 if (pincfg[pin].flag & SLEW) { 1467 switch (arg) { 1468 case 0: 1469 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, 1470 gpio); 1471 return 0; 1472 case 1: 1473 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, 1474 gpio); 1475 return 0; 1476 default: 1477 return -EINVAL; 1478 } 1479 } 1480 /* LPC Slew rate in SRCNT register */ 1481 if (pincfg[pin].flag & SLEWLPC) { 1482 switch (arg) { 1483 case 0: 1484 regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT, 1485 SRCNT_ESPI, 0); 1486 return 0; 1487 case 1: 1488 regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT, 1489 SRCNT_ESPI, SRCNT_ESPI); 1490 return 0; 1491 default: 1492 return -EINVAL; 1493 } 1494 } 1495 1496 return -EINVAL; 1497 } 1498 1499 /* Get drive strength for a pin, if supported */ 1500 static int npcm7xx_get_drive_strength(struct pinctrl_dev *pctldev, 1501 unsigned int pin) 1502 { 1503 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1504 struct npcm7xx_gpio *bank = 1505 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1506 int gpio = (pin % bank->gc.ngpio); 1507 unsigned long pinmask = BIT(gpio); 1508 u32 ds = 0; 1509 int flg, val; 1510 1511 flg = pincfg[pin].flag; 1512 if (flg & DRIVE_STRENGTH_MASK) { 1513 /* Get standard reading */ 1514 val = ioread32(bank->base + NPCM7XX_GP_N_ODSC) 1515 & pinmask; 1516 ds = val ? DSHI(flg) : DSLO(flg); 1517 dev_dbg(bank->gc.parent, 1518 "pin %d strength %d = %d\n", pin, val, ds); 1519 return ds; 1520 } 1521 1522 return -EINVAL; 1523 } 1524 1525 /* Set drive strength for a pin, if supported */ 1526 static int npcm7xx_set_drive_strength(struct npcm7xx_pinctrl *npcm, 1527 unsigned int pin, int nval) 1528 { 1529 int v; 1530 struct npcm7xx_gpio *bank = 1531 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1532 int gpio = BIT(pin % bank->gc.ngpio); 1533 1534 v = (pincfg[pin].flag & DRIVE_STRENGTH_MASK); 1535 if (!nval || !v) 1536 return -ENOTSUPP; 1537 if (DSLO(v) == nval) { 1538 dev_dbg(bank->gc.parent, 1539 "setting pin %d to low strength [%d]\n", pin, nval); 1540 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); 1541 return 0; 1542 } else if (DSHI(v) == nval) { 1543 dev_dbg(bank->gc.parent, 1544 "setting pin %d to high strength [%d]\n", pin, nval); 1545 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); 1546 return 0; 1547 } 1548 1549 return -ENOTSUPP; 1550 } 1551 1552 /* pinctrl_ops */ 1553 static void npcm7xx_pin_dbg_show(struct pinctrl_dev *pctldev, 1554 struct seq_file *s, unsigned int offset) 1555 { 1556 seq_printf(s, "pinctrl_ops.dbg: %d", offset); 1557 } 1558 1559 static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev) 1560 { 1561 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1562 1563 dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups)); 1564 return ARRAY_SIZE(npcm7xx_groups); 1565 } 1566 1567 static const char *npcm7xx_get_group_name(struct pinctrl_dev *pctldev, 1568 unsigned int selector) 1569 { 1570 return npcm7xx_groups[selector].name; 1571 } 1572 1573 static int npcm7xx_get_group_pins(struct pinctrl_dev *pctldev, 1574 unsigned int selector, 1575 const unsigned int **pins, 1576 unsigned int *npins) 1577 { 1578 *npins = npcm7xx_groups[selector].npins; 1579 *pins = npcm7xx_groups[selector].pins; 1580 1581 return 0; 1582 } 1583 1584 static int npcm7xx_dt_node_to_map(struct pinctrl_dev *pctldev, 1585 struct device_node *np_config, 1586 struct pinctrl_map **map, 1587 u32 *num_maps) 1588 { 1589 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1590 1591 dev_dbg(npcm->dev, "dt_node_to_map: %s\n", np_config->name); 1592 return pinconf_generic_dt_node_to_map(pctldev, np_config, 1593 map, num_maps, 1594 PIN_MAP_TYPE_INVALID); 1595 } 1596 1597 static void npcm7xx_dt_free_map(struct pinctrl_dev *pctldev, 1598 struct pinctrl_map *map, u32 num_maps) 1599 { 1600 kfree(map); 1601 } 1602 1603 static const struct pinctrl_ops npcm7xx_pinctrl_ops = { 1604 .get_groups_count = npcm7xx_get_groups_count, 1605 .get_group_name = npcm7xx_get_group_name, 1606 .get_group_pins = npcm7xx_get_group_pins, 1607 .pin_dbg_show = npcm7xx_pin_dbg_show, 1608 .dt_node_to_map = npcm7xx_dt_node_to_map, 1609 .dt_free_map = npcm7xx_dt_free_map, 1610 }; 1611 1612 /* pinmux_ops */ 1613 static int npcm7xx_get_functions_count(struct pinctrl_dev *pctldev) 1614 { 1615 return ARRAY_SIZE(npcm7xx_funcs); 1616 } 1617 1618 static const char *npcm7xx_get_function_name(struct pinctrl_dev *pctldev, 1619 unsigned int function) 1620 { 1621 return npcm7xx_funcs[function].name; 1622 } 1623 1624 static int npcm7xx_get_function_groups(struct pinctrl_dev *pctldev, 1625 unsigned int function, 1626 const char * const **groups, 1627 unsigned int * const ngroups) 1628 { 1629 *ngroups = npcm7xx_funcs[function].ngroups; 1630 *groups = npcm7xx_funcs[function].groups; 1631 1632 return 0; 1633 } 1634 1635 static int npcm7xx_pinmux_set_mux(struct pinctrl_dev *pctldev, 1636 unsigned int function, 1637 unsigned int group) 1638 { 1639 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1640 1641 dev_dbg(npcm->dev, "set_mux: %d, %d[%s]\n", function, group, 1642 npcm7xx_groups[group].name); 1643 1644 npcm7xx_setfunc(npcm->gcr_regmap, npcm7xx_groups[group].pins, 1645 npcm7xx_groups[group].npins, group); 1646 1647 return 0; 1648 } 1649 1650 static int npcm7xx_gpio_request_enable(struct pinctrl_dev *pctldev, 1651 struct pinctrl_gpio_range *range, 1652 unsigned int offset) 1653 { 1654 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1655 1656 if (!range) { 1657 dev_err(npcm->dev, "invalid range\n"); 1658 return -EINVAL; 1659 } 1660 if (!range->gc) { 1661 dev_err(npcm->dev, "invalid gpiochip\n"); 1662 return -EINVAL; 1663 } 1664 1665 npcm7xx_setfunc(npcm->gcr_regmap, &offset, 1, fn_gpio); 1666 1667 return 0; 1668 } 1669 1670 /* Release GPIO back to pinctrl mode */ 1671 static void npcm7xx_gpio_request_free(struct pinctrl_dev *pctldev, 1672 struct pinctrl_gpio_range *range, 1673 unsigned int offset) 1674 { 1675 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1676 int virq; 1677 1678 virq = irq_find_mapping(npcm->domain, offset); 1679 if (virq) 1680 irq_dispose_mapping(virq); 1681 } 1682 1683 /* Set GPIO direction */ 1684 static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev, 1685 struct pinctrl_gpio_range *range, 1686 unsigned int offset, bool input) 1687 { 1688 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1689 struct npcm7xx_gpio *bank = 1690 &npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK]; 1691 int gpio = BIT(offset % bank->gc.ngpio); 1692 1693 dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset, 1694 input); 1695 if (input) 1696 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); 1697 else 1698 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); 1699 1700 return 0; 1701 } 1702 1703 static const struct pinmux_ops npcm7xx_pinmux_ops = { 1704 .get_functions_count = npcm7xx_get_functions_count, 1705 .get_function_name = npcm7xx_get_function_name, 1706 .get_function_groups = npcm7xx_get_function_groups, 1707 .set_mux = npcm7xx_pinmux_set_mux, 1708 .gpio_request_enable = npcm7xx_gpio_request_enable, 1709 .gpio_disable_free = npcm7xx_gpio_request_free, 1710 .gpio_set_direction = npcm_gpio_set_direction, 1711 }; 1712 1713 /* pinconf_ops */ 1714 static int npcm7xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 1715 unsigned long *config) 1716 { 1717 enum pin_config_param param = pinconf_to_config_param(*config); 1718 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1719 struct npcm7xx_gpio *bank = 1720 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1721 int gpio = (pin % bank->gc.ngpio); 1722 unsigned long pinmask = BIT(gpio); 1723 u32 ie, oe, pu, pd; 1724 int rc = 0; 1725 1726 switch (param) { 1727 case PIN_CONFIG_BIAS_DISABLE: 1728 case PIN_CONFIG_BIAS_PULL_UP: 1729 case PIN_CONFIG_BIAS_PULL_DOWN: 1730 pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask; 1731 pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask; 1732 if (param == PIN_CONFIG_BIAS_DISABLE) 1733 rc = (!pu && !pd); 1734 else if (param == PIN_CONFIG_BIAS_PULL_UP) 1735 rc = (pu && !pd); 1736 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1737 rc = (!pu && pd); 1738 break; 1739 case PIN_CONFIG_OUTPUT: 1740 case PIN_CONFIG_INPUT_ENABLE: 1741 ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask; 1742 oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask; 1743 if (param == PIN_CONFIG_INPUT_ENABLE) 1744 rc = (ie && !oe); 1745 else if (param == PIN_CONFIG_OUTPUT) 1746 rc = (!ie && oe); 1747 break; 1748 case PIN_CONFIG_DRIVE_PUSH_PULL: 1749 rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask); 1750 break; 1751 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1752 rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask; 1753 break; 1754 case PIN_CONFIG_INPUT_DEBOUNCE: 1755 rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask; 1756 break; 1757 case PIN_CONFIG_DRIVE_STRENGTH: 1758 rc = npcm7xx_get_drive_strength(pctldev, pin); 1759 if (rc) 1760 *config = pinconf_to_config_packed(param, rc); 1761 break; 1762 case PIN_CONFIG_SLEW_RATE: 1763 rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin); 1764 if (rc >= 0) 1765 *config = pinconf_to_config_packed(param, rc); 1766 break; 1767 default: 1768 return -ENOTSUPP; 1769 } 1770 1771 if (!rc) 1772 return -EINVAL; 1773 1774 return 0; 1775 } 1776 1777 static int npcm7xx_config_set_one(struct npcm7xx_pinctrl *npcm, 1778 unsigned int pin, unsigned long config) 1779 { 1780 enum pin_config_param param = pinconf_to_config_param(config); 1781 u16 arg = pinconf_to_config_argument(config); 1782 struct npcm7xx_gpio *bank = 1783 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1784 int gpio = BIT(pin % bank->gc.ngpio); 1785 1786 dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin); 1787 switch (param) { 1788 case PIN_CONFIG_BIAS_DISABLE: 1789 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); 1790 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); 1791 break; 1792 case PIN_CONFIG_BIAS_PULL_DOWN: 1793 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); 1794 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); 1795 break; 1796 case PIN_CONFIG_BIAS_PULL_UP: 1797 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); 1798 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); 1799 break; 1800 case PIN_CONFIG_INPUT_ENABLE: 1801 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); 1802 bank->direction_input(&bank->gc, pin % bank->gc.ngpio); 1803 break; 1804 case PIN_CONFIG_OUTPUT: 1805 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); 1806 bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); 1807 break; 1808 case PIN_CONFIG_DRIVE_PUSH_PULL: 1809 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); 1810 break; 1811 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1812 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); 1813 break; 1814 case PIN_CONFIG_INPUT_DEBOUNCE: 1815 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio); 1816 break; 1817 case PIN_CONFIG_SLEW_RATE: 1818 return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg); 1819 case PIN_CONFIG_DRIVE_STRENGTH: 1820 return npcm7xx_set_drive_strength(npcm, pin, arg); 1821 default: 1822 return -ENOTSUPP; 1823 } 1824 1825 return 0; 1826 } 1827 1828 /* Set multiple configuration settings for a pin */ 1829 static int npcm7xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 1830 unsigned long *configs, unsigned int num_configs) 1831 { 1832 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1833 int rc; 1834 1835 while (num_configs--) { 1836 rc = npcm7xx_config_set_one(npcm, pin, *configs++); 1837 if (rc) 1838 return rc; 1839 } 1840 1841 return 0; 1842 } 1843 1844 static const struct pinconf_ops npcm7xx_pinconf_ops = { 1845 .is_generic = true, 1846 .pin_config_get = npcm7xx_config_get, 1847 .pin_config_set = npcm7xx_config_set, 1848 }; 1849 1850 /* pinctrl_desc */ 1851 static struct pinctrl_desc npcm7xx_pinctrl_desc = { 1852 .name = "npcm7xx-pinctrl", 1853 .pins = npcm7xx_pins, 1854 .npins = ARRAY_SIZE(npcm7xx_pins), 1855 .pctlops = &npcm7xx_pinctrl_ops, 1856 .pmxops = &npcm7xx_pinmux_ops, 1857 .confops = &npcm7xx_pinconf_ops, 1858 .owner = THIS_MODULE, 1859 }; 1860 1861 static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl) 1862 { 1863 int ret = -ENXIO; 1864 struct resource res; 1865 int id = 0, irq; 1866 struct device_node *np; 1867 struct of_phandle_args pinspec; 1868 1869 for_each_available_child_of_node(pctrl->dev->of_node, np) 1870 if (of_find_property(np, "gpio-controller", NULL)) { 1871 ret = of_address_to_resource(np, 0, &res); 1872 if (ret < 0) { 1873 dev_err(pctrl->dev, 1874 "Resource fail for GPIO bank %u\n", id); 1875 return ret; 1876 } 1877 1878 pctrl->gpio_bank[id].base = 1879 ioremap(res.start, resource_size(&res)); 1880 1881 irq = irq_of_parse_and_map(np, 0); 1882 if (irq < 0) { 1883 dev_err(pctrl->dev, 1884 "No IRQ for GPIO bank %u\n", id); 1885 ret = irq; 1886 return ret; 1887 } 1888 1889 ret = bgpio_init(&pctrl->gpio_bank[id].gc, 1890 pctrl->dev, 4, 1891 pctrl->gpio_bank[id].base + 1892 NPCM7XX_GP_N_DIN, 1893 pctrl->gpio_bank[id].base + 1894 NPCM7XX_GP_N_DOUT, 1895 NULL, 1896 NULL, 1897 pctrl->gpio_bank[id].base + 1898 NPCM7XX_GP_N_IEM, 1899 BGPIOF_READ_OUTPUT_REG_SET); 1900 if (ret) { 1901 dev_err(pctrl->dev, "bgpio_init() failed\n"); 1902 return ret; 1903 } 1904 1905 ret = of_parse_phandle_with_fixed_args(np, 1906 "gpio-ranges", 3, 1907 0, &pinspec); 1908 if (ret < 0) { 1909 dev_err(pctrl->dev, 1910 "gpio-ranges fail for GPIO bank %u\n", 1911 id); 1912 return ret; 1913 } 1914 1915 pctrl->gpio_bank[id].irq = irq; 1916 pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip; 1917 pctrl->gpio_bank[id].gc.parent = pctrl->dev; 1918 pctrl->gpio_bank[id].irqbase = 1919 id * NPCM7XX_GPIO_PER_BANK; 1920 pctrl->gpio_bank[id].pinctrl_id = pinspec.args[0]; 1921 pctrl->gpio_bank[id].gc.base = pinspec.args[1]; 1922 pctrl->gpio_bank[id].gc.ngpio = pinspec.args[2]; 1923 pctrl->gpio_bank[id].gc.owner = THIS_MODULE; 1924 pctrl->gpio_bank[id].gc.label = 1925 devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOF", 1926 np); 1927 if (pctrl->gpio_bank[id].gc.label == NULL) 1928 return -ENOMEM; 1929 1930 pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show; 1931 pctrl->gpio_bank[id].direction_input = 1932 pctrl->gpio_bank[id].gc.direction_input; 1933 pctrl->gpio_bank[id].gc.direction_input = 1934 npcmgpio_direction_input; 1935 pctrl->gpio_bank[id].direction_output = 1936 pctrl->gpio_bank[id].gc.direction_output; 1937 pctrl->gpio_bank[id].gc.direction_output = 1938 npcmgpio_direction_output; 1939 pctrl->gpio_bank[id].request = 1940 pctrl->gpio_bank[id].gc.request; 1941 pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request; 1942 pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free; 1943 pctrl->gpio_bank[id].gc.of_node = np; 1944 id++; 1945 } 1946 1947 pctrl->bank_num = id; 1948 return ret; 1949 } 1950 1951 static int npcm7xx_gpio_register(struct npcm7xx_pinctrl *pctrl) 1952 { 1953 int ret, id; 1954 1955 for (id = 0 ; id < pctrl->bank_num ; id++) { 1956 struct gpio_irq_chip *girq; 1957 1958 girq = &pctrl->gpio_bank[id].gc.irq; 1959 girq->chip = &pctrl->gpio_bank[id].irq_chip; 1960 girq->parent_handler = npcmgpio_irq_handler; 1961 girq->num_parents = 1; 1962 girq->parents = devm_kcalloc(pctrl->dev, 1, 1963 sizeof(*girq->parents), 1964 GFP_KERNEL); 1965 if (!girq->parents) { 1966 ret = -ENOMEM; 1967 goto err_register; 1968 } 1969 girq->parents[0] = pctrl->gpio_bank[id].irq; 1970 girq->default_type = IRQ_TYPE_NONE; 1971 girq->handler = handle_level_irq; 1972 ret = devm_gpiochip_add_data(pctrl->dev, 1973 &pctrl->gpio_bank[id].gc, 1974 &pctrl->gpio_bank[id]); 1975 if (ret) { 1976 dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id); 1977 goto err_register; 1978 } 1979 1980 ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].gc, 1981 dev_name(pctrl->dev), 1982 pctrl->gpio_bank[id].pinctrl_id, 1983 pctrl->gpio_bank[id].gc.base, 1984 pctrl->gpio_bank[id].gc.ngpio); 1985 if (ret < 0) { 1986 dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id); 1987 gpiochip_remove(&pctrl->gpio_bank[id].gc); 1988 goto err_register; 1989 } 1990 } 1991 1992 return 0; 1993 1994 err_register: 1995 for (; id > 0; id--) 1996 gpiochip_remove(&pctrl->gpio_bank[id - 1].gc); 1997 1998 return ret; 1999 } 2000 2001 static int npcm7xx_pinctrl_probe(struct platform_device *pdev) 2002 { 2003 struct npcm7xx_pinctrl *pctrl; 2004 int ret; 2005 2006 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 2007 if (!pctrl) 2008 return -ENOMEM; 2009 2010 pctrl->dev = &pdev->dev; 2011 dev_set_drvdata(&pdev->dev, pctrl); 2012 2013 pctrl->gcr_regmap = 2014 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); 2015 if (IS_ERR(pctrl->gcr_regmap)) { 2016 dev_err(pctrl->dev, "didn't find nuvoton,npcm750-gcr\n"); 2017 return PTR_ERR(pctrl->gcr_regmap); 2018 } 2019 2020 ret = npcm7xx_gpio_of(pctrl); 2021 if (ret < 0) { 2022 dev_err(pctrl->dev, "Failed to gpio dt-binding %u\n", ret); 2023 return ret; 2024 } 2025 2026 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, 2027 &npcm7xx_pinctrl_desc, pctrl); 2028 if (IS_ERR(pctrl->pctldev)) { 2029 dev_err(&pdev->dev, "Failed to register pinctrl device\n"); 2030 return PTR_ERR(pctrl->pctldev); 2031 } 2032 2033 ret = npcm7xx_gpio_register(pctrl); 2034 if (ret < 0) { 2035 dev_err(pctrl->dev, "Failed to register gpio %u\n", ret); 2036 return ret; 2037 } 2038 2039 pr_info("NPCM7xx Pinctrl driver probed\n"); 2040 return 0; 2041 } 2042 2043 static const struct of_device_id npcm7xx_pinctrl_match[] = { 2044 { .compatible = "nuvoton,npcm750-pinctrl" }, 2045 { }, 2046 }; 2047 MODULE_DEVICE_TABLE(of, npcm7xx_pinctrl_match); 2048 2049 static struct platform_driver npcm7xx_pinctrl_driver = { 2050 .probe = npcm7xx_pinctrl_probe, 2051 .driver = { 2052 .name = "npcm7xx-pinctrl", 2053 .of_match_table = npcm7xx_pinctrl_match, 2054 .suppress_bind_attrs = true, 2055 }, 2056 }; 2057 2058 static int __init npcm7xx_pinctrl_register(void) 2059 { 2060 return platform_driver_register(&npcm7xx_pinctrl_driver); 2061 } 2062 arch_initcall(npcm7xx_pinctrl_register); 2063 2064 MODULE_LICENSE("GPL v2"); 2065 MODULE_AUTHOR("jordan_hargrave@dell.com"); 2066 MODULE_AUTHOR("tomer.maimon@nuvoton.com"); 2067 MODULE_DESCRIPTION("Nuvoton NPCM7XX Pinctrl and GPIO driver"); 2068